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EE 4253/6253 Lecture Notes November 6, 1998 page 133 Clocked Systems inputs outputs Combinational Logic
EE 4253/6253 Lecture Notes
November 6, 1998
page 133
Clocked Systems
inputs
outputs
Combinational
Logic
present state
next state
Q
D
Flip-
Flop
CLK Single Phase System, edge triggered devices outputs inputs D Q logic D Q logic
CLK
Single Phase System, edge triggered devices
outputs
inputs
D
Q
logic
D
Q
logic
D
Q
CLK
Pipelined system, single phase clock, edge-triggered
outputs
inputs
D
Q
logic
D
Q
logic
D
Q
G
G
G
∅1
∅2
∅1
Two phase clocks, level-sensitive devices (latches)
∅1
∅2

Non-overlapping clock phases

EE 4253/6253 Lecture Notes

November 6, 1998

Latches (level sensitive)

S-R latch (NOR-based, non-clocked):

S

R

(level sensitive) S-R latch (NOR-based, non-clocked): S R Q   S R Q NOR-based SR latch

Q

 

S

R

Q

NOR-based SR latch
NOR-based SR latch
NOR-based SR latch
NOR-based SR latch
NOR-based SR latch

NOR-based

SR latch

SR latch
NOR-based SR latch
NOR-based SR latch
NOR-based SR latch
NOR-based SR latch

Q

Q

page 134

S

RQ n+1

Q n+1

Operation

0

0

Q n

Q n

hold

 

1010

set

0101

reset

1100

not allowed

V DD V DD Q Q S R
V DD
V DD
Q
Q
S
R

EE 4253/6253 Lecture Notes

November 6, 1998

S-R latch (NAND-based, non-clocked):

S

R

November 6, 1998 S-R latch (NAND-based, non-clocked): S R Q   S R Q NAND-based SR

Q

 

S

R

Q

NAND-based SR latch
NAND-based SR latch
NAND-based SR latch
NAND-based SR latch

NAND-basedSR latch

NAND-based

SR latchNAND-based

SR latch
NAND-based SR latch
NAND-based SR latch
NAND-based SR latch
NAND-based SR latch

Q

Q

page 135

S Operation RQ n+1 Q n+1 0011 not allowed 0110 set 1001 reset 1 1
S
Operation
RQ n+1
Q n+1
0011
not allowed
0110
set
1001
reset
1
1
Q n
Q n
hold
V DD
V DD
Q
Q
S
R
EE 4253/6253 Lecture Notes November 6, 1998 page 136 Clocked SR latch S Q CLK
EE 4253/6253 Lecture Notes
November 6, 1998
page 136
Clocked SR latch
S
Q
CLK
Q
R
V DD V DD CLK Q Q R S CLK CLK
V DD
V DD
CLK
Q
Q
R
S
CLK
CLK

S, R high true; CLK high true

Note that the transistor implementation is not a direct gate level implementation of the design. Used complex gate design:

Q = S CLK + Q

Q = R CLK + Q

S, R only affects state when CLK is high.

EE 4253/6253 Lecture Notes

November 6, 1998

page 137

Clocked D-latch

D

CLK

D

G

Q

Q

Q

Q

November 6, 1998 page 137 Clocked D-latch D CLK D G Q Q Q Q D

D

Q
Q

CLK

6, 1998 page 137 Clocked D-latch D CLK D G Q Q Q Q D Q

CLK

1998 page 137 Clocked D-latch D CLK D G Q Q Q Q D Q CLK

CLK

page 137 Clocked D-latch D CLK D G Q Q Q Q D Q CLK CLK

CLK

CLK CLK CLK V DD V DD Q D CLK CLK V DD CLK CLK
CLK
CLK
CLK
V DD
V DD
Q
D
CLK
CLK
V DD
CLK
CLK
CLK
CLK CLK V DD V DD Q D CLK CLK V DD CLK CLK CLK Transistor-level
CLK CLK V DD V DD Q D CLK CLK V DD CLK CLK CLK Transistor-level

Transistor-level implementation:

Q

Q

Transistor count (including clock inversion) = 10

Do local clock inversion to avoid loading of clock input

EE 4253/6253 Lecture Notes

November 6, 1998

page 138

Another implementation of the clocked D-latch

Tri-state buffers, "Z" when enable input is low

Tri-state buffers, "Z" when enable input is low CLK D CLK Q Q Transistor-level implementation: D

CLK

D

CLK
CLK

Q

Q

Transistor-level implementation:

D

V DD V DD V DD CLK CLK Q Q CLK CLK
V DD
V DD
V DD
CLK
CLK
Q
Q
CLK
CLK

EE 4253/6253 Lecture Notes

November 6, 1998

page 139

D-latch with low-true clock, low-true reset

CLOCKED LATCH with RESET

cell name: CLAT

Logic Symbol

 

DATA

Q

CLK QBAR

CLK

QBAR

   

R

 
 

Input Capacitance (pF)

Signal

1.2µm

CLOCK

0.12

DATA

0.12

RESET

0.16

Size

70λ × 250λ 1.2µm: 42µm × 150µm 2.0µm: 56µm × 200µm

Functional Table

CLK

DATA

RST

Q

QBAR

0*1

DATA

DATA

*

*00

1

1

*

1Q N-1

QBAR N-1

00*0

 

1

Functional Diagram

DATA

C C C Q C Q RESET
C
C
C
Q
C
Q
RESET

CLOCK

C C
C
C

From the CMOSN library distributed by MOSIS; original library done by the National Security Agency (NSA).

EE 4253/6253 Lecture Notes

D-Flip Flop

November 6, 1998

page 140

A D-flip flop is two latches in master-slave arrangement

D

D

Q

Q

D

D

Q

Q

CLK

CLK   CLK  
 

CLK

CLK   CLK  
 
 

rising-edge triggered

falling-edge triggered

master slave D D Q D Q Q CLK G G
master
slave
D
D
Q
D
Q
Q
CLK
G
G

rising-edge triggered

master

slave

D

 

D

Q

 

D

Q

Q

     

CLK

CLK G G

G

G

     
     

falling-edge triggered

EE 4253/6253 Lecture Notes

November 6, 1998

page 141

Falling-Edge Triggered D-Flip Flop w/ asynchronous low-true set & reset

D-FLIP FLOP w/ ASY SET, RESET

cell name: DFFSR

Logic Symbol

D-FLIP FLOP w/ ASY SET, RESET cell name: DFFSR Logic Symbol SET Q DATA QBAR RESET

SET

Q

DATA

w/ ASY SET, RESET cell name: DFFSR Logic Symbol SET Q DATA QBAR RESET Input Capacitance

QBAR

RESET

RESET cell name: DFFSR Logic Symbol SET Q DATA QBAR RESET Input Capacitance (pF) Signal 1.2

Input Capacitance (pF)

Signal

1.2µm

CLOCK

0.18

DATA

0.13

SET

0.27

RESET

0.31

Size 90λ × 250λ 1.2µm: 54µm × 150µm 2.0µm: 72µm × 200µm

Functional Table

CLK

SET

RST

Q

QBAR

1Q N - 1 N-1

1

QBAR N-1

11

1

DATA

DATA

*

*00

1

*011

0

Functional Diagram

C RESET C Q DATA V DD C C C V DD C Q C
C
RESET
C
Q
DATA
V DD
C
C
C
V DD
C
Q
C
CLOCK
SET
C
RESET
C
SET
Note that SET, RESET disable the internal clock signals C, C

EE 4253/6253 Lecture Notes

November 6, 1998

page 142

Previous examples were "traditional" static designs. Always looking for latch/flip-flop structures which reduce the numbers of transistors.

CLK

cross coupled inverters

the numbers of transistors. CLK cross coupled inverters D Q CLK "weak" (low-gain) inverter When CLK
D Q CLK
D
Q
CLK

"weak" (low-gain) inverter

When CLK is high, D input must be able to overdrive the feedback inverter output. Use low-gain devices in feedback inverter.

Another example:

D

Q Q CLK
Q
Q
CLK

This implementation requires 10 transistors but it might actually take up less area than the traditional clocked D-latch design because it avoids pass transistors.

EE 4253/6253 Lecture Notes

November 6, 1998

page 143

To eliminate more transistors, can eliminate feedback elements and create

"dynamic" registers

D

CLK

elements and create " dynamic " registers D CLK CLK Q In this case, the gate

CLK

Q
Q
and create " dynamic " registers D CLK CLK Q In this case, the gate capacitance
and create " dynamic " registers D CLK CLK Q In this case, the gate capacitance

In this case, the gate capacitance of the inverter becomes the state holding element.

"Dynamic" because the charge on the gate capacitance will eventually leak off.

How long for leakage? For example, assuming leakage current of 1nA and storage capacitance of 20fF, the total time for 5V (i.e., a 5V logic level) to "leak" off is

C × V i

20

× 10 -15 ×

5

=

1

× 10 -9

= 100µs

Hence, after approximately 100µs, the 20fF capacitor would be completely discharged to 0V.

A dynamic D-flip flop (falling-edge triggered)

CLK CLK D Q CLK CLK
CLK
CLK
D
Q
CLK
CLK

Really need CLK and CLK to be non-overlapping. If CLK and CLK overlapped, then a race condition could occur because there would be direct path from D to Q, particularly if the overlap period was large.

EE 4253/6253 Lecture Notes

November 6, 1998

page 144

The propagation delay, t pdCI , of the inverter which does the clock inversion = the overtime (t overlap ) in which a race condition could occur.

CLK

CLK

t pdCI
t pdCI

With high frequency clocks, this overlap period can be a problem

CLK CLK master slave D Q t pd CLK CLK V storage
CLK
CLK
master
slave
D
Q
t pd
CLK
CLK
V storage

If t pd < t overlap , then when CLK = 0 1 then CLK = 1 to 0 after t overlap and the V storage value will get set equal to D!!!

We only want V storage to be set equal to D value when CLK = 1 0 (falling edge)

Race condition exists during 1 — 1 overlap condition, D feeds thru to Q

EE 4253/6253 Lecture Notes

November 6, 1998

page 145

A better dynamic latch - C 2 MOS dynamic register

V DD V DD ∅ ∅ D Q ∅ ∅ ∅-section ∅-section
V DD
V DD
D
Q
∅-section
∅-section

Insensitive to overlap (proved later)

Basic operation:

1)

= 1, (= 0)

-section in evaluation mode, -section in hold mode

2)

= 0, (= 1)

roles now reversed, -section in hold mode, -section in evaluation mode

EE 4253/6253 Lecture Notes

November 6, 1998

page 146

Why is the C 2 MOS dynamic register insensitive to overlap?

During overlap, want to make sure that there is no possibility of a race condition in which D feeds directly thru to Q

D

D

V DD V DD 1 1 (1 - 1) overlap V V DD DD 0
V DD
V DD
1
1
(1 - 1) overlap
V
V
DD
DD
0
0

(0 - 0) overlap

Q

Q

No feed thru path exists for either 1 - 1 case or 0 - 0 case.

EE 4253/6253 Lecture Notes

November 6, 1998

page 147

Want to use dynamic latches to form fast pipelined circuits

Consider the datapath for computing log(|a + b|): a ∅ ⋅ log ∅ b REG
Consider the datapath for computing log(|a + b|):
a
log
b
REG
REG
REG

Nonpipelined version

Out

a

b

∅ ⋅ log ∅ ∅ ∅ REG REG REG REG REG
log
REG
REG
REG
REG
REG

Pipelined version

Out

Clock period T min = t clk-out (register) + t pd logic block + t setup register

Minimize t clk-out , t setup

EE 4253/6253 Lecture Notes

November 6, 1998

page 148

Pipelined System with Dynamic Latches

∅ ∅ ∅ In Out F G ∅ ∅ compute F compute G Suffers from
In
Out
F
G
compute F
compute G
Suffers from clock overlap problem
Try C 2 MOS latches
V DD
V DD
V DD
In
Out
F
G

A C 2 MOS-based pipelined circuit is race-free as long as all the logic functions F (implemented with static logic) between the latches are non-inverting! Why?

Use CAD tools to ensure this.

EE 4253/6253 Lecture Notes

November 6, 1998

page 149

Here's a potential race condition during (1-1) overlap in C 2 MOS-based design:

V DD

V DD

during (1-1) overlap in C 2 MOS-based design: V DD V DD V DD ∅ ∅

V DD

(1-1) overlap in C 2 MOS-based design: V DD V DD V DD ∅ ∅ ∅

overlap in C 2 MOS-based design: V DD V DD V DD ∅ ∅ ∅ ∅

overlap in C 2 MOS-based design: V DD V DD V DD ∅ ∅ ∅ ∅
overlap in C 2 MOS-based design: V DD V DD V DD ∅ ∅ ∅ ∅
overlap in C 2 MOS-based design: V DD V DD V DD ∅ ∅ ∅ ∅
overlap in C 2 MOS-based design: V DD V DD V DD ∅ ∅ ∅ ∅
∅

1

C 2 MOS-based design: V DD V DD V DD ∅ ∅ ∅ ∅ 1 The
C 2 MOS-based design: V DD V DD V DD ∅ ∅ ∅ ∅ 1 The
C 2 MOS-based design: V DD V DD V DD ∅ ∅ ∅ ∅ 1 The
C 2 MOS-based design: V DD V DD V DD ∅ ∅ ∅ ∅ 1 The

The above circuit would require sharp clock edges for correct operation.