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Printed Circuit Board Design Techniques for EMC Compliance

Mark I. Montrose

Published under the Sponsorship of the IEEE Electromagnetic Compatibility Society

of the IEEE Electromagnetic Compatibility Society IEEE PRESS The Institute of Electrical and Electronics

IEEE

PRESS

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Printed in the United States of America

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IEEE Order Number: PC5595

ISBN 0-7803-1131-0

Library of Congress Cataloging-in-Publication Data

Montrose, Mark I. Printed circuit board design techniques for EMC compliance / Mark Montrose. p. ISBN 0-7803-1131-0

cm.

To

Margaret,

Maralena, and

Matthew

Contents

Preface

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xi

Acknowledgments

xiii

Chapter 1—Introduction

. EMC and the Printed Circuit Board

Fundamental

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. North American Regulatory Requirements

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Worldwide Regulatory Requirements

 

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Additional North American Regulatory Requirements

 

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Supplemental Information

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.14

Chapter 2—Printed Circuit Board Basics

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Layer Stackup Assignment

 

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.17

Four-layer boards

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Six-layer boards

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.22

Eight-layer

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.24

Ten-layer

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.25

. Grounding Methods

20-H Rule

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.28

Single-point grounding

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.28

Multipoint grounding

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.30

Ground and signal loops (Excluding eddy currents)

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Image planes

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.34

Partitioning

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.38

Logic Families

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.41

viii

Contents

Velocity of Propagation

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.44

Critical Frequencies ( λ /20)

.44

References

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.45

Chapter 3—Bypassing and Decoupling

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.47

Resonance

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.48

Capacitor Physical Characteristics

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Capacitor Value Selection

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Parallel Capacitors

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.56

Power and Ground Plane Capacitance

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.59

Capacitor Lead Length Inductance .

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.60

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Power planes

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.61

Capacitors

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.62

Bulk

capacitors

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.65

References

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.68

Chapter 4—Clock Circuits

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.69

Placement

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.70

Localized Ground Planes

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.71

Impedance Control

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.73

Propagation Delay

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.76

Capacitive Loading

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.80

Trace Lengths

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.81

Impedance Matching—Reflections

 

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Calculating Trace Lengths

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.84

Microstrip

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.86

Loaded Stripline

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.88

Routing layers

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.89

. Layer jumping—use of vias

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.91

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.94

Crosstalk

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.100

Trace Termination

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.102

Calculating Decoupling Capacitor Values

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.108

Components

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.111

Trace Separation and the 3-W Rule

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.112

References

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.115

Chapter 5—Interconnects and I/O

Partitioning

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.117

.118

. Functional subsystems

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.118

. Internal radiated noise coupling

Quiet areas

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.119

.120

Contents

ix

Isolation and Partitioning (Moating)

.121

Method 1: Isolation in moating

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