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DFT Guidelines
www.xjtag.com
enquiries@xjtag.com | +44 (0) 1223 223007
XJTAG | St. John's Innovation Centre
Cowley Road | Cambridge | CB4 0WS | UK
Introduction
The following DFT guidelines are suggestions for improving the testability of circuits using XJTAG. These
guidelines should not be taken as a set of rules. The potential advantages in term of testability should be
considered together with all other implications which they may have (e.g. functionality, device cost and
board area).
It is assumed that readers of this document have some familiarity with IEEE standard 1149.1-1990 and the
1993 and 1994 revisions. Throughout this document the term 1149.1 refers to the IEEE 1149.1 (JTAG)
Boundary Scan standard.
T D ST
TD ST
S
S
O
O
K
K
R
R
I
I
TM
TM
TM
TD
TD
TD
TC
TC
TC
nT
nT
nT
TDI TDO
TCK
TMS
nTRST
100pF
avoid floating inputs (this value may require careful selection taking into account
the driver strength and the strength of any nTRST pull-ups provided in the 1149.1
compliant devices).
TAP
TD ST
TD ST
TD ST
Connector
S
S
O
O
K
K
R
R
I
I
TM
TM
TM
TD
TD
TD
TC
TC
TC
nT
nT
nT
TDI
TCK
TMS
nTRST
TDO
Optional device
TDI TDO
Link
Board
Detect
TDI TDO
Daughter board
connector
TDI TDO
ADDR
DATA
CONTROL
Single JTAG
Flash
compliant device
It can sometimes be advantageous to use short-chain 1149.1 compliant devices (e.g. 1149.1 enabled
buffers) to control circuit nodes which will be toggled frequently (e.g. the nWE pin on flash parts) as shown
in the following diagram. This allows the XJTAG development system to reduce the active chain length and
improve performance when addressing only these nodes. (Future versions of the XJTAG development system
will allow direct I/O access to these nodes which will further improve performance – to utilise this facility
when it becomes available it is recommended that these circuit nodes are made accessible at the test
connector, or at some suitable point in the circuit).
nWE
ADDR
DATA
Flash
Clock
Oscillator Buffer
CLK
ADDR
DATA
CONTROL
Single JTAG
SDRAM
compliant device
Where such testing is not possible design I/O ports so that loopback is possible. This extends testing through
off-board connections and greatly increase test coverage. Simple loopback connectors will suffice for most
interfaces (e.g. Ethernet, RS232, RS485 etc.) but external test circuitry can aid this if necessary and this can
even be controlled by the TAP chain if this is extended through the I/O connector.
ADC DAC
XJIO board
Device 1 Device 2
TDI TDO
Logic
cluster
Non-JTAG compliant
TDI
TDO
Make full use of onboard intelligent devices and advanced XJTAG features
If all else fails and some part of the circuit cannot be made testable using standard 1149.1 features or real-
time testing is required then consider using the advanced facilities of the XJTAG programming language
XJEase to facilitate testing of these parts by making use of on-board intelligent devices. For example a small
program can be loaded into an on-board flash or CPLD device which can enable the CPLD or a
microprocessor to perform additional real-time test and configuration functions.
Glossary