ECE/CS 5720/6720

ECE/CS 5720/6720 – Analog IC Design

Tutorial for Cadence –Layout, DRC, LVS & Layout
Simulation

In this tutorial you’ll build an inverter in two different ways: as a schematic and as
layout. You know how to simulate the inverter using an analog simulator. After you
design and simulate the schematic, you will design layout for an inverter and simulate a
circuit extracted directly from the layout. You will be able to compare the two
simulations and see how they differ. You will also check the layout for design rules, and
check that the layout matches the schematic. Layout consists of the mask designs for
each layer that gets sent to the chip fabrication service.

Schematic:
Draw the Schematic of an Inverter in Virtuoso Schematic Editor and make a
symbol.

Transistor Sizes: (W/L)p = 3.0/0.6 and (W/L)n = 1.5/0.6 (All in microns).

Body of pMOS is connected to Vdd and that of the nMOS is connected to Vss.

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Schematic test bench for the inverter:

Make a new schematic cell “inverter_test” to test the inverter you designed, as
shown below:

Input: voltage pulse of 1MHz (V1 = 0V, V2 = 5V)

Vdd: 5 V Vss: 0 V

Run a transient analysis for 2µs and make sure your output looks okay.

Drawing the layout of a CMOS Inverter.

In this phase of the tutorial you’ll draw the layout for an inverter in the Virtuoso tool.
You’ll check for design rule violations, and check that the extracted layout is the same
circuit as the schematic. You’ll then simulate the circuit extracted from the layout and
compare it with a simulation of the schematic you just drew.

In library manager, click File → New → Cell View. Select the library and the cell in
which you made the inverter schematic. Now, select Tool as Virtuoso. This would also
set your View Name to layout. Click OK.

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This will open two windows; The Virtuoso Editing window where the layout will be
drawn and the LSW (Layer Select Window), where you select the layers (diffusion,
metal1, metal2, polysilicon, etc) to draw.

Note: Before we start with the layout, the display should be set as follows to facilitate
layout for the current design rules. Click on Options → Display, you will see this
window: Set the Minor spacing, Major spacing, X Snap Spacing and Y Snap Spacing as
shown. Click Apply and then OK.

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(a) To draw the layout of a N- type Transistor

1) Click on the active (green) layer in the LSW window. In the Virtuoso Layout Editor
window, press r to activate the Rectangle command. Now you can draw a rectangle by
selecting the start and end points of the rectangle.

Press k to activate the Ruler command. You can click on one of the corners of the green
rectangle to place the ruler and measure the sides (Typing K will clear all rulers).
Remember that our N-transistor in the inverter schematic had a W/L of 1.5µm/0.6µm.
(The width of the diffusion will be usually the same as the width of the transistors but the
length of diffusion region has to account for the source/drain diffusions and the gate
length. A general rule of the thumb is to have the length of the diffusion region to be
3µm + Gate length).

Use the stretch command (by pressing s) and stretch the diffusion layer to be of the size
1.5µm x 3.6µm

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2) Draw contacts (black colored layer cc) of 0.6µm x 0.6µm size to be overlapped by
diffusion by (at least) 0.3µm on the outside edges, as shown below. Also draw Metal 1
layer (blue colored layer metal1) to overlap the contacts by 0.3µm on all sides.

3) Now draw the gate of the transistor by selecting poly (red in color) in the LSW
window. Note that the poly layer should have an overhang of 0.6µm.

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4) Now we have to surround the active region with nselect to make it n-type diffusion.
Select nselect (green outline) in the LSW and wrap it around the active rectangle such
that it extends beyond the active region by 0.6µm as shown below:

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Your NMOS transistor of W/L = 1.5/0.6 microns is done. Note that we have not
connected the body of this device to Vss (the substrate)

(b) To draw the layout of a P-Type Transistor

Draw the P- type transistor (W/L = 3µm/0.6µm) similarly. The only difference (apart
from the sizes) would be to use pselect instead of nselect so that we get p type diffusion.
The other change, or rather addition, would be put this entire device in n-well.

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(5-8) Draw a transistor similar to the N transistor for the increased width of 3µm
following steps 1 to 3. In step 4, use pselect (orange outline) instead of nselect.

9) Now, place n-well around this entire device so that it extends beyond the diffusion by
1.8µm in all directions.

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Now, your PMOS transistor is also ready. Again, we have not yet connected the body of
this device (the n-well) to Vdd.

We are now set to put together these two devices to make an inverter.

10) Select the entire N-transistor and place it exactly below the P transistor such that
there is a gap of at least 1.8µm between the n-well and the diffusion of the N transistor.

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11) Join the gates of the P and the N transistor as well the drains of the two transistors by
stretching the poly and metal1 respectively.

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12) Draw the supply lines for Vdd and Vss using Metal 1, such that the inverter is
sandwiched between the two supply lines. The line below the NMOS will be our Vss and
that above PMOS will be our Vdd. They are made wide to avoid electro-migration issues

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and ohmic voltage drops. I made them 4.8µm wide. Make sure that the metal1 strips, one
connecting the drains and other carrying the supply voltage, are at least 0.9µm away.

13) Now, connect the sources of the two transistors to Vdd and Vss respectively. Also
create a contact on the common gate, which is out input by placing a layer of metal1, cc
and poly as shown in the figure. Metal1 and poly should surround the contact by 0.3µm.

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14) Now label the different nodes on our layout that matches those on your schematic.
To do this, click on Create → Pin..

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You get the following window:

Enter the Terminal Name, Select Display Pin Name, Select I/O type and Pin type. The
nodes for the inverter would be in, vss, vdd (input pins) and out (output pin).

Note: a) For this layout, all the pins are of metal1 type.

b) Use the same node names as used in your schematic for the inverter

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Your layout now looks like this:

We are to connect the bodies of the two transistors now (i.e. for the NMOS, connect the
substrate to Vss and for the PMOS, connect the n-well to Vdd)

15) Body contact for NMOS:

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We need to put a P-type diffusion in the substrate and tie this to ground.

P type diffusion (active surrounded by pselect) with a contact is shown below. It consists
of an active (1.2µm x 1.2µm), surrounded by pselect and a contact of 0.6µm x 0.6µm in
the middle. The contact has to be surrounded by metal1. This metal1 has to be tied to
the Vss line.

16) Next, we need to tie the body of the PMOS transistor to Vdd.

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A PMOS body contact looks similar, just that it is n-type diffusion(active surrounded by
nselect) inside the n-well. This is shown in the figure below: The metal1 here is tied to
Vdd. The n-well has to surround the active by 1.8µm.

17) You have made it!

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The layout of the inverter is now complete. All dimensions used in this example have
been taken from the Design rules file posted on the class web site. Your final layout
may look like this:

Before proceeding to the next step, save the layout. It might be a good exercise to trace
the different nodes and make sure it is exactly identical to the inverter on your schematic.
Anyway, we will ask Cadence to do this check for us at a later stage.

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Design Rules Check

Next check whether any of the design rules have been violated. In the Virtuoso Layout
Editor Window, choose Verify → DRC… A new window pops up as shown below.

In the Rules file field, notice divaDRC.rul is entered and also that the Rules Library is
checked. It should say: UofU_TechLib_ami06. Click OK to start the Design Rule
Check. Check the CIW window for any errors. If you have followed the design rules
correctly, you should get ‘0 errors’ in the CIW window. If some errors manage to creep
into your layout, the erroneous parts will blink. You can find out the details of the errors
you made by selecting Verify → Markers → Find. In the new window, click the button
corresponding to Zoom To Markers. By pressing the Next button, you can go through
all the error markers and their descriptions. Once you find out the errors in your layout,
delete all markers by choosing Verify → Markers → Delete All…. Now you can easily
edit your layout and correct all your errors. You must do this repeatedly until you have
no errors in your layout.

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Extracting the Layout

Extract your layout by choosing Verify → Extract. In the new Extractor window notice
that the rules file divaEXT.rul and the rules library is checked. Press Ok to extract your
layout. Another view (like schematic, layout, and symbol) of the cell inverter by the
name extracted is created. You can verify this in the Library Manager.

Layout Versus Schematic Check

Finally we compare our layout with the schematic that we made earlier to see if they are
both the same. To do this, choose Verify → LVS… in your Virtuoso Layout Editor
Window. Check that the correct cells and views have been selected.

Click the Run button to run LVS. A window should pop up and tell you that the netlists
matched. (This might take a minute… be patient.)

If the window says failed instead of succeeded, the LVS window may be incorrectly
filled in. It may also fail if some schematics or layouts haven’t been updated, so make
sure everything has been saved and checked. If you still have problems, check the log

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file for hints. It is called “si.log” and is found in the LVS directory (ex:
IC_CAD\cadence\LVS\si.log)

Note that even if it says it succeeded, that doesn’t mean the circuits match. It only means
that the process completed! In order to see if the circuits match you need to check the
output of LVS. Check the output of the LVS, by clicking the Output button in the LVS
Window. A new window containing some text should pop up. If you have done your
layout right, the text file should read "The netlists match". If they don’t match you can
tell from the text what the problems were. If you didn’t use exactly the same names for
the input and output in the schematic and in the layout, for example, it will tell you that
the circuits matched, but the names didn’t.

Check the class web page for a sample LVS output file.

For performing Post layout simulation, an analog_extracted view for the inverter is
required. This view can be created by pressing the Build Analog button in the LVS
window. Click OK in the next window.

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Post Layout Simulation of a CMOS inverter.

Make sure you have the analog_extracted view for your inverter. The last few sentences
preceding this explained how to get an analog_extracted view.

In the previous schematic simulation, a testbench schematic for the inverter called
inverter_test was created. This testbench can also be used for the post-layout
simulation. To do this, a config view of inverter_test should be created. In the config
view, it is possible to select simulation models for different instances in the top-level
schematic. But before creating a config view, we need to make a small modification in
the schematic.

Open the inverter_test schematic from the Library Manager. Copy the inverter symbol
and connect the copied instance to a new output called out_layout. The reason for
having two inverters in the schematic is to compare the output of the "schematic inverter"
and that of a "layout inverter". There are some parasitics extracted from the layout,
which was not accounted for when we simulated the schematic.

Check and save the schematic.

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In Library Manager, choose File → New → Cell View

Choose the view name to be config. The tool Hierarchy-Editor should be

automatically selected in the Tool pull-down menu.

Two windows open up. In the one titled New Configuration, click Use Template and
choose spectreS in the new window and click OK. Replace myView with schematic
and click OK in the New Configuration window.

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In the Hierarchy Editor window, information about the different instances in the
inverter_test schematic view can now be seen. Select View → Tree in Hierarchy editor
window. You can see that two inverters each having a unique instance number is found.
In the design above the instance numbers for the inverters are I0 and I1.

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Now the simulation model for the inverter connected to the output out_layout should be
changed to analog_extracted. Remember the analog_extracted view was created after
performing the LVS of the layout.

To change the simulation model (in this case for inverter I1), right click on the instance in
the config view and choose: Set Instance View → analog_extracted. The simulation
model for the other inverter does not have to be changed since the default simulation
view is schematic.

Save the configuration by clicking View → Update and then File → Save.

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From the schematic view, open Analog Circuit Design Environment. Note that Analog
Environment does not automatically use the settings made in the config view.
Choose Setup → Design in the Analog Environment window and change the view from
schematic to config for the inverter_test simulation and press OK

If the question whether to save the current state pops up, click NO. The simulation is
now performed in the same way as the previous schematic simulation. Choose both the
outputs out_schematic and out_layout to be plotted.

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From the simulation above, it can be seen that the inverter layout seems to be working
properly. To view the difference between the schematic simulation model and the
analog_extracted simulation model, first drag and drop one of the output waveforms over
the other.
Now if you zoom in to one of the edges of the output waveform, you can see that the
layout produces a slightly slower inverter than that of the schematic simulation. Anyway,
there are not much different.

That winds up this tutorial. You have gotten started with layout, DRC, LVS and Analog
extraction of the layout. It may look confusing for students doing this stuff for the first
time, but you will realize it will become easy after some practice.

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