(NXP) .1-Day Hands-On Arm Training

ARM7 Microcontrollers
1-day Hands-On ARM Training

–Alexander Bashlykov
–Field Application Engineer
11/15/08
1
Agenda
– General Introduction
– Introduction to the ARM7 architecture
– NXP LPC2000 ARM Implementation and Tools
– Lunch break
– Verification of Setup, Introduction to Tools
– MAM, PLL, GP I/O
– PWM, ADC
– Serial Interfaces, SPI, I2C, UART
– USB Interface
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CONFIDENTIAL 2
Subject/Department, Author, MMMM dd, yyyy
Keil Software
an ARM Company
Compiler
– For Philips LPC900
– For Philips LPC2000
Debugger
– Simulator
– JTAG Debugger
Evaluation Boards
– For NXP LPC900
– For NXP LPC2000
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15.11.08 http://www.embeddedartists.com
CONFIDENTIAL 3
ETU NXP lab
Training Class and Consulting Services
Turnkey software&hardware development
Modern equipment
Various cores & architectures
Customer support
Operating systems porting
– Linux
– eCOS
– freeRTOS
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15.11.08 Web site coming soon ://
CONFIDENTIAL 4
Insider’s Guide Book:
How to start with LPC2000 family:
Published by Dodeca
Current Price:
– 230 Rub.
With CD-ROM
Includes USB block description and
programming manual.
11/15/08
15.11.08 http://www.book.dodeca.ru/books/.php
CONFIDENTIAL 5
Микроконтроллеры ARM7. Семейство LPC2000.
Руководство пользователя.
Published by Dodeca
Current Price:
– 420 Rub.
Contains CD-ROM
Full technical description of LPC2000
family
11/15/08
15.11.08 http://www.book.dodeca.ru/books/33044.php
CONFIDENTIAL 6
1. ARM - The Company
2. Architecture
3. Instruction Set
4. ARM7TDMI-S
5. NXP Implementation
6. Tools
7. ARM9 / LPC3000
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CONFIDENTIAL 7
ARM Holdings plc. (1)
Established as Advanced RISC Machines Ltd. in 1990 as a UK

based joint venture between Apple Computer, Acorn Computer Group
(computer manufacturer in the eighties) and VLSI Technology*
– Apple and VLSI provided funding
– Acorn supplied technology and first 12 engineers
Introduction of ARM6™ family in 1991, VLSI initial licensee

In April 1998 listed on the London Stock Exchange and Nasdaq
*: part of NXP since 1999

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CONFIDENTIAL 8
ARM Holdings plc. (2)
Develops the ARM range of RISC processor cores

Licenses its RISC microprocessor core and SoC IP to a network of
partners; semiconductor and system companies
ARM does not manufacture silicon itself
Also licenses architectural extensions, development tools, peripheral IP
and SoC solutions
ARM’s market share of the embedded RISC microprocessor market is
approx. 75% and to date, ARM Partners have shipped more than one
billion ARM core-based microprocessors
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CONFIDENTIAL 9
NXP is a leader in ARM
NXP relationship with ARM Ltd. spans a decade

– One of three founding partners of ARM
NXP offers the most ARM experience

– Over 500 ARM designs - more than anyone else in the industry
– In Top 3 for ARM shipments worldwide
– More than a dozen ARM cores in over 7 CMOS processes
NXP is a long-term ARM licensee

– Extensive license relationship provides continuous access to all architectures
– Announcing off-the-shelf ARM microcontrollers with embedded Flash
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CONFIDENTIAL 10
2. Architecture
3. Instruction Set
4. ARM7TDMI-S
6. Tools
7. ARM9 / LPC3000
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CONFIDENTIAL 11
Bus Width
Address Bus
ARM7TDMI is a 32-bit architecture
– Data pathes and ARM instructions Address Register Incr.
are 32 bits wide

Instruction
Decode &
– Von Neumann architecture Registers General
Control
• instructions and data use the Mult.

Thumb
same 32-bit data bus Decom-
Shifter pression
– There is a subset of 16-bit

instructions (Thumb) optimized for ALU
code density Data Out Data In
Data Bus
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CONFIDENTIAL 12
Thumb Mode
Set of instructions re-coded from 32 into 16 bits

– Improved code density by ~ 30%
– Saving program memory space
– Higher performance (up to 60%) when running from 16-bit wide external
memory
In Thumb state only the program code is 16-bit wide

– After fetching the 16-bit instructions from memory, they are de-
compressed to 32 bit instructions before they are decoded and executed
– All operations are still 32-bit operations
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CONFIDENTIAL 13
Thumb Code Size Comparison
Code size Benchmark
V850 V850
145.8
68K
68K
227.8
80C51 80C51
223
C167
C167
183.5
ARM ARM
121.1
AVR AVR
212
Z80 Z80 184.7
Mitsu16
Mitsu16
147.5
ST20
ST20
127.3
M-CORE
M-CORE
123.9
68HC12
68HC12
150.2
MIPS32
MIPS32
146.5
MSP430
MSP430
207.4
X86
X86
125.1
H8S
H8S
149.2
Thumb
Thumb
100
SH
SH
129.3
0 50 100 150 200 250

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40 kbyte “application like” code
CONFIDENTIAL 14
CMX-CANopen Code Size Comparison
(tested 7-Feb-05, with highest optimization level, all sizes in bytes)
Keil 166 compiler

Keil ARM compiler Infineon C167CR Keil 8051 compiler
Philips LPC2129 Philips P8xC591
Code: 11025
Code: 8512 Const: 526 Code: 10654
Const: 776 Data: 503 Const: 344
Data: 503 Stack: 512 (system) Data: 525

– includes “overlay”
Stack: 512 Stack: 512 (user)
Stack: 128
Other: 512
– CAN Rx buffer
CAN Rx ISR CAN Rx ISR

5 - 6 us Note: 250 - 300 us
These chips use very different CAN interfaces,
resulting in very different code on the driver level
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CONFIDENTIAL 15
Data Types and Alignment
Definitions:
– Word = 32 bits (four bytes) = UNSIGNED32
– Halfword = 16 bits (two bytes) = UNSIGNED16
– Byte = 8 bits = UNSIGNED8
1 2 3 4 1 2 3 4
Byte Byte Byte Byte Byte Byte Byte Byte
Halfword Halfword Halfword Halfword
Word Word
Halfword Halfword
Word Word
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CONFIDENTIAL 16
Processor Modes
ARM has seven operating modes

– User unprivileged mode under which most applications run
– FIQ entered, when a high priority (fast) interrupt is raised
– IRQ general purpose interrupt handling
– Supervisor protected mode for the operating system
entered on reset or software interrupt instruction
– System privileged mode using the same registers as user mode

– Abort used to handle memory access violations
– Undefined used to handle undefined instructions
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CONFIDENTIAL 17
Registers (1)
An ARM core has 37 registers (32-bit)
General purpose registers
– 1 program counter
– 30 general purpose registers
Status registers
– 1 current program status register
– 5 saved program status registers
These registers are not all accessible at the same time. The processor state and
operating mode determine which registers are available to the programmer.
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CONFIDENTIAL 18
Registers (2)
Depending on processor mode one of several banks is accessible. Each

mode can access
– the program counter r15 (PC)
– a particular r13 (stack pointer SP)
– a particular r14 (subroutine link register, LR)
– a particular set of r0-r12 registers
– the current program status register (CPSR)
Privileged modes (except System mode) can also access

– a particular SPSR (saved program status register)
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CONFIDENTIAL 19
User and System Register Banking
r0
r1
r2
r3
Used by
r4
Banked registers Software
r5 Interrupt
r6 FIQ IRQ Supervisor Abort Undefined
r7
r8 r8_fiq
r9 r9_fiq
r10 r10_fiq
r11 r11_fiq
r12 r12_fiq
r13 (SP) r13_fiq (SP) r13_irq (SP) r13_svc (SP) r13_abt (SP) r13_und (SP)
r14 (LR) r14_fiq (LR) r14_irq (LR) r14_svc (LR) r14_abt (LR) r14_und (LR)
r15 (PC)
CPSR
SPSR_fiq SPSR_irq SPSR_svc SPSR_abt SPSR_und
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CONFIDENTIAL 20
Registers in Thumb Mode
The Thumb state register set is a subset of the ARM state set. The
programmer has direct access to:
– eight general registers r0 - r7
– the program counter PC
– a Stack pointer SP
– a Link register LR
– the current program status register CPSR
In Thumb state, the high registers (r8 - r12) are not part of the standard
register set. The assembly language programmer has limited access to
them, but can use them for fast temporary storage
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CONFIDENTIAL 21
Thumb vs. ARM
r0 r0
r1 r1
r2 r2
Thumb state r3 r3
Low registers r4 r4
r5 r5
r6 r6
r7 r7
r8
Thumb ARM
r9
Mode Mode r10

Thumb state r11
High registers r12

r13 (SP) r13 (SP)
r14 (LR) r14 (LR)
r15 (PC) r15 (PC)
CPSR CPSR
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CONFIDENTIAL 22
Program Status Register (1)
31 30 29 28 27 24 23 16 15 8 7 6 5 4 0
N Z C V Q J I F T mode
Condition Reserved Control bits

code flags
Condition Code Flags

– N: Negative or less than
– Z: Zero
– C: Carry or borrow or extend
– V: Overflow
To not change reserved bits.
A read-modify-write strategy should be applied to change PSR bits.
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CONFIDENTIAL 23
Program Status Register (2)
31 30 29 28 27 24 23 16 15 8 7 6 5 4 0
N Z C V Q J I F T mode
Condition Reserved Control bits

code flags
Interrupt Disable Bits Mode Bits

– I: IRQ interrupts disable 10000 User
– F: FIQ interrupts disable 10001 FIQ
10010 IRQ
T Bit
10011 Supervisor
– Thumb mode (when set)
10111 Abort
– ARM mode (when cleared) 11011 Undefined
11111 System
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CONFIDENTIAL 24
Exception / Interrupt Handling
Entering an exception the ARM core

– saves the address of the next instruction in the appropriate LR
PC + 4 or PC + 8
r15 (PC) r14_<mode> (LR)
– copies the CPSR into the appropriate SPSR
CPSR SPSR_<mode>
– sets appropriate CPSR bits
• interrupt disable bits
• mode field bits 8 7 6 5 4 0
mode
CPSR: I F T
• if running in Thumb mode, enter ARM mode*
– forces PC to fetch next instruction from relevant exception vector

Control bits
*: all exceptions are handled in ARM mode!
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CONFIDENTIAL 25
Exception Vectors
Vector Table
.
.
.
0x1C FIQ
0x18 IRQ Each entry is a
branch instruction
0x14 (Reserved) with ‘always’
condition
0x10 Data Abort
0x0C Prefetch Abort
0x08 Software Interrupt
0x04 Undefined Instruction
0x00 Reset
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CONFIDENTIAL 26
Leaving Exception
To leave an exception, the exception handler must
– copy SPSR back into CPSR
SPSR_<mode> CPSR
(automatically restoring also I, F and T)

8 7 6 5 4 0
mode
CPSR: I F T
Control bits
– move contents of current LR minus offset* to PC
PC - offset
r14_<mode> (LR) r15 (PC)
*: varies according to type of exception: 2, 4 or 8
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CONFIDENTIAL 27
Multiple Exceptions
Exception priorities
– When multiple exceptions arise at the same time, a fixed priority sytem
determines the order in which they are handled
1. Reset highest priority

2. Data Abort (data memory access cannot be completed)
3. FIQ
4. IRQ
5. Prefetch Abort (instruction memory access cannot be completed)
6. Undefined Instruction
7. SWI - Software Interrupt (to enter supervisor mode) lowest priority
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CONFIDENTIAL 28
2. Architecture
3. Instruction Set
4. ARM7TDMI-S
6. Tools
7. ARM9 / LPC3000
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CONFIDENTIAL 29
Instruction Set
All instructions are 32-bits long

Many instructions execute in a single cycle
Instructions are conditionally executed
ARM is a load / store architecture
– Most operations are executed on registers
– Typical for RISC
Load or store multiple registers in a single instruction

using <register list>
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CONFIDENTIAL 30
Conditional Execution
Mnemonic Description
EQ Equal
NE Not equal
CS / HS Carry Set / Unsigned higher or same
CC / LO Carry Clear / Unsigned lower
MI Negative
PL Positive or zero
VS Overflow
VC No overflow
HI Unsigned higher
LS Unsigned lower or same
GE Signed greater than or equal
4 bits in the operand of LT Signed less than

each instruction are used GT Signed greater than
for the condition code LE Signed less than or equal
AL Always (normally omitted)
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CONFIDENTIAL 31
Advantages of conditional executions
Implementation with conditional Implementation with conditional

branch instructions
– Compare – Compare
– If condition is not true, branch to
• Conditional execute
else “if true”
• Execute “if true” • Conditional execute
• Jump to End “if not true”
– End:
– Else:
• Execute
“if not true”
– End:
No jumps or branches required,

better for pipelined execution
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CONFIDENTIAL 32
ARM “C” and assembly code comparison:
“C” code:
if ((c==1) && (z==0)) R1=R2+(R3*8);
Assembly code:
HIADDS R1, R2, R3, LSL,#3
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CONFIDENTIAL 33
Addressing Modes
In comparison to other chip architectures,

only a limited number of addressing modes are provided
– Register Addressing
– Indirect with Register (offset, increment)
– Indirect with 2 Register (base, index)
• PC can be base register
Direct addressing is not supported
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CONFIDENTIAL 34
Thumb Instruction Subset
Subset of most commonly used 32-bit ARM instructions

– 2 address format: destination register same as one source registers
Compressed into 16-bit wide code

– Improved code density
Decompressed on execution to full 32-bit instructions

– transparently
– in real-time
– no performance loss
ARM code can be combined with Thumb code for maximum flexibility
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CONFIDENTIAL 35
Thumb Instructions
ARM instruction set Thumb instruction set

31 0 15 0
Recoding
ARM instruction Thumb instruction
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CONFIDENTIAL 36
Thumb Instruction Set (1)
Instruction Types
– Branch
• Unconditional ± 2KBytes
• Conditional ± 256Bytes
• Branch with Link ± 4MBytes (2 Instructions!)
• Branch and exchange change to ARM state if Rm[0] = 0
• Branch and exchange with Link
– Data Processing
• Subset of ARM data processing instructions
• Not conditionally executed (but some update flags)
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CONFIDENTIAL 37
Thumb Instruction Set (2)
Instruction Types
– Load and Store
• Register plus 5-bit immediate addressing
• Register plus Register addressing
– Load and Store Multiple

• Load / Store list of registers
• Push / Pop (ARM equivalent: STMDB SP!, <registers>)
– Exception Generating Instructions
• SWI (switch to ARM mode and privileged mode)
• Breakpoint (prefetch abort, with debug monitor)
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CONFIDENTIAL 38
Translation of Thumb Instruction
Example: ADD Rd, # Constant

Thumb code
15 0
001 10 Rd 8-bit immediate
Major op-code
Minor op-code
denoting format 3 Destination and Immediate
denoting ADD
move/compare/add/sub/ source register value
instruction
with immediate value
31
1110 00 1 0100 1 0 Rd 0 Rd 0000 8-bit immediate 0
Always condition code ARM code

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CONFIDENTIAL 39
Program Counter (r15)
When the processor is executing in ARM mode

– all instructions are 32 bits wide
– all instructions must be word aligned
– bits [31:2] contain the PC, bits [1:0] are zero
(instructions cannot be halfword or byte aligned)
When the processor is executing in Thumb mode

– all instructions are 16 bits wide
– all instructions must be halfword aligned
– bits [31:1] contain the PC, bit [0] is zero
(instructions cannot be byte aligned)
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CONFIDENTIAL 40
ARM and Thumb Interworking
Switch between ARM mode and Thumb mode using BX instruction
– In ARM state: BX<condition> Rn
– In Thumb state: BX Rn
31 1 0
Rn
n: 0-15
ARM / Thumb
BX selection
0: ARM state
31 1 0 1: Thumb state
Destination
address 0
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CONFIDENTIAL 41
So what is better:
Thumb or ARM Mode?
Average code size reduction in Thumb mode: 30%

– Thumb code size shrinks to 70%
After ‘decompression’, code size doubles

– The ‘total’ code size for CPU to execute is 140%
Therefore ARM mode provides better performance as in total less code

gets executed
– Unless bus system slows down performance…
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CONFIDENTIAL 42
2. Architecture
3. Instruction Set
4. ARM7TDMI-S
6. Tools
7. ARM9 / LPC3000
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CONFIDENTIAL 43
ARM7TDMI-S
The ARM7TDMI-S is based on ARM7 core

– 3 stage pipeline
– Von Neumann architecture
– CPI ~1.9
– T: Thumb instruction set
– D: includes debug extensions
– M: enhanced multiplier (32x8) with instructions for 64-bit results
– I: core has EmbeddedICE logic extensions
– S: fully synthesisable (soft IP)
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CONFIDENTIAL 44
Instruction Pipeline
The ARM7TDMI-S core uses a pipeline to increase the speed of the

flow of instructions to the processor. This enables several operations to
take place simultaneously
The Program Counter (PC) points to
the instruction being fetched
rather than to the instruction being executed
During normal operation
- one instruction is being executed,
- its successor is being decoded,
- and a third is being fetched from memory
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CONFIDENTIAL 45
3-Stage Instruction Pipeline
ARM Thumb
PC PC Fetch Instruction Fetched from Memory
Thumb only: Thumb instruction

decompressed to ARM instruction
PC - 4 PC - 2 Decode
Instruction decoded
Registers read from Register Bank,

Execute Shift and ALU operations performed,
PC - 8 PC - 4 Registers written back to Register
Bank
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CONFIDENTIAL 46
Optimal Pipelining
– In this example it takes 6 clock cycles to execute 6 instructions
– All operations are on registers (single cycle instructions)
– Clock cycles per instruction (CPI) = 1
ADD Fetch Decode Execute

SUB Fetch Decode Execute
MOV Fetch Decode Execute
AND Fetch Decode Execute
ORR Fetch Decode Execute
EOR Fetch Decode Execute
CMP Fetch Decode
RSB Fetch
1 2 3 4 5 6 7 8
Cycle
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CONFIDENTIAL 47
LDR Pipeline Example
– In this example it takes 6 clock cycles to execute 4 instructions
– Clock cycles per instruction (CPI) = 1.5
ADD Fetch Decode Execute

SUB Fetch Decode Execute
LDR Fetch Decode Execute Data Write
MOV Fetch Decode Execute
AND Fetch Decode
ORR Fetch
1 2 3 4 5 6 7 8
Cycle
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CONFIDENTIAL 48
Branch Pipeline Example
– Branches break the pipeline
– Example in ARM state
BL 0x8000 Fetch Decode Execute Linkret Adjust

X 0x8004 Fetch Decode
X 0x8008 Fetch
ADD 0x8FEC Fetch Decode Execute
SUB 0x8FF0 Fetch Decode Execute
MOV 0x8FF4 Fetch Decode
AND 0x8FF8 Fetch
1 2 3 4 5 6 7
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CONFIDENTIAL 49
Example ARM Bus System
RAM ARM core

16 bit wide
Interrupt Peripherals I/O

Controller
ROM
8 bit wide RAM
32 bit wide
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CONFIDENTIAL 50
AMBA
Advanced Microcontroller Bus Architecture

– on-chip interconnect
– established, open specification
– framework for SoC designs
– enabler for IP reuse
– ‘digital glue’ that binds IP cores together
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CONFIDENTIAL 51
AHB and APB / VPB
Advanced High-Performance Bus

– high-performance
– pipelined
– fully-synchronous backbone
– multiple bus masters
Advanced Peripheral Bus / VLSI Peripheral Bus

– low-power
– non-pipelined
– simple interface
– wait support (VPB)
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CONFIDENTIAL 52
Example AMBA System
ARM core
Keypad
UART
High-
bandwidth APB
Memory AHB APB Timer
Bridge
Interface
Display
RTC
High-bandwidth DMA
on-chip RAM Bus Master
I/O
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CONFIDENTIAL 53
Default Usage of Bit Addressable Registers
In ARM7 implementations, bit addressable registers are typically

divided into two registers
– One used for setting bits
• Writing ‘1’ sets a bit, ‘0’ has no effect
– One used for clearing bits
• Writing ‘1’ clears a bit, ‘0’ has no effect
Benefit
– Unused bits are never written to
Drawback
– No atomic bit clear and set at the same time
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CONFIDENTIAL 54
2. Architecture
3. Instruction Set
4. ARM7TDMI-S
6. Tools
7. ARM9 / LPC3000
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CONFIDENTIAL 55
The different cores
Core Main differentiator Applications

ARM720T, BlueStreak LCD controller, MMU Larger applications with OS and
LCD
ARM7TDMI-S, BlueStreak LCD controller, 80MHz LCD controllers, external
memory
ARM7TDMI-S, LPC2000 LPC2000 family approach, portfolio Industrial, consumer,

communications general purpose
ARM968E-S, LPC2900 Lin interfaces, 80MHz - 90MIPS Industrial, motor control
ARM922T, BlueStreak 266MHz, 16-bit color LCD controller, Industrial, LCD display, hi-end
MMU, touch screen
ARM926EJ-S, LPC3000 208MHz, VFP co-processor, Low power hi-end applications,
Ultra low power options calculation
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CONFIDENTIAL 56
NXP LPC Continuum
LPC1000 LPC2000 LPC2900 LPC3000
EJ- S
NXP’s Cortex M3 based
92 6
LPC1000 range will be M
introduced 2H 2008 AR
Performance, speed, processing power
E -S
M 968 >200 MHz
AR 32KB D-cache, 32KB I-Cache
Up to 256KB RAM
I-S
ARM7TDM 80-100 MHz Vector Floating Point
t ex- M 3
ARM Cor 768 KB Flash Java co-processor
60-72 MHz 80KB RAM MMU
0 to 1MB Flash TCM 3V/1.8V
60-72 MHz
100 KB RAM CAN Low Power 0.9V mode
0-256 KB Flash
LCD controller LIN LCD controller
58 KB RAM
LCD interface PMU Ethernet 10/100
Low power
Ethernet ADCs USB Host/OTG
Ethernet
USB Dev/Host/OTG PWM I2S
USB Device
CAN CAN
I2S I2S
ADC / DAC
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CONFIDENTIAL 57
NXP Embedded Flash Process Roadmap
Mature product line
low-cost, 3-5V OTP
5V Flash family
Foundry Embedded
LPC900 Family Flash
3V Flash (in development)
ICN8 / ICF / ASMC NXP C90NV /
LPC2000 Family
TSMC eFlash
ARM7S-TDMI-STM TSMC10/12
1.8V Flash
ICN8 / SSMC
LPC3000 Family
ARM926EJTM CMOS65LP
CMOS90LP TSMC10/12
TSMC10/12
0.5μ 0.4μ 0.35μ 0.18μ 0.16μ 0.14μ 90n 65n 45n
Process Feature Size

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CONFIDENTIAL 58
ARM7-based 32-bit Microcontrollers (1)
Shared system architecture
– 32-bit ARM cores
– E-ICE RTM™ to support real-time debugging
– ETM™ to perform real-time tracing of the code being executed
– Vectored Interrupt Controller (ARM Prime Cell®)
All derivatives share

– high-bandwidth 128-bit Flash and on-chip programming interface
– memory map and interrupt structure
– ARM PrimeCell and NXP peripheral IP
– low-cost, high-volume production packages
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CONFIDENTIAL 59
0.18 µm process technology
– Dual supply voltages for lowest power and easy interfacing
• Core (incl. Flash Memory): 1.8V I/Os: 3.3V
– Single supply voltage on LPC213x and LPC214x
– Advanced power management on LPC23xx/LPC24xx and LPC288x (on 0,14
µm)
– Embedded Flash
• In-application programmable
• 2 transistor cell (0.78µm²), also easy implementation of on-chip E²PROM
– improved reliability; further enhanced by error correction
• on-chip charge pumps for programming/erasing

– down to 1.5V (reading down to 1.2V) Spec: 1.8V ± 0.15V !
• Memory Accelerator Module

11/15/08–
15.11.08 enables fast ARM core to operate from slower Flash without speed penalty
CONFIDENTIAL 60
Big pool of peripherals to select from for derivatives

– NXP, ARM PrimeCell™ and 3rd-party IP
– Serial / Communication Interfaces
• UARTs, I2C, SPI, CAN, Ethernet, USB, USB Host, HS USB, SD/MMC
– Timers
• General purpose, watchdog, Capture / Compare, PWM, RTC ...
– ADC, DAC ...
Comprehensive 3rd-party development tools

– ARM, Ashling, Green Hills, Hitex, Nohau, Keil, IAR, Embedded Artists
… plus many others
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CONFIDENTIAL 61
Portfolio
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CONFIDENTIAL 62
First Generation LPC2000 Family (1)
Some common features

– ARM7TDMI-S core with E-ICE RTM™ / ETM™
– Operation up to 60MHz
– 32-bit timers
• 2 (4 capture and 4 compare channels each)
• PWM (6 outputs)
• RTC
• Watchdog
– 2 UARTs (16C550)
– I²C (400kb/s)
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CONFIDENTIAL 63
First Generation LPC2000 Family (2)
Part Pins Flash RAM Ext. I/O A/D SPI CAN
LPC2104 48 128K 16K - 32 - 1 -
LPC2105 48 128K 32K - 32 - 1 -
LPC2106 48 128K 64K - 32 - 1 -
LPC2109 64 64K 8K - 46 4 channels 10-bit 1
LPC2114 64 128K 16K - 46 4 channels 10-bit 2 -
LPC2119 64 128K 16K - 46 4 channels 10-bit 2 2
LPC2124 64 256K 16K - 46 4 channels 10-bit 2 -
LPC2210 144 - 16K x 76 8 channels 10-bit 2 -
LPC2212 144 128K 16K x 112 8 channels 10-bit 2 -
LPC2214 144 256K 16K x 112 8 channels 10-bit 2 -
LPC2290 144 - 16K x 76 8 channels 10-bit 2 2
LPC2292 144 256K 16K x 112 8 channels 10-bit 2 2
11/15/08
15.11.08
LPC2294 144 256K 16K x 112 8 channels 10-bit 2 4
CONFIDENTIAL 64
Second Generation LPC2000 Family (1)
LPC210x, LPC213x, LPC214x
60/70 MHz Operation from both on-chip 3.3V Single-Voltage Supply

Flash and SRAM 32KHz RTC with Vbat input
2 I C, 2 UARTs, 1 SPI,
2
Brown Out Detect,
1 SPI/ SSP Power On Reset
USB (LPC214x only) Enhanced user-code security
6/8/14/16-channels10-bit ADCs Tiny Packages:
10-bit DAC – LQFP64 (10 x 10 x 1.4 mm)
4 Timers (Capture/Match/PWM/WDT) – HVQFN64 (9 x 9 x 0.85 mm)
32/45 I/O pins (5V tolerant) – LQFP48 (7 x 7 x 1.4 mm)
– 3.5 times faster than older I/O!
11/15/08
15.11.08
CONFIDENTIAL 65
Second Generation LPC2000 Family (2)
Part Pins Flash RAM I/O A/D DAC USB
LPC2101 48 8K 2K 32 8 channels 10-bit - -
LPC2132 64 64K 16K 47 8 channels 10-bit 1 -
LPC2141 64 32K 8K 45 6 channels 10-bit - 1
LPC2142 64 64K 16K 45 6 channels 10-bit 1 1
LPC2144 64 128K 16K 45 14 channels 10-bit 1 1
LPC2146 64 256K 32k+8K 45 14 channels 10-bit 1 1
LPC2148 64 512K 32k+8K 45 14 channels 10-bit 1 1
11/15/08
15.11.08
CONFIDENTIAL 66
Third generation LPC2000 family
11/15/08
15.11.08
CONFIDENTIAL 67
Part Pins Flash RAM I/O A/D Ethernet USB
LPC2364 100 128K 34K 70 No ext, DMA 1 1
LPC2366 100 256K 58K 70 No ext, DMA 1 1
LPC2368 100 512K 58K 70 No ext, DMA 1 1
LPC2378 144 512K 58K 104 Minibus 8bit, DMA 1 1
LPC2458 180 512K 98K 160 Ext. Bus 16bit, DAM 1 Host, OTG
LPC2468 208 512K 98K 160 Ext. Bus 32bit, DMA 1 Host, OTG
LPC2478 208 512K 96K 45 LCD Controller, 32bit ext, CAN 1 Host, OTG
LPC2880 180 0K 64K 85 16 bit ADC - HS
LPC2888 180 1024K 64K 85 16 bit ADC - HS
11/15/08
15.11.08
CONFIDENTIAL 68
11/15/08
15.11.08
CONFIDENTIAL 69
LPC247x Color LCD Controller
Based on the ARM PrimeCell® PL111

Single and dual panel Super Twisted Nematic (STN)
monochrome displays with 4 or 8 bit interfaces.
Single and dual panel STN color displays.
Thin Film Transistor (TFT) color displays.
Resolution up to 1024x768
15 level grey-scale, 3375 color STN and 32K color TFT display modes.
1, 2 or 4 bits-per-pixel (bpp) monochrome palettes for STN displays.
1, 2, 4 or 8bpp color palettes for STN and TFT displays.
16 bpp direct true-color for STN and TFT displays.
24 bpp direct true-color for TFT displays.
Hardware Cursor support for single panel displays.
Resistive Touchscreen capability by using internal ADC with port pins or
external switches
http://www.standardics.nxp.com/products/lpc2000/lpc24xx/
11/15/08
15.11.08
CONFIDENTIAL 70
LCD controller performance
The LCD controller is connected to the AHB1 bus, so it processes Frame data
independently of the Ethernet (AHB2 bus) and Flash (Local bus)
Example bandwidth calculations
– For 320 x 240 display: 76,800 pixels per frame ((x-bits x 76,800)/8 = # bytes/frame)
– 4-bits per pixel: 38.4 Kbytes per frame
LCD refresh rate is 70 Hz = 14.3 ms per frame.
For 16-bits/pixel - 153.6 Kbytes/ 14.28 ms = 10.76 Mbytes/sec
– An AHB1 transfer requires 2 clocks to transfer 4 bytes (one 32-bit word)
– For a 60 MHz clock => 120 MBytes per second.
So 16-bits/pixel requires:
– 10.76 MBytes/sec divided by 120 MBytes/sec =
– ONLY 9% of the AHB1 bandwidth
11/15/08
15.11.08
CONFIDENTIAL 71
LPC2104/5/6 Blocks 48 pins
SRAM FLASH
128k
TRST
16/32/64k
TMS
TDO
TCK
TDI
Vectored
SRAM Internal Flash External Static Memory Interrupt
Controller Controller E-ICE ETM Controller (ESMC) Controller
Local Bus
AHB Bus
ARM 7TDMI-S
ARM Local Bus AHB Bus
RST System
Functions
X1
X2 PLL AHB to VPB
Real Time Watchdog Bridge
Clock Timer
VLSI Peripheral Bus (VPB)
DAC ADC
GPIO CAN I2C SPI UART0 UART1 Timer0 Timer1 PWM
10-bits 10-bits 32x
PWM1 - 6
MAT0.0-2
MAT1.0-3
CAP0.0-2
CAP1.0-3
RX 0,1..
TX 0,1..
Inputs
AOUT
AVDD
AVSS
VssA
2 pins
8 pins
SSEL
SCK
MOSI
MISO
GPIO
V3A
Vref
SDA
SCL
11/15/08
15.11.08
CONFIDENTIAL 72
LPC2114/24 Blocks 64 pins
SRAM FLASH
128/256k
TRST
16k
TMS
TDO
TCK
TDI
Vectored
Local Bus
AHB Bus
ARM 7TDMI-S
RST System
Functions
X1
X2 PLL AHB to VPB
Clock Timer
DAC ADC
10-bits 10-bits 46x 2x
PWM1 - 6
MAT0.0-3
MAT1.0-3
CAP0.0-3
CAP1.0-3
4 Inputs
RX 0,1..
TX 0,1..
AOUT
AVDD
AVSS
VssA
2 pins
8 pins
SSEL
SCK
MOSI
MISO
GPIO
V3A
Vref
SDA
SCL
11/15/08
15.11.08
CONFIDENTIAL 73
SRAM FLASH
128/256k
TRST
16k
TMS
TCK
TDO
TDI
Vectored
Local Bus
AHB Bus
ARM 7TDMI-S
RST System
Functions
X1
X2 PLL AHB to VPB
Clock Timer
DAC ADC
10-bits 10-bits 32x 2x 2x
PWM1 - 6
MAT0.0-3
MAT1.0-3
CAP0.0-3
CAP1.0-3
4 Inputs
RX 0,1..
TX 0,1..
AOUT
AVDD
AVSS
VssA
2 pins
8 pins
SSEL
SCK
MISO
MOSI
GPIO
V3A
Vref
SDA
SCL
11/15/08
15.11.08
CONFIDENTIAL 74
LPC2210 Blocks 144 pins
SRAM FLASH
TRST
16k
TMS
TCK
TDO
TDI
Vectored
Local Bus
AHB Bus
ARM 7TDMI-S
RST System
Functions
X1
X2 PLL AHB to VPB
Clock Timer
DAC ADC
PWM1 - 6
MAT0.0-3
MAT1.0-3
CAP0.0-3
CAP1.0-3
8 Inputs
RX 0,1..
TX 0,1..
AOUT
AVDD
AVSS
VssA
2 pins
8 pins
SSEL
SCK
MISO
MOSI
GPIO
V3A
Vref
SDA
SCL
11/15/08
15.11.08
CONFIDENTIAL 75
SRAM FLASH
128/256k
TRST
16k
TMS
TCK
TDO
TDI
Vectored
Local Bus
AHB Bus
ARM 7TDMI-S
RST System
Functions
X1
X2 PLL AHB to VPB
Clock Timer
DAC ADC
PWM1 - 6
MAT0.0-3
MAT1.0-3
CAP0.0-3
CAP1.0-3
8 Inputs
RX 0,1..
TX 0,1..
AOUT
AVDD
AVSS
VssA
2 pins
8 pins
SSEL
SCK
MISO
MOSI
GPIO
V3A
Vref
SDA
SCL
11/15/08
15.11.08
CONFIDENTIAL 76
SRAM FLASH
TRST
16k
TMS
TCK
TDO
TDI
Vectored
Local Bus
AHB Bus
ARM 7TDMI-S
RST System
Functions
X1
X2 PLL AHB to VPB
Clock Timer
DAC ADC
10-bits 10-bits 76x 2x 2x
PWM1 - 6
MAT0.0-3
MAT1.0-3
CAP0.0-3
CAP1.0-3
8 Inputs
RX 0,1..
TX 0,1..
AOUT
AVDD
AVSS
VssA
2 pins
8 pins
SSEL
SCK
MISO
MOSI
GPIO
V3A
Vref
SDA
SCL
11/15/08
15.11.08
CONFIDENTIAL 77
-40 to +125°C
SRAM FLASH
256k
TRST
16k
TMS
TDO
TCK
TDI
Vectored
Local Bus
AHB Bus
ARM 7TDMI-S
RST System
Functions
X1
X2 PLL AHB to VPB
Clock Timer
DAC ADC
10-bits 10-bits 112x 2/4x 2x
PWM1 - 6
MAT0.0-3
MAT1.0-3
CAP0.0-3
CAP1.0-3
8 Inputs
RX 0,1..
TX 0,1..
AOUT
AVDD
AVSS
VssA
2 pins
8 pins
SSEL
SCK
MOSI
MISO
GPIO
V3A
Vref
SDA
SCL
11/15/08
15.11.08
CONFIDENTIAL 78
LPC2138 Block Diagram Package: LQFP64/HVQFN64
RST
Vdd
32KB 512 KB
TRST
Vss
TMS
TDO
TCK
X1
X2
TDI
SRAM FLASH
System
Test/Debug Trace PLL
Functions
SRAM Memory
ARM 7TDMI-S BrownOutDetect
Controller Accelerator System Clock
PowerOnReset
Local Bus and AHB
32 kHz AHB to VPB Bridge Vectored Interrupt

Real Time Watchdog Controller
Vbat
Clock Timer
2x I2C SPI Port SSP Port UART0 UART1 ADC0/1 DAC GPIO Timer0 Timer1 PWM
MAT0.0-2
PWM1 - 6
MAT1.0-3
CAP1.0-3
CAP0.0-2
1-10-bit
2 pins
2x8 pins
8 pins
SSEL
SSEL
MOSI
MOSI
SDA
MISO
MISO
SCK
SCL
GPIO
SCK
11/15/08
15.11.08
CONFIDENTIAL 79
LPC2142/44/46/48 Block Diagram 64-pin LQFP
RST
Vdd
16-32KB 64-512 KB
TRST
Vss
TMS
TDO
TCK
X1
X2
TDI
SRAM FLASH
System Clock PLL1 System
Test/Debug ETM
PLL2 Functions
USB Clock
SRAM Memory
ARM 7TDMI-S BrownOutDetect
Controller Accelerator VIC PowerOnReset
Local Bus AMBA AHB Bus
D+
AHB to 8 KB SRAM USB 2.0 Full D-
32 kHz shared w/ DMA
Real Time Watchdog VPB Speed Device Up_LED OR
(LPC2148 only) Connect
Vbat
Clock Timer Bridge w/ DMA Vbus
I2C 0/1 SPI Port SSP Port UART0/1 ADC 0/1 DAC Fast I/O Timer0/1 PWM
PWM1 - 6
Tx/RX 0,1
MAT x 8
CAP x 8
1-10-bit
6+8 pins
pins (6)
Modem
GPIO
46 max
SSEL
SSEL
MISO
MOSI
MISO
MOSI
SDA
SCK
SCL
SCK
11/15/08
15.11.08
CONFIDENTIAL 80
SRAM FLASH
TRST
64k
TMS
TDO
TCK
TDI
Vectored
Local Bus
AHB Bus
ARM 7TDMI-S
RST System
Functions
X1
X2 PLL AHB to VPB
75MHz
Clock Timer
DAC ADC
PWM1 - 6
MAT0.0-3
MAT1.0-3
CAP1.0-3
CAP0.0-3
8 Inputs
RX 0,1..
TX 0,1..
AOUT
AVDD
AVSS
VssA
2 pins
8 pins
SSEL
SCK
MOSI
MISO
GPIO
V3A
Vref
SDA
SCL
11/15/08
15.11.08
CONFIDENTIAL 81
LPC2101/2/3 Blocks 48 pins
2/4/8Kb 8/16/32Kb
FLASH
SRAM
Fast GPIO
Bootloader,
TRST
RealMonitor
TMS
TCK
TDO
TDI
Vectored
SRAM Internal Flash Fast Interrupt
Controller Controller GPIO E-ICE ETM Controller
Local Bus
AHB Bus
ARM 7TDMI-S
RST System
Functions
X1 AHB to VPB
X2 PLL 70MHz Bridge
Real Time Watchdog
Vbatt
Clock Timer
RTCX1
RTC
RTCX2
Osc
ADC Timer0 Timer1 Timer2 Timer3

GPIO 2 x I2C SPI SPI/SSP UART0 UART1
10-bits 32-bit 32-bit 16-bit 16-bit
3 x MAT0
4 x MAT3
4 x MAT1
3 x MAT2
3 x CAP0
4 x CAP1
3 x CAP2
8 Inputs
GPIO
2 pins
8 pins
AVDD
AVSS
SSEL
SSEL
MOSI
MISO
MISO
MOSI
SDA
SCL
SCK
SCK
11/15/08
15.11.08
CONFIDENTIAL 82
2. Architecture
3. Instruction Set
4. ARM7TDMI-S
6. Tools
7. ARM9 / LPC3000
11/15/08
15.11.08
CONFIDENTIAL 83
LPC2000 Development Tools
Available from traditional 8-bit tool providers as well as established 32-bit providers
Low cost evaluation kits

– IAR Kickstart kits with free 32K compiler
– Keil evaluation kits with free 16K compiler
Evaluation
Boards
Compilers,
LPC2000 RTOS
IDEs
Emulators
11/15/08
15.11.08
CONFIDENTIAL 84
IAR KS214x Плата разработки
ЖК интерфейс
RS232 порт для UART
Кнопки для внешних прерываний
SD card интерфейс для USB и SPI
Цена € 125.00
11/15/08
15.11.08
CONFIDENTIAL 85
Keil MCB2103 для LPC2103 и
LPC2103
Цена: $149 ($299 с ULINK)
11/15/08
15.11.08
http://www.keil.com/mcb2103/
CONFIDENTIAL 86
Keil MCB2130 для LPC213x серии
•LPC2131, LPC2132, LPC2134,

LPC2136 и LPC2138
•Цена: $149 ($299 с ULINK)
http://www.keil.com/mcb2130/
11/15/08
15.11.08
CONFIDENTIAL 87
Keil MCB2140 плата разработки
LPC2148 микроконтроллер
2x 9-pin D-type RS-232
8 LED статуса
Динамик на выходе ЦАП
Потенциометр на входе АЦП
SD Card интерфейс
Драйвера USB для Windows
Цена € 125.00
11/15/08
15.11.08
CONFIDENTIAL 88
Ashling ASK-2000 для LPC210x, LPC211x,
LPC212x, LPC22xx
•LPC2104, LPC2105, LPC2106,

LPC2114, LPC2119, LPC2124,
LPC2129, LPC2210, LPC2212,
LPC2214, LPC229х
•Встроенный JTAG
•Цена: $295 с LPC2106
•Добавьте $90 для LPC2129 или
LPC2294
•Доступен адаптер для версий
21xx and 22xx
11/15/08
15.11.08
http://www.ashling.com/support/lpc2000/eval_kits.html CONFIDENTIAL 89
Средства разработки EA
Embedded Artists’ QuickStart серия
– Все порты ввода-вывода доступны
– RS232 последовательный порт с ISP
– Специально для разработки прототипов
– Поставляется с большим набором программных средств. GCC based среда разработки
Огромный выбор периферии

– 100/10M Ethernet LPC2138
– 10M Ethernet LPC2138
– Bluetooth LPC2106
– LPC2148 USB
– LPC2138
– LPC2132
– LPC2129 CAN
– LPC2106 RS232
– LPC2106
– LPC2103 USB
– QuickStart Prototype Board
11/15/08
15.11.08 LPC213x/4x QuickStart Board 10M Ethernet LPC2138 QuickStart Board
http://www.embeddedartists.com/ CONFIDENTIAL 90
JTAG интерфейс
11/15/08
15.11.08
CONFIDENTIAL 91
Интегрированные среды разработки
RealView AsIDE EWARM
Multi 2000 µVision3 CrossWorks

11/15/08
15.11.08
CONFIDENTIAL 92
Компиляторы
ARM Compiler
http://www.arm.com/devtools/soft_dev_tools?OpenDocum
.
GHS Compiler
http://www.ghs.com/products/arm_development.html
IAR Compiler
http://www.iar.com/Products/?name=EWARM
GNU GCC
11/15/08
15.11.08
CONFIDENTIAL 93
Поддержка ОСРВ
Embedded Linux
Nucleus from
Accelerated Technology
a Mentor company
ChronOS™
from InterNiche
11/15/08
15.11.08
CONFIDENTIAL 94
Application notes available on the web
http://standardics.nxp.com/support
11/15/08
15.11.08
CONFIDENTIAL 95
Sample software availables on the web
http://www.standardics.nxp.com/support/documents/
?type=software
11/15/08
15.11.08
CONFIDENTIAL 96
40 New
Members last
week
MEMBERS
3645
11/15/08
15.11.08
CONFIDENTIAL 97
Russian language tech.support
(from February 2008)
AR
M.
su
pp
or
t. NX
P@
gm
ail
.c om
11/15/08
15.11.08
CONFIDENTIAL 98
www.standardics.nxp.com
http://ru.nxp.com
www.electronix.ru
www.keil.com
www.embeddedartists.com
11/15/08
15.11.08
CONFIDENTIAL 99
2. Architecture
3. Instruction Set
4. ARM7TDMI-S
6. Tools
7. ARM9 / LPC3000
11/15/08
15.11.08
CONFIDENTIAL 100
ARM Core Applications
The ARM range of processor cores addresses various system

categories
– ARM7: Embedded real-time systems
• Storage, automotive, industrial and networking applications
– ARM9: Open platforms

• Devices running platform operating systems including Linux, Palm OS,
Symbian OS and Windows CE
11/15/08
15.11.08
CONFIDENTIAL 101
Pipeline-Changes for ARM9TDMI
ARM7TDMI
Fetch Decode Execute
ARM decode
Thumb→ARM Reg. Reg.
Instruction Fetch Shift ALU
decompress read write
Reg. select
CPI:
∼1.9
ARM9TDMI
Fetch Decode Execute Memory Writeback
ARM or Thumb
instruction decode Memory Reg.
Instruction Fetch Shift + ALU
Reg. Reg. access write
decode read
CPI:
∼1.5
11/15/08
15.11.08
CONFIDENTIAL 102
ARM Technology Roadmap
H Cortex-A8 2000+ MIPS Uni-Proc
Applications ARM11 MPCore 2000+ MIPS Multi-proc

Processor ARM1176JZ(F)-S 600+ MIPS Uni-Proc
Market
ARM1136J(F)-S 600+ MIPS Uni-Proc
Bluestreak
L ARM926EJ-S 250+ MIPS Uni-Proc LPC3000
ARM1156T2(F)-S 600+ MIPS Uni-Proc

Real-Time H
ARM946E-S
Embedded
ARM968E-S 150+ MIPS Uni-Proc LPC2900
Market L
ARM7TDMI 100+ MIPS Uni-Proc Bluestreak
H ARM7TDMI 100+ MIPS Uni-Proc LPC2000

Microcontroller
Market
L Cortex-M3 100+ MIPS Uni-Proc LPC1000
11/15/08
15.11.08
CONFIDENTIAL 103
LPC3000 Overview
LPC3000 Overview
90nm Process
200 MHz Core
1.2V core operation
0.9V ultra low-power mode
3.3V I/O
32KB I- & D- caches
64KB SRAM
Standard E-ICE
JTAG Interface
6KB Emb. Trace
320-pin TFBGA package
11/15/08
15.11.08
CONFIDENTIAL 104
Data and Instruction Caches
The LPC3100 has

32K I and 32K D Caches
Cache Access is single-cycle if hit
Cache is organized as 4 Ways of 8K each
11/15/08
15.11.08
CONFIDENTIAL 105
HighComputational
PerformancePower
Bus Matrix
Simultaneous accesses allowed, for example:
– Data Cache to SRAM

– Instruction Cache to DRAM
– DMA to peripheral
Arbitration required only if accessing the same peripheral
Higher performance than a classic Bus master type scheme
11/15/08
15.11.08
CONFIDENTIAL 106
US B
VFP9 ETB ETM9
Bus Matrix
transceiver
High Performance Bus
interface
D-TCM I-TCM
0 kB
D-cache
ARM
9EJS
0 kB
I-cache
Matrix
32 kB 32 kB DMA Ctrl US B-OTG
D-side I-side PL080 AHB
MMU
controller controller Master
M M
Data Instr
0 1 GX175
Master Layer 0 1 2 3 32 bit, S DRAM
104 MHz Ctrl 32 bit wide
AHB external
Port 2
S lave port 0 memory
Port 3
S lave port 1 Port 4
S lave port 2 Port 0
S lave port 3
SRAM ROM
64 kB 16 kB
AHB slaves AHB- APB slaves
S lave port 5 2-APB
NAND MLC SPI SD
Ctrl NAND Ctrl x2 Card
AHB slaves
S lave port 6
DMA USB SDRAM ETB
regs config confg regs
AHB- APB slaves

S lave port 7
2-APB
32 bit, 104 MHz I2C UART
AHB Matrix x2 x4
Master/S lave connection supported by matrix System Key Interrupt

PWM RTC Debug
Control Scan Controller x3
AHB- FAB slaves
11/15/08
15.11.08 2-FAB
GPIO
Watchdog High Speed Millisecond High Speed 10-bit
Timer Timer Timer UART x3 ADC
CONFIDENTIAL 107
MMU and Cache Interaction
Portfolio 32-bit microcontrollers, >100MHz
MMU RAM LCD Touch USB Ethernet DMA VFP 0.9V Ultra
screen Low Power
LPC3180 X 64KB Host/OTG X X X
LPC3180/01 X 64KB Host/OTG X X X
LPC3230 X 256KB X Host/OTG X X X
LPC3240 X 256KB Host/OTG X X X X
LPC3250 X 256KB X Host/OTG X X X X
LH7A400 X 96KB X Device X

LH7A404 X 96KB X X Host / Device X
released
roadmap for 2008
11/15/08
15.11.08
CONFIDENTIAL 108
Phytec LPC3000 Development board
• LPC3180 on board
• VFP coprocessor
• NAND Flash 32Mb
• SDRAM 32Mb
• 32 Kb EEPROM
• USB OTG
• 208MHz
•Price: $250
11/15/08
15.11.08
http://www.phytec.com/ CONFIDENTIAL 109

Hands-On
11/15/08
15.11.08
CONFIDENTIAL 110
NXP LPC2000 Family
–Advanced ARM7TDMI Implementations

Memory Addressing
System Control Block
Memory Accelerator Module (MAM)
General Purpose I/O
Pin Connect Block / External Memory Controller
• Integrated Peripherals
Timer 0 / Timer 1, PWM, RTC, Watchdog, ADC
• Vectored Interrupt Controller
• Serial Communication Interfaces
UART 0 / UART 1, I²C, SPI, USB, CAN
11/15/08
15.11.08
CONFIDENTIAL 112
Memory Map
4.0 GB 0xFFFF FFFF Memory blocks not
AHB Peripherals
0xF000 0000 drawn to scale!
3.75 GB
VPB Peripherals 0xEFFF FFFF
3.5 GB 0xE000 0000
0xC000 0000
3.0 GB Reserved for External Memory
2.0 GB 0x8000 0000

Boot Block (re-mapped from On-Chip Flash)
0x7FFF E000
*: nnnn RAM
Reserved for On-Chip Memory
FFFF 64KB
7FFF 32KB
16 / 32 / 64 KB On-Chip Static RAM 0x4000 nnnn* 3FFF 16KB

0x4000 0000
1.0 GB
0x3FFF FFFF
**: m Flash
Reserved for On-Chip Memory 1 128KB
3 256KB
128 ... 512 KB On-Chip Non-Volatile Memory 0x000m FFF** 7 512KB
0.0 GB 0x0000 0000

11/15/08
15.11.08
CONFIDENTIAL 113
Flash Memory
LPC213X
Organization 512k
12K Boot Block 0x07 FFFF
0x07 CFFF
scale
Sector 26 4K
n ot to …
c
G raphi Sector 22 4k
Sector 21 32K
…
LPC2100, 256k Sector 15 32k
256k 0x03 FFFF
8K Boot Block 0x03 FFFF Sector 14 32K
Sector 16 8K …
LPC2100, 128k
… Sector 11 32k
8K Boot Block 0x01 FFFF Sector 10 8k 128k 0x01 FFFF
Sector 10 32K
Sector 14 8K Sector 9 64K
Sector 9 32K
Sector 13 8K Sector 8 64K 64k 0x00 FFFF
Sector 12 8K Sector 8 32K
Sector 7 8K 32k
… … 0x00 7FFF
Sector 7 4K
Sector 2 8k Sector 2 8k ...
Sector 1 8K Sector 1 8K Sector 1 4K
Sector 0 8K Sector 0 8K Sector 0 4K
0x0 0x0 0x0
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CONFIDENTIAL 114
Flash Memory IAP Programming
IAP: In Application Programming

Bootloader contains flash programming routines
– Erase Sectors
– Write blocks (of 512 bytes)
• Re-write to blocks possible, if bits are cleared in 32 byte groups (see hands-on example)
– Common entry point for IAP calls: 0x7ffffff1
During calls, all interrupts must be disabled

– Note: hands-on example only disabled IRQ, not FIQ
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CONFIDENTIAL 115
SRAM: 8, 16, 32 or 64 KB
0x4000FFFF
64KB SRAM 0x40007FFF

8KB SRAM
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RAM Int Vect RAM Int Vect RAM Int Vect RAM Int Vect 0x4000003F
0x40000000
CONFIDENTIAL 116
Memory Addressing
General Purpose I/O  Hands-On
• Vectored Interrupt Controller  Hands-On

 Hands-On
 Hands-On
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CONFIDENTIAL 117
System Control
Includes a number of important system features

– Power Control
– Memory mapping configuration
– Oscillator
– PLL
– VPB divider
– Reset (active low)
– Wakeup Timer
– External Interrupts
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CONFIDENTIAL 118
Power Control (1)
• Power Control Register [PCON – 0xE01FC0C0] R/W

PCON 0 IDL Idle mode - processor clock stopped, on-chip
peripherals remain active, interrupts cause wakeup
PCON 1 PD Power Down mode - oscillator and on-chip clocks

stopped, wakeup by external interrupt
20 uA at room For example 5 mA with most

temperature, peripherals powered down
50 uA with single
voltage supply
Biggest factors:
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15.11.08 temperature, clock rates
Peripheral Clock Divider: 20%
CONFIDENTIAL 119
Power Control (2)
• When disabled, peripherals are switched off to conserve power

• Power Control for Peripherals Register
[PCONP – 0xE01FC0C4] R/W
PCONP 1 PCTIM0 Enable Timer0
PCONP 2 PCTIM1 Enable Timer1 Each peripheral

typically below 1mA
PCONP 3 PCURT0 Enable UART0
PCONP 4 PCURT1 Enable UART1
PCONP 5 PCPWM0 Enable PWM0
PCONP 7 PCI2C Enable I2C
...
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CONFIDENTIAL 120
Power Control (3)
• Power Control for Peripherals Register cont'd

...
PCONP 8 PCSP0 Enable SPI0
PCONP 9 PCRTC Enable RTC
PCONP 10 PCSPI1 Enable SPI1
PCONP 11 PCEMC Enable External Memory Controller
PCONP 12 PCAD Enable A/D-Converter
PCONP 13 PCCAN1 Enable CAN Controller 1

Acceptance Filter
PCONP 14 PCCAN2 Enable CAN Controller 2 enabled with any
CAN Controller
PCONP 15 PCCAN3 Enable CAN Controller 3
PCONP 16
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CAN peripheral
typically below 2mA
CONFIDENTIAL 121
Boot Block
The uppermost Flash sector contains the Boot Loader
– controls physical interface for programming and erasing the Flash
– supports ISP mode for initial programming of customer code
– supports In-Application Programming in a running system under the control of customer
software
– buffers an entire Flash line (512 bytes) at once to keep programming time to a minimum
The Boot Loader is automatically run following reset

– checks for a “Valid User Program” key to prevent running code on incorrectly programmed
devices
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CONFIDENTIAL 122
Exception Vectors
Vector Table
.
.
.
0x1C FIQ
0x18 IRQ
Valid user program key:
0x14 (Reserved) Must contain a value that
Data Abort ensures that the checksum of
0x10
all vectors is zero
0x0C Prefetch Abort
0x08 Software Interrupt
0x04 Undefined Instruction
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15.11.08 Reset
CONFIDENTIAL 123
Memory Mapping Control (1)
Re-mapping of Exception Vectors

– always appear to begin at 0x0000 0000
– but can be mapped from different sources:
• User Flash
– Exception Vectors are not re-mapped and reside in Flash
On-chip Flash Memory
Active Exception Vectors 0x0000 003F

0x0000 0000
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CONFIDENTIAL 124
• Boot Loader
– Always executed after reset. Exception Vectors re-mapped from Boot Block
• User RAM
– Exception Vectors are re-mapped from RAM
Off-chip Memory 0x8000 0000
On-chip User RAM
0x4000 0000
Boot Loader
On-chip User Flash Memory

0x0000 0000
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CONFIDENTIAL 125
Re-mapping of Boot Block
– mapped from top of Flash to top of on-chip memory space
2.0 GB
On-chip User RAM
Boot Loader
On-chip User Flash Memory

0x0000 0000
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CONFIDENTIAL 126
Memory Mapping Overview
4.0 GB
AHB Peripherals 0xFFFF FFFF
VPB Peripherals
Reserved for External Memory
2.0 GB
Boot Block (re-mapped from On-Chip Flash) 0x7FFF FFFF
Exception Vector
re-mapping Reserved for On-Chip Memory
16/32/64 KB On-Chip Static RAM

0x4000 0000 Boot Block
re-mapping
Reserved for On-Chip Memory
Boot Block
Active Exception Vectors

0x3F 128 KB On-Chip Non-Volatile Memory
0x0000 0000
15.11.080x00
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CONFIDENTIAL 127
Memory Mapping Control Register
• Memory Mapping Control [MEMMAP – 0xE01FC040] R/W

MEMMAP 1:0 MAP 1:0 00: Boot Loader Mode
01: User Flash Mode (no re-mapping)
10: User RAM Mode
11: External Memory (where available)
Selects the memory being mapped to address zero
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CONFIDENTIAL 128
Phase Locked Loop (LPC21xx/22xx)
156 to 320 MHz 10 to 60 MHz

FOSC Fosc * 2 * M * P Fosc * M
XTAL1 FCCO
Current cclk
Phase
Oscillator Controlled ÷P
Detector
Oscillator
XTAL2 Divider
Value
10 to 25 MHz
1 to 30 MHz VPB pclk

without PLL ÷M Divider
÷ 1/2/4
Default: 4
Multiplier Value
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CONFIDENTIAL 129
Memory Addressing
General Purpose I/O
UART 0 / UART 1, I²C, SPI, CAN
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CONFIDENTIAL 130
On-chip Memory with 0-wait States
ARM7TDMI-S is a 1-clock core
– CPI of ~1.9, but many instructions execute in 1 cycle
– CPU requires one instruction per clock cycle
For highest performance
32 bits needed with every clock

Memory access time < 17ns @ 60MHz
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CONFIDENTIAL 131
On-chip RAM and FLASH
RAM is fast enough to supply 1 word in 1 cycle

Flash typically has access times <50 ns
– Flash limits the maximum speed of the ARM core to about 20 MHz
or
– Additional wait-states required for Flash accesses
NXP Flash Architecture

– No cache (size, overhead)
– Deterministic (important for real-time control applications)
– No wait-states (performance)
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CONFIDENTIAL 132
Memory Accelerator Module
Address Bus
ARM7
Bus Interface
Core
Flash Memory Flash Memory
Bank 1 Bank 2
128 bit 128 bit
Prefetch Buffer 1 Prefetch Buffer 2

Local Bus
Branch Trail Buffer 1 Branch Trail Buffer 2
128 bit (2x) 128 bit (2x)
Data Buffer
Selection
Data Bus (32 / 16 bit)

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CONFIDENTIAL 133
Power Consumption and MAM
Enabling the MAM for low-clock applications does not bring a performance gain
However, enabling the MAM reduces the overall power consumption

– Less fetches from Flash memory will be made
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CONFIDENTIAL 134
Memory Addressing
General Purpose I/O  Hands-On
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CONFIDENTIAL 135
General Purpose I/O (1)
Pins available for GPIO:

– 48-pin devices: 32
– 64-pin devices: 46
– 144 pin devices: 76 (max.) (with external memory)
– 144 pin devices 112 (w/o external memory)
– 208 pin devices 160
Shared with
– Alternate functions of all peripherals
– Data/address bus and strobe signals for external memories
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CONFIDENTIAL 136
Direction control of individual bits

Separate set and clear registers
Pin value and output register can be read separately
Slew rate controlled outputs (10 ns)
5 registers used to control I/Os
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CONFIDENTIAL 137
Register
IOPIN The current state of the port pins is read from this register
IOSET Writing "1" sets pins high, writing "0" has no effect
IOCLR Writing "1" sets pins low and clears corresponding bits in IOSET
IODIR Port pin direction: 0 = INPUT 1 = OUTPUT
PINSEL Selects function of pins (Pin Connect Block)
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CONFIDENTIAL 138
Conventional GPIO
Implementation Drawbacks
Conventional ARM GPIO is implemented on the APB peripheral bus
Toggling speed of the GPIO is limited due to the 3-stage pipeline, AHB bridge
and the APB bus
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CONFIDENTIAL 139
Understanding the slow port behavior
It takes 5 clocks to execute a port write

Total time from instruction fetch to port change is 7 clocks
Maximum achievable period is 14 clocks (cclk/14) = (60/14) = 4.28MHz
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When cpu_clken_I is low indicates core is stalled
CONFIDENTIAL 140
Block diagram of new port configuration
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CONFIDENTIAL 141
Subject/Department, Author, MMMM dd, yyyy 10
Improving Speed
GPIO registers are now interfaced directly to the ARM7 Local bus
Ports can now toggle every 2 clocks giving a clock period of cclk/4= 15Mhz
This is a 3.5x speed increase

Enables faster ‘soft’ peripherals
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CONFIDENTIAL 142
Results of change (speed of writes)
Port output
Fetching Fetching Fetching Fetching Fetching Fetching

Writing E580500 Writing E580500 Writing E580500
Decoding Decoding Decoding Decoding Decoding Decoding
E5803000 Nothing E5804000 Nothing E5805000 Nothing
Executing Executing Executing Executing Executing Executing
E5802000 E5803000 E5803000 E5804000 E5804000 E5805000
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CONFIDENTIAL 143
Fast GPIO
Special features
– GPIO registers accessed via ARM local bus in addition to conventional peripheral bus access
– Mask registers allow treating sets of port pins as a group, leaving other bits unchanged
– Local bus GPIO registers are now byte addressable
– Entire port value can be written in one instruction using the IOPIN register
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CONFIDENTIAL 144
Mask Register- Advantages
Provides the capability to the user to separate the GPIO pins into groups
Any modifications to the FIOSET,FIOCLR and FIOPIN is only effected if the

corresponding bits in the FIOMASK are set
Using Mask registers…
Individual I/O pins can be addressed separately
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CONFIDENTIAL 145
Pin Connect Block (1)
Many on-chip functions can use I/O pins

Number of I/O-pins is limited
⇒ I/Os can be configured to adapt various functions
Pin function selection is done by Pin Connect Block
PINSEL0/1/2
GPIO
UART
PIN
Timer/Counter
reserved
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CONFIDENTIAL 146
Pin Function Select Registers

– PINSEL0 and PINSEL1
• Configuration of P0
• Assign P0.0 ... P0.31 to GPIO or an alternate function (1 of max. 3)
– PINSEL2 (not available in 48-pin devices)
• Configuration of P1 (64/144-pin devices) and P2, P3 (144-pin devices)
• Select availability of debug and trace ports on Port1 pins
• Controls use of address/data bus and strobe pins (144-pin devices)
• Selection of additional ADC-inputs (144-pin devices)
Note: Peripherals should be connected to appropriate I/Os before activation
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CONFIDENTIAL 147
Example:
• Pin Function Select Register 0 [PINSEL0 - 0xE002C000)] R/W

... ... ...
PINSEL0 21:20 P0.10 00: GPIO Port 0.10

01: RTS (UART1)
10: Capture 1.0 (Timer 1)
11: reserved
... ... ...
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CONFIDENTIAL 148
Pulse Width Modulator
Dedicated 32-bit PWM timer

– similar functionality to Timer0 / Timer1
Three additional match registers for a total of 7

– All PWM outputs have the same rate, which is programmable
– Allows up to 6 single edge controlled or 3 double edge controlled PWM outputs in any
combination
– Single edge controlled PWM outputs all go high at the beginning of each cycle and low at a
programmed time
– Double edge controlled PWM outputs can be programmed to be either positive going or negative
going pulses, with edges at any location in the cycle
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CONFIDENTIAL 149
Single-Edge Controlled PWM
PWM outputs all go high at the beginning of each cycle and go low on a Match
Match Register 0 Value

Compare (Match) Value z
mer
Compare (Match) Value y Ti ue
l
Compare (Match) Value x Va
0000 0000h
PWMx
PWMy
PWMz
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CONFIDENTIAL 150
Double-Edge Controlled PWM
Double edge controlled PWM outputs can have either edge occur at any
position within a cycle
Match Register 0 Value (100)

(PWM Period)
MR5=65 (PWM5)
MR3=53, MR4=27 (PWM4)
MR1=41, MR2=78 (PWM2) r
Time
0000 0000h e
Valu
PWM2
PWM4
PWM5 (single-edge)
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CONFIDENTIAL 151
PWM Diagram and Registers
Match Register 0
Match Latch Enable 0
Shadow Register 0 = S Q PWM1
= R EN Enable
Interrupt S Q PWM2
= R EN Enable
Control 32-bit Timer Counter
32-bit Pre-Scaler
S Q PWM6
Enable
= R EN
PCLK
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CONFIDENTIAL 152
Real Time Clock (1)
Full Clock/Calendar function with alarms

– Generates its own 32.768 kHz reference clock from any crystal frequency
– Counts seconds, minutes, hours, day of month, month, year, day of week and day of year
– Can generate an interrupt or set an alarm flag for any combination of the counters
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CONFIDENTIAL 153
Real Time Clock (2)
PCLK
Clock Divider
(prescaler)
Time Alarm
Comparators
Counters Registers
Clock
The Counter Interrupt Generator

Increment can
cause an
interrupt
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CONFIDENTIAL 154
(Mis-)Using the RTC clock for a regular timer
If the RTC is not used it could be used as a simple timer

Fastest interrupt that can be provided in regular operation
– 1 second
Changing the value for the prescaler and clock divider could produce faster
interrupts
– NOTE: Renders other RTC values inusable
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CONFIDENTIAL 155
Watchdog Timer (1)
Once activated, the Watchdog will reset the entire chip if it is not fed regularly
Feed is accomplished by a specific sequence of data writes
Watchdog flag allows software to tell that a watchdog reset has occurred
Selectable overflow time (µs ... minutes)
Debug Mode generates an interrupt instead of a reset
Secure: watchdog cannot be turned off once it is enabled
Watchdog Timer value can be read in one cycle
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CONFIDENTIAL 156
Watchdog Timer (2)
Watchdog Timer
WDFEED Constant
PCLK /4 32-bit Down Counter
UNDERFLOW
Current Timer Count
(WDTC)
WDMOD Register WDEN WDTOF WDINT WDRESET
11/15/08
15.11.08 Sticky bits! RESET
(cleared by WDT underflow or
ext. reset) INTERRUPT
CONFIDENTIAL 157
Hands-On Index Hands-On
0. Tools Setup / New project
1. MAM / PLL
2. GPIO
3. PWM
4. SPI
5. ADC / UART
6. USB
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CONFIDENTIAL 158
Start Keil uVision3
Hands-On
Menu Selection:
Project /
New Project
Select
HANDS_ON_2
Select readme.txt
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CONFIDENTIAL 159
MAM and PLL setup Hands-On
Explanation of MAM Register values
–“Partially Enable”:
Open project 01_MAM_PLL.
Code fetches only
Run it and notify LEDs blinking –“Fully enable”:
speed: Code and data fetches
–MAM Timing
Number of clock cycles used for one
flash memory access
Try to increase core frequency up to 60

MHz:
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CONFIDENTIAL 160
S tep
3.
S tep
1.
S tep
2.
Rebuild the project and load it to

flash.
Try to enable MAM. Rebuild and
load to flash. Make a conclusion.
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CONFIDENTIAL 161
MSEL = 5, PSEL = 2, MAM Control = Fully Enabled.
Solution
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CONFIDENTIAL 162
GPIO Exercise Hands-On
 Open project 02_GPIO.
 Run it and remember the result.

 Try to use Fast I/O instead of normal GPIO. Rewrite
the code.
 Rebuild and run your solution.
 Compare the results.
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CONFIDENTIAL 163
GPIO Exercise Hands-On
Solution
Just do the following replacement:

SCS = 0x00 → SCS = 0x01
IODIR0 → FIO0DIR
IOSET0 → FIO0SET
IOCLR0 → FIO0CLR
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CONFIDENTIAL 164
PWM Exercise Hands-On
Open project 03_PWM.
Run it.
Note the color LEDs are blinking not very frequently.
- Modify PWM initialization

code to get a ‘soft’ violet
light.
- When done, the motor will
start rotating automatically.
- Try to increase motor speed.
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CONFIDENTIAL 165
PWM Exercise - solution Hands-On
InitPWM ():
PWMMR0 = 0x000FFFFF;→PWMMR0 = 0x00000FFF;.
A and B values should be

reduced to make a ‘soft’
light.
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CONFIDENTIAL 166
PWM Exercise - solution Hands-On
EnableMotor ():
maxSpeed = PWMMR0 / 2; →maxSpeed = PWMMR0;
Value B should be increased

closer to A.
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CONFIDENTIAL 167
A/D Converter
Features
– 10 bit successive approximation analog to digital converter
– Multiplexed inputs
• 4 pins (64-pin devices)
• 8 pins (144-pin devices)
– Power down mode
– Measurement range 0V ... 3V
– Minimum 10 bit conversion time: 2.44 µS
– Burst conversion mode for single or multiple inputs
– Optional conversion on transition on input pin or Timer Match signal
– Programmable divider to generate required 4.5MHz from VPB clock
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CONFIDENTIAL 168
A/D Converter – Burst mode
CLKS: bit 17, 18, 19 of ADCR select the number of clocks used per conversion and
the accuracy
– 000b: 11 clocks, 10 bits
– …
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CONFIDENTIAL 169
ADC LPC213X, LPC214X
Separate result register for each channel

– Reduces the interrupt overhead by a factor of 8
Measurement range of 0 V to 3 V
– Separate voltage pins for analogue 3V supply (V3A) and analogue ground (VSSA)
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CONFIDENTIAL 170
ADC – Software Controlled Mode
All conversions are 10-bit and take 11 clocks

4.5Mhz Maximum Clock
Allows conversion to start on an external edge
ADC Inputs
7 6 5 4 3 2 1 0
ADDR0
ADDR1
Select Single Channel 10-bit ADC
ADCR (7:0) (11 Clocks/Conv)
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15.11.08 ADDR7
V3A VSSA
CONFIDENTIAL 171
ADC – Burst Mode
Result accuracy and speed are programmable

Input selected by the SEL bits are scanned
ADC Inputs
ADC Clock
(CLKS Bits)
1-8 n-bit ADC

Select Multiple Channels
ADCR (7:0) Input Scan (n Clocks/Conv)
(SEL Bits)
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ADDR0 ADDR1 ADDR7
CONFIDENTIAL 172
LPC213x DAC
Digital-to-Analog Converter (DAC)

– 10-bit resolution DAC with a buffered output
• Last output value is held as long as DAC is on
– Output from Zero Volt to Reference Voltage
• In 1024 steps
– Selectable Conversion speed vs. power
• Settling time 2,5us, up to 350uA
• Settling time 1us, up to 700uA
– Selective power down
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CONFIDENTIAL 173
• Memory Addressing
• System Control Block
• Memory Accelerator Module (MAM)
• General Purpose I/O  Hands-On
Vectored Interrupt Controller  Hands-On
Serial Communication Interfaces

UART 0 / UART 1, I²C, SPI, USB CAN
 Hands-On
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CONFIDENTIAL 174
Vectored Interrupt Controller (1)
ARM PrimeCell™
32 interrupt request inputs
16 IRQ interrupts can be auto-vectored
– Single instruction vectoring to ISR
– Dynamic software priority assignment
16 non-vectored interrupts
Software interrupts
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CONFIDENTIAL 175
Vectored Interrupt Controller (2)
FIQStatus
Interrupt Source FIQ
FIQ
IntEnableClear
RawInterrupt
32
IntEnable
High Prio
OR VectorCntl
SoftIntClear
En Channel VICVectorAddr 0
SoftInt
IRQStatus 5 0:4
IRQ
...
16 Prioritized
32
IntSelect En Channel VICVectorAddr 15

5 0:4
VICDefVectAddr
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CONFIDENTIAL 176
VIC - Vectored Interrupts
Interrupt source
linked to vector 4
VICVectAddr4 Load PC with Vector Address
PC
VICVectAddr ISR
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CONFIDENTIAL 177
VIC - Non-Vectored Interrupts
Interrupt
ISR
VICDefVectAddr
ISR
ISR
PC
CODE
ISR
VICVectAddr
ISR
ISR
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Load PC with Common
Vector Address
CONFIDENTIAL 178
VIC - FIQ Interrupt
FIQs have higher priority than IRQs
– Serviced first
– FIQs disable IRQs
• FIQ Vector is last in vector table (allows handler to be run sequentially from that address)
• FIQ mode has 5 extra banked registers, r8-12 (interrupt handlers must always preserve
non-banked registers)
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CONFIDENTIAL 179
Block Flag(s) VIC IR Source #
VIC
WDT Watchdog Interrupt (WDINT) 0
- Reserved for software interrupts only 1
IR Sources ARM Core
ARM Core
Embedded ICE, DbgCommRx
Embedded ICE, DbgCommTx

2
Timer 0 Match 0 -2 (MR0, MR1, MR2, MR3) 4

Capture 0 - 2 (CR0, CR1, CR2)
LPC2104 Timer 1 Match 0 -3 (MR0, MR1, MR2, MR3)

Capture 0 - 3 (CR0, CR1, CR2, CR3)
5
LPC2105 UART 0 Rx Line Status (RLS) 6
LPC2106 Transmit Holding Register empty (THRE)

Rx Data Available (RDA)
Character Time-out Indicator (CTI)
UART 1 Rx Line Status (RLS) 7

Transmit Holding Register empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
Modem Status Interrupt (MSI)
PWM 0 Match 0 - 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6) 8
I2C SI (state change) 9
SPI SPIF, MODF 10
- reserved 11
PLL PLL Lock (PLOCK) 12
RTC RTCCIF (Counter Increment), RTCALF (Alarm) 13
System Control External Interrupt 0 (EINT0) 14
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CONFIDENTIAL 180
Block Flag(s) VIC IR Source #
add'l ... ... ...
VIC
A/D A/D Converter 18
IR Sources CAN
CAN
CAN Error
CAN 1 Transmit
19
20
CAN CAN 2 Transmit 21
CAN CAN 3 Transmit 22
LPC2114/24 CAN CAN 4 Transmit 23
LPC2119/29 CAN CAN 1 Receive 26
LPC2194 CAN CAN 2 Receive 27
LPC2210/12/14LPC2 CAN CAN 3 Receive 28
290/92
CAN CAN 4 Receive 29
LPC2294
plus more flags for UART0, Timer1,
Capture 0 - 3 (CR0, CR1, CR2, CR3)
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CONFIDENTIAL 181
VIC Interrupt Latency
Some instructions take multiple cycles to execute and cannot be interrupted
– The longest STM and LDM instructions take 20 cycles
– Subsets can be reduced to 7 cycles
FIQ:
12 (25) cycles, 200ns (416ns) @ 60MHz
First Vectored IRQ (assuming no FIQ pending):
26 (39) cycles, 433ns (650ns) @ 60MHz
Default IRQ Vector (assuming no other IRQ pending):
42 (55) cycles, 700ns (916ns) @ 60MHz
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CONFIDENTIAL 182
Interrupt Prioritizing with Nesting
IRQ Service Routine of “lower” priority:
1. Clear IRQ source

2. Push SPSR to LR and on stack
3. Switch to System Mode (write CPSR, enable IRQ)
4. Push system mode link register on stack
5. Execute “real” service routine, can be interrupted
6. Pop system mode link register from stack
7. Switch back to IRQ mode
8. Pop SPSR to LR and restore SPSR
9. Reset VIC
Macros provided by ESAcademy’s ESLIB
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CONFIDENTIAL 183
Interrupt Prioritizing with RTOS
IRQ Service Routine starts RTOS task:

1. Start appropriate RTOS task with desired priority
2. Clear IRQ source
3. Reset VIC
Prioritizing is handled by
Real-Time Operating System
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CONFIDENTIAL 184
Caution: Spurious Interrupts
Core and VIC operate asynchronous

“Unwanted” interrupts can occur, as disabling IRQ/FIQ and their sources is not
instantaneous
– Instructions in pipeline continue to execute
One of multiple work-a-rounds:
– Upon entry of IRQ/FIQ check if since occurrence the interrupt was disabled
• If yes, exit interrupt
– Execute “protected code” as an IRQ interrupt
• which cannot be interrupted by another IRQ
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CONFIDENTIAL 185
Serial Communication Interfaces
UARTs
I2C
SPI
10100101
CAN
10110110
01111000
001
USB* 00
10 000
11
01
01
0
1010010110110110
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CONFIDENTIAL 186
UART
UART 0, UART 1
– 16 byte Receive and Transmit FIFOs
– PC UART 16C550 “look-alike”
– Built-in baud rate generator
– Supports 6 modem control signals
• CTS, RTS, DCD, DSR, DTR and RI functions are selectable
• Note:
UART 0 has Tx and Rx pins only
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CONFIDENTIAL 187
I2C Bus
Fast-I2C compliant bus interface

– Configurable as Master, Slave, or both
– Multi-master bus
– Bi-directional data transfer between masters and slaves
– Up to 400kb/s
– Arbitration between simultaneously transmitting masters without corruption of serial data
on the bus
– Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
– Programmable clock rate
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CONFIDENTIAL 188
SPI Bus
Compliant with Serial Peripheral Interface (SPI) specification

Combined SPI master and slave function
Maximum data bit rate of 1/8 of the peripheral clock rate
Programmable clock polarity and phase for data transmit/receive operations
No. of SPI channels:
– 1 (48-pin devices)
– 2 (64/144-pin devices)
– Up to 3
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USB 2.0
Since USB is a standard doesn’t that make all microcontrollers with USB the
same?
NO!!
Architectural choices and implementation details make a big difference in

performance and ease of use.
The LPC2148 is a high performance USB device.
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LPC2148 key high performance
USB features
Flexible endpoint architecture

– Supports all 32 USB endpoints
Large data FIFO

– Can double buffer full isochronous packets
Flexible DMA capability

– USB Buffer is present on the AHB bus
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CONFIDENTIAL 191
USB 2.0 in LPC2148
Fully Compliant with USB 2.0 Spec
Supports 32 physical endpoints
Scalable realization of Endpoints during run time
Double buffering supported for Bulk and Isochronous Endpoints
Supports DMA transfer on all non-control endpoints
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CONFIDENTIAL 192
USB 2.0 in LPC2148
Supports Control, Bulk, Interrupt and Isochronous endpoints
Supports SoftConnect™ feature
Supports GoodLink™ LED indicator
Flexible clock architecture (own PLL)
Remote wakeup
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CONFIDENTIAL 193
LPC2148 USB Block Diagram
AHB Bus
8K AHB
Memory Using the DMA, the
USB Logic has direct
DMA access to memory
Engine
VPB Bus
ATX
USB Logic PADS
Force SE0 D+
TX D
OE D-
Endpoint ram Serial Interface Engine
Register access control (SIE)
Interface
RX D
2K FIFO Receivers
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CONFIDENTIAL 194
Transfer Modes
Slave Transfer Mode
DMA Transfer Mode
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Slave Mode Transfer
USB Block acts like a slave
It can only issue interrupts to the CPU
Control Endpoint uses this mode of transfer exclusively
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CONFIDENTIAL 196
DMA Mode Transfer
USB Block acts like a Master
Will transfer data directly from the 8K SRAM to the EP_RAM and vice
versa.
For Isochronous transfers, the DMA transfer is synchronized to the

frame interrupt
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CONFIDENTIAL 197
SoftConnect™ and GoodLink™ LED
SoftConnect™
– Can connect/re-connect to the host through software
– No need to unplug and plug the cable back again
GoodLink™ LED
– Needs a shared GPIO pin
– Shows indication on a LED if connection is established
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CONFIDENTIAL 198
LPC2148 connections
3.3 volt system power
Vusb bus sense

Logic level p
Good Link channel FET
LPC2148 Philips BSH203
Soft connect_n
1.5k Vusb supply

D-
33
ATX D-
Pad 33
D+
D+
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CONFIDENTIAL 199
LPC2148 Clock Architecture
LPC2148 clocks
Main cclk
XTAL PLL
VPB pclk VPB clock must be 16 MHz

minimum for the USB vpb interface
divider
USB USB clk

PLL
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CONFIDENTIAL 200
Flexible Clocking Scheme
Two separate PLL’s provide lot of flexibility to the user to run the core and the USB
independently at different speeds
Considering the three possible option

– Crystal Frequency –12MHz
• Core Freq= 12,24,36,48,60MHz
• USB Freq =48MHz
• Core Freq= 16,32,48MHz
• USB Freq =48MHz
• Core Freq= 24,48MHz
• USB Freq =48MHz
Fastest USB operation available at any CPU frequency

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CONFIDENTIAL 201
Exercise: 04 - SPI Hands-On
Load project
Build
Run on hardware
Use joystick to move a point on the LED display
Browse through the program
Make a “worm” game on the LED display
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CONFIDENTIAL 202
Exercise: 05 – ADC and UART Hands-On
- Open project 05_ADC_and_UART
- Change UART speed to 57600.

- Rebuild and run the code.
- Check HyperTerminal for correct output.
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CONFIDENTIAL 203
- Rotate analog input AIN1 and notify the
results.
- Try to increase ADC accuracy.
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CONFIDENTIAL 204
Solution:
InitUART():
U0DLL = ( 12000000 * 5 ) / ( 19200 * 16 * 4 ); →
U0DLL = ( 12000000 * 5 ) / ( 57600 * 16 * 4 );
InitADC ():
ADCR = … (7 << 17) …; →
ADCR = … (0 << 17) …;
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CONFIDENTIAL 205
Exercise: 06 - USB Hands-On
Load project
Build
Run on hardware
Watch the new disk in Windows My Computer
Try to put something on it
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CONFIDENTIAL 206
Lowest power consumption (less than 1 mW / MHz)
Very small package options (as small as 7mm x 7mm)
The highest performance and most flexible external memory interface
available
Product highlights:
– ARM7 microcontrollers with Flash that operates up to the maximum clock
speed (60 - 72 MHz) thanks to our patented Memory Accelerator Module
with 128-bit wide memory interface – competitive ARM7 products are
limited to 30 – 45 MHz Flash speeds
– The only ARM7 MCU that allows multiple connectivity protocols to run at
full performance at the same time (LPC2300 and LPC2400 family with dual
AHB bus)
– The only ARM7 microcontrollers with full USB specification and
implementation (LPC214x, LPC2300 and LPC2400)
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CONFIDENTIAL 207
IT’S A TEST TIME!

(NXP) .1-Day Hands-On Arm Training

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ARM7 Microcontrollers

1-day Hands-On ARM Training

Established as Advanced RISC Machines Ltd. in 1990 as a UK

Introduction of ARM6™ family in 1991, VLSI initial licensee

*: part of NXP since 1999

Develops the ARM range of RISC processor cores

NXP relationship with ARM Ltd. spans a decade

NXP offers the most ARM experience

NXP is a long-term ARM licensee

are 32 bits wide

• instructions and data use the Mult.

– There is a subset of 16-bit

code density Data Out Data In

Set of instructions re-coded from 32 into 16 bits

In Thumb state only the program code is 16-bit wide

0 50 100 150 200 250

Keil 166 compiler

Const: 776 Data: 503 Const: 344

Data: 503 Stack: 512 (system) Data: 525

CAN Rx ISR CAN Rx ISR

Halfword Halfword Halfword Halfword

ARM has seven operating modes

– System privileged mode using the same registers as user mode

Depending on processor mode one of several banks is accessible. Each

Privileged modes (except System mode) can also access

Mode Mode r10

High registers r12

Condition Reserved Control bits

Condition Code Flags

Condition Reserved Control bits

Interrupt Disable Bits Mode Bits

Entering an exception the ARM core

– copies the CPSR into the appropriate SPSR

– forces PC to fetch next instruction from relevant exception vector

(automatically restoring also I, F and T)

– move contents of current LR minus offset* to PC

*: varies according to type of exception: 2, 4 or 8

1. Reset highest priority

All instructions are 32-bits long

Load or store multiple registers in a single instruction

4 bits in the operand of LT Signed less than

Implementation with conditional Implementation with conditional

No jumps or branches required,

In comparison to other chip architectures,

Direct addressing is not supported

Subset of most commonly used 32-bit ARM instructions

Compressed into 16-bit wide code

Decompressed on execution to full 32-bit instructions

ARM instruction set Thumb instruction set

• Branch and exchange with Link

– Load and Store Multiple

Example: ADD Rd, # Constant

Always condition code ARM code

When the processor is executing in ARM mode

When the processor is executing in Thumb mode

Average code size reduction in Thumb mode: 30%

After ‘decompression’, code size doubles

Therefore ARM mode provides better performance as in total less code

The ARM7TDMI-S is based on ARM7 core

The ARM7TDMI-S core uses a pipeline to increase the speed of the

PC PC Fetch Instruction Fetched from Memory

Thumb only: Thumb instruction