MASTER IN VLSI DESIGN

VLSI

VLSI (Very Large Scale Integration) is an efficient way to get reliability, less volume, low
weight and less power consumption for designing hardware, now a days due to use of VLSI,
millions of gates can be formed on a single programmable chip. As time progresses
complexity of digital system is increasing and sophisticated design tools are being
introduced in to hardware design process. Hardware description language such as VHDL and
VERILOG are used to describe hardware for this purpose.

The Background

With tremendous pressures on developing low cast mass production designs with ease in
upgradability, the future definitely belongs to IC Designing. With increasing number of
companies getting in to core of VLSI designing excellent job opportunities are opening up.
As the technology keep scaling to sub 45nm, design complexity is increasing, at the same
time reducing design time due to increasing pressure to meet time to market. First time
silicon success has become a very distinct competitive advantage in current scenario

To meet this growing demand our courses has been designed by BrainSupport
team to meet present and future needs of the industry. The course is carefully
planned to meet the need of corporate within unique learning contexts and
environments. To be in par with industrial requirements trainers who will conduct
the course have more than 10 years of industrial experience in FPGA/ ASIC
design.

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 Curriculum Structure

Master In VLSI Design : Duration 12 months

Course will be conducted for 48 Weeks

Training period will be for 36 weeks.

Last 12 weeks for the project work.

Lectures will be conducted from Monday to Friday.

Expert Lectures will be conducted on weekends

Day wise break up:

1. Lecture : 3 hrs
2. Lab : 4 hrs

Important Dates:

Sr. No. Tasks Important Date

1 Admission Commencing on 19 July 2010
2 Admission Closes on 9 Aug 2010
3 Course Commencing on 16 Aug 2010
4 Course Completion on 15 Aug 2011

Course Structure
1. Digital and advanced digital Design:
Duration 3 Weeks
(a) Fundamentals of Digital Design
(b) Combinational Logic Design
(c) Sequential Logic Design
(d) State Machines
(e) ALU Design
(f) Processor Logic Design

2. System Architecture
Duration 2 Weeks
(a) Memories

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 (b) Computer Architecture
(c) Communication Fundamentals
(d) Programmable Logic Devices
(e) FPGA Architecture
(f) FPGA Family
(g) FPGA & CPLD Downloading and Board Bring Up

3. HDL (VHDL/Verilog)
Duration 4 Weeks
(a) HDL Basic Concepts
(b) Concurrent Statements
(c) Sequential Statements
(d) Design Using HDL
(e) Test Cases and Test vectors
(f) Synthesis and Optimization
(g) Efficient Coding using HDL
(h) Constraining Design and optimization
(i) State Machines using HDL
(j) Multiple clock Domains and Design

4. Synthesis and Simulation

Duration 2 Weeks
(a) Concept of Simulation and Synthesis
(b) Combinational Logic Synthesis
(c) State Machine Synthesis
(d) Efficient Coding Styles
(e) Modeling Issues
(f) Hierarchical and Flat Design
(g) Timing Constraints
(h) Partitioning For Synthesis
(i) Pipelining
(j) Resource Sharing
(k) Optimization
(l) Static Timing Analysis

5. ASIC Design
Duration 6 Weeks
(a) Introduction to ASIC
(b) ASIC design Flow
(c) ASIC Synthesis
(d) ASIC EDA Tools and Flow
(e) Design and optimization constraints
(f) Area, Power and Speed minimization techniques
(g) HDL efficient coding and analysis
(h) Pipelining, resource sharing and register balancing
(i) Netlist generation and SDF files
(j) State machine optimization

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 (k) Report generations for power, area and speed
(l) STA using primetime
6. ASIC Verification
Duration 3 Weeks
(a) HVLs (System Verilog and System C)
(b) Verification Methodologies
(c) Verification Plans and Flow
(d) Transaction level modeling
(e) Coverage driven verification
(f) Assertion Based Verification

7. Design for testability

Duration 2 Weeks
(a)DFT concepts and flow
(b) Stuck at Fault modeling
(c)DFT friendly architectures
(d)Logic and memory BIST
(e)TAP controller and design
(f)DFT Test protocol
(g) DEF and Still format files
(h) Netlist generation and ATPG
(i) Simulation for fault analysis
(j) Coverage estimation

8. CMOS VLSI Design

Duration 4 Weeks
(a) Logic Families (RTL, DTL, I2L, ECL, TTL)
(b) Introduction to MOS Technologies
(c) Design of Gates & Combinational Logic using CMOS
(d) Sequential logic Design using CMOS
(e) Fabrication Process Technologies
(f) Design Rules for CMOS Layout
(g) Introduction to Layout and Simulation Tools

9. Physical Design
Duration 8 Weeks
(a) Backend Design flow
(b) Technology files and library formats
(c) Floor planning
(d) Power planning
(e) Placement of Standard cells and macros\
(f) Clock Tree Synthesis
(g) Global and detailed routing
(h) Parasitic extraction and back annotation
(i) STA
(j) GDS II

10. Advanced System Architecture

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 Duration 2 Weeks
(a) Ethernet Protocol
(b) PCI Express
(c) USB 2.0 and 3.0
(d) Memory Controller design and Interfaces
(e) AHB Bus

11. PROJECT
Duration 12 Weeks
(a) RISC processor design at 65 nm
(b) ORCA Processor implementation
(c) Logical, Physical Design and timing closure at 65, 40 nm.

Design Flow

Eligibility criteria

Graduate Engineers in Computer Science, E & TC, Electronics, Instrumentation,

MSC (Electronics, Instrumentation, Computers) with strong knowledge of digital and
processor design and in depth understanding of logic families.

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 Trainer and mentors
Quality knowledge and presentation skills are two features that will be given highest priority
while training the candidates. Teachers and mentors have very strong practical knowledge
to deliver the lectures and to explain practical fundamentals.

Mentors are ME/M.Tech in electronics from IITs and other leading institutions with strong
fundamentals in chip design and working experience on ASIC/FPGA designs. All the Mentors
have more than 10 years of Industrial experience.

Methodology and delivery model

Training will be delivered at BrainSupport Premises by experienced trainers. Classroom
training followed by Lab sessions, where classroom training will be delivered using
interactive PPTs and Lab sessions will be provided in the form of assignments.

Learner’s study material

Learners will be provided with the study material so that it will be helpful for them to come
prepared for the lectures

Software/Hardware tools

EDA Tools

1. MODELSIM SE

2. XILINX ISE 10.1 or above

3. LEONARDO Spectrum Level III

4. Altera Quartus II

5. XILINX/ALTERA FPGA Boards

6. ASIC Synthesis, DFT, STA Tools

7. Physical design Tools for Floor/Power planning, Routing, CTS, GDSII

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 PROJECT WORK
Learners can work on any one of the project listed below as these projects meets industrial
standards and requirements or project work can be finalized according to corporate
requirements.

Contact Information

BrainSupport Integration Technologies

SF/30, Rudra Square,
Judges Bungalow Chowk
Bodakdev, Ahmedabad
Gujarat 380054
Contact No. 079-40039474
Mobile: 9998885137
Email: info@brainsupport.org.in
Web:www.brainsupport.org.in

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