IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 62, NO.
11, NOVEMBER 2015 2685
A Reconfigurable 5-to-14 bit SAR ADC for
Battery-Powered Medical Instrumentation
Schekeb Fateh, Student Member, IEEE, Philipp Schönle, Student Member, IEEE, Luca Bettini, Student Member, IEEE,
Giovanni Rovere, Student Member, IEEE, Luca Benini, Fellow, IEEE, and Qiuting Huang, Fellow, IEEE
Abstract—In battery-powered medical instrumentation, the
resolution and signal bandwidth of analog-to-digital converters
(ADCs) have to be adapted to the needs of the application to avoid
power wastage. This paper presents a reconfigurable successive
approximation register (SAR) ADC implemented in 130 nm
CMOS that resolves 5–14 bit with a maximum achievable effective
number of bits (ENOB) of 13.5 using non-subtractive dither.
In the proposed ADC design, the power consumption can be
traded for accuracy to improve the energy efficiency and extend
its application range, while reducing system integration com-
plexity. A figure-of-merit (FoM) of 59 fJ/conversion is achieved
at 1.2 V supply and the converter occupies an area of 0.42 .
Measurement results of the ADC integrated in a multi-channel
analog front-end (AFE) circuit show the suitability of the ADC for
portable medical monitoring devices.
Index Terms—Analog front-end, biopotential signals, fully dy-
namic comparator, majority voting, multi-channel biomedical in-
strumentation, non-subtractive dither, perturbation based digital
calibration, reconfigurable analog-to-digital converter, successive
approximation register.
I. INTRODUCTION
A GING population and high medical costs in industrialized
countries demand for the development of inexpensive and
miniaturized medical instrumentation with a wireless link to
cloud based networks to enable patients being continuously and
real-time monitored out of ambulatory care [1]. Autonomous
biomedical sensor nodes for monitoring various biopotential
signals (ECG, EEG, EMG, EOG), temperature, pressure, and
pulse oximetry, require low-power sampling systems to operate
with a battery power supply [2]. Integration of these sensor
nodes is a necessity in practice to enable the device not only
to be low-power but also miniaturized, e.g., to be comfortable
to wear in preventive healthcare as a fitness tracking device. The
dimension of such a device, however, is mainly limited by the
requirements on battery lifetime and consequently battery size.
The development of system-on-chips (SoCs) acquiring dif-
ferent biopotential signals, thereby extending their application
Manuscript received June 06, 2015; revised August 08, 2015; accepted
August 22, 2015. Date of current version October 26, 2015. This work is
mainly supported by the Nano-Tera.ch RTD Project WearMeSoc, which is
financed by the Swiss Confederation and scientifically evaluated by Swiss
National Science Foundation (SNSF). Additionally, this project is supported
by SNFS under the grant 157048: Transient Computing Systems. This paper
was recommended by Associate Editor N. Maghari.
The authors are with the Dept. of Information Technology and Electrical
Engineering (D-ITET), ETH Zurich, 8092 Zurich, Switzerland (e-mail:
sfateh@iis.ee.ethz.ch; schoenle@iis.ee.ethz.ch; bettini@iis.ee.ethz.ch;
rovereg@iis.ee.ethz.ch; lbenini@iis.ee.ethz.ch; huang@iis.ee.ethz.ch).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2015.2477580
1549-8328 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
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range, is highly attractive to also justify the significant costs con-
sisting of research, application specific integrated circuit (ASIC)
manufacturing, operating costs, and in particular medical regu-
latory approval. However, multi-functional SoCs often experi-
ence a time-to-market pressure because of their increased de-
sign complexity [3]. A solution to this problem is design-reuse
[4] which demands for flexible and reconfigurable circuits.
In this paper, we propose a flexible and reconfigurable ADC
to be employed in a multi-channel biomedical ASIC, which
adapts the performance of the conversion to the characteristics
of the biopotential signals to avoid consuming power on unnec-
essary signal bandwidths and accuracies [5]–[7]. Reconfigura-
tion of the ADC is essential to enhance the lifetime of battery
powered medical devices. The proposed flexible ADC can be
tuned to operate at ultra low-power to only fulfill minimal spec-
ifications on the signal quality, e.g., when awaiting activity or a
specific pattern in biopotential signals. The system, however, is
able to recover full performance if required, e.g., when activity
or the specific pattern is detected.
The energy efficiency of the SAR ADC architecture makes
it an ideal candidate for the implementation of low-power data
sampling systems [8]–[13]. Except for the reference buffers,
SAR ADCs can be designed to consume only dynamic power.
Furthermore, due to their switched-capacitor implementation,
SAR ADCs benefit much more from technology scaling than
other converter architectures and their power consumption and
conversion time become smaller with technology advancement
[8], [13]. In order to design a flexible ADC for multi-channel
biomedical devices, not only a high data rate is favorable to
maximize the number of multiplexed analog channels but also a
one-to-one mapping between its analog input and digital output
(memoryless transfer characteristic) to associate each sample
unambiguously to the correspondent channel. ADCs with
memory, e.g., based converters due to integration, have to
properly settle after switching the input channel. Typically, this
costs some extra samples. Thus, the ADC has to run at higher
sampling rates which makes it power-inefficient.
The SAR ADC has been chosen in this paper over other con-
verter architectures not only because of its power efficiency or
its advantage of being memoryless, but also because it offers a
flexible conversion algorithm to support reconfigurability. The
SAR ADC is capable to trade-off bandwidth, precision, and
power on the fly, i.e., for each conversion. Conversion steps
in the successive approximation (SA) can be skipped while re-
solving equivalently less bits and the ADC, including its ref-
erence buffers, can be put in a reset state between consecu-
tive samples to minimize power consumption. The maximum
achievable resolution of SAR ADCs is typically determined by
the capacitor array mismatch and noise [8], [9], whereas the
2686 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 62, NO. 11, NOVEMBER 2015
maximum conversion speed is limited by the settling time and
accuracy of the individual conversion steps. The former issue is
addressed by advanced digital calibration techniques [13], [14],
the latter by clocking schemes and redundancy [15].
1) Contributions: In this paper, we present a 14 bit
sub-radix-2 SAR ADC implementation, employing a redundant
segmented capacitor array with a merged capacitor switching
scheme [15]. We propose a non-uniform and reconfigurable
clocking scheme that renders the SAR ADC energy efficient
over a wide range of resolutions and signal bandwidths. The
capacitor array is designed to be highly flexible, allowing
capacitors to be disconnected from the array for biomedical
applications requiring lower resolutions. A perturbation-based
least-mean-squares (LMS) start-up calibration [9], [13] has
been implemented directly on-chip to correct capacitor mis-
match and enhance the effective resolution by more than 10 dB.
Oversampling, non-subtractive dither [16], majority voting
[17], and several other options can be controlled via serial
peripheral interface (SPI) to further increase the resolution of
the ADC. The converter is as accurate as required for a desired
biomedical application and is able to remain in a reset state
where no power is consumed to minimize the overall power
consumption. The overhead given by reconfigurability in the
ADC is minimal in the digital domain with the exception of few
logic gates in the analog domain to provide additional switches
for disabling capacitors when targeting lower resolutions.
We present a corresponding SAR ADC ASIC in 130 nm
complementary metal-oxide-semiconductor (CMOS) tech-
nology. Measurement results of the SAR ADC integrated with
a multi-channel AFE in a biomedical data acquisition ASIC
show the suitability of the reconfigurable ADC in low-power
and portable medical monitoring sensor nodes.
2) Outline: The remainder of this paper is organized as fol-
lows. Section II introduces the ADC architecture and the pro-
posed reconfigurable non-uniform clocking scheme. Section III
details the LMS based digital start-up calibration. Section IV
presents measurement results of the SAR ADC. Details on the
biomedical data acquisition ASIC are presented in Section V,
and Section VI illustrates corresponding measurement results.
Conclusions are drawn in Section VII.
II. SAR ADC ARCHITECTURE
This section describes the implementation of the prototype
SAR ADC which is illustrated in Fig. 1. The input signal
is directly sampled onto the top plates of the capacitor array
which is connected to the input of the 1 bit dynamic comparator.
A bootstrapped sampling switch [18] is used to reduce signal-
dependent charge injection and enhances the linearity of the
switch. The SAR logic controls the switches of the capacitor
array according to the output of the dynamic comparator and the
reconfiguration settings. For this reason, the digital SAR logic
is implemented to be fully flexible. Start-up calibration and cor-
responding post-correction are implemented in the digital do-
main to correct the mismatch of the capacitor array. During cal-
ibration, an LMS based iterative algorithm is applied to esti-
mate the capacitor weights used in the correction unit to gen-
erate the output of the converter denoted as . The cal-
ibrated values of the capacitor weights, including the configura-
tion information for both analog and digital circuits, are stored
in the memory. The analog domain further features a R-ladder
digital-to-analog converter (DAC) (explained in Section II-E)
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Fig. 1. Architectural level block diagram of our SAR ADC. Figs. 2, 3, 5, 6,
and 7 give more insight into the design of the capacitor array, the reconfigurable
non-uniform clocking scheme, the comparator, the reference buffers, and the
calibration circuit. The memory contains both registers used by the calibration
circuit and for the configuration of both, the analog and digital circuits.
and reference buffers. The negative and positive voltage refer-
ences for the converter have been chosen as
and respectively in our 1.2 V implementa-
tion, leading to a maximum input signal swing of 1.6 . The
common-mode voltage is set to . The frequency of
the global clock in the SAR ADC is denoted as . The syn-
chronous high speed clock is used in the digital domain of the
ADC to derive the clock phases to control the analog switches of
the capacitor array using integer number of cycles of the global
clock. This counter based clocking strategy simplifies the im-
plementation of reconfiguration in the ADC. The sampling fre-
quency of the SAR ADC is denoted as and is derived from
the global clock equivalently.
A. Capacitor Array
The capacitor array is based on the principle of charge redis-
tribution in the condition of preserved total charge (top-plate).
Thus, the original, sampled voltage, can be restored by reset-
ting all bottom-plate switches to their initial state. This enables
both, perturbation injection based calibration and non-subtrac-
tive dithering, with little extra hardware resources.
The implemented 14-bit segmented capacitor array is
depicted in Fig. 2. Besides the two main segments, the most-sig-
nificant-bit (MSB) and least-significant-bit (LSB) capacitor
arrays, there are additional perturbation capacitors used during
calibration (as explained in Section III) and a dithering capac-
itor array. These extra capacitors occupy only negligible die
area compared to the two main segments. The merged capacitor
switching scheme proposed in [15] is employed. The input
signal is directly sampled onto the capacitors top plates, which
are connected to the comparator input, instead of being sampled
on the capacitors bottom plates as in the conventional scheme
[19], [20]. This approach avoids the initial charge redistribution
prior to the first comparison, necessary in the conventional
scheme, thereby ensuring high switching energy efficiency and
reducing conversion time. To prevent any charge accumulation
on floating nodes, all capacitors are reset once per conversion
to the common-mode voltage .
The capacitor array is a sub-radix-2 design [14], [21], i.e.,
the approximation steps are slightly lower than in the case of
binary search and a full conversion requires steps. This
FATEH et al.: A RECONFIGURABLE 5-TO-14 BIT SAR ADC FOR BATTERY-POWERED MEDICAL INSTRUMENTATION
Fig. 2. Detailed schematic of the capacitor array. It is a sub-radix-2 split-array
design featuring a dithering array used to further enhance the resolution of the
SAR ADC.
results in redundancy which ensures a correct approximation of
the sampled voltage to zero even in presence of mismatched ca-
pacitors. This prevents missing codes and preserves linearity.
Furthermore, redundancy allows incomplete settling and thus
can reduce conversion time although it increases the number
of comparisons and approximation steps. The presented design
can tolerate more than capacitor mismatch. Matching and
thermal noise considerations led to the choice of a total sam-
pling capacitance , divided into
unit elements with . This results in a theoretical
upper signal-to-noise ratio (SNR) limit given by thermal noise
of 87.6 dB. Quantization noise clearly dominates and lowers the
theoretical SNR to 85.3 dB for conventional conversions.
To further enhance the resolution of the ADC, non-subtrac-
tive dither [16] is used. Basically, non-subtractive dither allows
oversampling of an already sampled signal by slightly modu-
lating the latter from conversion to conversion with a zero-mean
pseudo-random signal. Similar to real oversampling, this vir-
tual oversampling results in a quantization noise reduction, but
in contrast to the former not in a reduction of sampled kT/C
thermal noise. In the presented implementation, a deterministic
dither sequence of 8 levels is injected to the capacitor array
after sampling [2], [22]. The capacitor array is extended with
additional capacitors, while a simple counter generates the de-
sired dither sequence. The dither range is set to approximately
1.2 LSB. Dithering is particularly interesting for sub-radix-2
SAR ADCs since the redundant capacitor weighting allows to
repeat just the last few conversion steps. Furthermore, it is of
great interest in applications for which real oversampling is not
possible due to static measurands, e.g., temperature, or is costly,
e.g., in pulse oximetry. For the latter, power consumption is
dominated by the light emitting diode (LED) current pulses.
Thus, real oversampling would dramatically increase the overall
power consumption while virtual oversampling affects it only
marginally.
B. Non-Uniform and Reconfigurable Clocking Scheme
The sampling frequency of high-precision SAR ADCs is usu-
ally limited by the settling behavior of the comparator input
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2687
Fig. 3. Illustration of the implemented highly configurable non-uniform
clocking scheme. The radial axis represents different possible configurations
for the various FSM states and sub-states (angular axis). Each state (except for
“reset/regeneration”) is divided in two independently configurable sub-states,
one defining the settling time and one defining the number of comparisons taken
(to reduce the impact of comparator thermal noise by majority voting). Each
rectangle corresponds to one clock cycle, the yellow marked path illustrates
a sample configuration. The innermost white segment represents the 0-cycle
option, i.e., skipping a certain state and thus disconnecting a certain capacitor
from the array. The “reset/regeneration” state is not only used to reset the ADC
after a conversion is complete, but also to regenerate the sampled analog signal
in case of perturbation or dithering injection.
voltage, which is in turn determined by the sampling capaci-
tance and the on-resistance of the switches . A conventional
-bit capacitor array requires at least identical cycles for one
conversion. However, as the voltage on the capacitor array re-
duces by a factor at each conversion step, the settling
time for a given settling error scales as well according to
The allotted time can be for instance reduced by about 30%
every 3 steps for 13 bit resolution. Capacitor array redundancy
allows the converter to tolerate even a larger settling error, there-
fore we can afford to reduce the allocated time even more ag-
gressively. For instance, in the presented design, it is sufficient
to let the signal settle only to 98.5% prior to the
second comparison. This is nearly a 50% reduction in conver-
sion time compared to an irredundant implementation of a 14-bit
SAR ADC. For a given application, the non-uniform clocking
scheme can be well optimized due to a highly configurable im-
plementation, visualized in Fig. 3. The settling time for each
conversion step can be set individually over the SPI interface as
an integer number of clock cycles in the range 1–32. In order
to optimize the converter for a specific biomedical application,
the ADC is tuned externally during testing to find the optimal
circuit settings. Comparator noise can be mitigated by majority
voting: an odd number of comparisons in the range 1–5 can be
set for each conversion step individually. While fine-tuning of
the settling time of the most significant conversion steps can in-
crease the performance, majority voting is only effective for the
least significant conversion steps.
The timing diagrams for two different resolution settings are
given in Fig. 4. For higher resolutions, SA steps need
to be performed in 56 clock cycles. Majority voting is activated
for the last two LSBs to reduce noise. Configuring the ADC for
a resolution of 6 bit requires 17 clock cycles. In order to reduce
the resolution, less settling time is needed in the sampling phase
2688 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 62, NO. 11, NOVEMBER 2015
Fig. 4. (a) Timing diagram of SAR ADC to achieve highest resolution without
dithering and (b) a resolution of 6 bit. Each square corresponds to one clock
cycle. A conversion always starts with sampling and ends with a capacitor array
reset. If necessary, the ADC is able to stay for more than one clock cycle in the
reset state. Achieving highest resolution in the ADC requires majority voting
which corresponds to consecutive comparisons and comparator resets in the
LSBs of the ADC.
Fig. 5. Schematic of the implemented double-tail latch (DTL).
and there is no need to perform any resolution enhancement
techniques.
C. Dynamic Comparator
A high-speed fully-dynamic double-tail latch (DTL) com-
posed of a pre-amplifier and an output latch has been chosen as
comparator [23], [24], and is depicted in Fig. 5. Together with
the inverter, the dynamic pre-amplifier provides a limited gain
( 10) that reduces the input-referred offset of the regenerative
stage. Furthermore, the kick-back noise of the latch does not
propagate backwards towards the capacitor array. A single clock
signal (clk) is sufficient to control the reset and the
latch phase . With respect to the scheme in [24],
we added two additional programmable capacitors and
to the input and the output of the inverter to filter the comparator
noise [25]. The capacitor is dimensioned to make the noise
of the inverter negligible. In each comparison the total noise at
the comparator input can be approximated as
where is the input transistors transconductance at the latch
toggling instant, and is the noise bandwidth
of the comparator input stage [26]. Since also determines the
energy per comparison, in a power-efficient implementation it
cannot be made arbitrarily large. For this reason, is chosen to
render the sampling noise negligible to achieve an overall SNR
of about 85.3 dB. The capacitor is configurable between
22–800 fF. However, to operate the SAR ADC efficiently, in-
stead of increasing the value of any further, majority voting
is performed at the output of the comparator to provide pro-
grammable noise performance at different bit cycles during a
conversion [27].
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Fig. 6. Schematic of the on-chip reference buffers for (a) the negative and
(b) positive reference, respectively. For the common-mode reference voltage,
the same reference buffer architecture as designed for the negative reference is
used. It covers a voltage range of 0.1–0.6 V.
D. Reference Buffers
In order to allow the integration of the converter into a multi-
channel medical instrumentation ASIC, the generation of the re-
quired voltage references on-chip is a compelling necessity. For
such reason, a fully-integrated reference buffer has been imple-
mented [28] and is shown in Fig. 6. The positive and negative
voltage references are buffered to feed the ADC core. A third
buffer, identical to the one shown in Fig. 6(a), is employed for
the common-mode reference voltage.
The buffer is composed of a feedback loop, made of transis-
tors M1–M3, and of the operational amplifier, whose task is to
sense the band-gap voltage and regulate the gate of the output
transistor M4. A compensation capacitor has been added to
ensure sufficient stability margins. The open-loop output branch
composed of transistors M4–M5 drives the load, ensuring fast
settling at the maximum speed. The complete buffer occupies a
silicon area of 0.043 , and consumes 1 mW from the 1.2 V
supply running at maximum speed.
E. Resistor Ladder DAC
The 6-bit resistor ladder DAC enables an autarkic calibration,
which is crucial when the ADC is used in a system which does
not guarantee a sufficiently conditioned input signal at start-up.
The LMS based start-up calibration is particularly unsuited for
acquiring biopotential signals that have a signal component with
small amplitude superimposed to a slowly moving large offset.
The LMS algorithm imposes only two conditions to the input
signal during calibration: a coverage of the signal range and to
ensure that all capacitors of the array toggle. Thus, there are no
constraints on the linearity and the noise level. Indeed, circuit
noise can be beneficial since it increases the amount of distin-
guishable input values, which allows for a fairly simple circuit
realization. During calibration, a triangular wave is generated
by the R-ladder. The step size and input range of the calibra-
tion sequence can be controlled over SPI. Since the R-ladder is
connected directly to the supply instead of reference voltages,
the 6-bit DAC is even able to go above the input range of the
ADC. However, digitally controlled resistors are used to scale
the signal range of the DAC to the one of the SAR ADC.
FATEH et al.: A RECONFIGURABLE 5-TO-14 BIT SAR ADC FOR BATTERY-POWERED MEDICAL INSTRUMENTATION
Fig. 7. Top-level block diagram of the digital calibration unit and area distri-
bution of the main building blocks relative to the total digital area [13].
In the presented SAR ADC, a 6-bit resistor ladder has been
implemented which occupies only a small fraction of the overall
circuit area, that is 0.012 .
III. DIGITAL START-UP CALIBRATION
The capacitor array mismatch is corrected by means of the
perturbation-based algorithm proposed in [8], [10], which has
been implemented directly on-chip to avoid the need for ex-
pensive off-chip computation. A block diagram of the digital
calibration unit is shown in Fig. 7. The calibration sequence is
generated by the resistor-ladder DAC discussed earlier.
Notation: The following notation will be used in the re-
mainder of this paper. Lowercase boldface letters stand for
column vectors having elements, where is the
number of SAR iterations required to resolve each sample. The
th entry of a vector at time instant k is denoted by .
A. Perturbation Injection
The implementation of the calibration algorithm requires that
an analog offset is injected into the sampled signal in order to
generate two different digital output codes from the same input.
This is accomplished with a minimum overhead of two addi-
tional perturbation capacitors which can be connected to either
the positive or the negative reference, as depicted in Fig. 2.
B. Calibration Algorithm
Because the capacitor array is not binary weighted, the two
generated output codes are first converted to a binary represen-
tation according to
(1)
where is the -th resolved bit of the non-binary
output code, and is the bit weight of the capacitor array.
If all the weights of the array were exactly known, the differ-
ence between the two output codes would be identical to twice
the digital representation of the analog offset. An error func-
tion for LMS can therefore be defined as
If is not zero, the calibration algorithm updates the value
of the weights trying to minimize the LMS of the error signal,
according to the update equations
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2689
Fig. 8. Fixed-point MATLAB simulation of the SAR ADC resolution before and
after calibration for different unit capacitors using 1000 Monte Carlo simulations.
The learning factors have been chosen equal to μ and μ ,
respectively.
The learning factors μ and μ determine the convergence
speed and the precision of the weights. Since the input needs
to be sampled twice, we calibrate the capacitor array during
start-up and disable the calibration in normal operation to re-
cover full speed and to save power. It takes about 5000 samples
before LSB, which is equivalent to a convergence
time of 17.5 ms at 286 kS/s. With smaller learning factors
which can be controlled through the SPI interface, the LMS is
able to estimate the capacitor values with higher precisions and
convergence times.
The achievable resolution of the calibrated SAR ADC was
evaluated from MATLAB Monte Carlo simulations for different
unit capacitor values, and is shown in Fig. 8. Capacitor mis-
match is based on the characterization data of the employed
130 nm CMOS technology. Each point in the plot represents the
average of 1000 independent simulations with a calibration time
of samples. A random (up to ) offset on each capacitor
has been added to simulate the effect of capacitor mismatch.
Thermal noise is added to the samples, whereas the comparator
noise is neglected in this analysis.
In the current implementation, a unit capacitor value of
70 fF has been chosen as a good trade-off between precision
and speed. The LMS based digital calibration improves the
resolution by about 11 dB (1.8 ENOB).
C. VLSI Circuit Implementation
In order to minimize the power consumption, the calibration
unit is only operating during start-up and is switched off after-
wards using clock gating. The digital circuitry is partitioned into
three main parts: the memory unit, the correction unit, and the
LMS update (or calibration) unit, as depicted in Fig. 7.
Two shift-registers, denoted as and , are employed at
the input to store the output decision of the comparator for
both the positive and the negative injected perturbation. In order
to correct the resolved sample, the capacitor weights and
the perturbation value are stored in the memory unit. The
correction unit loads the weight vector and adds them according
to (1). A SPI interface is used at the output to minimize the
number of required pads.
For minimum area occupation, no multipliers but only three
adders and shift operations are employed. The digital calibration
unit measures 0.156 , corresponding to 28.4 kGE (one gate
equivalent GE corresponds to a 2-input drive-1 NAND gate).
2690 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 62, NO. 11, NOVEMBER 2015

Fig. 12. Measured output spectrum before (blue) and after (black) calibration
without dithering with a 1.6 input signal at 1.98 kHz. ( points FFT).

Fig. 9. Micrograph of the stand-alone SAR ADC test chip with the most im-
portant sub-circuits marked. The digital circuitry is roughly divided in its main
blocks.

Fig. 13. Measured output spectrum before (blue) and after (black) calibration
with dithering with a 1.6 input signal at 1.98 kHz. ( points FFT).

Fig. 11 shows the ENOB versus Nyquist bandwidth where

Fig. 10. Measured INL and DNL before (blue) and after (black) calibration.
The inset highlights maximum INL and DNL.
Fig. 11. Trade-off of ENOB versus Nyquist bandwidth and power
consumption. Measurement results generated for the SAR ADC prototype
operated at different clock frequencies: 1) , 2)
3) , and 4) . The power consumption of the
SAR ADC core, denoted as , scales with . an EEG recording device with 256 channels [33] or a neural
IV. MEASUREMENT RESULTS OF THE SAR ADC
The proposed 14 bit SAR ADC has been fabricated in a
130 nm 1P8ML mixed-signal CMOS technology with MiM-ca-
pacitor option and a single 1.2 V supply. The chip micrograph
is shown in Fig. 9. The converter measures 0.42 , 52% of
which is occupied by the on-chip digital unit and about 14% by
the capacitor array. The static performance of the converter is
depicted in Fig. 10. The peak integral nonlinearity (INL) and
differential nonlinearity (DNL) are reduced from 9 LSB and
2 LSB respectively before calibration, to 0.7 LSB and 0.6 LSB
after calibration. The LSB is referred to a 14 bit integer number.
several measurements of the SAR ADC have been collected at
different converter clock frequencies . Since the power con-
sumption in the digital domain is dominant and proportional to
the clock frequency, the signal bandwidth that meets the spec-
ification for a given application scenario can be optimized by
pre-scaling . Furthermore, a slower clock frequency relaxes
the settling time of the capacitor array, allowing to reduce the
static power consumption of the reference buffers. The ADC
covers a Nyquist bandwidth of more than 1 MHz when running
at at an ENOB of 12.6. The Nyquist bandwidth
can be extended to 2 MHz , when the accu-
racy of the ADC is tuned to bit by disabling the number of
switching capacitors in the capacitor array. The Nyquist band-
width is increased in this measurement because the ADC is only
permitted to enter the reset state for only one clock cycle such
that a new conversion can start immediately (see Fig. 4 for fur-
ther explanation).
An increase of Nyquist bandwidth in the converter can be
beneficial in practice when using the ADC in a time-multi-
, plexed fashion to sample a large amount of input channels
in a multi-channel biomedical data acquisition ASIC, e.g., in
recording implant capable of simultaneously observing the
activity of more than one thousand neurons in the 0.1–6 kHz
frequency band [6], [34].
Fig. 12 shows the uncalibrated and calibrated output spectra
at 286 kS/s with no dither. A signal-to-noise-and-distortion ratio
(SNDR) of 79.1 dB can be achieved in practice which corre-
sponds to 12.9 ENOB. The SAR ADC core consumes 130 μ
at 16 MHz where 92 μ is consumed in the digital and 38 μ
in the analog domain, respectively. Enabling dithering by in-
jecting a zero-mean pseudo random sequence to the signal re-
sults in the spectrum shown in Fig. 13. With an oversampling
factor of 4 and , the achieved ENOB is 13.5.

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FATEH et al.: A RECONFIGURABLE 5-TO-14 BIT SAR ADC FOR BATTERY-POWERED MEDICAL INSTRUMENTATION
TABLE I
COMPARISON OF OUR SAR ADC WITH RECENTLY PUBLISHED MEDIUM-TO-HIGH PRECISION SAR ADCS
Fig. 14. Comparison of the FoM versus ENOB of the SAR ADC prototype
with the state-of-the-art (black dots). Different measurements are obtained by
disabling pairs of capacitors in the fully-differential capacitor array, starting with
the LSB. The ADC consumes 130 μ at 12.9 ENOB and 37 μ at 5.9 ENOB.
All measurements have been performed with the same clock and sampling fre-
quency of . Enabling the dithering sequence and over-
sampling, a resolution similar to [29] is achieved in practice.
Fig. 14 shows the FoM versus ENOB of the measured SAR
ADC prototype, where capacitors are disconnected from the
array while the ADC is forced into the reset state to trade the
resolution of the converter for power consumption. This mea-
surement has been again performed at . The
FoM is calculated as
Black dots represent recently published ADC implementations
listed in [35] with a resolution 14 bit and with a sampling
rate 80 MS/s. Most of the published ADCs are not reconfig-
urable and therefore optimized to achieve a certain resolution
for a constant Nyquist bandwidth and power consumption. For
this reason, their FoM is well optimized. However, they are not
able to trade power consumption for resolution as it is the case
in our converter solution where the power consumption is re-
duced by 70% when lowering the resolution from 14 down to
5 bit. In particular the ADC implementation proposed in [29]
that achieves an ENOB of 13.5, is interesting to be compared
with since our ADC achieves the same resolution with enabled
dithering sequence.
The performance comparison of our ADC SAR with other
recently published medium-to high-resolution ADCs is sum-
marized in Table I. The ADC implementations proposed in
[29]–[31] both achieve high sampling rates above 40 MS/s
but are nevertheless interesting in this comparison due to their
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2691
targeted resolution of above 13 bit. To achieve the desired
accuracy, the SAR ADC in [31] applies noise-shaped dithering
generated by a -modulator. Additional capacitors are used
in the MSB array to increase the SNR and in the LSB array for
correction of settling errors and to improve the SNR by aver-
aging. The SAR ADC prototype in [2] uses a 14 bit capacitor
array segmented into 4 bit unary MSB and 10 bit binary LSB
sections and similar to [17] performs dynamically multiple
comparisons for majority voting. In order to increase its reso-
lution, non-subtractive dither combined with oversampling is
applied, similar to our solution, as well as chopping to cancel
out noise and distortion. The SAR ADC implementation in [32]
consists of a 13 bit capacitor array with redundant elements.
The comparator runs in one of the two different modes, i.e.,
a low-power mode and an offset-compensated high-precision
mode. In contrast to our solution which uses all digital output
codes of the ADC for the start-up calibration, only some special
output codes are used to perform the calibration procedure.
When enabling the dithering sequence in our SAR ADC, we
achieve similar ENOB as reported in [29], and our proto-
type outperforms all other SAR ADCs in Table I by at least
0.8 ENOB.
V. MULTI-CHANNEL AFE
To verify the silicon performance of the reconfigurable SAR
ADC acquiring biopotential signals, the multi-channel AFE pre-
sented in [36] which employs a single-loop 3rd order modu-
lator with a 3-level quantizer is modified replacing the with
our SAR ADC implementation. The previous converter archi-
tecture had the main disadvantage that 3 out of 4 samples were
discarded to avoid cross-coupling effects given by the internal
state memory of the based ADC.
The main task of an AFE is to amplify biopotential signals
to an appropriate level for analog-to-digital conversion while
suppressing all unwanted signals such as electrode DC-offset,
mains interference, and circuit noise. Our multi-channel AFE, as
depicted in Fig. 15, has eight differential data acquisition chan-
nels with a maximum data rate of 8 kS/s that are time-multi-
plexed for data conversion. Reconfiguration in the SAR ADC
does not only optimize the power efficiency of the converter
but also of the biomedical ASIC, e.g., if less than eight channels
cover the needs for a specific application, the ADC can be recon-
figured to lower its sampling frequency . Thus, the non-used
channels can be deactivated. The resolution, bandwidth, and
power consumption for the remaining channels can be opti-
mized through the SAR ADC. Using a single converter which
is reconfigurable instead of multiple ADCs to record time-mul-
tiplexed multiple channels is not only advantageous in terms of
2692 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 62, NO. 11, NOVEMBER 2015

Fig. 15. Architecture block level diagram of our multi-channel biomedical data Fig. 16. Chip micrograph of the multi-channel biomedical data acquisition
acquisition system employing the proposed SAR ADC. ASIC employing the presented SAR ADC.

power consumption and silicon area but also in terms of gain

and offset mismatch between the channels.
With , the SAR ADC is able to cover all eight
channels. The ADC, however, is designed to operate even at
to either support more channels for future use
cases or provide more signal bandwidth per channel if desired.
Each channel consists of a variable-gain instrumentation ampli-
fier (IA) followed by a first order active RC low-pass filter. The
IA is chopper-stabilized to remove the flicker noise from the
signal band. Two current-mode DACs compensate DC-offset at Fig. 17. ECG signal with 60 BPM generated by Fluke ProSim 8 Vital Signs
the IA input: the first DAC removes the input referred offset of Patient Simulator and measured with the presented multi-channel biomedical
data acquisition ASIC.
the IA itself whereas the second, chopped DAC removes the dif-
ferential input offset caused by the electrode-to-skin contact.
VI. MEASUREMENT RESULTS OF THE INTEGRATED AFE
The presented SAR ADC has been integrated with a multi-
channel AFE in a biomedical data acquisition ASIC as shown
in Fig. 16. It has been implemented in a 130 nm CMOS tech-
nology and measures 2.27 . The signal quality achieved
by our data acquisition ASIC for a typical ECG signal with 60
beats per minute (BPM) is shown in Fig. 17, while Fig. 18 shows
the spectrum of the noise floor, where the input-referred (IR)
noise is 0.89 μ when integrating over the signal band-
width 1–100 Hz. Fig. 19 shows the effectiveness of the ADC
Fig. 18. Measured output noise floor of an electrode channel of the biomedical
calibration in the output spectrum of the biomedical ASIC. The data acquisition ASIC ( point FFT).
SFDR is enhanced by more than 20 dB after calibration. The
electrode input channels have a common-mode rejection ratio
(CMRR) of over 100 dB and an input impedance of 235
with the offset compensation DAC allowing for a high dynamic
range (DR) of 108 dB. The performance of the biomedical data
acquisition ASIC is summarized in Table II. The chip is com-
petitive with commercially available state-of-the-art biomedical
AFEs [37], [38] and consumes less power. Compared to the
multi-channel implementation discussed in [36], where a
modulator is used for digitizing the analog input signal, the SAR
ADC based AFE consumes 77% less power while achieving
similar performance.
VII. CONCLUSIONS Fig. 19. Measured output spectrum of the biomedical data acquisition ASIC
before (blue) and after (black) calibration with a 6 input signal at 11 Hz.
In this paper we have reported the design of a 5-to-14 bit ( points FFT).
reconfigurable sub-radix-2 SAR ADC in 130 nm CMOS.
The converter employs a non-uniform clocking scheme and when applying dithering. The converter covers a wide range
embeds fully integrated voltage reference buffers. A digital of potential biomedical applications ranging from EEG and
perturbation-based start-up calibration technique is, for the ECG to EMG and beyond. To demonstrate the effectiveness of
first time to our knowledge, implemented entirely on-chip. the proposed ADC, it has been integrated in a multi-channel
The ADC achieves 12.9 ENOB at 286 kS/s and 13.5 ENOB biomedical data acquisition ASIC.

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FATEH et al.: A RECONFIGURABLE 5-TO-14 BIT SAR ADC FOR BATTERY-POWERED MEDICAL INSTRUMENTATION
TABLE II
COMPARISON WITH STATE-OF-THE-ART AFE ASICS
For a signal bandwidth of 1–100 Hz.
Highest gain setting.
Power consumption of biomedical ASIC with a single active
channel. It consumes 3.5 mW when all eight analog channels are
activated.
ACKNOWLEDGMENT
The authors gratefully acknowledge the support of C. Zhang,
T. Kleier, N. Brun, M. Lanz, L. Müller, F. Tebbenjohanns,
F. Glaser, J. Treicher, T. Burger, R. Ulrich, and F. Gürkaynak.
REFERENCES
[1] A. Tzavaras and B. Spyropoulos, “Development of a low-cost wireless
monitoring system supporting the continuity of medical care of the pa-
tient at home,” in Proc. IEEE Eng. Med. Biol. Soc. Conf. (EMBC), Jul.
2013, pp. 5191–5194.
[2] P. Harpe, E. Cantatore, and A. van Roermund, “An oversampled
12/14 b SAR ADC with noise reduction and linearity enhancements
achieving up to 79.1 dB SNDR,” in IEEE ISSCC Dig. Tech. Papers,
Feb. 2014, pp. 194–195.
[3] T. A. Claasen, “Platform design: The next paradigm shift to deal with
complexity,” in VLSI Circuits Symp. Dig., Oct. 2003, pp. 8–12.
[4] H. Chang, L. R. Cooke, M. Hunt, G. Martin, A. McNelly, and L. Todd,
Surviving the SoC Revolution: A Guide to Platform-Based Design.
Norwell, MA, USA: Kluwer Academic, 1999.
[5] M. Yip and A. Chandrakasan, “A resolution-reconfigurable 5-to-10 b
0.4-to-1 V power scalable SAR ADC,” in IEEE ISSCC Dig. Tech. Pa-
pers, Feb. 2011, pp. 190–192.
[6] S. O'Driscoll, K. Shenoy, and T. Meng, “Adaptive resolution ADC
array for an implantable neural sensor,” IEEE Trans. Biomed. Circuits
Syst., vol. 5, no. 2, pp. 120–130, Apr. 2011.
[7] Z. Zhu, Z. Qiu, M. Liu, and R. Ding, “A 6-to-10-Bit 0.5 V-to-0.9 V
reconfigurable 2 MS/s power scalable SAR ADC in 0.18 CMOS,”
IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 3, pp. 689–696,
Mar. 2015.
[8] W. Liu, P. Huang, and Y. Chiu, “A 12-bit 45-MS/s 3-mW redundant
successive-approximation-register analog-to-digital converter with
digital calibration,” IEEE J. Solid-State Circuits, vol. 46, no. 11, pp.
2661–2672, Nov. 2011.
[9] Y.-Z. Lin, S.-J. Chang, Y.-T. Shyu, G.-Y. Huang, and C.-C. Liu, “A
0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS,” in
Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2011, pp.
69–72.
[10] W. Liu, P. Huang, and Y. Chiu, “A 12-bit 50-MS/s 3.3-mW SAR ADC
with background digital calibration,” in Proc. IEEE Custom Integr.
Circuits Conf., Sep. 2012.
[11] Y. Tao and Y. Lian, “A 0.8-V, 1-MS/s, 10-bit SAR ADC for multi-
channel neural recording,” IEEE Trans. Circuits Syst. I, Reg. Papers,
vol. 62, no. 2, pp. 366–375, Feb. 2015.
[12] J.-Y. Lin and C.-C. Hsieh, “A 0.3 V 10-bit 1.17 f SAR ADC with merge
and split switching in 90 nm CMOS,” IEEE Trans. Circuits Syst. I, Reg.
Papers, vol. 62, no. 1, pp. 70–79, Jan. 2015.
[13] S. Fateh, “Calibration techniques for digitally assisted Nyquist-rate
ADCs,” Ph.D. dissertation, Swiss Federal Institute of Technology,
Zurich, Switzerland, 2015.
[14] B. Murmann, “On the use of redundancy in successive approximation
A/D converters,” in Proc. Int. Conf. Sampling Theory Appl. (SampTA),
Jul. 2013.
Authorized licensed use limited to: Université de Montréal. Downloaded on March 28,2020 at 23:33:14 UTC from IEEE Xplore. Restrictions apply.
2693
[15] V. Hariprasath, J. Guerber, S. Lee, and U. Moon, “Merged capacitor
switching based SAR ADC with highest switching energy-efficiency,”
Electron. Lett., pp. 620–621, Apr. 2010.
[16] R. Wannamaker, S. Lipshitz, J. Vanderkooy, and J. Wright, “A theory
of nonsubtractive dither,” IEEE Trans. Signal Process., vol. 48, no. 2,
pp. 499–516, Feb. 2000.
[17] P. Harpe, E. Cantatore, and A. van Roermund, “A 10 b/12 b 40 kS/s
SAR ADC with data-driven noise reduction achieving up to 10.1 b
ENOB at 2.2 fJ/conversion-step,” IEEE J. Solid-State Circuits, vol. 48,
no. 12, pp. 3011–3018, Dec. 2013.
[18] A. Abo and P. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline
analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 34, no.
5, pp. 599–606, May 1999.
[19] J. L. McCreary, “Successive approximation analog-to-digital conver-
sion in MOS integrated circuits,” Ph.D. dissertation, Univ. California,
Berkeley, CA, USA, 1975.
[20] J. L. McCreary and P. R. Gray, “All-MOS charge redistribution analog-
to-digital conversion techniques—Part I,” IEEE J. Solid-State Circuits,
vol. 10, no. 6, pp. 371–379, Dec. 1975.
[21] I. Daubechies, R. DeVore, C. Gunturk, and V. Vaishampayan, “Beta
expansions: A new approach to digitally corrected A/D conversion,”
in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), 2002, vol. 2, pp.
784–787.
[22] M. Pilgrom, Analog-to-Digital Conversion. New York: Springer,
2013.
[23] D. P. M. Miyahara, Y. Asada, and A. Matsuzawa, “A low-noise self-
calibrating dynamic comparator for high-speed ADCs,” in Proc. IEEE
Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2008, pp. 269–72.
[24] H. Jeon and Y. Kim, “A CMOS low-power low-offset and high-speed
fully dynamic latched comparator,” in Proc. IEEE Int. Syst.-on-Chip
Conf., Sep. 2010, pp. 285–288.
[25] M.-H. Wu, Y.-H. Chung, and H.-S. Li, “A 12-bit 8.47-fJ/conver-
sion-step 1-MS/s SAR ADC using capacitor-swapping technique,” in
Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Dec. 2012, pp.
157–160.
[26] T. Sepke, “Comparator design and analysis for comparator-based
switched-capacitor circuits,” Ph.D. dissertation, Mass. Inst. Technol.,
Cambridge, MA, USA, 2006.
[27] M. Ahmadi and W. Namgoong, “Comparator power reduction in low-
frequency SAR ADC using optimized vote allocation,” in IEEE Trans.
Very Large Scale Integr. (VLSI) Syst., 2014.
[28] L. Bettini, T. Christen, T. Burger, and Q. Huang, “A reconfigurable
DT modulator for multi-standard 2G/3G/4G wireless receivers,”
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015, to be published.
[29] M. Hesener, T. Eichler, A. Hanneberg, D. Herbison, F. Kuttner, and H.
Wenske, “A 14 b 40 MS/s redundant SAR ADC with 480 MHz clock
in 0.13 CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp.
248–600.
[30] R. Kapusta, J. Shen, S. Decker, H. Li, E. Ibaragi, and H. Zhu, “A 14 b
80 MS/s SAR ADC with 73.6 dB SNDR in 65 nm CMOS,” IEEE J.
Solid-State Circuits, vol. 48, no. 12, pp. 3059–3066, Dec. 2013.
[31] T. Morie, T. Miki, K. Matsukawa, Y. Bando, T. Okumoto, K. Obata,
S. Sakiyama, and S. Dosho, “A 71 dB-SNDR 50 MS/s 4.2 mW CMOS
SAR ADC by SNR enhancement techniques utilizing noise,” in IEEE
ISSCC Dig. Tech. Papers, Feb. 2013, pp. 272–273.
[32] M. Ding, P. Harpe, Y.-H. Liu, B. Busze, K. Philips, and H. de Groot, “A
5.5 fJ/conv-step 6.4 MS/s 13 b SAR ADC utilizing a redundancy-fa-
cilitated background error-detection-and-correction scheme,” in IEEE
ISSCC Dig. Tech. Papers, Feb. 2015, pp. 1–3.
[33] X. Zou, W.-S. Liew, L. Yao, and Y. Lian, “A V 22 32-channel
implantable EEG recording IC,” in IEEE ISSCC Dig. Tech. Papers,
Feb. 2010, pp. 126–127.
[34] R. Harrison and C. Charles, “A low-power low-noise CMOS amplifier
for neural recording applications,” IEEE J. Solid-State Circuits, vol.
38, no. 6, pp. 958–965, Jun. 2003.
[35] B. Murmann, ADC Performance Survey—1997–2015 [Online]. Avail-
able: http://web.stanford.edu/murmann/adcsurvey.html
[36] P. Schönle, F. Schulthess, S. Fateh, R. Ulrich, F. Huang, T. Burger, and
Q. Huang, “A DC-connectable multi-channel biomedical data acqui-
sition ASIC with mains frequency cancellation,” in Proc. Eur. Solid-
State Circuits Conf. (ESSCIRC), 2013, pp. 149–152.
[37] Texas Instruments, “Low-power, 8-channel, 24-bit analog front-end for
biopotential measurements,” ADS1298 datasheet, 2012.
[38] Analog Devices, “Low power, five electrode electrocardiogram (ECG)
analog front end,” ADAS1000 datasheet, 2012.
2694 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 62, NO. 11, NOVEMBER 2015
Schekeb Fateh (S’03) received the M.S. degree
in electrical engineering from the Eidgenössische
Technische Hochschule (ETH) Zurich, Switzerland,
in 2009. In the same year, he joined the Integrated
Systems Laboratory (IIS) of ETH Zurich, where he
is currently pursuing his Ph.D. degree. His research
interests include the design of high-speed analog
and mixed-signal circuits and systems for wireless
communications with emphasis on analog-to-dig-
ital converters as well as the implementation of
multi-purpose low-power and miniaturized biomed-
ical devices. Currently, he is Researcher at IIS and Senior Design Engineer at
ACP AG. He received (jointly with Dr. Studer and Dr. Seethaler) the Swisscom
and ICTnet Innovations Award 2010 for the work on “VLSI Implementation
of Soft-Input Soft-Output Minimum Mean-Square Error Parallel Interference
Cancellation.”
Philipp Schönle received the B.Sc. and M.Sc. de-
grees in electrical engineering from the Swiss Fed-
eral Institute of Technology (ETH), Zurich, Switzer-
land, in 2009 and 2011, respectively. Currently, he is
working towards the Ph.D. degree in the Integrated
Systems Laboratory at ETH. His research focuses on
analogue sensor front-end design.
Luca Bettini (S’10) received the B.Sc. and the
M.Sc. degrees (cum laude) in electrical engineering
from Politecnico di Milano, Milan, Italy, in 2003
and 2006 respectively. Since 2010, he has been with
the Swiss Federal Institute of Technology (ETH)
Zurich, Zurich, Switzerland working toward the
Ph.D. degree. From 2006 to 2010, he was an Analog
IC Design Engineer at STMicroelectronics, Agrate
Brianza, Italy, designing embedded non-volatile
memories (PCM, EEPROM) for automotive and
consumer electronics applications. Since 2015, he is
a Senior Design Engineer at Advanced Circuit Pursuit (ACP), Zurich, working
on high-speed data converters for wireless transceivers. Mr. Bettini holds 3
U.S. patents.
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Giovanni Rovere received the M.S. degree in elec-
trical engineering from the University of Padova,
Padova, Italy, in 2013. He was a visiting student
at the Institute of Neuroinformatics, UZH-ETH,
Zurich, Switzerland. From 2013 to 2014 he was
an Asynchronous Digital Designer at the Italian
Institute of Technology, Italy, involved in the design
of a de/serializer for event-driven vision sensor
for robotic applications. He is currently working
towards the Ph.D. degree in the Integrated Systems
Laboratory at ETH, Zurich. His current research
focuses on biomedical acquisition systems, focusing on low power analog front
end.
Luca Benini is Full Professor at the University of
Bologna and he is the chair of Digital Circuits and
Systems at ETHZ. Dr. Benini’s research interests are
in energy-efficient system design and Multi-Core
SoC design. He is also active in the area of en-
ergy-efficient smart sensors and sensor networks for
biomedical and ambient intelligence applications.
He has published more than 700 papers in peer-re-
viewed international journals and conferences, four
books and several book chapters. He is a member of
the Academia Europaea.
Qiuting Huang received his Ph.D. degree in applied
sciences from the Katholieke Universiteit Leuven,
Belgium, in 1987. Between 1987 and 1992 he was
a lecturer at the University of East Anglia, Norwich,
U.K. Since January 1993, he has been with the In-
tegrated Systems Laboratory, Swiss Federal Institute
of Technology (ETH), Zurich, where he is Professor
of Electronics. In 2007 he was also appointed as
a part-time Cheung Kong Seminar Professor by
the Chinese Ministry of Education and the Cheung
Kong Foundation and has been affiliated with
the South East University, Nanjing, China. Prof. Huang’s research interests
span RF, analog, mixed analog-digital as well as digital application specific
integrated circuits and systems, with an emphasis on wireless communications
applications in recent years. He has published widely on those topics in leading
solid-state circuits conferences and journals.