OCTOBER 29, 2020

+3.3V DC POWER SUPPLY DESIGN

LAB 6

CLIFFORD GALLI
ECE 311
University of Idaho
Table of Contents
Objectives: .................................................................................................................................................... 2
Procedures .................................................................................................................................................... 2
Task 1: ....................................................................................................................................................... 2
Task 2: ....................................................................................................................................................... 2
Presentation of the Results....................................................................................................................... 3
Task 1: ....................................................................................................................................................... 3
Task 2: ....................................................................................................................................................... 5
Conclusion ..................................................................................................................................................... 7
In Lab Notes: ................................................................................................................................................. 8
Objectives:
The goal of this lab is to design a 3.3V. This requires working with the Linux operating system, using

Virtuoso, and circuit simulation. This will cover the basics of how Zener diodes can be used and can

replace standard diodes to manipulate AC waveforms. The first circuit is the Zener regulator, and the

second circuit it a full wave rectifier.

Procedures
This lab first required the completion of the preliminary requirements. This required that the circuits be

created in cadence. This is used to simulate the circuit behavior and record its values. The circuits are

also evaluated by hand.

Task 1:
In task 1 the Zener regulator is created in a protoboard. The real values of each element is recorded.
Measurements are then recorded for the load line (LL) ranging from 1% to 20%. The data is then
graphed

Task 2:
In task 2 the full wave rectifier is assembled on the protoboard using four of the diode 1N4002, Zener
1N5226 resistor, capacitor and Zener selected in the preliminary. The circuit is tested with varying
resistor value. Finally, the data is graphed.
Presentation of the Results
This lab was successful at creating the full wave and Zener regulator. The circuits operate correctly. As

the Vripple differs from spec %LL increases on the regulator. As the load resistance differs from spec, LR

increases. Diodes, capacitors, and resistors used will all effect the accuracy of the simulation results

when compared to the measurements. Due to element limitations it was impossible to achieve the

correct capacitor values. This caused the output voltage to be lower than 3.3V. Overall, the lab results

are as expected.

Task 1:
Theoretical Simulation Data
% Vripple Vripple(mV) VHL VLL Vin Vin %LL %change of input voltage
peak+ peak-
1% 64 3.298 3.2863 6.43 6.37 0% 1%
5% 320 3.3225 3.262 6.5583 6.2417 2% 5%
10% 640 3.3519 3.2251 6.716 6.08 4% 9%
15% 960 3.37 3.19 6.86 5.9375 6% 13%
20% 1280 3.4 3.15 7.03 5.76 8% 18%

%Vripple Vripple(mV) VHL VLL %LL %change of input voltage

1% 64 3.298 3.2863 0% 0%
5% 320 3.51 3.22 9% 9%
10% 640 3.77 3.41 11% 11%
15% 960 3.98 3.19 25% 25%
20% 1280 4.1 3.15 30% 30%
 Theoretical Trend
9%
8%
7%
6%
5%
%LL

4%
3%
2%
1%
0%
0% 5% 10% 15% 20% 25%
%Vripple

Measurment Trend
35%

30%

25%

20%
LL%

15%

10%

5%

0%
0% 5% 10% 15% 20% 25%
%Vripple
Task 2:
Value Theoretical Actual
RL 80.66 79.6
RS 50.9 50.6
C 793u 830u

Theoretical Data
R VNL VFL LR
80.66 3.597 3.335 8%
500 3.597 3.88 -7%
1000 3.597 3.92 -8%
1500 3.597 3.92 -8%
2000 3.597 3.925 -8%
2500 3.597 3.9 -8%
3000 3.597 3.93 -8%
3500 3.597 3.94 -9%
4000 3.597 3.944 -9%
5600 3.597 3.95 -9%

Measurement Data
R VNL VFL LR
74.232 2.82 2.4 18%
464 2.82 2.5 13%
980 2.82 2.55 11%
1523 2.82 2.6 8%
2000 2.82 2.66 6%
2532 2.82 2.7 4%
2950 2.82 2.76 2%
3470 2.82 2.77 2%
4230 2.82 2.78 1%
5560 2.82 2.82 0%
 LR Theoreical
10%
8%
6%
4%
2%
LR

0%
-2% 0 2 4 6 8 10 12

-4%
-6%
-8%
-10%
R

LR Actual
20%
18%
16%
14%
12%
LR

10%
8%
6%
4%
2%
0%
0 1000 2000 3000 4000 5000 6000
R
Conclusion

This lab effectively designed and measured the full wave, and Zener regulator. The data was effectively

collected with a number of methods and the error is reasonable. As the Vripple increases, the LL%

increases. As the resistance increases, the LR% decreases. Overall, the lab effectively analyzed a set of

zener circuits.
 In Lab Notes:
Setup:

• The proto board runs its nodes left to right on the inside and is all one node on the outsize runs.

• The voltage of the function generator source can be adjusted with number inputs rather than with the

dial.

• The oscilloscope needs to use the probes due to the DC voltage being applied. The oscilloscope cam be

damaged by a DC charge.

Task 1:

• As voltage ripple increases the LR% increases.

Task 2:

• As load resistance increases, the LR% decreases.

• Larger then expected error due to incorrect capacitor value

 Clifford Galli

Preliminary Lab 6

Lab #6: +3.3V DC Power Supply Design

1.)
a.) P=V*I
135mW=3.3*I
IL=40.9mA
RL=V/I
RL=3.3/40.9mA
RL=80.66

RL=80.66666667

b.) Iz is 20mA
RL is 40.9mA
Is=60.9mA
Rs=V/I
RS=(6.4-3.3)/60.9mA
Rs=50.9
c.)
 Hand Calc
Vout Power(mW) ILoad(mA) RL(Ω) RS Iz(mA) Is
3.3 135 40.90909091 80.66666667 50.9 20 60.90373281

Simulation

Is avg(mA) Iz avg(mA) Iload avg(mA) VHL VLL LL

61.13 20.35 40.73 3 .3519 3.2251 4%

% Vripple Vripple(mV) VHL VLL Vin Vin %LL %change of input

peak+ peak- voltage
1% 64 3.298 3.2863 6.43 6.37 0% 1%
5% 320 3.3225 3.262 6.5583 6.2417 2% 5%
10% 640 3.3519 3.2251 6.716 6.08 4% 9%
15% 960 3.37 3.19 6.86 5.9375 6% 13%
20% 1280 3.4 3.15 7.03 5.76 8% 18%

%change of input voltage

20%
18%
16%
14%
12%
LL%

10%
8%
6%
4%
2%
0%
0% 1% 2% 3% 4% 5% 6% 7% 8% 9%
%Change of input

2.) a.) Rmid=Vin/IS

Rmid=6.4/0.06113
Rmid=104.69

b.) Vripple=Vp/(R*C*F)
0.64=6.4/(Rmid*C*60)
C=793uF
c.)
R VNL VFL LR
80.66 3.597 3.335 8%
500 3.597 3.88 -7%
1K 3.597 3.92 -8%
2K 3.597 3.925 -8%
3K 3.597 3.93 -8%
4K 3.597 3.944 -9%
5.6k 3.597 3.95 -9%