Reliability Evaluation of Monolithic ICs

T. I. Båjenescu
Company for Consulting C.F.C., La Conversion, Switzerland
M. I. Bâzu
National Research Institute for Microtechnology I. M. T., Bucharest, Romania

ABSTRACT: The paper gives an overview of the present situation in the domain, the front line in the battle
for the best products. After a short introduction, the main problems arisen in reliability evaluation of
monolithic integrated circuits, the evaluation itself and some new points of view concerning the dynamic life
testing, screening and burn-in, accelerated tests, physics of failure of plastic encapsulated microcircuits
(PEM) and process reliability are presented. Characterization techniques for Hg1-xCdxTe epilayers are
mentioned.
1 INTRODUCTION now only some Fits in a single digit are required. It
is worthwhile to note the change in the predictions
The huge progress obtained in the integrated made by the Semiconductor Industry Association
circuit field led to smaller dimension electronic (SIA) in the editions 1994, 1995 and 1997 of the
equipment and reduced costs, but also to National Technology Roadmap for Semiconductors
improvements in power capability, reliability and [1][3]. From Table 1, one may see that the forecast
maintainability. The predictions are that the strong was overpassed by the reality: the performances
world-wide increase of computer and previewed in 1994 and 1995 for 1998 were attained
communication market will lead to an even higher earlier, in 1997.
growth rate of semiconductor industry in the next Basically, two types of integrated circuits were
decade, 20% per year, with a level of $300 billion developed since now: bipolar and MOS, taking into
immediately after the year 2000 [1]. account the basic cell: bipolar transistors or MOS
The complexity of ICs increased every year. In ones, respectively. In the beginning, the MOS ICs
fact, Gordon Moore, in the 70‘s, talked about a were n-channel MOS ICs or p-channel MOS ICs,
doubling of IC complexity every 18 months, with a but sooner complementary MOS ICs (or CMOS IC)
corresponding decrease in cost per function1. This including both types were developed. The main
became the so-called Moore’s Law, proved to be characteristic of CMOS circuits is the small supply
true for more than the subsequent twenty years. voltage. As the portable–electronics market
Many factors contributed to keeping this model on increases, low-power and low-voltage technologies,
course: the improvement of design tools and such as CMOS, became the most used. Also, the
manufacturing technologies, but also the permanent technological improvements leading to the remove
growth of the reliability level. The intrinsic of sodium contamination in the Si–SiO2 system
reliability of a transistor from an IC improved with encourage the use of CMOS ICs, because a high
two orders of magnitude (the failure rate decreases reliability level becomes possible to get. Recently
from 10-6h-1 in 1970, to 10-8h-1 in 1997). But also, in [4] reduced standard digital CMOS power supply
the same period of time, the number of transistors voltage of 3.3 V was obtained, reducing the power
per device increased with 9 orders of magnitude! consumption by 70%. These ULP (Ultra Low
Therefore, the IC reliability increased even faster Power) CMOS ICs were deeply investigated [4] and
than the prediction given by Moore’s Law. The proved to have a large potential.
model for reliability growth was called “Less’s The last challenge in the IC family is the
Law”, taking into account the known philosophy microsystem. Arisen in the early 90‘s, the
from the architectural design: “Less is More” [1]. microsystem represents a superior integration step
Actually, Less’s Law means a tremendous increase compared with common ICs: the “intelligent”
of the requirements for the IC’s failure rate: from element (the signal processing part) is integrated
1000 failures in 109 devices x hours (or 1000 Fits), with micro sensors and with micro actuators, in a
single component, basically still an IC [5]. In fact,
1 The cost per function is made up by two terms: aebN (increasing the microsystem is a “smart” sensor, able also to
with complexity [2] and representing the chip cost) and c/N actuate. This device determines the development of
(representing assembly and testing costs), where N is the number some new microtechnologies. Many disciplines
of functions and a, b, c are constants.
being involved, hybrid terms, such as: mechatronics,
 chemtronics, bioinformatics were used [6], but the
term microtechnology (technology of are MEMS (Micro-Electro-Mechanical Systems),
microfabrication) seems to be the most adequate. In BIO-MEMS (BIOlogical MEMS) and MEOMS
Europe, the term microtechnology includes both (Micro-Electro-Opto-Mechanical-Systems). Silicon
microelectronics (the “classical” devices) and is still the basic material and the CMOS technology
microsystem technology (MST) [12]. Other related can be used for the manufacturing.
terms

Table 1 Predictions for Si CMOS technology development: 1994, 1995 and 1997 editions of the National Technology Roadmap for Semiconductors

Year Minimum feature (µm) Lithography

1994 199 1997 1994 1995 1997

5
1995 0.35 0.35 - Optical Optical -
1997 - - 0.25 - - 248 nm
1998 0.25 0.25 - 248 nm 248 nm -
1999 - - 0.18 - - 248/193 nm
2001 0.18 0.18 - 248/193 248/193 nm -
nm
2003 - - 0.13 - - -
2004 0.13 0.13 - - - 193 nm
2006 - - 0.10 193 nm 193 nm -
2007 0.10 0.10 - - - -
2009 - - 0.07 - - -
2010 0.07 0.07 - - - -

Recently, a new term, nanotechnology, was
proposed, because the structures have now
characteristic features of a few nanometers.
Accordingly, the tools used for manufacturing these
new technologies (micro- and nano-) are called
micromachines and nanomachines, respectively.
A practical example of how a technology
improvement influences the IC features is given in
Fig. 2. The addition of copper to aluminium–copper
alloys used for metallisation allows to avoid the
electromigration (a well-known failure mechanism)
and to increase the current density. This tendency
was observed from 1982 till 1995. Further on, the
increase of the copper content produces a growth of
the resistivity, limiting the allowed current density
(see the Al–Cu line in Fig. 2). The solution seems to
be the use of copper as a supplementary
metallisation layer, over the Al–Cu layer (the dotted
line Cu/Al–Cu in Fig.2).
1.1 Modeling IC reliability
First, only simulators for one or two subsytems or
failure mechanisms were arise, such as: RELIANT
[14], only for predicting electromigration of the
interconnects and BERT EM [15]. Both use SPICE
for the prediction of electromigration by derivating
the current. Other electromigration simulators were
CREST [15], using switch-level combined with
Monte-Carlo simulation, adequated for the simula-
tion of VLSI circuits and SPIDER [16].
Other models were built for hot-carrier effects:
CAS [17] and RELY [18], based also on SPICE. An
important improvement was RELIC, built for three
failure mechanisms: electromigration, hot-carrier
effects and time-dependent dielectric breakdown
[19].
A high-level reliability simulator for
electromigration failures, named GRACE [20],
assured a higher speed simulation for very large ICs.
Compared with the previously developed simulators,
GRACE has some advantages [20]:
• an orders-of-magnitude speedup allows the
simulation of VLSI many input vectors;
• the generalised Eyring model [21] allows to
simulate the ageing and eventually the failure of
physical elements due to electrical stress;
• the simulator learns how to simulate more
accurately as the design progresses.
If the typical failure mechanisms are known, by
taking into account the degradation and failure
phenomena, models for the operational life of the
devices can be elaborated. Such models, in contrast
with the regular CAD tools determining only
wearout phenomena, predicts also the failures linked
to the early-failure zone.
A Monte-Carlo reliability [26] simulation for IC,
incorporating the effect of process-flaw, test
structure data, mask layout and operating
environmental conditions was proposed by Moosa
and Poole [13]. The device was divided into
subsystems (metallisation, gate oxide, wire bonds runs, vias, contacts), which may have various failure
and packaging), affected by various failure modes/mechanisms. The reliability-measures of the
mechanisms. Further on, these systems were divided objects are obtained by accelerated life testing on
into elementary objects (e.g. for metallisation: metal specially designed test
structure. Then the data are extrapolated at the subsystem and device level.

Table 2 Incidence of main failure mechanisms (in %) arising in infant mortality period

Failure Commercial circuits Memories Western Electric ICs

mechanism
TTL CMOS TTL Memories
(Beam (Wire
lead) bond)
Electrical 4 60 17 35 9
overcharge
Oxide defects 2 1 51 - 53
Surface 18 - 24 - -
defects
Connections 37 5 7 29 27
Metallisation 30 34 - 4 2
Various 9 - 1 22 9

Process
defect Layout
Defect generation
distribution
s

Failure Defect
distribution probabilitie
s s
Calculation of net fai-
lure probabilities

Annotated
netlist

System failure simulation

Fig. 1 Monte-Carlo reliability simulation procedure for ICs

The simulation procedure is detailed in Fig. 1.
This simulator was used for a two-layers metal
interconnect subsytem and the typical failure
mechanism was electromigration. The effect of
various grain size distributions and defect (voids)
size distributions was checked and the results
(given as cumulative failures vs. system failure
times) agree well with previously reported results.
2. RELIABILITY EVALUATION
2.1 Some reliability problems
From a theoretical viewpoint, a higher reliability
is expected for integrated circuits than for discrete
components. In practice, these expectations were
surpassed, because some basing conditions were
fulfilled:

• high level and automated industrial fabrication,

• constant quality materials, screening tests for
finished products.

Current density (mA/cm2)


0.7
Cu
0.5 Al
0.3
0.1 Year
1980 1985 1990 1995 2000 2005
Fig. 2 Evolution of the metallisation technology
corresponding allowed current densities
Before stating which type of integrated circuit is
adequate for a specific use, one must carefully
analyse the design, the most important parameters,
the dimensions, the costs and the limits imposed
by the reliability. Such studies must take into
account:
• a comparison of the total costs (development,
manufacturing and testing costs),
• a comparison of the important parameters
(resistor tolerances, temperature coefficient,
speed, voltage level) with limitations specific
to each type,
• an evaluation of the dissipated power of the
circuit and of the thermal resistance of the
encapsulated circuit, because an acceptable
temperature of the substrate must be assured.
2.2 Evaluation of integrated circuit reliability
Generally, three main problems arise at the eva-
luation of integrated circuit reliability.
1. For modern devices, the failure rates decrease
under a certain limit and the conventional methods
become less usable. To overcome these
difficulties, two solutions may be discussed:
a) To perform on a very high number of integrated
circuits reliability tests in normal operational
conditions, with the duration of a couple of years.
Obviously, this solution is unacceptable. As an
example, if one has to test a failure rate of 10-9h-1
(called also 1 FIT), 1000 devices must be tested
for 114 years and only one device to be found
defect.
b) To perform on some integrated circuits
reliability tests in higher than normal
conditions, the so-called accelerated tests. This
method may be applied only if at the
accelerated tests the failure mechanisms are the
same as for normal operational conditions. And
this fact must be indubitably demonstrated.
The accelerated tests are used in the purpose to
obtain quickly and with a minimum of expense
information about the reliability of the product.
The used stresses are higher than for normal
operational conditions, the results are extrapolated
and the fai-lure rate for normal conditions is
obtained. Usually, the accelerated tests contain
combinations of stres-ses such as: temperature,
bias, pressure, vibrations, etc. [11]. If the
temperature is the only variable of the accelerated
tests, the Arrhenius model may be used. To obtain
reliable results, relatively short tes-ting times must
be used2. So, using various levels of the same
stress factor one may follow the real behaviour3.
The analysis of the physico–chemical process
leading to failure allows obtaining the correlation
and between the speed of these phenomena and the
stress and, as a result, the real dependence of time
to failure on stress levels.
2. The rapid development of the manufacturing
technology for integrated circuits, needed by the
aim to improve the control and to reduce the costs,
makes difficult the reliability evaluation. Usually,
any modification in the technology or used
materials is followed by the appearance of a new
failure mechanism. Consequently, any
manufacturing mo-dification must include a new
reliability evaluation.
3. The last problem is linked to the increasing
complexity and costs of integrated circuits vs.
discrete devices. Although the cost of a certain
electronic function decreases substantially by
integration, the basic costs are always higher for an
integrated circuit than for a discrete component
fulfilling the same function.
The definition of the failure criteria is,
unavoidably, very difficult because the complexity
of ICs is increasingly higher. Even for a simple
device, like a transistor, it is hard to define the
failure limits. For an integrated circuit, the basic
parameters are more complex and hard to be
measured and the degradation of these parameters
differs from an utilisation to another.
For evaluating the various stresses able to be
used in reliability accelerated tests, the following
aspects must be taken into account [7][8]:
• The stress must be encountered in the
operational environment. In principle, one
must note that the failure rate of integrated
circuits is influenced by the thermal, electrical
and mechanical conditions of the operational
environment. But for common industrial use,
mechanical shock and vibrations have a little
influence on the integrated circuits
encapsulated in epoxy packages, able to assure
the necessary mechanical stability and a good
protection. For instance, the acceleration
measured at a sudden stop of a running car
2 Even if the purpose is to minimise the testing time, a too stron-
ger stress level must not be used, because new failure mecha-
nisms may be induced.
3 If the time is the accelerated variable, this means that an hour of
tests at high stress level produces the same effect on the com-
ponent reliability as n hours at normal operation time.
 reaches 40g, for airplanes take-off and landing
– up to 5g and for missiles – up to 50g.
Compare these values with the acceleration
level used for periodic tests: 30,000g.
Consequently, mechanical factors will be used
only rarely for accelerated tests. On the
contrary, the temperature is the most used
stress for this kind of tests. The experimentally
observed correlation between failure rate and
temperature is based on the fact that the speed
of chemical reactions arising in the device is
thermally increased.
• The failure mechanisms must be always those
arising in the operational environment.
• All samples of integrated circuits used in
accelerated tests must behave in the same way
at a stress modification: the same circuits
should be the first to fail at any stress level.
3 DYNAMIC LIFE TESTING
The failure of an IC in operational life is an
unpleasant event not only because the owner of the
equipment must replace it, but also because this
failure may induce serious damages to the equip-
ment, loss of important information or even of
human life. Therefore, it is desirable to replace a
IC before failure. From economical reasons, this
replacement must take place shortly before the
anticipated failure. This implies that the lifetime of
the IC be accurately estimated. This operation may
be done only if laboratory tests simulating as
closed as possible the real operational life are
performed. In this respect, in the laboratory, not
only static, but also dynamic testing must be done.
The purpose is to quantify the performance
degradation during IC operation. An example of
such testing is given by Son and Soma [9]. First,
the IC parameters which will be monitored during
dynamic life testing are chosen by two criteria: (i)
to be measurable at existing pin-outs, and (ii) to
predict progressively IC degradation. Than, the
typical failure and degradation mechanisms must
be studied. In fact, there are two major types of
degradation mecha-nisms: electrical ones (such as:
latchup, ESD, hot-carrier effect, dielectric break-
down, electro-migra-tion, etc.) and environmental
ones (produced by thermal and mechanical stress,
humidity, etc.). By means of appropriately chosen
electrical para-meters (such as: static / transient
current level change, noise level in current, cut-off
frequency, input offset voltage of CMOS
differential amplifier, etc.), these mechanisms are
monitored during dyna-mic life testing.
Eventually, aging models for various failure
mechanisms must be elaborated. In [9] a model for
hot-carrier effect is given. Starting from a widely
accepted empirical relationship between parameter
deviation and the elapsed stress time for the hot-
carrier degradation mechanism, given in [10], an
aging curve due to hot-carrier effect under the
static or periodically repeated AC stress was
obtained [9], defined by the equations:
∆V/Vo = k · ta (1)
k = C · [Ids/w · exp(-Φ√i/(q· p ·Ech))]a (2)
where C is a constant, a and k are coefficients of
the aging curve (depending on the technology and
on IC structure), Ids is the drain current, w is the
channel width of a MOS transistor, Φi - the
minimum energy required to cause impact
ionization, q - the electron charge (1.6 x 10-19C), p
– the hot electron mean free path, Ech – the channel
electric field, ∆V/Vo – circuit aging and t –
elapsed stress-time. In a log(∆V/Vo) vs. log t plot,
a straight line with slope a and y-intersection log k
is obtained (see Fig. 3).
log(∆V/Vo)
slope = a
log k
log t
Fig. 3 A log (∆V/Vo) vs. log t plot for hot-carrier degradation
mechanism
From the case study given in [9], one may
understand the procedure for IC replacing before
to occur a failure by hot-carrier effect. For a 31-
stage inverter chain, designed according to MOSIS
0.8 µm HP technology rules, the device operation
was simulated, the ageing being modeled by
randomly changing device parameters. Based on
this model, the probability of survival until the
next inspection may be quantified at each
inspection of dynamic-life testing. Then, the
optimal moment for replacement may be
calculated with respect to maintenance cost (the
recovery cost of an unanticipated failure and the
wasted cost of replacing an IC too early).
4 SCREENING AND BURN-IN
To better understand the role of screening tests
for the reliability estimation, it will be given an
example concerning the failure causes. Assume
that a printed circuit board (PCB) has 60
integrated circuits (ICs), and the probability of
failure for an IC is 2%; it is considered that all
the ICs are statistical independent. It results that
the probability to find at least one defect IC is 1
- 0.9860 = 0.7. Some reasons can lead to
 components failures; for example, if the
components are very old, or if they are
overloaded. In these cases, the screening tests
have no sense. Other defects result from the
intrinsic weaknesses of the components. These
weaknesses are surely unavoidable and - for
very good defined li-mits - are accepted even by
the manufacturing. With the aid of electrical
tests and/or operating tests (during the
fabrication or before the delive-ring) these
components with defects can be identified and
eliminated. Nevertheless it remains a small
percentage4 of components with hidden defects
which - although still operational - have a small
reliability and influence negatively the reliability
of the components batch. The role of the
screening tests is to identify the components
partially unreliable, with defects that do not lead
immediately to non-operation.
For at least two reasons it is difficult to define a
cost-effective screening sequence, while: (i) it may
activate failure mechanisms that would not appear
in field operation; (ii) it could introduce damage
(transients, electrostatic discharges ESD) which
may be the cause of further early failures.
Generally, the selection is a 100% test (or a
combination of 100% tests), the stress factors being
the temperature, the voltage, etc. followed by a
parametric electrical or functional control
(performed 100%), with the aim to eliminate the
defect items, the marginal items or the items that
will probably have early failures (potentially
unreliable items). To overcome these problems,
recently, a method was proposed [13]. The method
was called MOVES, an acronym for Monitoring
and Verifying a Screening sequence. MOVES
contains five procedures, namely VERDECT,
LODRIFT, DISCRIM, POSE and INDRIFT.
By definition, an accelerate test is a trial during
which the stress levels applied to the components
are superior to these foreseen for operational level;
this stress is applied with the aim to shorten the
necessary time for the observation of the
component behavior at stress.
2 ACCELERATED TESTS
The first accelerated tests were made in the
early 60’s and tried to shorten the time period
necessary to obtain significant results from life
tests. The failure mechanisms must be investigated
4 It is considered that the early failures vary between 1% and 3%
for SSI/MSI ICs, and respectively between 4% and 8% for LSI
ICs [2.2]. The defective probability of a PCB with about 500
components and 3,000 solder joints can have the following
average values: 1-3% defective PCBs (1/3 assembling, 1/3
defective components, 1/3 components out of tolerance) and 1.2
to 1.5 defects per defective PCB.
with great care, because it is essential that the
failure mechanism acting at the higher stress level
to be the same with that acting at normal stress
level. Lately, two tendencies were observed: the
increase of the stress level and accelerated tests
performed early on the manufacturing process
(even at the wafer level). The main problems
which must be solved in the next years are: (i) the
identifying of the accelerated laws with different
stress factors; (ii) the taking into account at the
design of the accelerated tests of the synergies
between the stress factors encountered in the
operational environment [14]; and (iii) the
dependency of the activation energy on the stress
level.
3 PHYSICS OF FAILURE
The failure mechanism identification is
essential for the reliability accelerated testing,
because the obtained degradation laws must be
extrapolated beyond the time period of the test and
the extrapolation must be made separately for each
population affected by a failure mechanism. The
subject is still modern, taking into account that
new failure mechanisms are discovered and even
the old ones are not completely examined.
Consequently, a series of tutorial papers on failure
mechanisms were published from 1973 by IEEE
Transactions on Reliability, almost in each issue.
Most of these papers were written by the research
team led by Michael Pecht, from Maryland
University (USA). Trends in microsystems
(integrating electronic, micro-electro-mechanical,
electro-optical and micro-fluidic devices) are
taking miniaturization close to its physical limits
and creating a need for extensive reliability
physics effort to identify and counter failure
mechanisms in new devices [14].
4 PLASTIC ENCAPSULATED MICROCIRCUITS
(PEM)
The great effort made for reliability evaluation
is best by PEM. Also, the current use of these
devices is an example of reliability engineering
responding to both technology trends and customer
policies [5]. The Acquisition Reform policy
encouraged U. S. Military to use PEM over other
packages. On the technical side, user of PEM are
employing Highly Accelerated Stress Testing
(HAST) and acoustic microscopy to screen out
flawed devices. While the reliability of PEM is
constantly impro-ving, the variability between
suppliers remains a problem [16].
5 RELIABILITY PREDICTION
In the concurrent engineering era, Reliability
Prediction Procedures (RPP) are valuable tools for
designers and users of any product. The designer
needs RPP to avoid the lag in feedback occurring
when the predictions are made by a reliability
team. The user, which in turn is a designer of a
complex system, wants to have correct information
about the part reliability. All the usual RPP (the
most known being MIL-HDBK-217) have some
common features which diminish the prediction
accuracy:
(i) a constant failure rate model is used;
(ii) the failure mechanisms (FM) are not
analysed. Lately, improved RPP - with failure rate
models other than the exponential and starting
from the physics of failure - were considered
desirable and as "a change in direction for
reliability engineering" [15]. In 1995, an improved
methodology, called SYRP, for predicting the
failure rate of a lot was proposed, with the
following characteristics: (a) a log-normal
distribution for each FM used involved, and (b) the
interaction (synergy) between the technological
factors, depending on the manufacturing and
control techniques, is considered.
6 CHARACTERIZATION TECHNIQUES FOR
MERCURY CADMIUM TELLURIDE
EPILAYERS
The approach of p-on-n junctions in a
heterostructure configuration with extrinsic p-type
and n-type doping for photovoltaic devices [27]
has taken a critical role in the long-wavelength IR
(LWIR) technology based on a Hg1-xCdxTe. The
effect of the acceptor species diffusion commonly
observed is the difficulty in achieving precise
control of the electrical junction which in turn
translates into nonuniform and nonreproducible
device performance. Lacking suitable
characterization techniques, the heterojunction
cannot be evaluated, and the effects of As
implant/diffusion on the composition of the
material at various depths cannot be studied. In
addition, the electrical activation of the p-type
species in a p-on-n structure cannot be assessed
because of the high carrier mobility ratio (~200) in
HgCdTe.
The dissertation [27] reports on the study of As
diffusion mechanism in HgCdTe grown by
metalorganic chemical vapor deposition
(MOCVD-IMP) technique from an ion-implanted
source and on application of the resultant findings
to the As diffusion from a grown source. A
diffusion model was developed from a chemical
analysis (secondary ion mass spectroscopy –
SIMS) and a Gaussian theoretical modeling. The
nature of p-type species diffusion mechanism and
associated components was investigated. The most
desired mechanism found in the controlled atomic
vacancy-based component in which As starts on
the Te-sublattice. The dislocation density and
distribution as the main cause for the
uncontrollable enhancement of As diffusion in the
tailing components was demonstrated. It was
found that the proper choice of ion implantation
and anneal conditions helped reduce the tails of the
implantation and anneal conditions helped reduce
the tails of the diffusion profiles for a given
dislocation density in the material. High
performance of p-on-n photodiodes, at 77K and at
40K, limited by thermal processes, was
demonstrated. Also reported is a very sensitive
novel technique which was developed for
analyzing the relative variations of material
composition, and for quantitatively measuring the
absolute value of composition at various depth.
This technique is based on matrix effects on Te-
electronegative ion yield which occurs in SIMS
when a reactive primary ion beam of Cs is used.
Another novel technique was developed to
measure the p-type carrier concentration in a p-on-
n structure, which was differential Hall effect
analysis of the p-type region after the entire
structure is converted into p-type by a Hg-vacancy
anneal at low temperatures.
A reliability study is on the point to be realized.
10 CONCLUSIONS
This overview showed the dynamic in the field
of the evaluation of monolithic integrated circuits
reliability. Starting from some reliability problems,
the main aspects arisen in dynamic life testing,
screening and burn-in, accelerated tests, physics of
failure of plastic encapsulated microcircuits (PEM)
and process reliability were presented.
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