Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
ON
SUBMITTED BY
ZATIN GUPTA
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INDEX
Acknowledgement
DTMF Signal
Embedded System
Microcontroller
Introduction to Project
Hardware used
DTMF Decoder IC
Microcontroller IC
ULN IC
Software used in Project
Testing
Hardware testing
Software testing
Application of project
Further work
Reference
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Acknowledgement
ZATIN GUPTA
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DTMF Signal
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connected directly to that end office, yet the
signaling would work over any sort of link. This idea
of using the existing network for signaling as well as
the message is known as in-band signaling. DTMF
tones were also used by some cable television
networks to signal the local cable company to insert
a local advertisement. These tones were often heard
during a station ID preceding a local ad inserts.
Terrestrial television stations also used DTMF tones
to shut off and turn on remote transmitters.
Keypad
When you press the buttons on the keypad, a
connection is made that generates two tones at the
same time. A "Row" tone and a "Column" tone. These
two tones identify the key you pressed to any
equipment you are controlling. If the keypad is on
your phone, the telephone company's "Central
Office" equipment knows what numbers you are
dialing by these tones, and will switch your call
accordingly.
1 2 3 697 Hz
4 5 6 770 Hz
7 8 9 852 Hz
* 0 # 941 Hz
1209 Hz 1336 Hz 1477 Hz
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When you press the digit 1 on the keypad, you
generate the tones 1209 Hz and 697 Hz. pressing the
digit 2 will generate the tones 1336 Hz and 697 Hz.
Sure, the tone 697 is the same for both digits, but it
take two tones to make a digit and the telephone
company's equipment knows the difference between
the 1209 Hz that would complete the digit 1, and a
1336 Hz that completes a digit 2.
Low High
Event
frequency frequency
Busy signal 480 Hz 620 Hz
Dial tone 350 Hz 440 Hz
Ring back tone (US) 440 Hz 480 Hz
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volume or louder as the low frequencies when sent
across the line. The loudness difference between the
high and low frequencies can be as large as 3
decibels (dB) and is referred to as "twist".
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Embedded system
A hardware system which is designed to perform
a specific task in a particular time period, e.g.
mobile phones
Hardware
Input & Output
Software
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Software’s Hardware’s
Machine language Digital IC’s (driver,
decoder, MUX)
Assembly language linear IC’s (op amp,
ADC, DAC, comparator)
High level language Passive components
(L, C, R’s)
C, C++, java PCB, Relays,
Motors
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Cell-phone a very common example of embedded
system
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Industrial process controllers &
avionics/defense
Applications…
Computer/Communication products, e.g.,
printers, FAX Machines…
Emerging multimedia applications & consumer
electronics e.g. cell phones, personal digital
assistants…
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Microcontroller
µC 8051
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Micro-controller can be of following types
4 – Bit microcontroller
8 – Bit microcontroller
16 – Bit microcontroller
32 – Bit microcontroller
4 – BIT MICROCONTROLLERS
8 – BIT MICROCONTROLLERS
16 –BIT MICROCONTROLLERS
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Applications: control of servomechanism like
robot arms
32 – BIT MICROCONTROLLERS
8052 MICROCONTROLLER
Has all the features of 8051 along with extra
128 bytes of RAM, a timer and an extra 4K bytes of
on chip ROM
8051 is upward compatible to 8052
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8031 MICROCONTROLLER
ROM-less 8051 i.e. contains 0 K bytes of on chip
ROM
An external ROM must be added to make it
functional.
VERSIONS OF 8051 µC
8751 microcontroller
4K bytes of on chip UV-EPROM require PROM burner,
as Ill as UV-EPROM to erase its contents and takes 20
min erase cycle.
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DS5000 from Dallas Semiconductor
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Introduction to Project
Title
“A2Z RoBo”
Hardware used
DTMF decoder IC
One Microcontroller
ULN IC
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Brief overview of peripherals attached
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CIRCUIT DIAGRAM
Power supply
DTMF Decoder
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DTMF decoder IC
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Pin Description
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11-14 Q1, Q2, Q3, Q4 Tri-statable data outputs.
When enabled by OE, provides the code
corresponding to the last valid tone pair Received.
15 StD Delayed steering output. Presents logic
high when a received tone pair has been registered
and the output latch is updated. Returns to logic low
when the voltage on St/GT falls below VTSt
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Microcontroller
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Pin Description
VCC
Supply voltage.
GND
Ground
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port.
As an output port, each pin can sink eight TTL
inputs. When 1s are written to port 0 pins, the pins
can be used as high impedance inputs. Port 0 can
also be configured to be the multiplexed low order
Address/data bus during accesses to external
Program and data memory in this mode, P0 has
internal Pullups. Port 0 also receives the code bytes
during Flash programming and outputs the code
bytes during program verification. External pullups
are required during program verification.
Port 1
Port 1 is an 8-bit bidirectional I/O port with internal
pullups. The Port 1 output buffers can sink/source
four TTL inputs. When 1s are written to Port 1 pins,
they are pulled high by the internal pullups and can
be used as inputs. As inputs, Port 1 pins that are
externally being pulled low will source current (IIL)
because of the internal pullups. In addition, P1.0
and P1.1 can be configured to be the timer/counter
2 external count input (P1.0/T2) and the
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Timer/counter 2 trigger input (P1.1/T2EX),
respectively, as shown in the following table. Port 1
also receives the low-order address bytes during
Flash programming and verification.
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal
pullups. The Port 2 output buffers can sink/source
four TTL inputs. When 1s are written to Port 2 pins,
they are pulled high by the internal pullups and can
be used as inputs. As inputs, Port 2 pins that are
externally being pulled low will source
Current (IIL) because of the internal pullups Port 2
emits the high-order address byte during fetches
from external program memory and during accesses
to external data memory that use 16-bit addresses
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(MOVX @ DPTR). In this application, Port 2 uses
strong internal pullups when emitting 1s. During
accesses to external data memory that uses 8-bit
addresses (MOVX @ RI); Port 2 emits the contents of
the P2 Special Function Register.
Port 2 also receives the high-order address bits and
some control signals during Flash programming and
verification.
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal
pullups. The Port 3 output buffers can sink/source
four TTL inputs. When 1s are written to Port 3 pins,
they are pulled high by the internal pullups and can
be used as inputs. As inputs, Port 3 pins that are
externally being pulled low will source current (IIL)
because of the pullups. Port 3 also serves the
functions of various special features of the AT89S52,
as shown in the following table. Port 3 also receives
some control signals for Flash programming
And verification
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P3.7 RD (external data memory read
strobe)
RST
Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the
device. This pin drives High for 96 oscillator periods
after the Watchdog times out. The DISRTO bit in SFR
AUXR (address 8EH) can be used to disable this
feature. In the default state of bit DISRTO, the
RESET HIGH out feature is enabled.
ALE/PROG
Address Latch Enable (ALE) is an output pulse for
latching the low byte of the address during accesses
to external memory. This pin is also the program
pulse input (PROG) during Flash programming. In
normal operation, ALE is emitted at a constant rate
of 1/6 the oscillator frequency and may be used for
external timing or clocking purposes. Note, however,
that one ALE pulse is skipped during each access to
external data memory. If desired, ALE operation can
be disabled by setting bit 0 of SFR location 8EH.
With the bit set, ALE is active only during a MOVX or
MOVC instruction. Otherwise, the pin is weakly
pulled high. Setting the ALE-disable bit has no
Effect if the microcontroller is in external execution
mode.
PSEN
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Program Store Enable (PSEN) is the read strobe to
external program memory. When the AT89S52 is
executing code from external program memory,
PSEN is activated twice each machine cycle, except
that two PSEN activations are skipped during each
access to external data memory.
EA/VPP
External Access Enable EA must be strapped to GND
in order to enable the device to fetch code from
external program memory locations starting at
0000H up to FFFFH. Note, however, that if lock bit 1
is programmed, EA will be internally latched on
reset. EA should be strapped to VCC for internal
program executions. This pin also receives the 12-
volt programming enable voltage (VPP) during Flash
programming.
XTAL1
Input to the inverting oscillator amplifier and input
to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier
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ULN 2004A IC
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Logic Diagram
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Pin Description
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SOFTWARE USED IN THE PROJECT
;***********************************************************
; NAME OF THE PROGRAMMER: ZATIN GUPTA
; STATUS: DEVELOPING
;******************HARDWARE DECALARATION*************
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relay2 bit p2.2
relay3 bit p2.1
relay4 bit p2.0
signal equ p1
;**********************POWER ON*****************************
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mov P0,#0FFh ;PORT0 SHOULD BE
INTIALLY HIGH
mov P1,#0ffh ;PORT1 SHOULD BE
INTIALLY HIGH
mov P2,#0FFh ;PORT2 SHOULD BE
INTIALLY HIGH
mov P3,#0ffh ;PORT3 SHOULD BE
INTIALLY HIGH
;********************RAM_CLR ROUTINE********************
mov r0,#7fh
ram_clr: mov @R0,#00H
DJNZ R0,ram_clr
;*********************MAIN
PROGRAM***************************
acall delay
main:
mov a,signal
anl a,#00011110b
cjne a,#0001110b,check1
mov p2,#11110001b
acall delay
sjmp main
check1:
acall delay
mov a,signal
anl a,#00011110b
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cjne a,#00000010b,check2
mov p2,#11111000b
acall delay
sjmp main
check2:
acall delay
mov a,signal
anl a,#00011110b
cjne a,#00010010b,check3
mov p2,#11110010b
acall delay
sjmp main
check3:
acall delay
mov a,signal
anl a,#00011110b
cjne a,#00011010b,check4
acall delay
sjmp main
check4:
acall delay
mov a,signal
anl a,#00011110b
cjne a,#00001010b,check5
mov p2,#11110100b
acall delay
sjmp main
check5:
acall delay
mov a,signal
anl a,#00011110b
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cjne a,#00000110b,exit
mov p2,#11110000b
acall delay
sjmp main
exit:
acall delay
sjmp main
;**************************DELAY****************************
delay:
mov r1,#100d
again: mov r2,#100d
back: mov r3,#20d
loop: djnz r3,loop
djnz r2,back
djnz r1,again
ret
;*****************************END**************************
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HARDWARE TESTING
WITHOUT IC
Continuity in between
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Vcc=5v
Gnd=0v
Reset=0v initial & 5v pressed
EA=5v
WITH IC
Vcc=5v
Gnd=0v
Reset= low-high-low
EA=5v
Crystal Oscillator: in this there are 2 parameters as
below
Voltage
Frequency
Voltage at 18 & 19 pin <=2v
Frequency=11.0592MHz
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SOFTWARE TESTING
RELAYS
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delay:
MOV R5,#20d
lp2: MOV R6,#200d
lp1: MOV R7,#250d
lp0: djnz R7,lp0
djnz R6,lp1
djnz R5,lp2
Ret
delay:
MOV R5,#20d
lp2: MOV R6,#200d
lp1: MOV R7,#250d
lp0: djnz R7,lp0
djnz R6,lp1
djnz R5,lp2
Ret
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For Third relay
delay:
MOV R5,#20d
lp2: MOV R6,#200d
lp1: MOV R7,#250d
lp0: djnz R7,lp0
djnz R6,lp1
djnz R5,lp2
Ret
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mov relay,#0fbh
acall delay
mov relay,#0fdh
acall delay
mov relay,#0feh
acall delay
sjmp main
delay:
MOV R5,#20d
lp2: MOV R6,#200d
lp1: MOV R7,#250d
lp0: djnz R7,lp0
djnz R6,lp1
djnz R5,lp2
Ret
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APPLICATION OF PROJECT
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FURTHER WORK
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REFERENCE
Websites
www.google.com
www.emtech.in
www.howstuffworks.com
www.alldatasheet.com
www.dogpile.com
www.electroguys.com
www.wikipedia.com
www.efy.com
Books
Mazidi
Programming & customizing the PIC &
microcontrollers ( e-book)
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