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Electronic Principles
Eighth Edition
Chapter 1 Introduction us more insight into how changes in load resistance affect the
load voltage.
SELF-TEST 12. It is usually easy to measure open-circuit voltage and shorted-
1. a 7. b 13. c 19. b load current. By using a load resistor and measuring voltage
2. c 8. c 14. d 20. c under load, it is easy to calculate the Thevenin or Norton
3. a 9. b 15. b 21. b resistance.
4. b 10. a 16. b 22. b
5. d 11. a 17. a 23. c PROBLEMS
6. d 12. a 18. b
1-1. Given:
V = 12 V
JOB INTERVIEW QUESTIONS RS = 0.1 Ω
Note: The text and illustrations cover many of the job interview
Solution:
questions in detail. An answer is given to job interview questions
only when the text has insufficient information. RL = 100RS
RL = 100(0.1 Ω)
2. It depends on how accurate your calculations need to be. If RL = 10 Ω
an accuracy of 1 percent is adequate, you should include the
source resistance whenever it is greater than 1 percent of the Answer: The voltage source will appear stiff for values of
load resistance. load resistance of ≥10 Ω.
5. Measure the open-load voltage to get the Thevenin voltage 1-2. Given:
VTH. To get the Thevenin resistance, reduce all sources to
RLmin = 270 Ω
zero and measure the resistance between the AB terminals to
RLmax = 100 kΩ
get RTH. If this is not possible, measure the voltage VL across
a load resistor and calculate the load current IL. Then divide Solution:
VTH – VL by IL to get RTH. RS < 0.01 RL (Eq. 1-1)
6. The advantage of a 50 Ω voltage source over a 600 Ω voltage RS < 0.01(270 Ω)
source is the ability to be a stiff voltage source to a lower RS < 2.7 Ω
value resistance load. The load must be 100 greater than the
internal resistance in order for the voltage source to be con- Answer: The largest internal resistance the source can
sidered stiff. have is 2.7 Ω.
7. The expression cold-cranking amperes refers to the amount 1-3. Given: RS = 50 Ω
of current a car battery can deliver in freezing weather
when it is needed most. What limits actual current is the Solution:
Thevenin resistance caused by chemical and physical RL = 100RS
parameters inside the battery, not to mention the quality of the RL = 100(50 Ω)
connections outside. RL = 5 kΩ
8. It means that the load resistance is not large compared to the Answer: The function generator will appear stiff for
Thevenin resistance, so that a large load current exists. values of load resistance of ≥5 kΩ.
9. Ideal. Because troubles usually produce large changes in
voltage and current, so that the ideal approximation is ade- 1-4. Given: RS = 0.04 Ω
quate for most troubles. Solution:
10. You should infer nothing from a reading that is only
RL = 100RS
5 percent from the ideal value. Actual circuit troubles
RL = 100(0.04 Ω)
will usually cause large changes in circuit voltages. Small
RL = 4 Ω
changes can result from component variations that are still
within the allowable tolerance. Answer: The car battery will appear stiff for values of
11. Either may be able to simplify the analysis, save time when load resistance of ≥ 4 Ω.
calculating load current for several load resistances, and give
1-1
“Copyright © McGraw-Hill Education. Permission required for reproduction or display.”
RL = 0.01RS (Eq. 1-4)
RL = 0.01(100 kΩ)
RL = 1 kΩ (a) Circuit for finding VTH in Prob. 1-12. (b) Circuit for
Answer: The maximum load resistance for the current finding RTH in Prob. 1-12.
source to appear stiff is 1 kΩ.
1-13. Given:
1-10. Given:
VTH = 12 V
IS = 20 mA RTH = 2 kΩ
RS = 200 kΩ
RL = 0 Ω Solution:
Solution: I = V/R (Ohm’s law)
I = VTH/(RTH + RL)
RL= 0.01RS I0Ω = 12 V/(2 kΩ + 0 Ω) = 6 mA
RL= 0.01(200 kΩ) I1kΩ = 12 V/(2 kΩ + 1 kΩ) = 4 mA
RL= 2 kΩ I2kΩ = 12 V/(2 kΩ + 2 kΩ) = 3 mA
Answer: Since 0 Ω is less than the maximum load resis- I3kΩ = 12 V/(2 kΩ + 3 kΩ) = 2.4 mA
tance of 2 kΩ, the current source appea rs stiff; thus the I4kΩ = 12 V/(2 kΩ + 4 kΩ) = 2 mA
current is 20 mA. I5kΩ = 12 V/(2 kΩ + 5 kΩ) = 1.7 mA
I6kΩ = 12 V/(2 kΩ + 6 kΩ) = 1.5 mA
1-11. Given:
I = 5 mA Answers: 0 Ω 6 mA; 1 kΩ, 4 mA; 2 kΩ, 3mA; 3 kΩ,
RS = 250 kΩ 2.4 mA; 4 kΩ, 2 mA; 5 kΩ, 1.7 mA; 6 kΩ, 1.5 mA.
RL = 10 kΩ
1-2
Solution:
100 V
VTH = VR2
VR2 = VS[(R2)/(R1 + R2)] (Voltage divider formula)
VR2 = 18 V[(3 kΩ)/(6 kΩ + 3 kΩ)] Thevenin circuit for Prob. 1-17.
VR2 = 6 V
RTH = [(R1 × R2)/(R1 + R2)] (Parallel resistance formula) 1-18. Given (from Prob. 1-12):
RTH = [(6 kΩ × 3 kΩ)/(6 kΩ + 3 kΩ)] VTH = 12 V
RTH = 2 kΩ RTH = 2 kΩ
Answer: The Thevenin voltage decreases to 6 V, and the Solution:
Thevenin resistance is unchanged. RN = RTH (Eq. 1-10)
1-15. Given: RN = 2 kΩ
VS = 36 V IN = VTH/RTH (Eq. 1-12)
R1 = 12 kΩ IN = 12 V/2 kΩ
R2 = 6 kΩ IN = 6 mA
Solution: Answer: RN = 2 kΩ, and IN = 6 mA
VTH = VR2
VR2 = VS[(R2)/(R1 + R2)] (Voltage divider formula) IN RN
VR2 = 36 V[(6 kΩ)/(12 kΩ + 6 kΩ)]
VR2 = 12 V
RTH = [(R1R2)/(R1 + R2)] (Parallel resistance formula) 6 mA 2 kV
RTH = [(12 kΩ)(6 kΩ)/(12 kΩ + 6 kΩ)]
RTH = 4 kΩ Norton circuit for Prob. 1-18.
Answer: The Thevenin voltage is unchanged, and the
Thevenin resistance doubles. 1-19. Shorted, which would cause load resistor to be connected
across the voltage source seeing all of the voltage.
1-16. Given:
VTH = 12 V 1-20. a. R1 is open, preventing any of the voltage from reaching
RTH = 3 kΩ the load resistor. b. R2 is shorted, making its voltage drop
zero. Since the load resistor is in parallel with R2, its volt-
Solution: age drop would also be zero.
RN = RTH 1-21. The battery or interconnecting wiring.
RN = 3 kΩ
1-22. RTH = 2 kΩ
IN = VTH/RTH
IN = 12 V/3 kΩ Solution:
IN = 4 mA RMeter = 100RTH
RMeter = 100(2 kΩ)
Answer: IN = 4 mA, and RN = 3 kΩ RMeter = 200 kΩ
Answer: The meter will not load down the circuit if the
IN
meter impedance is ≥ 200 kΩ.
RN
4 mA 3 kV
CRITICAL THINKING
1-23. Given:
VS = 12 V
Norton circuit for Prob. 1-16.
IS = 150 A
1-17. Given:
Solution:
IN = 10 mA
RS = (VS)/(IS)
RN = 10 kΩ
RS = (12 V)/(150 A)
RS = 80 mΩ
1-3
1-27. Answer: Thevenin’s theorem makes it much easier to Since RTH is one-third of 10 kΩ, we can use R1 and R2
solve problems where there could be many values of a values that are three times larger.
resistor. Answer:
1-28. Answer: To find the Thevenin voltage, disconnect the load R1 = 30 kΩ
resistor and measure the voltage. To find the Thevenin R2 = 15 kΩ
resistance, disconnect the battery and the load resistor, Note: The criteria will be satisfied as long as R1 is twice
short the battery terminals, and measure the resistance at R2 and R2 is not greater than 15 kΩ.
the load terminals.
1-32. Answer: First, measure the voltage across the terminals.
1-29. Given: This is the Thevenin voltage. Next, connect the amme-
RL = 1 kΩ ter to the battery terminals—measure the current. Next,
I = 1 mA use the values above to find the total resistance. Finally,
subtract the internal resistance of the ammeter from this
Solution:
result. This is the Thevenin resistance.
RS > 100RL
RS > 100(1 kΩ) 1-33. Answer: First, measure the voltage across the terminals.
RL > 100 kΩ This is the Thevenin voltage. Next, connect a resistor
V = IR across the terminals. Next, measure the voltage across
V = (1 mA)(100 kΩ) the resistor. Then, calculate the current through the load
V = 100 V resistor. Then, subtract the load voltage from the Theve-
nin voltage. Then, divide the difference voltage by the
Answer: A 100 V battery in series with a 100 kΩ resistor. current. The result is the Thevenin resistance.
1-30. Given: 1-34. Solution: Thevenize the circuit. There should be a
VS = 30 V Thevenin voltage of 0.148 V and a resistance of 6 kΩ.
VL = 15 V
RTH < 2 kΩ IL = VTH/(RTH + RL)
Solution: Assume a value for one of the resistors. Since IL = 0.148 V/(6 kΩ + 0)
the Thevenin resistance is limited to 2 kΩ, pick a value IL = 24.7 μA
less than 2 kΩ. Assume R2 = 1 kΩ. IL = 0.148 V/(6 kΩ + 1 kΩ)
VL = VS[R2/(R1 + R2)] (Voltage divider formula) IL = 21.1 μA
R1 = [(VS)(R2)/VL] – R2 IL = 0.148 V/(6 kΩ + 2 kΩ)
R1 = [(30 V)(1 kΩ)/(15 V)] – 1 kΩ IL = 18.5 μA
R1 = 1 kΩ
IL = 0.148 V/(6 kΩ + 3 kΩ)
RTH = (R1R2/R1 + R2)
IL = 16.4 μA
RTH = [(1 kΩ)(1 kΩ)]/(1 kΩ + 1 kΩ)
RTH = 500 Ω
1-4
1-5
1-6
PT = PD + PL 3-13. Given:
PT = 13.5 mW + 372 mW VS = 12 V
PT = 386 mW RL = 470 Ω
Answer: Solution: The diode would be reversed-biased and acting
IL = 19.3 mA as an open. Thus the current would be zero and the volt-
VL = 19.3 V age would be source voltage.
PL = 372 mW Answer:
PD = 13.5 mW
VD = 12 V
PT = 386 mW
ID = 0 mA
1-7
1-8
1-9
1-10
1-11
1-12
1-13
1-14
4-45. Given:
Turns ratio = N1/N2 = 8:1 = 8
Output waveform for Prob. 4-40. V1 = 120 V ac
Solution:
4-41. Given: V2 = V1/(N1/N2) (Eq. 4-5)
Turns ratio = N1/N2 = 1:10 = 0.1 V2 = 120 V ac/8
V1 = 120 V ac V2 = 15 V ac
Solution: VP = 1.414 Vrms
V2 = V1/(N1/N2) (Eq. 4-5) VP = 1.414 (15 V ac)
V2 = 120 V ac/0.1 VP = 21.21 V
V2 = 1200 V ac Since each resistor is in the same current path and both
VP = 1.414 Vrms have the same value, they equally divide the voltage.
VP = 1.414 (1200 V ac) Since they both have a capacitor input filter, they divide
VP = 1696.8 V the peak voltage.
Since it is a doubler, the output is 2VP. Answer: Each power supply has 10.6 V, but the load
connected to the right side of the bridge is a positive
Vout = 2VP 10.6 V and the load connected to the left side is a
Vout = 2 (1696.8 V) negative 10.6 V.
Vout = 3393.6 V
4-46. Given:
Answer: The output voltage will be 3393.6 V. VP = 21.21 VP from Prob. 4-1
4-42. Given: R = 4.7 Ω
Turns ratio = N1/N2 = 1:5 = 0.2 Solution: The maximum surge current would be all of the
V1 = 120 V ac peak voltage dropped across the resistor.
Solution: I = V/R (Ohm’s law)
I = 21.21 V/4.7 Ω
V2 = V1/(N1/N2) (Eq. 4-5)
I = 4.51 A
V2 = 120 V ac/0.2
V2 = 600 V ac Answer: The maximum surge current will be 4.51 A.
1-15
1-16
1-17
5-11. Given: Answer: The regulator will fail since the series resistor
is greater than the maximum series resistance. For this
VS = 21.5 to 25 V regulator to work properly, the series resistor should be
RS = 470 Ω 167 Ω or less.
RZ = 14 Ω
VZ = 15 V 5-14. Given:
Solution: VS = 18 to 25 V
RS = 470 Ω
IS = (VS – VZ)/RS (Eq. 5-3) IL = 1 to 25 mA
IS = (25 V – 15 V)/470 Ω VZ = 15 V
IS = 21.28 mA
Solution:
IL = VL/RL (Eq. 5-5, Ohm’s law) V – VZ
IL = 15 V/1.5 kΩ RS(max) = ______
S(min)
IL(max) (Eq.
5-10)
IL = 10 mA RS(max) = (18 V – 15V)/25 mA
RS(max) = 120 Ω
IZ = IS – IL (Eq. 5-6, Kirchhoff’s current law)
IZ = 21.28 mA – 10 mA Answer: Yes, the regulator will fail since the series resis-
IZ = 11.28 mA tance is greater than the maximum series resistance. For
this regulator to work properly, the series resistor should
ΔVL = IZRZ (Eq. 5-7)
be 120 Ω or less.
ΔVL = (11.28 mA)(14 Ω )
ΔVL = 157.9 mV 5-15. Given:
IS = (VS – VZ)/RS (Eq. 5-3) VS = 24 V
IS = (21.5 V – 15 V)/470 Ω RS = 470 Ω
IS = 13.83 mA VZ = 15 V
IL = VL/RL (Eq. 5-5, Ohm’s law) Solution:
IL = 15 V/1.5 kΩ RS(max) = [(VS(min) /VZ) – 1]RL(min) (Eq. 5-9)
IL = 10 mA RL(min) = RS(max) /[(VS(min) /VZ) – 1]
IZ = IS – IL (Eq. 5-6, Kirchhoff’s current law) RL(min) = 470 Ω /[(24 V/15 V) – 1]
IZ = 13.83 mA – 10 mA RL(min) = 783 Ω
IZ = 3.83 mA Answer: The minimum load resistance is 783 Ω .
ΔVL= IZRZ (Eq. 5-7) 5-16. Given:
ΔVL = (3.83 mA)(14 Ω) VZ = 10 V
ΔVL = 53.6 mV IZ = 20 mA
Answer: The load voltage changes from 15.054 V when Solution:
the supply is 21.5 V, to 15.158 V when the supply is
25 V. PZ = VZIZ (Eq. 5-11)
PZ = (10 V)(20 mA)
5-12. Given: PZ = 0.2 W
VS = 24 V Answer: The power dissipation is 0.2 W.
RS = 470 Ω
RL = 1.5 kΩ 5-17. Given:
VZ = 15 V VZ = 20 V
Solution: The regulation is lost once the load voltage IZ = 5 mA
drops below 15 V.
1-18
1-19
1-20
1-21
1-22
6-18. Answer: β = 85
1-23
6-22. Given:
VCC = 20 V (b)
VBB = 10 V (a)
RB = 500 k (c)
RC = 3.3 kΩ
VCE
Solution:
Load lines for (a) Prob. 6-23, (b) Prob. 6-24, and (c)
IC(sat) = VCC/RC (Eq. 6-11) Prob. 6-25
IC(sat) = 20 V/3.3 kΩ
IC(sat) = 6.06 mA 6-26. Given:
VCE(cutoff) =VCC VCC = 20 V
VCE(cutoff) = 20 V VBB = 10 V
RB = 1 MΩ
Answer: The load line does not change. RC = 3.3 kΩ
6-23. Given: β = 200
VCC = 5 V Solution:
VBB = 5 V IB = (VBB − VBE)/RB (Eq. 6-13)
RB = 680 kΩ IB = (10 V − 0.7 V)/1 MΩ
RC = 470 Ω IB = 9.3 μA
IC = β IB (Eq. 6-3)
IC = 200(9.3 μA)
IC = 1.86 mA
1-24
1-25
1-26
1-27
1-28
1-29
1-30
1-31
1-32
1-33
1-34
1-35
1-36
Solution: XC = 1/(2πfC)
XC < 0.1REQ (Eq. 8-1)
XC = 1/(2πfC) 1/(2 πfC) = 0.1REQ
XC < 0.1R (Eq. 8-1) f = 1/{[2π(47 μF)][0.1(1.8 kΩ)]}
1/(2πfC) = 0.1R f = 18.8 Hz
1/(2πC) = (0.1R)f
f = 1/{[2π(100 μF)][0.1(10 kΩ)]} Answer: The lowest frequency where good coupling
f = 1.59 Hz exists is 18.8 Hz.
Answer: The lowest frequency where good coupling 8-8. Given:
exists is 1.59 Hz. f = 1 kHz
8-4. Given: R1 = 2.2 kΩ
R2 = 10 kΩ
f = 100 Hz
R = 10 kΩ Solution:
Solution: REQ = (R1 × R2)/(R1 + R2) (Parallel resistance formula)
REQ = (2.2 kΩ × 10 kΩ)/(2.2 kΩ + 10 kΩ)
XC = 1/(2πfC) REQ = 1.8 kΩ
XC < 0.1R (Eq. 8-1)
1/(2πfC) = 0.1R XC = 1/(2πfC)
C = 1/[2π(100 Hz)(0.1)(10 kΩ)] XC < 0.1REQ (Eq. 8-1)
C = 1.59 μF 1/(2πfC) = 0.1R
C = 1/[2π(1 kHz)(0.1)(1.8 kΩ)]
Answer: A capacitor value of 1.59 μF is required for good C = 0.88 μF
coupling.
Answer: A capacitor value of 0.88 μF is required for good
8-5. Given: coupling.
C = 220 μF
8-9. Given:
R1 = 2.2 kΩ
R2 = 10 kΩ R1 = 1.5 kΩ
R2 = 330 Ω
Solution: RC = 1.2 kΩ
REQ = (R1 × R2)/(R1 + R2) (Parallel resistance formula) RE = 470 Ω
REQ = (2.2 kΩ × 10 kΩ)/(2.2 kΩ + 10 kΩ) VCC = 15 V
REQ = 1.8 kΩ VBE = 0.7 V
XC = 1/(2 πfC) Solution:
XC < 0.1REQ (Eq. 8-1) VBB = [R2/(R1 + R2)]VCC
1/(2πfC) = 0.1REQ VBB = [330 Ω/(1.5 kΩ + 330 Ω)]15 V
f = 1/{[2π(220 μF)][0.1(1.8 kΩ)]} VBB = 2.7 V
f = 4 Hz
VE = VBB − VBE
Answer: The lowest frequency where good coupling VE = 2.7 V − 0.7 V
exists is 4 Hz. VE = 2.0 V
8-6. Given: IE = VE/RE
C = 220 μF IE = 2.0 V/470 Ω
R1 = 10 kΩ IE = 4.26 mA
R2 = 10 kΩ
1-37
1-38
1-39
1-40
1-41
1-42
1-43
1-44
1-45
1-46
1-47
1-48
1-49
1-50
1-51
1-52
1-53
1-54
1-55
1-56
1-57
CRITICAL THINKING
Chapter 11 JFETs
10-48. Answer: The input is larger than the maximum allowed
input for an undistorted output. The input is driving the SELF-TEST
output into saturation, clipping the wave off, and turning 1. a 8. c 14. d 20. c
it into a square wave. 2. d 9. d 15. a 21. c
3. c 10. c 16. b 22. b
10-49. Answer: Electrically, it would be safe to touch, but it may 4. d 11. c 17. c 23. b
be hot and cause a burn. 5. b 12. a 18. c 24. d
10-50. Answer: No, the maximum efficiency of anything is 6. b 13. c 19. a 25. d
100 percent. It is impossible to get more power out of a 7. d
device than is put into the device.
JOB INTERVIEW QUESTIONS
10-51. Answer: No, the ac load line is more vertical because the
ac collector resistance is usually less than the dc collec- 7. The gate can be triggered using the static electricity of the
tor resistance. If the collector had an inductor instead of human hand to put the device into saturation briefly, enough
a resistor, the ac resistance would be greater than the dc to trigger another circuit, such as a one-shot multivibrator.
resistance and make the ac load line less vertical. 10. It has low input capacitance that allows it to amplify higher fre-
quencies (VHF and UHF) than are possible with a CS amplifier.
10-52. Given: 11. Although they do not have as much voltage gain as bipolar
transistors, they have a high input impedance and very low
IC(sat) = 16.67 mA (from Prob. 10-1)
noise. This is preferred in applications in which the incoming
VCC = 15 V
signal may be a few microvolts to be followed by an amplifi-
ICQ = 9.77 mA (from Prob. 10-2)
cation of a million or more.
MP = ICQ rc = 5.31 V (from Prob. 10-3)
VCEQ = 6.21 V (from Prob. 10-3)
PROBLEMS
Solution:
The left side of the dc load line is IC(sat), and the right side 11-1. Given:
is VCC. The Q point is ICQ, VCEQ. The ac load line passes IG = 1 nA
through the Q point. The right side of the ac load line is Reverse voltage = –15 V
ICQ rc above the Q point, or 11.52 V. This gives the line Solution:
a slope of ICQ/ICQ rc = 9.77 mA/5.31 V = 1.84 mA/V. To
find the ac saturation current, take the ac voltage maxi- Rin = Reverse voltage/IG
mum multiplied by the slope = (11.52 V) (1.84 mA/V) = Rin = 15 V/1 nA
21.2 mA. Rin = 15 GΩ
Answer: The input resistance is 15 GΩ.
1-58
Answer: The input resistance of the gate is 20 MΩ at Answer: The gate voltage at the 1/2 cutoff point is –3 V,
100°C. and the drain current is 4 mA.
Solution: Solution:
IDSS = Maximum drain current = 20 mA VGS/VGS(off) = 1/2
VGS(off) = –VP (Eq. 11-2) VGS = 1/2(VGS(off))
VGS(off) = –4 V VGS = 1/2(–4 V)
VGS = –2 V
RDS = VP /IDSS (Eq. 11-1)
RDS = 4 V/20 mA ID/IDSS = 1/4
RDS = 200 Ω ID = 1/4 10 mA
ID = 2.5 mA
Answer: The maximum drain current is 20 mA, the
gate-source cutoff voltage is –4 V, and the value of RDS Answer: The gate voltage at the 1/2 cutoff point is –2 V,
is 200 Ω. and the drain current is 2.5 mA.
1-59
Solution: Solution:
VGS(off) = –VP (Eq. 11-2) ID(sat) = VDD/(RD + RS)
VP = 6 V ID(sat) = 25 V/(10 kΩ + 22 kΩ)
ID(sat) = 0.781 mA
RDS = VP/IDSS (Eq. 11-1)
RDS = 6 V/30 mA VS ≈ VG
RDS = 200 Ω
VDSQ = VD – VS
VD = [RDS/(RDS + RD)]VDD VDSQ = 20.45 V – 10 V
VD = [200 Ω/(200 Ω + 20 kΩ)]20 V VDSQ = 10.45 V
VD = 0.198 V
Answer: The drain voltage is 0.198 V. ID (mA)
0.781
11-12. Given:
Q
VDD = 20 V 0.455
RD = 10 kΩ
VGS(off) = –6 V
IDSS = 30 mA
Solution: 10.45 VDS (V) 25
ID(sat) = VDD/RD DC load line and Q point for Prob. 11–14.
ID(sat) = 20 V/10 kΩ 11-15. Given:
ID(sat) = 2 mA
VDD = 25 V
VGS(off) = VP (Eq. 11-2) VSS = –25 V
VP = 6 V RD = 7.5 kΩ
RDS = VP/IDSS (Eq. 11-1) RS = 18 kΩ
RDS = 6 V/30 mA Solution:
RDS = 200 Ω ID = VSS/RS (Eq. 11-12)
VD = [RDS/(RDS + RD)]VDD ID = –25 V/18 kΩ
VD = [200 Ω/(200 Ω + 10 kΩ)]20 V ID = 1.39 mA
VD = 0.392 V VD = VDD – IDRD (Eq. 11-4)
Answer: The drain saturation current is 2 mA, and the VD = 25 V – (1.39 mA)(7.5 kΩ)
drain voltage is 0.392 V. VD = 14.58 V
11-13. Given: Answer: The drain voltage is 14.58 V.
R1 = 1.5 MΩ 11-16. Given:
R2 = 1 MΩ VDD = 25 V
RS = 22 kΩ VSS = –25 V
RD = 10 kΩ RD = 7.5 kΩ
VDD = 25 V RS = 30 kΩ
1-60
1-61
1-62
1-63
1-64
1-65
1-66
1-67
1-68
1-69
1-70
1-71
Answer: The input voltage required to turn on the SCR 13-12. Given:
is 7.3 V. R1 = 1 kΩ
R2 = 4.6 kΩ
13-8. Answer: The highest output occurs when 0.8 V is across C = 0.47 μF
the 500-Ω resistor. The current through this resistor is
0.8 V divided by 500 Ω, which equals 1.6 mA. This Solution:
1.6 mA must flow through the 3.3-kΩ resistor. The XC = 1/(2πfC)
200 μA of gate current must also flow through the XC = 1/2π(60 Hz)(0.47 μF)
3.3-kΩ resistor. If we ignore the 200 μA on the grounds XC = 5644 Ω
that it is much smaller than 1.6 mA, we get an approximate ________
answer of: Z = √_________________
R2 + XC2
V = 0.8 V + (1.6 mA)(3.3 kΩ) = 6.08 V Z = √5.6
kΩ2 + 5.644 kΩ2
Z = 7.95 kΩ
If we include the 200 μA, we get a slightly larger output
voltage:
X
( )
θZ = ∠ – arctan ___C
R
V = 0.8 V + (1.6 mA + 200 μA)(3.3 kΩ) = 6.74 V
θZ = ∠ – 45º
(
5.644 kΩ
θZ = ∠ – arctan ________
5.6 kΩ )
13-9. Given:
Vin
VGT = 1.5 V IC ∠ θ = _______________
IGT = 15 mA
IH = 10 mA
( )
X
ZT ∠ – arctan ___C
R
VCC = 12 V 120 V ∠
______________
IC ∠ θ =
0º
RG = 2.2 kΩ 7.95 kΩ ∠ – 45º
RL = 47 Ω IC ∠ θ = 15 mA ∠ 45º
1-72
θZ = ∠ – 80º
(
5.644 kΩ
θZ = ∠ – arctan ________
1 kΩ
) 13-19. Given:
VB = 20 V
Vin VGT = 2.5 V
IC ∠ θ = _______________
ZT ∠ – arctan __
X
( )
RC Solution: Ignore the gate current in the triac. Then
120 V ∠ 0º
IC ∠ θ = _______________
VC = VB + VGT
5.732 kΩ ∠ – 80º VC = 20 V + 2.5 V
IC ∠ θ = 20.9 mA ∠ 80º VC = 22.5 V
VC = (IC ∠ θ) (XC ∠ – 90º) Answer: The capacitor voltage required to turn on the
VC = (20.9 mA ∠ 80º)(5644 Ω ∠ – 90º) triac is 22.5 V.
VC = 118 V ∠ – 10º
13-20. Given:
θºcond = 180º – θºfiring
θºcond = 180º – 10º Vin = 100 V
θºcond = 170º RL = 15 Ω
Answer: The minimum conduction angle is 96.3º, and the Solution: Ideally, when the triac is conducting, the volt-
maximum conduction angle is 170º. age drop across it is 0 V.
13-15. Given: I = Vin/RL
I = 100 V/15 Ω
VGT = 0.8 V I = 6.67 A
IGT = 200 μA
VZ = 10 V Answer: The load current is 6.67 A.
1-73
Solution: Ignore the current through the diac and triac. Tmax = 0.2(RC1 max)
Then Tmax = 0.2(5.1 ms)
Tmax = 1.02 ms
VC = VB + VGT
VC = 28 V + 2.5 V Tmin = 0.2(RC1 min)
VC = 30.5 V Tmin = 0.2(0.1 ms)
Tmin = 0.02 ms
Answer: The capacitor voltage required to turn on the
triac is 30.5 V. fmax = 1/Tmin
fmax = 1/0.02 ms
13-22. Given: fmax = 50 kHz
VCC = 15 V
R2 = 1 kΩ fmin = 1/Tmax
R3 = 2 kΩ fmin = 1/1.02 ms
fmin = 980 Hz
Solution:
Answer: The maximum frequency is 50 kHz, and the
Vgate = [R3/(R2 + R3)]VCC (Voltage divider formula) minimum is 980 Hz.
Vgate = [2 kΩ/(1 kΩ + 2 kΩ)]15 V
Vgate = 10 V 13-28. Given:
Vanode = VTrig + 0.7 V RL = 100 Ω
Vanode = 10 V + 0.7 VCC = 15 V
Vanode = 10.7 V Solution: In a dark room the SCR is off and the output
Answer: The gate trigger voltage is 10 V and the anode voltage is 15 V. Once the SCR fires, its voltage drops to
is 10.7 V. 0.7 V.
I = (VCC – 0.7 V)/RL
13-23. Given: I = (15 V – 0.7 V)/100 Ω
VCC = 15 V I = 143 mA
Vgate = 10 V
Vanode = 10.7 V Answer: The output voltage when it is dark is 15 V and
when it is light is 0.7 V, and the current through the resis-
Solution: tor is 143 mA when it is light.
VR4 = Vanode – 0.7 V 13-29. Answer:
VR4 = 10.7 V – 0.7
VR4 = 10 V Trouble 1: Since there is voltage at D and not at E, the
Answer: The peak voltage across R4 = 10 V. wire connecting the two is open.
13-24. Answer: The output waveform will be a sawtooth wave- Trouble 2: No supply voltage.
form from 0 V to 10.7 V. Trouble 3: Since there is voltage at B and not at C, the
transformer is the problem.
CRITICAL THINKING Trouble 4: Since there is voltage at A and not at B, the
fuse is open.
13-25. Answer: The breakover voltage of the diode, which is
10 V. 13-30. Answer:
13-26. Answer: The breakover voltage of the diode, which is Trouble 5: Since there is an overvoltage and the crowbar
10 V. is off, the problem is the crowbar.
13-27. Given: Trouble 6: Since there is voltage at C and not at D and the
load resistor is not shorted, the rectifier is the problem.
R1 = 0 to 50 kΩ
R2 = 1 kΩ Trouble 7: Since there is voltage at E and not at F, the
C1 = 0.1 μF wire connecting the two is open.
T = 20%(RC) Trouble 8: Since there is voltage at A and not at B, the
Solution: fuse is open.
Rmax = R2 + R1(max) 13-31. The fuse is open
Rmax = 1 kΩ + 50 kΩ
Rmax = 51 kΩ 13-32. The SCR D3 has been triggered on
Rmin = R2 + R1(min) 13-33. Open transformer secondary
Rmin = 1 kΩ + 0 kΩ
Rmin = 1 kΩ 13-34. C1 is open
RCmax = RmaxC1 13-35. VS is 0 V
RCmax = (51 kΩ)(0.1 μF)
RCmax = 5.1 ms
1-74
SELF-TEST Av
1. a 6. c 11. c 16. a
2. b 7. b 12. c 17. d
3. c 8. c 13. d 18. b 500,000
4. c 9. c 14. a 19. c 353,000
5. b 10. d 15. c 20. a
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1-76
14-17. Given: From the graph below, the gain at 1 MHz is 6 dB.
PdBm = 20 dBm Av = antilog(Av(dB)/20) (Eq. 14-15)
Av = antilog(6 dB/20)
Solution:
Av = 2
P = antilog(PdBm/10) (Eq. 14-17)
P = antilog(20 dBm/10) Answer: The voltage gain at 1 MHz is 2.
P = 100 mW Av(dB)
Answer: The output power is 100 mW. 106 dB
14-18. Given:
86 dB
VdBV = –45
66 dB
Solution:
V = antilog(VdBV/20) (Eq. 14-19) 46 dB
V = antilog(–45 dBV/20)
V = 5.6 mV 26 dB
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1-78
Solution: Answer: The lower cutoff frequency for the base cou-
pling circuit is 119 Hz.
Cin(M) = C(Av + 1) (Eq. 14-26)
Cin(M) = 100 pF(150,000 + 1) 14-34. Given:
Cin(M) = 15 μF Cout = 4.7 μF
f2 = 1/(2πRC) RC = 3.6 kΩ
f2 = 1/[2π(1 kΩ)(15 μF)] RL = 10 kΩ
f2 = 11 Hz Solution:
Av(dB) = 20 log Av (Eq. 14-9) R = RC + RL
Av(dB) = 20 log(150,000) R = 36 kΩ + 10 kΩ
Av(dB) = 104 dB R = 13.6 kΩ
Answer: See figure below. fC1 = 1/(2πRCout)
fC1 = 1/[2π(13.6 kΩ)(4.7 μF)]
Av(dB) fC1 = 2.49 Hz
104 dB Answer: The lower cutoff frequency for the collector
84 dB coupling circuit is 2.49 Hz.
64 dB
14-35. Given:
CE = 25 μF
44 dB
RG = 50 Ω
24 dB RE = 1 kΩ
4 dB Solution:
11 Hz 110 Hz 1.1 kHz 11 kHz 110 kHz 1.1 MHz fC1 = 1/(2πzoutCE)
fC1 = 1/[2π(22.4 Ω)(25 μF)]
Ideal Bode plot for Prob. 14-29. fC1 = 284 Hz
14-30. Given: Answer: The lower cutoff frequency for the emitter
TR = 10 μs bypass circuit is 284 Hz.
Solution: 14-36. Given:
f2 = 0.35/TR (Eq. 14-29) C'c = 2 pF
f2 = 0.35/10 μs C'e = 10 pF
f2 = 35 kHz C'Stray = 5 pF
R1 = 10 kΩ
Answer: The upper cutoff frequency is 35 kHz.
R2 = 2.2 kΩ
1-79
1-80
1-81
IE = 1/2 IT Answer: The output voltage is 518 mV, and the input
IE = 1/2(60 μA) impedance is 125 kΩ.
IE = 30 μA 15-6. Given:
Right Side VCC = 15 V
VC = VCC – (30 μA)(200 kΩ) VEE = –15 V
VC = 6 V RE = 68 kΩ
RC = 47 kΩ
Left Side β = 275
VC = 12 V v1 = 2.5 mV
Answer: The tail current is 60 μA, the emitter current is Solution:
30 μA, and the quiescent voltage is 6 V on the right side IT = (VEE – VBE)/RE (Eq. 15-5)
and 12 V on the left side. IT = (15 V – 0.7 V)/68 kΩ
15-4. Given: IT = 210.3 μA
VCC = 12 V IE = 1/2 IT (Eq. 15-6)
VEE = –12 V IE = 1/2(210.3 μA)
RE = 200 kΩ IE = 105.2 μA
RC = 200 kΩ r'e = 25 mV/ IE (Eq. 8-10)
Solution: r'e = 25 mV/105.2 μA
IT = (VEE – VBE)/RE r'e = 237.6 Ω
IT = (12 V – 0.7 V)/200 kΩ Av = RC/r'e (Eq. 15-10)
IT = 56.5 μA Av = 47 kΩ/237.6 Ω
IE = ½ IT Av = 197.8
IE = 1/2(56.5 μA) vout = Av(v1 – v2) (Eq. 15-2)
IE = 28.3 μA vout = 197.8(2.5 mV – 0)
Right Side vout = 494 mV
VC = VCC – (28.3 μA)(200 kΩ) zin = 2β r'e (Eq. 15-11)
VC = 6.35 V zin = 2(275)(237.6 Ω)
zin = 131 kΩ
Left Side
Answer: The output voltage is 494 mV, and the input
VC = 12 V
impedance is 131 kΩ.
Answer: The tail current is 56.5 μA, the emitter current is
15-7. Given:
28.3 μA, and the quiescent voltage is 6.35 V on the right
side and 12 V on the left side. VCC = 15 V
VEE = –15 V
15-5. Given: RE = 68 kΩ
VCC = 15 V RC = 47 kΩ
VEE = –15 V β = 275
RE = 68 kΩ v1 = 0 mV
RC = 47 kΩ v1 = 1 mV
β = 275
Solution:
v1 = 2.5 mV
IT = (VEE)/RE (Eq. 15-5)
Solution: IT = (15 V)/68 kΩ
IT = (VEE/RE) (Eq. 15-5) IT = 220.6 μA
IT = (15 V)/68 kΩ
IE = 1/2 IT (Eq. 15-6)
IT = 220.6 μA
IE = 1/2(220.6 μA)
IE = 1/2 IT (Eq. 15-6) IE = 110.3 μA
IE = 1/2 (220.6 μA)
r'e = 25 mV/IE (Eq. 8-10)
IE = 110.3 μA
r'e = 25 mV/110.3 μA
r'e = 25 mV/IE r'e = 226.7 Ω
r'e = 25 mV/110.3 μA
Av = RC/r'e (Eq. 15-10)
r'e = 226.7 Ω
Av = 47 kΩ /226.7 Ω
Av = RC/r'e (Eq. 15-10) Av = 207.3
Av = 47 kΩ/226.7 Ω
Av = 207.3
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1-86
At 1 kHz the voltage gain is the closed loop gain. 16-9. Given:
vout = Av(CL)(vin) Iin(bias) = 50 pA
Iin(off) = 10 pA
vout = 10(25 mVp-p)
Vin(off) = 2 mV
vout = 250 mVp-p
Solution:
At 10 MHz the voltage gain is reduced.
Av(CL) Av(CL) = −Rf /R1 (Eq. 16-3)
Av(10 MHz) = __________
________ Av(CL) = −300 kΩ/15 kΩ
√
1 + (f/f2)2 Av(CL) = −20
10
Av(10 MHz) = ____________________
__________________
RB2 = Rf || R1 (Eq. 16-11)
√ 1
+ (10 MHz/2 MHz)2
RB2 = 300 kΩ || 15 kΩ
Av(10 MHz) = 1.96 RB2 = 14.29 kΩ
vout = Av(10 MHz)(vin) V1 err = (RB1 − RB2)Iin(bias) (Eq. 16-8)
vout = 1.96(25 mVp-p) V1 err = (0 − 14.29 kΩ)(50 pA)
vout = 49 mVp-p V1 err = −714.3 nV
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1-88
1-89
16-24. Answer: The output will go to positive or negative Verror = ± Av(CL)(±V1 err ±V2 err ±V3 err)
saturation. Verror = 1(50 mV + 10 mV + 6 mV)
Verror = 66 mV
16-25. Answer: Answer: The output error voltage is 66 mV.
Position 1: The input voltage is applied directly to the
noninverting input. Because of the virtual short between 16-29. Given:
the noninverting and inverting input terminals, there is R1 = 2 kΩ
no ac voltage across the left 10-kΩ resistor. Since there is Rf = 100 kΩ
no ac voltage across the resistor, it can be removed from C = 1 μF
the circuit without changing the operation. With the resis- vin = 50 mVp-p
tor removed, the circuit reduces to a voltage follower and f = 1 kHz
Av(CL) = 1 and a closed-loop bandwidth of Solution:
funity XC = 1/2πfC
f2(CL) = _____
1 MHz
= _____ = 1 MHz
XC = 1/[2π(1 kHz)(1 μF)]
Av(CL) 1
XC = 159 Ω
Position 2: The circuit is an inverting amplifier. The
magnitude of the voltage gain is Av(CL) = 1. Note that the Since XC is less than one-tenth of 2 kΩ, the bottom of the
closed-loop bandwidth is only half as much because 2 kΩ is approximately an ac ground.
Av(CL) = (Rf/R'1) + 1 (Eq. 16-12)
funity 1 MHz Av(CL) = (100 kΩ/2 kΩ) + 1
f2(CL) = ________ = ______
= 500 kHz
Av(CL) + 1 1+1 Av(CL) = 51
This was covered briefly in the chapter. See the equation vout = Av(CL)vin
at the top of p. 682 and the brief explanation that follows. vout = 51(50 mVp-p)
Chapter 17 discusses the closed-loop bandwidths in more vout = 2.55 Vp-p
detail. Answer: The output voltage is 2.55 Vp-p.
16-26. Answer: 16-30. Given:
Position 1: With the left resistor open, the circuit reduces Iin(bias) = 500 nA
to a voltage follower and Av(CL) = 1. Iin(off) = 200 nA
Position 2: With the left resistor open, the voltage gain Vin(off) = 6 mV
is zero. R1 = 2 kΩ
16-27. Answer: Go to positive or negative saturation. Rf = 100 kΩ
Solution:
16-28. Given:
R'1 = XC = R1
Iin(bias) = 500 nA
R'1 = 0 + 2 kΩ
Iin(off) = 200 nA
R'1 = 2 kΩ
Vin(off) = 6 mV
R1 = 2 kΩ RB2 = R1 || Rf (Eq. 16-11)
Rf = 100 kΩ RB2 = 2 kΩ || 100 kΩ
C = 1 µF RB2 = 1.96 kΩ
Solution: V1 err = (RB1 – RB2)Iin(bias) (Eq. 16-8)
XC = 1/2πfC V1 err = (0 – 1.96 kΩ)(500 nA)
XC = 1/[2π(0)(1 µF)] V1 err = 980 μV
XC = ∞ V2 err = (RB1 + RB2)(Iin(off)/2) (Eq. 16-9)
R'1 = XC + R1 V2 err = (0 + 1.96 kΩ)(200 nA/2)
R'1= ∞ + 2 kΩ V2 err = 196 μV
R'1= ∞ V3 err = Vin(off) = 6 mV
RB2 = R1 || Rf (Eq. 16-11) Av(CL) = (Rf /R'1) + 1 (Eq. 16-12)
RB2 = ∞ || 100 kΩ Av(CL) = (100 kΩ/2 kΩ) + 1
RB2 = 100 kΩ Av(CL) = 51
V1 err = (RB1 – RB2)Iin(bias) (Eq. 16-8) Verror = ±Av(CL)(±V1 err ± V2 err ± V3 err)
V1 err = (0 – 100 kΩ)(500 nA) Verror = 51(980 μV + 196 μV + 6 m∆V)
V1 err = 50 mV Verror = 366 mV
Answer: The output voltage is 366 mV.
1-90
1-91
1-92
1-93
1-94
1-95
1-96
f2(max) = Bfunity Answer: The midband voltage gain is 42, the upper cutoff
f2(max) = 0.0382(1 MHz) frequency is 71.4 kHz, and the lower cutoff frequency is
f2(max) = 38.2 kHz 79.6 Hz.
–Rf –180 kΩ 18-6. Given:
Av = ____
= ________
= –18
R1 10 kΩ
R1 = 3.3 kΩ
Answer: The voltage gain is 18 with an inverted output. Rf = 150 kΩ
The minimum bandwidth is 712 Hz and the maximum R2 = 100 kΩ
bandwidth is 38.2 kHz. RL = 10 kΩ
C1 = 1 µF
18-4. Given:
C2 = 10 µF
R1 = 1.5 kΩ C3 = 4.7 µF
Rf = 100 kΩ funity = 1 MHz
Rmin = 100 Ω
Rmax = 5.1 kΩ Solution:
funity = 1 MHz Av = (Rf/R1) + 1
Av = (150 kΩ/3.3 kΩ) + 1
Solution:
Av = 46.5
Bmin = (R1 || Rmin)/(R1 || Rmin + Rf)
Bmin = (1.5 kΩ || 100 Ω)/(1.5 kΩ || 100 Ω + 100 kΩ) f2 = funity/Av
Bmin = 0.000937 f2 = 1 MHz/46.5
f2 = 21.5 kHz
Bmax = (R1 || Rmax)/(R1 || Rmax + Rf)
fC1 = 1/(2πR2C1)
Bmax = (1.5 kΩ || 5.1 kΩ)/(1.5 kΩ || 5.1 kΩ + 100 kΩ)
fC1 = 1/[2π(100 kΩ)(1 µF)]
Bmax = 0.01146
fC1 = 1.59 Hz
f2(min) = Bminfunity fC2 = 1/(2πRLC2)
f2(min) = 0.000937(1 MHz) fC2 = 1/[2π(10 kΩ)(10 µF)]
f2(min) = 937 Hz fC2 = 1.59 Hz
f2(max) = Bmaxfunity fC3 = 1/(2πR1C3)
f2(max) = 0.01146(1 MHz) fC3 = 1/[2π(3.3 kΩ)(4.7 µF)]
f2(max) = 11.5 kHz fC3 = 10.3 Hz
Av = –Rf/R1 Answer: The midband voltage gain is 46.5, the upper cut-
Av = –100 kΩ/1.5 kΩ off frequency is 21.5 kHz, and the lower cutoff frequency
Av = –66.7 is 10.3 Hz.
vout = Avvin 18-7. Given:
vout = –66.7(4 mV)
vout = –266.8 mV R1 = 2 kΩ
Rf = 100 kΩ
Answer: The minimum bandwidth is 937 Hz and the vin = 10 mV
maximum bandwidth is 11.5 kHz. The output voltage is
–266.8 mV. Solution:
Av = (Rf/R1) + 1
18-5. Given: Av = (100 kΩ/2 kΩ) + 1
R1 = 2 kΩ Av = 51
Rf = 82 kΩ
RL = 25 kΩ vout = Avvin
C1 = 2.2 µF vout = 51(10 mV)
C2 = 4.7 µF vout = 510 mV
funity = 3 MHz Answer: The output voltage at A, B, and C is 510 mV.
1-97
Answer: When the gate is low, the output is 4.4 mV, and ϕ = –2 arctan (f/fC)
when the gate is high, the output is 72.4 mV. ϕ = –2 arctan (100 Hz/362 Hz)
ϕ = –30.9°
18-10. Given:
ϕ = –2 arctan (f/fC)
R1 = 10 kΩ ϕ = –2 arctan (1 kHz/362 Hz)
Rf = 10 kΩ ϕ = –140°
Vin = 2.5 V
ϕ = –2 arctan (f/fC)
Solution: ϕ = –2 arctan (10 kHz/362 Hz)
Av = (Rf/R1) + 1 ϕ = –176°
Av = (10 kΩ/10 kΩ) + 1
Av = 2 Answer: The phase shift is –30.9° at 100 Hz, –140° at
1 kHz, and –176° at 10 kHz.
Vout = Av(vin)
Vout = 2(2.5 V) 18-15. Given:
Vout = 5 V R1 = 1.5 kΩ
R2 = 30 kΩ
Answer: The new output reference voltage is 5 V.
1-98
1-99
1-100
1-101
Answer: The minimum gain is 98, and the maximum gain 18-44. Answer:
is 102. Trouble 1: Since there is voltage at E and not at F, there
is an open between E and F.
18-42. Given:
Transistor: Trouble 2: Since the output is only 200 mV, which is the
R1 = 22 kΩ amplified output of A, R2 is open.
R2 = 10 kΩ Trouble 3: Since the input is 2 mV and the output is maxi-
RS = 1 kΩ mum, R1 is shorted.
RE = 5.6 kΩ
RC = 6.8 kΩ 18-45. Answer:
VCC = 15 V Trouble 4: Since there is no voltage at B, there is an open
between K and B.
Op amp
R3 = 1 kΩ Trouble 5: Since the voltage at C is 3 mV and the voltage
Rf = 47 kΩ at D is zero, there is an open between C and D.
Solution: Trouble 6: Since the voltage at A is zero, there is an open
VBB = [R2/(R1 + R2 + RS)]VCC between J and A.
VBB = [10 kΩ/(22 kΩ + 10 kΩ + 1 kΩ)]15 V
VBB = 4.54 V
1-102
18-54. Vout = (Av)(Vin) = (11)(0.5 Vp-p) = 5.5 Vp-p Answer: The bandwidth is 2.5 kHz, the center frequency
is 21.2 kHz, the Q is 8.48, and it is narrowband.
18-55. Av = AVOL; The output would be clipped at (+) and (–)
12 V 19-3a. Given:
f1 = 2.3 kHz
18-56. 0 Hz to 1.36 MHz f2 = 4.5 kHz
Solution:
Chapter 19 Active Filters BW = f2 – f1 (Eq. 19-1)
BW = 4.5 kHz – 2.3 kHz
SELF TEST BW = 2.2 kHz
____
1. c 9. d 17. a 25. b f0 = √f1 f2
2. b 10. d 18. b 26. c ________________
3. d 11. d 19. d 27. b f0 = √(2.3
kHz)(4.5 kHz) (Eq. 19-2)
4. c 12. b 20. d 28. d f0 = 3.2 kHz
5. c 13. c 21. a 29. a
Q = f0/BW (Eq. 19-3)
6. b 14. d 22. d 30. d
Q = 3.2 kHz/2.2 kHz
7. c 15. a 23. b 31. b
Q = 1.45
8. d 16. b 24. b
Since Q > 1, it is narrowband.
JOB INTERVIEW QUESTIONS Answer: Narrowband.
6. Low attenuation and the edge frequency. High attenuation 19-3b. Given:
and the edge frequency. f1 = 47 kHz
7. A filter designed to control the phase of a signal rather than f2 = 75 kHz
its amplitude.
8. It compares the voltage gain to the frequency. Solution:
BW = f2 – f1 (Eq. 19-1)
PROBLEMS BW = 75 kHz – 47 kHz
BW = 28 kHz
19-1. Given: ____
f0 = √
_______________
f1 f2
f1 = 445 Hz f0 = √(75
kHz)(47 kHz) (Eq. 19-2)
f2 = 7800 Hz f0 = 59.4 kHz
Solution: Q = f0/BW (Eq. 19-3)
BW = f2 – f1 (Eq. 19-1) Q = 59.4 kHz/28 kHz
BW = 7800 Hz – 445 Hz Q = 2.12
BW = 7355
____ Since Q > 1, it is narrowband.
f0 = √
f1 f2
________________ Answer: Narrowband.
f0 = √
(445
Hz)(7800 Hz) (Eq. 19-2)
f0 = 1.86 kHz
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1-107
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1-110
1-111
1-112
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1-114
1-115
1-116
1-117
(
R3 = 5 kΩ
f = __
C R1 + R2 )
2 _______
1
f2(CL) = 15.9 kHz
(
2 ____________
f = ______ 1
0.1 μF 2 kΩ + 10 kΩ )
Solution:
XC = 1/(2πfC)
f = 1.67 kHz
XC = 1/[2π (15.9 kHz)(0.001 μF)]
D = R1/(R1 + R2) XC = 10 kΩ
D = 2 kΩ/(2 kΩ + 10 kΩ)
ϕ = −arctan(R/XC)
D = 0.167
ϕ = −arctan(10 kΩ/10 kΩ)
Answer: The frequency is 1.67 kHz, and the duty cycle ϕ = −45°
is 0.167.
Below its critical frequency, the op amp has 180° of
21-29a. Decrease. With the lamp open, there is no path for feed- phase shift. At 15.9 kHz, the op amp has an additional
back current. Thus the voltage at the inverting terminal phase shift of 90° because it is well above its critical fre-
will equal the output voltage and it should be driven quency. This means that the op amp has approximately
to 0 V. 270° of phase shift at 15.9 kHz. Each lag circuit has a
21-29b. Increase. With the inverting input grounded, there is no phase shift of 45° at 15.9 kHz. Therefore, the total or
feedback and the gain is open-loop gain and the output loop phase shift is 270° plus 45° plus 45°, or 360°.
will be saturation.
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