1

Explaining Synthesis of Three-Phase Sinusoidal

Voltages Using SV-PWM in the First Power
Electronics Course
Ned Mohan, Philip Jose, Ted Brekken, Krushna Mohapatra Waldemar Sulkowski, Narvik University, Narvik, Norway
University of Minnesota, Minneapolis, USA Tore Undeland, NTNU, Trondheim, Norway

Abstract-- In undergraduate power electronics courses, +

students are taught the sinusoidal pulse-width-modulation (Sine-
PWM) principle to synthesize three-phase sinusoidal voltages. It a
Vd
is well known that the space vector PWM approach (SV-PWM) +

utilizes the available dc-bus voltage of the inverter to its vaN

− N −
maximum, resulting in an improved voltage capability of nearly
vctrl , aN
15% compared to Sine-PWM. However, SV-PWM is not qaN (t )
(a )
discussed in the first course due to its perceived complexity in vtri
(c )
explanation and implementation. This paper describes how SV-
PWM can be discussed in a basic course on power electronics. vctrl , aN Vˆtri vtri

1 INTRODUCTION
This paper can be categorized in thee parts. The first part 0 t
reviews a new approach that uses a switching power-pole as 1
qaN
the building block of switch-mode converters [1]. It describes d aN
0 t
the choice of the carrier signal for PWM that is better suited Tup
for this building-block approach in synthesizing dc and ac 2
Vd
outputs. It also shows the limitation of Sine-PWM for three- vaN
phase synthesis. The second part describes the reasons and the vaN = d aN (t )Vd
0
t
approach for using space vector PWM (SV-PWM) in Ts
2 (b )
synthesizing three-phase outputs, and how it utilizes the dc-
bus voltage of the inverter to its maximum. The third part Fig. 1 Switching power-pole and its waveforms.
explains how the carrier-based modulation, like in Sine-PWM, A carrier-based PWM waveform is shown in Fig. 1b, where
can be used for implementing SV-PWM. This digest provides a control voltage vctrl ,aN is compared with a high-frequency
the framework and further details would be provided in the carrier signal vtri of a triangular waveform that establishes the
paper.
switching-frequency fs and the switching time-period
2 PWM OF SWITCHING POWER-POLE AS A BUILDING BLOCK Ts ( = 1/ f s ) of the converter. In contrast to the traditional
Fig. 1a shows a switching power-pole which consists of a
description, where the carrier signal is assumed to vary
bi-positional switch, considered to be ideal, within a two-port
between −Vˆtri and Vˆtri [2, 3], it varies between 0 and Vˆtri to
comprised of a voltage-port and a current-port. As described
in [1], this switching power-pole is the basic building block be better suited for this building-block approach. It is similar
which is replicated twice in converters for dc-motor drives and to the use of ramp signal in dc-dc converters, where the signal
1-phase UPS, and thrice for three-phase ac drives and UPS. varies between 0 and Vˆ . As shown by the symmetry in Fig.r

1b, only one-half of the switching time-period needs to be

considered within which Tup / 2 is the interval during which
vctrl ,aN > vtri that results in the switching-function qaN = 1 and
 2

causes the switch to be in the “up” position; otherwise qaN = 0 2π

+ a e
j
3
and the switch is in the “down” position. The pole duty-ratio
d aN ( = Tup / Ts ) is the fraction of the time that the switch is in
Vd b n e j0
the “up” position, which can be derived from the waveforms in
Fig. 1b as c
v (t )
− 4π
j
d aN (t ) = ctrl ,aN 0 < d aN < 1 (1) N e 3
V ˆ
tri
(a )
where the duty-ratio d aN (t ) in (1) is the average value of the
switching-function qaN (t ) shown in Fig. 1b. The pole output
voltage vaN (t ) equals qaN (t ) ⋅Vd and its average value depends
on the duty-ratio:
vaN (t ) = d aN (t )Vd 0 < vaN < Vd (2)
where the average refers to a voltage averaged over one
switching time-period and is indicated as “ v ”. From(1) and
(2), and as shown in Fig. 1c by an ideal-transformer
representation
v (t ) vaN (t )
(b )
d aN (t ) = ctrl ,aN = (3)
Vˆtri
Vd Fig. 2 Three-phase inverter.
It is clear from Fig. 1a that the output voltage vaN and its vaN = vcm + van
vbN = vcm + vbn (5)
average vaN are limited between 0 and Vd . However, in
vcN = vcm + vcn
applications such as motor drives, the output voltages need to
where van , vbn and vcn are the desired balanced three phase
be both positive and negative, which are realized by
introducing a common-mode offset in the output voltage of load voltages, and sum to zero at any time instant. These
each pole. This common-mode voltage is nullified in the output voltages are shown in Fig. 2b. The common-mode
differential output as described in the following sections. voltages, being zero-sequence, do not appear across the load
Therefore, the output voltage is synthesized to be and only van , vbn , and vcn appear across the load with respect
vaN = vcm + van (4) to the load-neutral.
where vcm is the common-mode voltage that allows the 4 SINE-PWM
desired voltage va to become both positive and negative In Sine-PWM (similar to converters for dc-motor drives and
around this common-mode voltage. 1-phase UPS) the average output of each power pole has a
Vd
common-mode dc offset voltage equal to around which
3 SYNTHESIS OF THREE-PHASE AC IN DRIVES AND UPS 2

Converters for three-phase outputs consist of three power- van , vbn , and vcn can vary sinusoidally as shown in Fig. 3a [1-
poles as shown in Fig. 2a. The application is shown to be for 3]. The power-pole output voltages are shown in Fig. 3b. At
motor drives but the same applies to other applications such as the limit, van can become a maximum of Vd
2 and hence
three-phase UPS. In this converter, the average output voltages
(Vˆph ) max =
Vd
2
. Therefore, the maximum amplitude of the line-
are synthesized according to (4) as
line voltage in Sine-PWM, which occurs at t1 in Fig. 3a, is
limited to
V
(VˆLL ) max = 3 d (6)
2
 3

G
time. Given vs (t ) , any phase voltage can be obtained by the
G
projection of vs (t ) on that axis and multiplying it by a factor
Vd vcN
vaN vbN of 2 / 3 . If the three-phase voltages, each of phase
amplitude Vˆph , vary sinusoidally in time with a
frequency f ( = ω / 2π ) , then the space vector will have
Vd
2
constant amplitude Vˆs (= 32 Vˆph ) and will rotate
counterclockwise with a speed of ω (= 2π f ) rad/s. In Fig. 1a,
in terms of the switching power-pole instantaneous output
0 t voltages with respect to the negative dc bus
t1
van = vaN + v Nn ; vbn = vbN + v Nn ; vcn = vcN + vNn (8)
(a ) The above equation will also be valid in terms of the average
b quantities:
van = vaN + v Nn ; vbn = vbN + v Nn ; vcn = vcN + vNn (9)
Therefore, substituting (9) into (7) and recognizing that
a
n e j 0 + e j 2π / 3 + e j 4π / 3 = 0 , the average voltage space vector can
be written in terms of the average output voltages of the
van (t ) vbn (t ) vcn (t ) switching power-poles as
G
c vs (t ) = vaN (t )e j 0 + vbN (t )e j 2π / 3 + vcN (t )e j 4π / 3 (10)
Vd Vd Vd A switch in a switching power-pole of Fig. 2a is either “up” or
2 2 2 “down”, with the instantaneous output voltage either 1 or 0
times Vd . With three poles, eight switch-status combinations
N
(b ) are possible. From (10), the voltage space vector can instantly
assume one of the six distinct non-zero instantaneous values as
Fig. 3 Sine-PWM.
shown in Fig. 4a, where phase "a" is represented by the least
5 SPACE VECTOR PWM (SV-PWM) significant digit and phase “c” by the most significant digit.
Use of space vectors has been recently introduced in a The amplitude of each of these six vectors equals Vd . These
physical basis such that it can be used in teaching the first resulting instantaneous voltage vectors, which we will call the
course dealing with 3-phase ac machines [4]. This approach G
“basic vectors”, are shown in Fig. 4a forming six sectors. v0
has numerous benefits. In the power electronics courses, G
and v7 are the zero vectors because of their zero values.
although the synthesis of three-phase ac is general, it is best to
imagine that it is being synthesized for a three-phase motor b − axis
G
0
with three magnetic axes 120 apart in space, as shown in Fig. G v3 (011)
v2 (010)
2a. In terms of the desired phase voltages, the voltage space
II
vector can be written by multiplying the phase voltages by G
III I vs
their respective axes orientations in Fig. 2a: G
v6 (110)
G G a − axis
vs (t ) = van (t )e j 0 + vbn (t )e j 2π / 3 + vcn (t )e j 4π / 3 (7) v1 (001)
G IV VI
where the space vector vs (t ) is a complex variable expressed G
vG7 (111) = 0 V
by an arrow on top, and it is the average value, just like the v0 (000) = 0 G G
G v4 (100) v5 (101)
phase voltages. Eq. 7 shows that the space vector vs (t ) is a
compact notation such that a single variable contains
c − axis
information about the voltages of all three phases at a given
Fig. 4(a) Instantaneous basic vectors
 4

π π
G j
v3 = V d e 3 (Vˆ )
s
max
= Vd cos( ) =
6 2
3
Vd (13)

The corresponding phase voltage peak, 2

3 times the space
vector peak, has the following maximum from (13)

(Vˆ ) =
Vd
(14)
Vˆs ,max
ph
max
3
and hence the maximum line-line voltage is
G G
y v3 vs (Vˆ ) = V
LL max d (15)
Comparison of (6) and (15) shows that SV-PWM results in a
θs G higher limit on the available output voltage by a factor of ,
v1 = Vd e j 0
2
G 3

x v1 or by approximately 15 percent higher, compared to Sine-

PWM.
G
Fig. 4(b) Synthesis of vs (t ) .
6 CARRIER-BASED IMPLEMENTATION OF SV-PWM
The average voltage space vector is synthesized by time- The major difficulty in implementing SV-PWM as described
weighted averaging of the two adjacent basic non-zero voltage above is that it requires a sector-based calculation. However, it
vectors that form the sector in which the average voltage can be explained and implemented using carrier-based
vector to be synthesized lies, but using both the zero voltage modulation similar to Sine-PWM. Note that in Fig. 4b in
vectors of equal duration. In the following analysis, we will G G
G sector 1, with the basic non-zero vectors v1 (001) and v3 (011) ,
focus on vs (t ) as shown in Fig. 4b, with the aim of G G
G and the zero-vectors v0 (000) and v7 (111) , the power-pole “c”
generalizing the discussion to all sectors. To synthesize vs (t )
G G voltage is always 0 except for a 2z Ts interval corresponding to
in Fig. 4b, the adjacent basic vectors v1 and v3 are applied for G
G v7 (111) . Therefore, the average value of the power-pole “c”
intervals xTs and yTs respectively, and the zero vectors v0
G output is
and v7 are applied for a duration 2z Ts each. By time-weighted z
vcN (t ) = Vd (16)
averaging 2
G 1 G G G G Similarly, the switching-pole “a” voltage is always Vd except
vs (t ) = [ xTs v1 + yTs v3 + zTs ⋅ 0] = xv1 + yv3 (11)
Ts G
for a 2z Ts interval corresponding to v0 (000) . Therefore, the
where, x + y + z = 1 . In (11), expressing the basic vectors in
average value of the switching-pole “a” output is
terms of their amplitude and phase angles results in z
G vaN (t ) = Vd − Vd (17)
vs (t ) = Vˆs e jθs (t ) = Vd ( xe j 0 + ye jπ / 3 ) (12) 2
Equating the values given by (16) and (17) to the switching-
From Fig. 4b and (12), it is clear that the ratio y / x dictates
G pole voltages in Fig 2b,
the orientation θ s of vs (t ) , whereas the amplitude Vˆs is z
vcn (t ) + vcm (t ) = Vd (18)
controlled by introducing the two zero states. At the limit, 2
where z = 0 and hence x + y = 1 , the tips of the voltage space z
van (t ) + vcm (t ) = Vd − Vd (19)
vectors lie on the straight line connecting the two non-zero 2
basic vectors, as shown in Fig. 4b. However, normally the Solving (18) and (19),
three voltages to be synthesized vary sinusoidally in time, and Vd  van (t ) vcn (t ) 
vcm (t ) = + − − (20)
as mentioned earlier, result in a rotating voltage vector of a 2  2 2 
constant amplitude, that at the limit, as shown by the dashed Eq. 20 is valid only for sector 1. To generalize for all sectors,
circle in Fig. 4b, has a maximum value at the angle of (20) can be expressed as
π / 6 rad:
 5

Vd  max(van , vbn , vcn ) min(van , vbn , vcn ) 

vcm (t ) = + − − (21)
2  2 2 
 

vk ( t )

Eq. 21 shows that the common-mode voltage in SV-PWM

Vd
consists of 2 , as in Sine-PWM, plus an extra voltage term
vk (t ) . As in Sine-PWM, it is possible to achieve SV-PWM by
using a high-frequency triangular-waveform carrier and the
control voltage (equal to d if Vˆ = 1 ) shown in Fig. 5,
aN tri

compared to that for Sine-PWM.

vctrl ,aN
d aN =
Vˆ tri
1
Sine-PWM

SV-PWM

vctrl , com, SV − PWM

0.5

0 t

Fig. 5 Comparison of Sine-PWM and SV-PWM control

voltages in phase-a for the same output.

7 CONCLUSIONS
This paper describes how SV-PWM can be taught in the first
course in power electronics since it has many advantages over
Sine-PWM. The original contributions of this paper are as
follows: 1) a better carrier modulation in PWM, 2) rationale
for using space vectors in the first course, and 3) a clear
explanation of carrier-based implementation of SV-PWM.

REFERENCES
[1] Mohan, N., First Course on Power Electronics, MNPERE, 2003.
[2] Mohan. N., Undeland T.M., Robbins W.P., Power Electronics –
Converters, Applications and Design, 3/e, John Wiley & Sons, 2003.
[3] Holmes, D.G., Lipo, T.A, Pulse Width Modulation for Power
Converters, IEEE Press, 2003.
[4] Mohan, N., Electric Drives: An Integrative Approach, MNPERE, 2003.