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Abstract- In this paper, we propose a the bigger gates like 3×3quantum gate.
reversible 4-Bit binary counter with parallel Number of the 1×1 and 2×2 gates is quantum
load. It has minimum complexity and quantum cost (QC) of a reversible or quantum circuit.
cost considerably. The planned circuit is the Number of gates (NOG), number of constant
first attempt of designing a 4-Bit binary inputs (Gin), number of garbage outputs
counter with parallel load. Counter is (Gout), number of transistors and quantum
basically a register that goes through a cost are major factors of complexity in
predetermined sequence of state. The reversible logic design. The quantum cost is an
reversible gates in the counter are connected important factor for evaluating a circuit
in such a way as to produce the prescribed design. One of the major problems of
sequence of binary states. Then this counter reversible gates is that Fan-out is not allowed.
receives a 4-Bit data from input and delivers
data to D Flip Flop in subsequently cycle. Traditional irreversible logic circuits
Loading data from input is determined with were more simplex circuits than quantum or
Load property. Then the important reversible reversible logic circuits. Reversible logic has
gates used for our reversible logic synthesis efficient characteristic that constructs the
are Feynman gate, Fredkin gate and Peres circuits as a optimal design. The Conventional
gate. The planned circuit becomes a robust circuits if different with synthesis of a
design by our optimal method and using these reversible logic circuit. Some of the reversible
gates. The proposed circuit has minimum logic circuits are synthesized and optimized by
number of the garbage outputs and constant genetic algorithms. A reversible logic circuit
inputs in reversible circuit. The planned should use the below features:
circuit is the first attempt and efficient state
Minimum number of reversible gates.
for a nanometric reversible 4-Bit binary
counter. Further complex systems could be C Minimum number of garbage
constructed using the proposed circuit. outputs.
C Minimum constant inputs.
1. INTRODUCTION C Keep the length of cascading gates
minimum.
Reversible gates have applications in
quantum computing, low power CMOS Garbage output is some of the inputs
design, low power computing, optical that are not used for further computations.
computing, optimal information processing, Constant input is some of the inputs that are
nanotechnology and DNA computing. added to an n x k function. It causes to make
Quantum computing theory is basis of the circuits as reversible state. A circuit with
quantum gates. The reversible state of flip-flops is considered a sequential circuit
Quantum mechanical system is foundation of even in the absence of combinational logic.
reversible quantum circuits. The 1×1 and 2×2 Circuits that consist of flip-flops are usually
quantum gates are introduced in some classified by the function of them. Counter is
quantum techniques (Kaye, 2007). We use essentially a register that goes through a
from 1×1 and 2×2 quantum gates to implement predetermined sequence of states. Gates in the
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INTERNATIONAL JOURNAL OF INNOVATIVE TECHNOLOGIES, VOL. 01, ISSUE 03, SEP 2013 ISSN 2321 –8665
counter are connected in such a way as to system than you are accustomed to. Generally
produce the prescribed sequence of binary we use a decimal counting system; meaning
states. These gates construct a counter circuit. each digit in a number is represented by one of
A counter with parallel load can be used to 10 characters (0-9). In a binary system, there
create any desired count sequence. A 4-bit can only be two characters, 0 and 1.A
counter with parallel load can be used to computer does not recognize 0 or 1. It just
generate a BCD count in two ways: works on voltage changes. What we call logic
0 to a computer is zero volts. What we call
Using the load input: Overview of this design logic 1 is +5 volts. When a logic state changes
is shown in Fig. 1. from a zero to a one the voltage at the pin in
Using the clear input: Overview of this design question goes from zero volts to +5 volts.
is shown in Fig. 2. Likewise, when a logic state changes from a
one to a zero the voltage is changing from +5
volts to zero volts. While counting up in a
decimal system, we start with the initial digit.
When that digit ‘overflows’, i.e. gets above 9,
we set it to 0 and also add one to the next digit
over. The similar goes for a binary system.
While the count goes above 1 we add one to
the next digit over and set the first digit to 0.
Here, an example.
BINARY COUNTING
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3. REVERSIBLE LOGIC
Fig. 4 D Flip Flop gate.
In this section, we describe the
structure and functionality of reversible gates Nanometric Reversible 4-Bit Binary
that are used in our design. Some of the Counter with Parallel Load
reversible gates are described to compare with
other studies. Finally, we will discuss about The construction and operations of a
quantum gates. There is a one-to-one 4-Bit binary counter with parallel load is
correspondence between the inputs and the shown in Fig. 5. The important reversible
outputs. Thus an n-input n-output function F is gates used for our reversible logic synthesis
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INTERNATIONAL JOURNAL OF INNOVATIVE TECHNOLOGIES, VOL. 01, ISSUE 03, SEP 2013 ISSN 2321 –8665
SIMULATION RESULTS
6. CONCLUSION
In this paper, we proposed a robust
reversible circuit for a 4-Bit binary counter
with parallel load. The proposed reversible
circuit is the first attempt of designing the
Fig 5. 4-Bit binary counter with parallel load mentioned counter. It has minimum
complexity and quantum cost considerably.
We have performed XOR, AND, OR Table 2 demonstrates the proposed reversible
operations using Peres gates. in the second circuit is a first attempt and efficient design in
approach, we have used D Flip Flop to stores term of hardware complexity, garbage outputs,
the entered or incremented data. In addition, it constant inputs, and number of gates.
wants four Feynman gates to copy the outputs However, restricts of the reversible circuits
data and feedback them to the circuit inputs. were avoided excellent. More complex
systems could be also constructed using our
proposed circuit. Some of the techniques to
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INTERNATIONAL JOURNAL OF INNOVATIVE TECHNOLOGIES, VOL. 01, ISSUE 03, SEP 2013 ISSN 2321 –8665
reduce the constant inputs and garbage outputs [9]. Kaye, P., R. Laflamme and M. Mosca,
might be possible. In addition, some other 2007. An Introduction to Quantum Computing
optimization techniques like genetic algorithm (Oxford University Press).
may be utilize to reduce the quantum cost of
the circuit. [10]. Gupta, P., A. Agrawal and K.J. Niraj,
2006. An algorithm for synthesis of reversible
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