Substrate

Substrate Noise
Noise
Ruey-Beei Wu
Department of Electrical Engineering
National Taiwan University
May 2005

Contents
• Introduction and Experiment
• Noise Injection Mechanism
• Noise Reception Mechanism
• Noise Propagation Mechnism

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National Taiwan University

1
 Noise in Mixed-Signal Design
• Corsstalk between noisy digital and sensitive
analog portions, through
– Interconnect parasitics
– Silicon substrate.
• Especially highly doped bulks used in low-cost CMOS desig

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Substrate Noise Coupling Mechanism

• Threshold voltage
• Impact ionization
variations (body effect)
current Noise propagates
• Capacitive coupling
• Capacitive coupling through substrate
between substrate & G,
from junctions
D, S nodes
• Resistive coupling

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2
 Experimental setup

2x2 mm CMOS test

chip in a 2µm n-well
technology

NMOS
current source

12 CMOS
Quantification of
inverter
substrate noise
• Vp-p
• Settling time to
0.5mV

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Simulation Setup

Device/circuit structure for

PISCES-IIB simulation

• L1, L2, L3: bond wires &

package traces inductances
• L4: inductance series with
backside substrate contact
• 50Ω: Zin of oscilloscope
• Excitation: -5V to 0V pulse
with 1ns rise/fall times
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3
 Effect of Physical Separation
• Vp-p indep. of distance between
current source & noise source

Current flow 0.1ns after excitation

• Most of lateral current flows in

heavily doped bulk.
• Heavily doped bulk works as a
single node.
• Analog & digital circuits should
> 4X thickness of lightly doped
epitaxial layer.
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Effect of Current-Source Guard Rings

(a) (b)

• A p+ guard ring close to current course provides reduction of ~20%

in substrate noise, but more distant one has little effect
• Guard rings connected to large substrate contacts result in an
increase in substrate noise 國立台灣大學
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 Inductance in Substrate Bias

• Use of a low-impedance connection to negative supply

voltage can reduce substrate crosstalk.
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Effect of Lightly Doped Substrates - Simulation

• Isolation between digital

& analog circuits
improves as separation
• P+ guard ring diffusion
reduce the switching
noise by almost an order.

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5
 Circuit Modeling

R EP 1 = R AREA // R PER ;
ρT
T R AREA = ;
A
A: surface area of
substrate contact
ρ
R PER =
P
P: perimeter of
substrate contact

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Schematic Representation & Results

• CS8: cap. (bulk & IC package cavity), n-well

• RS3: spreading res. (surface substrate & bulk
node)
• LP5: ind., # bonding pads & package pins. 國立台灣大學
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 Reducing Substrate Crosstalk
• Transfer function
– Resonance freq.

• VTRANS unit step

• Noise reduction
– Decrease Cc w.r.t. Cs
– Decrease Ls w.r.t. Rs

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Digital-to-Bulk Coupling
• Resistive coupling: switching transients couple resistively into
bulk though p+ bulk contact, if bulk is biased with a switching ground.
• Capacitive coupling: Voltage fluctuations on source & drain can
couple to the bulk through junction-bulk capacitance.
• Impact ionization: least-significant. Generated at the pinch-off
point of nMOS
transistors and
causes a hole
current in the bulk.

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7
 Device Noise Injection Mechanisms
Current inject from MOSFET into substrate, (CMOS device from
an 0.25µm, 3.3V technology, fabricate on a p-epi/p+-Si substrate)
• Impact ionization current
– Some “hot” carriers scatter and swept to the substrate
• Capacitive coupling
– Voltage fluctuations on source & drain can couple to the bulk
through junction-bulk capacitance.
• Gate induced drain leakage (GIDL)
– Does not have a significant impact on substrate crosstalk
• Delta-I noise at power-supply lines
– Power-supply lines are typically used to bias n-wells and substrate.

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Impact Ionization Current

GIDL

n-channel p-channel

Channel width W=15µm, & various length L. VDS=3.5V

II current in PMOSFET is one order of magnitude less than in NMOSFET,
hence only II current in NMOSFET is considered.
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 Relative Impact Ionization Current

α II = α 0 e − β / E Switching current of an inverter

vs. VIN and resultant II current

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Substrate Current due to an Ideal Inverter

• NFET bulk node is tied directly to ground, and PFET bulk
node (n-well) to VDD.
• Simulated substrate current
• For low-freq excitation, II
causes the larger rms current
• Capacitive coupling begins
to dominate around 10MHz,
and is proportional to freq.

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9
 Substrate Injection vs. Output Load
• Excitation: square wave with 0.2ns
rise/fall times, for a 100fF load

For typical internal loads, II

currents are one order smaller
than capacitive currents which
are in turn one order smaller
than the switching current.
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Influence of Circuit & Substrate Parasitics

• It is the voltage fluctuations in the substrate that couple to sensitive
analog transistors and cause crosstalk.
• VSUB to VSS by RSUB
– Dashed line is shorted
– VSUB-VSS ~0
– VSS mainly by circuit
switching current
• Separate connection
– Dashed line is open
– VSS has additional low-freq
fluctuations, & a nonzero
components
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10
 Substrate Voltage due to a Large Circuit

•Total Vrms is N
times Vrms of a
single switching Total Vrms is N
current. times Vrms of a
•Low freq comp., single switching
e.g., impact current
ionization, play a
more important
role in large
circuits
σT: Gaussian uncertainly in starting time
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Bulk-to-Analog Coupling
• Resistive coupling: substrate noise couple resitively thourgh p+
bulk contact, if bulk is biased with the analog ground rail.
• Capacitive coupling: substrate noise coupled into analog circuit
power and ground rails through n-well junction capacitance and the
source-to-bulk junctions.
• Body effect: Channel depletion causes increases in Vt, results in a
sporadic decrease
in Ids current.

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11
 Noise Reception Mechanisms
• Through junction capacitances
– Diffused resistors and capacitors may be affected
capacitively by substrate noise
• Through body-effect
– Increases with substrate doping
• Through power-supply lines
– Substrate noise may be acquired by these lines through
the contacts, and thus affect analog circuitry.

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Test IC Designed
• 1.2µm CMOS technology
• Wafer:
– p- with 8.5 Ω cm
– p+ with 0.7mΩ cm, and an
epitaxial layer 12 µm & 8.5 Ω cm
• Digital section:
– 0~512 buffers
– Clock driven at 1MHz and 1ns
transition time
– 0.5ns rise time and 0.4ns fall time
• Analog sensor:
– two-transistor amplifier
– Output to analog pad, with a
1MΩ//2pF probe

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12
 Measurement – in a heavily-doped wafer p+
Noise waveforms detected with the amplifier sensor by (a) rising (b) falling
edges at the output of noisy buffers.

essentially
the same

Most of the noise is introduced to the substrate from digital power-

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supply lines, not through the junctions of switching transistors
National Taiwan University

Measurement – in a lightly-doped wafer p-

essentially
the same

• Most of the noise is from digital power-supply lines.

• Noise levels are ~1/3 of those in heavily-doped wafer p+
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 Discussion
• Noise attenuation behavior depends on wafer type.
Lightly-doped wafers are ~1/3 less noisy, and are more
advisable than heavily-doped ones.
• Delta-I noise at the power-supply line a a major contributor
to substrate noise, while junctions and body-effect are
minor. The reduction:
– Accurate package and pin assignment selection to minimize
inductances of the power-supply pins
– Policies to partition and disable pars of the digital circuitry to
reduce number of switching gates
– Avoid the use of analog lines to ground the substrate, using wells
for isolation purposes
– Minimize the noise introduced through IC periphery by caring for
the substrate contacts in the pads.
– The last, add guard rings or use circuit topologies to reject noise.

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Modeling & Analysis

• Modeling of substrate coupling
• Analysis for functional dependence of
– substrate model-elements
– substrate isolation on the cross-section of the substrate
– contact-to-contact distances
– other relevant parameters.
• Discussion of guard rings.
• Experimental verification

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 Equivalent Resistance Modeling

1 2

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Electrostatic Green’s Function

r r
J = σE = −σ∇ φ
σN In substrate :
σ2 r
σ1 ∇ ⋅ J = −∇ ⋅ σ∇ φ = 0
r
σ0 J ⋅ nˆ = 0 ⇒ ∂φ ∂n = 0
r r r r
φ (r ) = ∫ J n (r ′)G (r , r ′)dr ′
r On contact, I = ∫ σ ∂φ ∂n
V'

1 β N tanh (γ mn d ) + ΓN
f mn = ×
ab γ mnσ N β N + ΓN tanh (γ mn d )
⎡ β k ⎤ ⎡ σ k −1 σ k − θ k2 (σ k −1 σ k − 1) ⋅ θ k ⎤ ⎡ β k −1 ⎤
⎢ Γ ⎥ = ⎢(1 − σ k −1 ) ⋅ θ ⎥
1 − σ k −1 σ k ⋅ θ k2 ⎦ ⎢⎣ Γk −1 ⎥⎦
⎣ k⎦ ⎣ σk k
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15
 Resistance/Conductance Matrices
φi r r r r
pij = =∫ ∫ G (r , r ′)dr dr ′
Ij Vi V j

k mn ⇒
DFT

k mn ⇒
DFT

[φ ] = [ p ][I ]matrix⇒
inversion
[I ] = [g ][φ ]φ =const. on⇒same contact g IJ ' s
N3 complexity! Special methods are required to expedite the
computation.
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Isolation on Substrate Properties

Equivalent
substrate
model

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 Isolation in Low-Resistivity Substrate

For low-resistivity substrate, isolation is indep. of separation between

contacts beyond a certain critical separation (2.5-5X epitaxial thickness)
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Isolation in High Resistivity Substrate

For high-resistivity substrate, isolation is a weak function of back-

plane inductance

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 Modeling for Guard Ring

Guard ring

• Guard ring is not effective in improving isolation in low-resistivity

substrate due to vertical current flow. It works well in high-
resistivity substrate because of surface current flow.
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Effect on Isolation

• Isolation is weakly
related to guard ring
width.
• Thin guard rings are
preferable to wide ones
for which more noise
can be sensed and
injected to substrate.

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18
 Experimental Verification

• 20 distributed contact, with sizes

from 2x2 to 120x120 µm2,
• Edge to edge spacing between
contacts vary from 2 to 150µm.

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Comparisons between Measurement/Simulation

The measured current exiting

other contacts with voltage at
the largest contact is set at 1V

voltage division ratio

Vi V
j =1, all other Vk ≠i , j = 0

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 Noise Reduction Methods
• Providing a low-noise, low-impedance connection
for power, ground, and substrate
• Making any listeners less noise sensitive
• Suppressing/silencing the talkers
• Separating the talker/listener by either proximity
separation, time separation, or frequency
separation.

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Some Tips (-1)

• Differential circuits and signals provide common-mode
noise rejection and less sensitivity to power and ground
noise.
• Limiting circuit bandwidth helps to avoid noise
amplification – using just enough bandwidth to get the job
done. Plus, RF filters on analog signals can cut down on
parasitic coupling of noise.
• Reducing the number of external analog signals minimizes
opportunities for noise coupling. Using large amplitude
signals directly improves the S/N ratio.
• Internally distributed power filtering places in unused areas,
under metal traces, and in similar locations can provide
better power stability, especially at high frequencies.
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 Some Tips (-2)
• Extensive use of grounded substrate contacts, n-well tie-ups, and
guard rings will reduce substrate noise.
• Signal separation/shielding helps to avoid noise coupling through
parasitic capacitance. By using separated analog-digital routing
and keeping talker-listener signals apart, noise concerns improve.
• Major source of noise for mixed-signal ASICS comes from
digital transition switching. Strategies to decrease its generation
include minimum drive strength devices, low-noise logic types,
differential output drivers, and limited slew-rate devices.
• Some analog circuits produce noise due to transition switching.
On/off current situations, current and voltage pulses, and any
switched step voltages may happen. Removing these elements, or
reducing their effects as a noise generator, will give better noise
performance.
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Circuit Placement Tips

• Use independent power/ground connections for digital and
analogy circuits. It provides no direct path for noise due to
digital transition switching on analog circuit power.
• Parallel filter capacitors of different values can provide
more effective power filtering at higher frequencies.
• Empty locations in the IC layout can be filled with filter
capacitors.
• Keep analog signal paths short. Digital and analog signals
should be kept away from each other when possible.

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 Pin Placement Tips
• Analog pins can be isolate by the use of adjacent ground or
“quiet” dc power pins.
• Static digital signals are low noise and can be used for
separation.
• Any high-frequency digital pins should be separated by
static controls of power/ground pins. Doing so decreases
cross-coupling effects between adjacent digital pins.
• Avoid long interconnects on any analog signals.
• Any externally connected analog signals should have their
internal circuits at close proximity to their I/O cell.
• With a careful selection for pin placement, the analog area
should not have any close-proximity digital drive I/O cells.
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Further Reading (1)

• D. K. Su, M. J. Loinaz, S. Masui, and B. A. Wooley, “Experimental
results and modeling techniques for substrate noise in mixed-signal
integrated circuits,” IEEE J. Solid State Cir., vol.28, pp.420-430, April
1993.
• J. Briaire and K. S. Krisch, “Principles of substrate crosstalk
generation in CMOS circuits,” IEEE Trans. CAD, vol. 19, pp.645-653,
June 2000.
• X Aragones and A. Rubio, “Experimental comparison of substrate
noise coupling using different wafer types,” IEEE J. Solid State Cir.,
vol.34, pp.1405-1409, Oct. 1999.
• R. Gharpurey and R. Meyer, “Modeling and analysis of substrate
coupling in integrated circuits,” IEEE J. Solid State Cir., vol.31,
pp.344-353, March 1996.

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 Further Reading (-2)
• T. Li, . H. Tsai, E. Tosenbaum, and S. M. Kang, “Substrate modeling and
lumped substrate resistance extraction for CMOS ESD/latchup circuit
simulation,” Proc. Design Automat. Conf., pp.549-554, June 1999.
• M. Felder and J. Ganger, “Analysis of ground-bounce induced substrate
noise coupling in a low resistive bulk epitaxial process: design strategies
to minimize noise effects on a mixed-signal chip,” IEEE Trans. Cir. Sys.
II, vol. 46, pp.1427-1436, Nov. 1999.
• J. Twomey, “Noise reduction is crucial to mixed-signal ASIC design
success (Part I, II),” Electronic Design Mag., Oct./Dec. 2000.

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