1

Module 1 1
Laboratory Exercises

Introduction to Logic gates and Circuit Design

Jeffrey
Sarmient
o
Intended Learning
Outcomes
1. Understand the
concept of Logic
Gates and Logic Circuits
2. Introduced to basic circuit wiring and trouble shooting
3. Simulate basic circuit connection using Logic Devices
4. Knows and Understand the IC families and their pin configuration
5. Able to make a schematic diagram and simulate a result

1.1 Introduction
This experiment aims to introduce the basic circuit wiring and troubleshooting. The
behaviour of several basic logic gates will tested and in this lab we will also connect several
logic gates to create a simple circuits.

1.2 Materials
Basic Logic Gates Connecting wire Wire Stripper
Breadboard (Optional) or Trainer Board Multimeter

Or

Logic Circuit Simulation Software

1.3 Theory
The basic logic gates are the building blocks of more complex logic circuits.
These logic gates perform the basic Boolean functions, such as AND, OR, NAND, NOR,
Inversion, Exclusive-OR, Exclusive-NOR. Fig.1.0 below shows the circuit symbol, Boolean
function, and truth. It is seen from the Fig that each gate has one or two binary inputs,
A and B, and one binary output, C. The small circle on the output of the circuit symbols
designates the logic complement. The AND, OR, NAND, and NOR gates can be extended

Authors : Sarmiento, J.; Macabagdal, C.B.; Serrano, R.R.; Magboo, A.

 Module 1 2
Laboratory Exercises

to have more than two

inputs. A gate can be
extended to have multiple
inputs if the binary
Jeffrey
Sarmient
o
operation it represents is
commutative and
associative. These basic
logic gates are
implemented as small-scale integrated circuits (SSICs) or as part of more complex
medium scale (MSI) or very large-scale (VLSI) integrated circuits. Digital IC gates are
classified not only by their logic operation, but also the specific logic-circuit family to
which they belong. Each logic family has its own basic electronic circuit upon which
more complex digital circuits and functions are developed. The following logic families
are the most frequently used. TTL Transistor-transistor logic ECL
Emitter-coupled logic MOS Metal-oxide semiconductor CMOS Complementary metal-
oxide semiconductor TTL and ECL are based upon bipolar transistors. TTL has a well
established popularity among logic families. ECL is used only in systems requiring high-
speed operation. MOS and CMOS, are based on field effect transistors. They are widely
used in large scale integrated circuits because of their high component density and
relatively low power consumption. CMOS logic consumes far less power than MOS logic.
There are various commercial Logic Design Laboratory Manual integrated circuit chips
available. TTL ICs are usually distinguished by numerical designation as the 5400 and
7400 series.

1.4 Procedure
We Will test in this experiment the different behaviour of Basic Logic gates,
including AND, inverters, XOR gates, OR gates, NOR gates, NAND gates. The gate is
implanted in an IC package. The Figure 1.1 and 1,2 shows the pinouts for these circuits. The
detailed specification of the TTL IC can be seen on their datasheet which is available for
download in their respected website

Authors : Sarmiento, J.; Macabagdal, C.B.; Serrano, R.R.; Magboo, A.

 Module 1 3
Laboratory Exercises

Jeffrey
Sarmient
o

Experiment 1

LEARNING OBJECTIVES

To know the basic connections to implement a logic circuits using various IC

74LS04 (inverter) gate.

1. Check the pinout for this chip on figure 1.2.

2. Insert the 7404 chip on the middle of the breadboard and it should be like the figure
1.1

Authors : Sarmiento, J.; Macabagdal, C.B.; Serrano, R.R.; Magboo, A.

 Module 1 4
Laboratory Exercises

Figure 1.1

3. By looking on the pinout,

identify the power source
(VCC) and ground (GND).
Connect the VCC on the +
Jeffrey
Sarmient
o
source and the GND to
the – source.
4. The chip (7404) contains
6 inverter gates and each
input and output has
their own corresponding pin number. From the pin configuration, choose the gate to
be tested. Connect a wire to both HIGH (1) and LOW (0) consecutively to the input pin
of the chosen gate.
5. To test the functionality of the gate, connect 330 ohm resistor to the output pin of the
chosen gate to any place outside the IC. Connect the Light Emitting Diode (LED) as
seen in figure 1.2.

6. Turn on the power supply. If the Input pin is connected to the LOW(0) voltage the
output LED should Light ON(1) otherwise if the input pin is connected to the HIGH(1)
the output LED should have no light (0)

33
0Ω

LE
D

Figure 1.2

7. Assume A is the input to the inverter (either 0 or 1) and that Y is the output.
Fill in Table 1.1 according to the logic behavior that you observe.

Note: First fill in the second column of the table using the readings from the
multimeter. Then determine the answers to the last column based upon these
readings. If the output is high (H), the multimeter will read approximately 4.4 volts;
when it is low (L), the multimeter will read about 0.15 volts. If you read a voltage
between these values, you have likely wired your circuit incorrectly.

Table. 1.1
Inverter logic behavior
A Y

Authors : Sarmiento, J.; Macabagdal, C.B.; Serrano, R.R.; Magboo, A.

 Module 1 5
Laboratory Exercises

Jeffrey
Sarmient
o
Voltag Curren Logic
e t
0

Authors : Sarmiento, J.; Macabagdal, C.B.; Serrano, R.R.; Magboo, A.

 Module 1 6
Laboratory Exercises

Jeffrey
Fig. 1.3:
Pinouts of
the 7400
series TTL
logic
gates.
Sarmient
o
Fig. 1.4:
Pinouts of
the 7400
series TTL logic gates.

Experiment 2
LEARNING OBJECTIVE

Identify various ICs and their specification.

1. Repeat the same experiment with the other basic gates 74LS00 (NAND), 74LS02 (NOR),
74LS08 (AND), 74LS32 (OR), and 74LS86 (XOR).
***Note Refer to figure 1.2 and 1.3 for pin configuration, The pin configuration may differ on every
IC.

Complete the table below.

Table 1.2

NAND
A B
Voltage Current Logic
0 0
0 1
1 0
1 1

AND
A B
Voltage Current Logic
0 0
0 1
1 0

Authors : Sarmiento, J.; Macabagdal, C.B.; Serrano, R.R.; Magboo, A.

 Module 1 7
Laboratory Exercises

1 1

Jeffrey
Sarmient
o
OR
A B
Voltage Current Logic
0 0
0 1
1 0
1 1

NOR
A B
Voltage Current Logic
0 0
0 1
1 0
1 1

XOR
A B
Voltage Current Logic
0 0
0 1
1 0
1 1

Authors : Sarmiento, J.; Macabagdal, C.B.; Serrano, R.R.; Magboo, A.

 Module 1 8
Laboratory Exercises

Jeffrey
Sarmient
o
A B

XNOR
Voltage Current Logic
0 0
0 1
1 0
1 1

Findings and Conclusion:

Authors : Sarmiento, J.; Macabagdal, C.B.; Serrano, R.R.; Magboo, A.

 Module 1 9
Laboratory Exercises

Experiment 3
Learning Objective
Able to make a schematic
diagram and simulate a
Jeffrey
Sarmient
o
result

The logic gates can be

connected to each other to form a combinational circuit with unique functions. The
experiment aims to introduce a procedure for wiring schematic diagrams. Connect the
circuit shown in figure 1.3

Fig. 1.5: Circuit A

Table 1.3 Circuit A logic behaviour

A B C OUTPUT
(F)
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1

Authors : Sarmiento, J.; Macabagdal, C.B.; Serrano, R.R.; Magboo, A.

 Module 1 10
Laboratory Exercises

Jeffrey
Sarmient
o
1 0
1 1 1

. Findings and Conclusion

Authors : Sarmiento, J.; Macabagdal, C.B.; Serrano, R.R.; Magboo, A.