22 Chapter 2 VHDL and Digital Circuit Primitives

2.4 COMBINATIONAL GATES

Basic combinational gates perform various logical operations such as NAND, NOR,
AND, OR, and INVERTERS. These basic gates can be generated with various VHDL
constructs. The following VHDL code shows four, two-input NOR gates which can be
generated with different VHDL statements. Line 10 uses the VHDL Boolean operator
`nor' in a simple signal assignment statement. Lines 11 and 12 use the conditional
signal assignment statement to generate Y2 and Y3. Lines 13 to 20 use a process
statement with an if statement to generate Y4. Figure 2-13 shows the synthesized
schematic. It is clear that two-input NOR gates are used for these four different types
of VHDL constructs. The key is to write efficient good VHDL to model the circuit
function correctly. Most of the rest are left to the synthesis tools to generate function-
ally correct circuits that satisfy design requirements.

1 library IEEE;
2 use IEEE.std_logic_1164.all;
3 entity NORGATE is
4 port(
5 D1, D2, D3, D4, D5, D6, D7, D8 : in std_logic;
6 Yl, Y2, Y3, Y4 : out std_logic);
7 end NORGATE;
8 architecture RTL of NORGATE is
9 begin
10 Yl <= D1 nor D2;
11 Y2 <= '0' when (D3 or D4) = '1' else '1';
12 Y3 <= '1' when (D5 nor D6) = '1' else '0';
13 p0 : process (D7, D8)
14 begin
15 if (D7 = '1') or (D8 = '1') then
16 Y4 <= '0';
17 else
18 Y4 <= '1';
19 end if;
20 end process;
21 end RTL;
2.4
24 Combinational Gates 23
Chapter 2 VHDL and Digital Circuit Primitives

D1 Y1

D SE>
D 4r> Y2
- 1 1
1 DYE
C ) . -

D5
D
Figure 2-13 Synthesized schematic for norgate.vhd.

Other basic combinational circuit primitive gates include the multiplexer (or
simply called MUX) and AND-NOR gates. However, they do not have a single
VHDL Boolean operator to correspond. The following VHDL code shows examples
to describe the multiplexer and AND-NOR functions. Line 13 uses VHDL Boolean
operators 'and' and 'nor' to describe the AND-NOR gate function. Line 14 describes
a multiplexer function. A multiplexer is also called a selector because the output is
selected from the inputs based on the selection signal. In line 14, D4 is the selection
signal. Y2 is assigned to D5 if D4 is '1', otherwise, Y2 is assigned to D6. Line 23 is
similar except that the target signal is 2-bit wide and the concatenation operator '&' is
used. Line 24 is a concurrent procedure call statement. Lines 15 to 22 use a pro-
cess statement with an if statement inside. Note that the sensitivity list (line 15)
should include all signals that are read within the process statement. Figure 2-14
shows the synthesized schematic with AND-NOR and 2-to-1 MUX gates.
UX2 111

(> Y2
 OV EC2I61
UX2 1E4
YVEt 1121

AEc31., DVEC2[1:0] UX2 1

NUX21H
___Ej . Y3 YVEL1I11
DVEC3[1:01:1*__
D V E C 1 [ 1 , 0 1 : › _____ DV EC1 I

Figure 2-14 Synthesized schematic for complex.vhd.

MUX2 1
YVEL 2.31
YVEC2[1:0]
1 library IEEE; D E C I I 8

2 use IEEE.std_logic_1164.all;
3 use work.pack.all;
4 entity COMPLEX is flUX2 1
5 port( YVE L2,11

6 D1, D2, D3, D4, D5, D6 : in std_logic;

7 DVEC1, DVEC2, DVEC3 : in std_logic_vector(1 downto 0);
8 YVEC1, YVEC2 : out std_logic_vector(1 downto 0);
9 Yl, Y2, Y3 : out std_logic);
10 end COMPLEX;
11 architecture RTL of COMPLEX is
12 begin

Y1
2.4 Combinational Gates 25

13 Yl <= (D1 and D2) nor D3;

14 Y2 <= D5 when D4 = '1' else D6;
15 p0 : process (DVEC1, DVEC2, D6)
16 begin
17 if (D6 = '1') then
18 YVEC1 <= DVEC1;
19 else
20 YVEC1 <= DVEC2;
21 end if;
22 end process;
23 YVEC2 <= D3 & D4 when D2 = '0' else D5 & DVEC1(0);
24 KMUX21(D1, DVEC3(0), DVEC3(1), Y3);
25 end RTL;

The same complex.vhd can also be synthesized with the schematic shown in
Figure 2-15 without using MUX gates. Figure 2-14 schematic has the following area
statistic.

1 Number of ports: 19
2 Number of nets: 19
3 Number of cells: 7
4 Number of references: 2
5
6 Combinational area: 26.000000
7 Noncombinational area: 0.000000
8 Net Interconnect area: 41.065342
9
10 Total cell area: 26.000000
11 Total area: 67.065338

Figure 2-15 schematic has the following area statistic. Based on these two sche-
matics and area statistics, they have a different number of gates, interconnect nets, and
total area measurements. Their timing delays are not shown here, but they are also dif-
ferent. However, they should have the same logical function. They conform to the
golden rule of synthesis: meet the timing requirement (speed) with the smallest possi-
ble area. When the design is big and complex, there is no time to worry about what
types of combination gates synthesis tools use for the design. The particular type of
combinational gates used by the synthesis tools should be the lower priority that
designers need to worry. Designers can spend more time on the architecture, function-
ality, speed, and area requirements by applying the synthesis tools to achieve their
goals.
1 Number of ports: 19
2 Number of nets: 26
3 Number of cells: 14
4 Number of references: 5
5
6 Combinational area: 24.000000
26 Chapter 2 VHDL and Digital Circuit Primitives

7 Noncombinational area: 0.000000

8 Net Interconnect area: 60.131393
9
10 Total cell area: 24.000000
11 Total area: 84.131393

Figure 2-15 Synthesized schematic for cornplex.vhd without MUX gates.

2.5 VHDL SYNTHESIS RULES

We have discussed various ways to write VHDL code so that flip-flops, latches,
three-state buffers, and combinational circuits can be generated by synthesis tools. It