Future perspective for the mainstream CMOS technology and their

contribution to green technologies

Hiroshi IWAI

Frontier Research Center,

Tokyo Institute of Technology
4259, Nagatsuta, Midori-ku, Yokohama 226-8502, Japan

E-mail: iwai.h.aa@m.titech.ac.jp

Abstract Recently, CMOS technology has been recognized as an ultimate technology towards the limit of downscaling of
electronic devices for logic circuits. In other words, CMOS will keep the position of mainstream device technology as the key
components for logic integrated circuits almost for ever as long as the integrated circuits are necessary for our society, even
after all the logic electronic devices reach their downsizing limits. It is expected that there are still several generations or 15 ~
25 years until the CMOS device really reaches the downsizing limit caused by the direct-tunneling between the source and
drain. In order to accomplish the downscaling of CMOS devices successfully, suppressing the SCE (Short Channel Effect) or
suppressing the off-leakage current with keeping its high performance is the most important. There are two major solutions to
suppress the SCE; One is pushing high-k gate insulator technologies to keep thinning the gate oxide, and the other is changing
the transistor structure from the planar to the 3D multiple gate structures towards nanowire FETs. In this paper, future
perspective for the mainstream CMOS technology is described from the view point of its downsizing. The downsizing of
CMOS devices is still the very effective way to increase the performance and to decrease the power consumption of integrated
circuits, and the progress of CMOS device technology will contribute to the ‘green technologies’ by increasing the efficiency
of the operation of every system controlled by microprocessors.

Key words Silicon, CMOS, mainstream, high-k, nanowire, green,

 further aggressive for the most of logic semiconductor
1. Introduction companies to catch up. Thus, the future trend for logic
Recently, power saving for all the human activities are device has to be adjusted to be slightly less aggressive in
strongly requested in order to prevent the global warming, ITRS 2009, resulting in the delay in the gate-length
and high efficiency control of every system by shrinkage for several years in future as shown in Fig. 1
high-performance microprocessors is thought to be very [2].
important to save the energy loss. At the same time,
energy required for information and data communication
becomes non-negligible value in our society, as we can see
in the case of data centers, and thus, the saving of the
power consumption of integrated circuits temselves
becomes also very important.
For more than 40 years, the down-scaling of
MOSFETs has been the most important and effective way
for achieving the high performance and low power
consumption of LSIs. Now, the power consumption
became the limiting factor for the LSI technology design
[1], and clock frequency and chip area cannot very much
increased recently. Furthermore, the concern for the
technological difficulty for the downsizing becomes much
stronger than the past with expected large variations of Fig. 1 2009 ITRS trend for gate length [2]
electrical characteristics of smaller geometry MOSFETs.
We are also facing the tremendous cost increase in future However, the trend of gate length shrinkage continues
EUV lithography as well as that in the development till 8 nm in 2024 in the roadmap. Now, the question is
various sophysiticated new technologies. what is the limit of the gate length shrinkage. Of course,
However, still, the downsizing is the ‘royal road’ for there are many arguments regarding the reasons for the
increasing the performance and decreasing the production limit, such as sub-threshold leakage and cost of small
cost and power consumption, and thus, the effort of geometry lithography. However, the fundamental limit
downsizing of CMOS devices will be continued by all will be caused by the direct-tunneling between source and
means towards the limit at least for several more drain and that the limit will be about 3 nm as shown in
generations or 15 to 20 years, even though the duration Fig.2, and there is a possibility that CMOS gate length is
between the generations would become longer, because the reduced to that value.
products with successfully down-scaled CMOS device will
dominate the market.
Tunneling MOSFET operation
This paper describes a future perspective for the distance
mainstream CMOS technology from the view point of its Lg = 3 nm?
downsizing. 3 nm S D

2 . Limit of CMOS downscaling and important

Fig.2 Gate length shrinkage limit by SD direct-tunneling
technology development towards the limit

Although, we do not know how far we can down-scale the

So far, the physical gate length of the logic CMOS has
CMOS device, the following three technologies are thought
been much smaller than the half pitch of the lithography,
to be the keys for pursuing the downsizing CMOS devices
however, the trends of the physical gate-length shrinkage
as the mainstream technology; The first is high-k gate
predicted by recent versions of the ITRS have been even
stack with EOT (Equivalent Oxide Thickness) less than
0.5 nm, the second is Si nanowire FET technology, and the
third one is metal (silicide) source/drain technology. Those
three are very effective to suppress the SCE or off-leakage
current between source and drain, and also to increase the
on-current. In this paper, the status of high-k gate and
Si nanowire technologies are explained.
3 . High-k gate technology with EOT less than
0.5 nm
The increasing power consumption is the limiting
factor of the logic CMOS, and lowering the supply voltage
is the most effective way to decrease the dynamic power
consumption. However, in order to decrease the supply
voltage, the threshold voltage has to be reduced. This
It should be noted that the gate insulator EOT value
stay at 0.5 nm as shown in Fig. 4. This kind of improper
down scaling, ― with keeping higher supply voltage and
larger gate oxide thickness ―, is the scheme of the
downsizing for the moment. However, the improper
scaling as shown in Fig. 5 enhances the short channel
effects, resulting in the larger off-leakage current and
larger variation of the threshold voltage. The solution to
the above problems is to develop high-k gate technology
with EOT below 0.5 nm, and key to this technology is to
use the direct contact between the high-k and silicon
substrate using rare earth oxides as the material as
shown in Fig. 6.
Solution

Without
results in the significant increase in the ‘off-leakage’ Gate Oxd
With
Gate Oxd
Gate Oxd
scaling
current because of the significant increase of the scaling

subthreshold leakage current with low threshold voltage.

Thus, the threshold and hence, the supply voltages cannot Problems
SCE
be scaled-down easily. Their values are supposed to stay Variation in Vth
Increase in Off-leakage current
above 0.1 and 0.9 V, respectively for next 10 years in
Fig. 5 Problems caused by improper scaling scheme with
recent ITRS as shown in Fig.3.
out gate oxide thickness scaling

1.2 SiO2/SiON
2008 update interfacial layer
2008 Metal
(S

1 For the past 45 years

ca

Metal
lin

20 SiO2 and SiON SiO2/SiON

P∝
g)

03 For gate insulator HfO2

0.8 ,2 Si 0.5～0.7nm
00
Lg
19

SiO2/SiON
3

5,
99
Vdd (V)

20 Si
Power per MOSFET (P)

07 45nm node
0.6 2008up (bulk) Introduction of High-k
Lg=22nm
20 2008up (UTB)
01 2008up (DG) Still SiO2 or SiON
0.4 2007 (bulk) Today Is used at Si interface
2007 (UTB) EOT=1.0nm Metal Direct contact
2007 (DG)
2005 (bulk) High-k High-k/Si
0.2 2005 (UTB) EOT Limit
2005 (DG) 0.7~0.8 nm Si
2003
2001 One order of Magnitude
0 1999 Direct Contact
EOT=0.5nm Of high-k and Si
2004 2007 2010 2013 2016 2019 2022

Year
EOT can be reduced further beyond 0.5 nm by using direct contact to Si
By choosing appropriate materials and processes.

Fig. 3 Supply voltage trend in ITRS Now Year

1.2 2008up (bulk)

2008up (UTB)

Fig. 6 Direct contact of high-k film to Si substrate

2008up (DG)
2007 (bulk)
2007 (UTB)
for HP Logic

1 2007 (DG)
2005 (bulk)
EOT (nm)

2005 (UTB) (a) EOT=0.37nm (b) EOT=0.43nm (c) EOT=0.48nm

2005 (DG)
3.5 Vth=-0.04V Vth=-0.03V Vth=-0.02V
Drain current (mA)

2003 (bulk)
0.8 2001 3 W/L=2.5/50m
W/L=50/2.5m
1999 PMA 300oC (30min) 4%up 14%up

2
0.6

0.4
0 insufficient
2004 2007 2010 2013 2016 2019 2022 compensation region 0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1
0
0 0.2
0.2 0.4
0.4 0.6
0.6 0.8
0.8 1
1 0 0.2 0.4voltage
Drain 0.6 0.8
(V) 1 0 0.2 0.4voltage
Drain 0.6 0.8
(V) 1
Delay Year Drain voltage (V)
Is 0.5nm real limit? Saturation
14% of Id increase is observed even at saturation region
Fig.4 Gate insulator EOT trend in ITRS
Fig. 7 MOSFET operation with EOT less than 0.4 nm
 nanowire FETs have advantages not only on the
We have already experimentally confirmed a good suppression of off-leakage current, but also on the
operation of MOSFETs with EOT of 0.37 nm using the on-current as shown in Fig. 8. Multi-layer nanowire [4]
La2O3 gate insulator as shown in Fig 7 [3]. Thus, in will increase the drain current density significantly.
future the EOT value predicted in the roadmap will Because the nanowire pattern itself is simple,
decreases a little further to solve the problems, and then, nano-inprint technology could be used for future
the supply voltage would decrease further in order to high-density lithography with extremely small pitch.
suppress the short channel effects. Also, The Si nanowire FET has higher on-current
conduction due to their quantum nature. If the ideal one
4 . Si nanowire FET dimensional ballistic conduction is realized for the
The planar logic CMOS devices will encounter its nanowire, the nanowire itself has basically a high
downsizing limit due to the huge off-leakage. In fact, quantum conduction with very small freedom of carrier
according to ITRS 2009, planar MOSFETs will disappear scattering. In addition, the channel current is multiplied
from the advanced MOSFET structure, and 3D multiple with the number of the quantum channel available for the
gate (or Fin type) structure will be introduced because of conduction.
its nature to easily suppress the SCE as shown in Fig. 8.
It is a natural trend that the Fin FETs will change to
nanowire FETs, because of more control of SCE and more
channel surface in a unit area as shown also in the figure

2010 2015 2020

Planar FET
FD-SOI FET

Multiple Gate
Si nanowire
(Fin) FET
FET

SiSiナノワイヤ
Nanowire
Bulk or SOI
Fin

Fig. 8 MOSFET structure trend in ITRS 2009

Planar structure 1
S D
1. Compatibility with
nanowire structure
current CMOS process Wdep
2. Good controllability of IOFF
cut-off
Off電流の
Leakage current カットオフ

3. High drive current

source
Drain drain
Source
Gate:OFF
Gate: OFF

Multi quantum
1D ballistic Channel High integration
conduction
バンド図 of wires
E

量子チャネル
Quantum channel
Quantum
量子チャネル channel
量子チャネル
Quantum channel
量子チャネル
Quantum channel Fig. 10 Band structure for different width and
k

orientation nanowire
1 With increasing the diameter of the nanowire, the number
of the conduction band available significantly increases as
Fig. 9 Advantages of nanowire FET over planer shown in Fig. 10 [5]. However the increase of the
quantum channel degrades the conduction because of the
One of the big advantages of Si nanowire FETs are carrier scattering between the conduction bands, and
their compatibility with today’s Si CMOS process. Si there is a trade off relation between the one-dimensional
ballistic conduction and the number of quantum channel FETs into the products is that there is no compact model
in terms of the nanowire width. Smaller wire diameter is to describe the Id-Vd characteristics of the MOSFETs for
desirable for one-dimensional ballistic conduction and the circuit designers. Recently, primitive model under
larger diameter is desirable for the umber of quantum ideal ballistic conduction [6] and that with scattering [7,8]
channel. were published as shown in Figs. 11 and 12, respectively.
Qf
Energy Figure 13 shows the comparison of the calculated
S Qb E2max
characteristics with ballistic conduction and scattering
D
E2min E2min
model. The calculation needs the E-k relation in the band
O xmax xmin x
D
qVD E1
S
structure, which is significantly affected by the nanowire
E0
diameter and orientation. It would take several more
k
Q  Q f  Qb 
Qb

 Qf  years to describe the Id-Vd characteristics with nanowire

  k i min 
q  dk dk 


 gi 
k  E ( k )   
 
 E ( k )     diameter and orientation dependence.
 i min 1  exp 1  exp
i  
 
i S i D

  k BT   k BT  

40
Vg-Vt=1.0 V 45
35

30
40
Current (uA)

25 T=1K 35 VG-Vt=0.1V,Bal.
0.7 V
20 T=300K VG-Vt=0.1V,Qbal
Current [uA] 30
15 VG-Vt=0.4V,Bal.
10 0.3 V 25
VG-Vt=0.4V,Qbal.
5 20 VG-Vt=0.7V,Bal.
0
0.05 V
VG-Vt=0.7V,Qbal.
0 0.1 0.2 0.3 0.4 0.5 15
Drain Bias (V) VG-Vt=1.0V,Bal.
10
VG-Vt=1.0V,Qbal.
5
Fig. 11 Compact model for Si nanowire with ideal
0
ballistic conduction and calculated Id-Vd characteristics 0 0.1 0.2 0.3 0.4 0.5 0.6
Drain Bias [V]

Linear Potential Approx. ： Electric Field E

Fig.13 Comparison of the calculated Id-Vd characteristics
Elastic Backscatt.
F(0)
Elastic Backscatt. ＋（Optical Phonon Emission） with ballistic conduction (broken line) and scattering
~kBT G(0)
Transmission (solid line) model.
V(x) Optical * Probability : Ti

Phonon 40
Source Channel x Vg-Vth=1.2V
Drain current (A)

x0 35
0 Initial Elastic Optical Phonon To Drain (step 0.2V)
Zone Emission Zone 30
25
Transmission F ( 0)  G ( 0) 
Probability T ( )   20
to Drain F (0)  Injection from Drain 0
15
10
2  ox 5
q CG 
 g   f ( ,  )  f ( ,  ) T d 
.
I  2r  t ox  t ox  Planar
 i
i s D i
ln   Gate 0
 2r  t ox  t ox  0 0.2 0.4 0.6 0.8 1.0
S  0 Q f  Qb
(VG  Vt )    .  S   D  qVD C  2  ox
. Drain voltage (V)
 r  t ox 
G
q CG GAA
ln 
(Electrostatics requirement)  r 




0 



 Fig. 14 Experimental results of Id-Vs characteristics of
  
gi  
q dk 1 1
Q f  Qb      Ti ( i (k ))dk 
 i
    i ( k )   S   
 1  exp   
  i (k )   S 
1  exp 
  i (k )   D  
 1  exp    Si nanowire FET with 10 nm diameter with gate length
  k BT    k BT   k BT  

2 D0 qE (Carrier distribution 200 nm and gate oxide thickness 3 nm

T ( )  in Subbands)
 qEx0   
 B0  D0  D0 qE  2mD0 B0 ln 
 
 

Experimental results of Si nanowire FETs show
extremely high drain current with good off-leakage control
Fig. 12 Compact model for Si nanowire with carrier
as shown in Fig. 14 [9]. Furthermore, recent experimental
scatterig
data shows very good potential for the Si nanowire FET as
One of the big problems for introducing Si nanowire
shown in Fig. 15 [10]. Based on those result, nanowire
FET will have much higher on-current which is predicted
in ITRS for future planar, SOI and multiple gate
MOSFETs.
Fig. 15 Bench mark of published naowire FET drain
current and our resent work.
5 . Long term future perspective
Fig. 16 Long term road map
Figure 16 [11] shows a long range roadmap including
the period which ITRS does not covers. The Si nanowire
FETs is the most promising candidate as explained. III-V
and Ge nanowire FETs are the 2nd candidate, which could
replace Si nanowire FETs. However, technical barrier for
the fabrication process is much higher compared with the
Si nanowire at this moment. In further future, CNTs
(Carbon Nanowire Transistor) and graphene ribbon FETs
could be candidates to replace the Si nanowire FETs.
However, they are still too far to say at this moment
because of no substantial idea for the integration method
of so huge number transistors in a chip and bandgap
control for high on/off ratio.
7 .Acknowledgement
This study was partially supported by the NEDO with
Nanoeletronic device program and Power saving program.
The author would like thank Profs. K. Shiraishi of
Tsukuba University, Profs. K. Yamada and K. Ohmori of
Waseda University, and Profs. K. Natori, K. Kaukshima
and P. Ahmet of Tokyo Institute of Technology and Drs. H.
Wantnabe, Y. Ohji, and K. Ikeda of Selete for the useful
information, materials, discussion and support for the
preparation of materials.
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[4] K. Tachi et al., IEDM Tech. Dig. 2009
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[8] K. Natori,JJAP, vol.48, p.03504-1, 2009
[9]K. Yamada, K. Kakusima et al. G-COE PICE
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