DEPARTMENT OF COMPUTER SCIENCE GOVERNMENT

COLLEGE UNIVERSITY, LAHORE

Final Examination Session (2019-2023)

Course: DLD (Practical) Semester: 2nd

Course Code: 2033-P Total Marks: 45
Dated: 03-09-2020 Time allowed: 3 hours and 15 minutes

INSTRUCTIONS
• Attempt any THREE (3) questions of the following.
• The submission folder will be consisting of two types of files. One type is
Proteus(Including all source file in one zip file) and the other is .docx
• In .docx file, you will have 3 heading for each task. Heading 1 for truth table and
circuit diagram with equations, Heading 2 for task’s output screenshot. Add as
many as to justify your output result. In addition, Heading 3 for viva voce questions,
and answer it in your own words.
• Write your name and roll number on each page. While taking picture of the paper, you
must place your student card along with the paper and then take snap of it. The picture
without student card will not be graded. Also, take picture of your laptop screen as well
with student ID card or CNIC against each task and paste in word file in the end,
Labeling as Task 1, Task 3, Task 6 and so on…..
• After that Copy all the files (.docx, Proteus) in a submission folder. The name of the
folder must be like Section-Roll No. (e.g. E1-0026-BSCS-13).
• Late submission will be marked as ZERO.
• Do not copy anything from others. Your circuit, document, output screenshot must
be unique. Plagiarized content will also be marked as ZERO.
• Upload your .docx and proteus file on LMS.

TASKS
1. Task: 1: Design and verify the truth table of a 3-bit Odd Parity generator and checker.
(Viva Voce): What is the use of Parity generator and checker in digital logic design?
(10+5 =15 Marks)
2. Task: 2: Implement and verify the truth table of a serial in Parallel out shift register.
(Viva Voce): Write down application of SIPO shift register and describe basic working
principle of shift register. (10+5=15 Marks)
3. Task: 3: Implement and verified expression of 4x1 multiplexer & 1x4 Multiplexer using
Logic Gates only.
 (Viva Voce): How to recognize selection lines for the designing of Mux and Demux?
Describe the basic working principle of Mux and Demux and write down its uses in
digital communication system? (Marks 10+5=15)

4. Task: 4: Design and verify the SR-Gated Latch using Universal Gates (NAND or NOR
Gates).
(Viva Voce): Why race condition occur in SR-Latch and how to overcome it?
(Mark10+5=15)
5. Task: 5: Implement the following Boolean expression using NAND gate Only?

(Viva Voce): Why use only NAND gates or only NOR gates? (Marks 10+5=15)

6. Task: 6: Design and implement 4-bits parallel adder (Using IC) for the given values
A3A2A1A0=0101 & B3B2B1B0=1111
OR
1-bit full Adder using Logic gates only
(Viva Voce): is it possible to design full adder using half adder? Yes or No justify your
answer. (Marks 10+5=15)