IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY-PART A, VOL NO 3, SEFTEMBER 1994

Design and Scaling of a SONOS Multidielectric

Device for Nonvolatile Memory Applications
Margaret L. French, Member, IEEE, Chun-Yu Chen, Student Member, IEEE,
Harikaran Sathianathan, Student Member, IEEE, and Marvin H. White, Fellow, IEEE

Abstract-The evolution of high-density EEPROM’s continu- TABLE I

ally imposes a demand on reducing power consumption while SUMMARY
OF NONVOLATILE
MEMORYTRANSISTOR
improving data retention and endurance. To meet these de- CHARACTERISTICS APPLICATIONS
FOR VARIOUS
mands, we propose a scalable multidielectricnonvolatile memory Applications Endurance Erase/Write Retention I
technology where the data storage is in the form of charge trap-
ping within the oxide-nitride-oxide (ONO) gate dielectric. This
Semiconductor Disk I lo5 Ims 10 years
NVRAM I 107 100 us 10 davs
technology, called SONOS (polysilicon-blocking oxide-silicon
nitride-tunnel oxide-silicon), has demonstrated remarkable
I Neural Network 109 us I minutes
scalability in programming voltage. To determine our scaling
guidelines, we have developed an analytical model for the tran-
sient characteristics that examines the influence of the dielectric grammed very frequently, it is necessary for the nonvolatile
composition and programming voltage on programming speed. transistor to have the features such as fast programming time,
These guidelines have resulted in a scaled SONOS nonvolatile high endurance, and moderate retention. The requirements of
memory device that has demonstrated 8-9 V programmability
with an extension towards 5 V and can be used as an ideal the nonvolatile memory transistor are summarized in Table
candidate for semiconductor disk, NVRAM, and neural network I. Depending on the application, different scaling guidelines
applications. may be followed.
Although present day Flash EEPROM’s are CMOS voltage
I. INTRODUCTION compatible, the input voltage is charge pumped from the
input power supply (3.3-5 V) to 12-20 V internally for

T HE increasing demand on low-power, low-voltage elec- programming [14, I]. T. Takeshima et. al. have designed
tronics has accelerated the pace of circuit designers to a 3.3-V single-power-supply 64-Mbit flash memory which
seek a promising candidate for high-density EEPROM’s. This requires 12 V internally to erase and 8 V on the bit line
new generation of EEPROM’s, characterized by high pack- and 5 V on the word line to write The high voltage
ing density, fast programming time, long memory retention, requirement has created a reliability issue, as it has exceeded
and high endurance for programming cycles, would gener- the voltage limit where a normal CMOS device can operate
ate an impact on applications such as semiconductor disks, without dielectric or junction breakdown. Therefore, special
nonvolatile random access memories, and neural networks. attention must be paid to designing high-voltage devices,
Semiconductor disks have shown their attractiveness in the which complicates the processing technology and hinders
replacement of the hard disks in portable computers which yield. Reduction of the programming voltage to 8-9 V with
mandates moderate programming speed and endurance but an extension towards 5 V simplifies the design and process
long retention. In the application of nonvolatile random access technology.
memory (NVRAM), the normal READWRITE operation is In this paper, we describe an alternative EEPROM technol-
undertaken by a SRAM cell that is accompanied in parallel ogy (SONOS) whose dielectric composition and programming
by a nonvolatile memory transistor acting as a shadow RAM voltage can be scaled according to the required application.
[20]. The nonvolatile memory is programmed every minute to First, we demonstrate the implementation of the SONOS
provide nonvolatility. Therefore, the EEPROM’s must possess device in an EEPROM array that can be applied to the semi-
fast programming speed, good endurance, and good retention. conductor disk application. Section 111 outlines the fabrication
On the other hand, for neural network application where the of the n-channel SONOS transistor. Since our main goal is
nonvolatile memory transistor can be used as the electrically to scale the programming voltage, we review the theoretical
reprogrammable synaptic element and is required to be repro- device behavior, including our closed-form transient analysis
Manuscript received March 8, 1994; revised May 12, 1994. This paper was and the basic retention characteristics in Section IV, and
presented at the Nonvolatile Memory Technology Review, Baltimore, MD, discuss how scaling the device affects both the speed and
June 22-24, 1993. This work was funded in part by the National Science retention. We present the measurement results of our devices
Foundation under Contract ECS-9023607 and the Office of Naval Research
under Contract “14-92-J-1672. in Section V and relate these results to the various NVSM ap-
M. L. French is with Elizabethtown College, Department of Computer plications. In particular, our results demonstrate a new scaled
Science, Elizabethtown, PA 17022 USA. SONOS structure (1.8-nm tunnel oxide, 5-nm nitride, and 4-
C.-Y. Chen, H. Sathianathan, and M. H. White are with the Sherman
Fairchild Laboratory, Department of Electrical Engineering and Computer nm blocking oxide) and the advantages and disadvantages of
Science, Lehigh University, Bethlehem, PA USA. scaling the tunnel oxide and blocking oxide.
1070-9886/94$04.00 1994 IEEE

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FRENCH et al.:DESIGN AND SCALING OF A SONOS MULTIDIELECTRIC DEVICE 39

x2

,i:,[[tn[innr,

(a) I

(a)

(b)
Fig. 2. Programming scheme for our SONOS EEPROM. A single program-
ming voltage (Vp)or ground is applied to the select lines (Xl, X2), word
(b) lines (Wl,W2), bit lines (BI, B2), and p-well (PW) or n-well (NW) to erase,
write, read, or inhibit the cell. Also, a sense amplifier (SA) is applied to one
Fig. Proposed (a) n-channel dual-gate SONOS memory cell in a p-well of the bit lines during the read mode.
and (b) p-channel dual-gate SONOS memory cell in an n-well.
TABLE I1

t
DUAL-GATE
MEMORYCELL SONOS DEVICESTRUCTURES
SONOS3
Using a dual-gate SONOS memory cell, previous investiga-
tors have obtained a high-density 1-Mbit SONOS EEPROM
1.1 nm
with n-channel transistors 1181. All the sources and p-wells nitride (XN) 5.0 nm
are tied together to reduce the memory area. Their SONOS 3.3 nm
EEPROM has been designed with a 1.2-pm address gate
length and a 1.5-pm memory gate length, yielding an 18.4
pm2 cell size. N. Ajika et al. have proposed a 16-Mbit floating
except for the formation of the tunnel oxide and the thickness
gate Flash EEPROM with a 3.6 p m 2 cell size given a 0.6-pm
of the blocking oxide. These transistors are formed using a
gate length [14]. We can project a 5.76 p m 2 cell size for the
LOCOS process starting with 2-3 52 cm 100 p-type
SONOS technology given a 0.6-pm design rule which is only
substrates. Fig. 3 illustrates the device cross section and TEM
slightly larger than the floating gate technology.
photomicrograph of the completed device structure. The key
The 1-Mbit SONOS EEPROM designed by Nozaki et al.
steps in the fabrication process involve the triple dielectric
requires both +5 V and -4 V, thus producing an effective 9-
since the electrical properties of the tunnel oxide, nitride, and
V programming voltage We propose a scheme to program
blocking oxide strongly depend on the processing conditions
a SONOS array with a single positive programming voltage
for each of these layers.
using either dual-gate n-channel SONOS transistors in a p-well
First, the tunnel oxide is formed either in situ within the low-
or dual-gate p-channel SONOS transistors in a n-well (Fig.
pressure chemical vapor deposition (LPCVD) silicon nitride
1). When integrating the CMOS and SONOS technologies, the
furnace for an ultra-thin 1.1-nm tunnel oxide or grown at
SONOS devices must have a separate bulk (memory well) than
700°C in a triple wall oxidation furnace to form a 1.8-nm
the CMOS peripheral circuitry. The memory well is employed
layer. The tunnel oxide thickness can be controlled to less than
to apply a positive programming voltage to the bulk to
0.05 nm, which is similar to results obtained by Kamagaki et
erase (write) the n-channel (p-channel) SONOS device while
al. [24]. Superior retention and endurance characteristics are
maintaining the peripheral CMOS substrate at ground. Thus
obtained by using a triple-wall oxidation furnace instead of the
a single power supply (Vp) can be used to accomplish both
conventional single-wall furnace [233. After tunnel oxidation,
the erase and write operations. The proposed programming
the silicon nitride (5 nm) is deposited at 725°C with a 1O:l
scheme is illustrated in Fig. 2.
NH3:SiClZHz ratio and a 300 mtorr pressure. Finally, we form
the blocking oxide by LPCVD (1O:l NzO:SiClZHz, 725°C
DEVICEFABRICATION 800 mtorr) followed by a 900°C steam anneal to densify the
In order to study the scaling of the SONOS device, we oxide. Minami and Kamigaki have demonstrated improved
have fabricated three different n-channel transistors (Table endurance by using this method, instead of the traditional
11). For each device, the processing conditions are the same steam oxidation at high temperatures (900°C to llOO°C),

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392 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY-PART A, VOL. 17, NO. 3, SEPTEMBER 1994

p-Si

Fig. 3. TEM photomicrograph and cross section of a wchannel SONOS transistor

which they attribute to the sharper potential banier of the In scaling the SONOS device, we must consider each of
CVD oxide 161. the following characteristics: programming voltage, speed,
retention, and endurance. The scaling process is complex
IV. SCALINGTHEORY since varying the thickness of each dielectric layer can in-
fluence both the programming speed and retention. In order
During writing (erasing) of an n-channel SONOS device, an
to investigate the scaling of the SONOS device, we have
electron (hole) tunnels through the tunnel oxide and is trapped
developed a closed-form solution for its transient behavior
in the nitride. The threshold voltage of a SONOS transistor
[3]. Previous models have required numerical simulations [4],
includes information about the amount of charge stored in the
or obtained long analytical solutions where it is difficult
nitride layer and is given by
to determine how the change in threshold voltage depends on
the device parameters [4], [9]. Several of these models also
have required that the nitride thickness be much greater than
the tunnel oxide thickness [9], [8]. As the SONOS device is
scaled, the nitride thickness is reduced such that it no longer
meets the criteria mentioned above. In our analysis, we extend
where +GS is the gate to semiconductor work function; is the Lundstrom and Svensson model [9] to the scaled SONOS
the bulk Fermi potential; N B is the bulk doping; XOT. X N , device. We approximate the tunneling current by a first-order
and XOB are the tunnel oxide, nitride, and blocking oxide binomial expansion to yield a simpler solution, locate the
thicknesses, respectively; cox, en, and are the dielectric nitride traps in the center of the nitride bulk, and allow the
constants for an oxide, nitride, and silicon, respectively; and tunnel oxide thickness to approach the nitride thickness. From
C,ff is the effective capacitance of the triple dielectric. our model we find the change in turn-on voltage (AV,,) as
The charge stored in the nitride layer, Q N , depends on a function of the programming time (t,) is given by
the programming voltage Vp and the programming time t,.
A transistor in a memory cell may be characterized more
accurately by measuring the turn-on voltage corresponding to
the gate-to source voltage (VGS) at a specified current (usually
10 PA) in the constant current regime. For a SONOS transistor
in the constant current regime, the drain to source current can
be approximated by
where
IDS -(vGS VTHl2 (2)
where

Lff(F)Gff. (3)
EOt(0)
VP (EZ)QN(O)
W is the width of the transistor, L is the length of the xeff

1
transistor, and p e p f is the field-dependent effective mobility.
Thus, we find the turn-on voltage can be given by

vGS(IDS 10PA) v T O ( v P ,t p ) 1 ETX.4

7=-
ABET
(zE)QN(O)]

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FRENCH et al.: DESIGN AND SCALING OF A SONOS MULTIDIELECTRIC DEVICE 393

-
0
3

C O

O
Programming Time, (seconds) Programming Time, (seconds)
Fig. 4. Simulated change in turn-on voltage versus the programming time Fig. 5. Erasdwrite simulation of a 1.8-nm tunnel oxide, 5-nm nitride,
given XOT 1.8 nm, XN 5 nm, XOB 4 nm, E,t(O) 7.46 MV/cm, and 4-nm blocking oxide device given E,t(O) 7.46 MV/cm. When the
and Vp 5 V. We observe that the erasdwrite speed is determined by the programming voltage is reduced from 9 V to 5 V, the turn-on time increases
turn-on time and the slope of the eradwrite curve from to and the erase/write slope decreases from Spl to Sp2. resulting
in an overall slower programming speed.

erase/write slope is increased, just opposite to the effect of

reducing the programming voltage. In conclusion, to maintain
the same erase/write speed when the programming voltage is
scaled, the effective thickness must be scaled in accordance
with the reduction of the programming voltage. Scaling the
effective thickness corresponds to decreasing either the tunnel
oxide, nitride, or blocking oxide thickness.
However, we may degrade the retention characteristics by
increasing the speed of the device. The dominant mechanism
for charge loss in a scaled SONOS device is back tunneling of
charge. Lundkvist et al. have performed a detailed analysis
x,ff is the effective triple dielectric thickness, Eot(0) is the of the discharge due to back tunneling of electrons [lo].
initial electric field, ET is a constant field, is the turn-on They have determined the discharge has a logarithmic time
time, A and B are model constants, is the silicon surface dependence after a certain time ( t d ) , before which the threshold
potential, $1 and $2 are the bamer heights of an oxide and voltage is virtually constant. The time before decay t d iS
nitride, respectively, mzx is the effective mass in the oxide, exponentially related to the tunnel oxide thickness. When the
and FL is the reduced Planck's constant. tunnel oxide thickness is scaled, t d will decrease and the
We observe the erase/write speed is determined by the overall retention time will be reduced.
turn-on time 7 (see (8)) and the slope of the erase/write curve
(see Fig, 4), where S, can be approximated by V. DEVICEMEASUREMENTS
Now we will discuss the scaling of the SONOS device
by examining the measurements of our devices fabricated at
Lehigh University and relate these measurements to the previ-
ous erase/write analysis. First, we will verify the accuracy of
From the expressions for the slope and turn-on time (see
our erase/write analysis. The write (erase) characteristic of the
(8) and (12)), we can easily observe the dependence of
SONOS device is measured by placing the device in the erase
the erase/write characteristics on the physical device and
(write) state and then applying a write (erase) pulse with a
operational parameters, including the dielectric thicknesses,
varying pulse width. Fig. 6 shows an erase/write measurement
initial stored nitride charge, and programming voltage.
for SONOSl given a 5-V programming voltage. The initial
The turn-on time is exponentially related to the inverse
turn-on voltage is -1.2 V for the write characteristic and 2.1
of the programming voltage, and the slope is proportional
V for the erase characteristic. To compare these measurements
to the square of the programming voltage. A reduction
to our analysis, we must extract the initial electric field from
in the programming voltage will increase the turn-on time
the measured initial turn-on voltages (-1.2 V and 2.1 V). By
and decrease the erase/write slope, resulting in an overall
combining (l), and we find the following relationship
slower programming speed (Fig. 5).
between the initial turn-on voltage and electric field
Thus, we must find a method to maintain the erase/write
speed when the programming voltage is reduced. Recalling
(8) and (12), we find the turn-on time is exponentially related
to the effective thickness, and the erase/write slope is inversely
proportional to the effective thickness. If the effective thick-
ness is reduced, then the turn-on time is decreased and the

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394 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY-PART A, VOL. 17, NO. 3, SEPTEMBER 1994

$2

-6
I nm tunnel
,I
- 2 2
-2
loo lo2 1 1o -~ 10 10 O
Programming Time, (seconds) Programming Time, (seconds)
Fig. 6. Eradwrite measurement of SONOSl at a 5-V programming voltage. Fig. Eradwrite measurement of two different scaled SONOS transistors
The initial threshold voltage is -1.2 V for the write characteristic and 2.1 V with an 1.8-nm tunnel oxide [9], and a 2-nm tunnel oxide [5] comparing
for the erase characteristic, corresponding to an initial electric field of 7.46 the speed of the devices at f 9 V. By comparing these devices, we see the
MV/cm and -6.4 MV/mc, respectively [9]. importance of controlling the tunnel oxide thickness and the trap density in
the silicon nitride films. The 1.8-nm tunnel oxide device has a faster speed
than the 2-nm tunnel oxide device.

3
f
p
s

cn
c

9K
0 -1
10
Programming Time, (seconds)
Fig. 7. Comparison of the erasdwrite measurement with our analytical model 1 1 1
given the initial electric field is 7.46 MV/cm for the write curve and -6.4
MV/cm for the erase curve (SONOS 1 , L'p 5 V). Our analytical model agrees
with the measured data except for large programming times, when additional Fig. 9. Retention measurement of SONOSl (1.8-nm tunnel oxide, 5-nm
low-field tunneling mechanisms become important [9]. nitride, and 4-nm blocking oxide) demonstratingten-year retention for a 0.1-V
detection window, f 9-V programming voltage, write time, and I-ms
erase time [16].
Given W 140pm, L 100pm, IDS 100 pA, and
pejf 400 cm2 V-ls-l we calculate the initial electric a 50-ps write and a 1-ms erase time to obtain the same 2.5-
field across the tunnel oxide to be 7.15 MVkm for the write V memory window as Nozaki et al. Furthermore, the 1.8-nm
characteristic and -6.56 MVkm for the erase characteristic. tunnel oxide transistor can achieve ten-year retention given
Comparing the measurements from SONOS 1 with our closed- a 0.1-V detection window, f 9 V programming voltage,
form analytical model, we find close agreement except for 100 write, and 1-ms erase time (see Fig. 9). Excellent
large pulse widths when the electric field in the tunnel oxide endurance characteristics (greater than lo6 cycles) for scaled
is less than 6.25 MV/cm (see Fig. 7). This deviation is due SONOS devices have already been demonstrated by previous
to the addition of another tunneling mechanism, trap-assisted investigators [18], [22]. Thus, this scaled device can be used
tunneling, which occurs only at low fields [2], [3], and is in a semiconductor disk, NVRAM, and neural network.
neglected in our closed-form solution. Still, a desire exists to scale the programming voltage
To guarantee reliability, the nonvolatile memory device below 9 V. We have studied two different cases, 1) scaling
must be scaled along with the CMOS peripheral circuitry. the tunnel oxide thickness and 2) scaling the blocking oxide
Nozaki et al. have reported a f 9 V programmable SONOS thickness in order to investigate the limits of scaling SONOS
memory transistor with a 100-ps write time and a 10-ms microstructures. First, we have decreased the tunnel oxide
erase time [18]. Typically, Flash floating gate EEPROM's thickness from 1.8 nm (SONOS1) to 1.1 nm (SONOS2). Fig.
program in lops or less [14], [l]. We have scaled the SONOS 10 illustrates a comparison between the measured erase/write
microstructure from a 2-nm to a 1.8-nm tunnel oxide, and characteristics of SONOSl and SONOS2. From our analysis,
Fig. 8 illustrates the comparison of our device measurements a reduction in the tunnel oxide thickness is manifested in a
with the measurement results published by Nozaki et al. [3], decrease in the tum-on time (see (8)). Examining Fig. 10, we
[13]. Both device structures have a 5-nm silicon nitride storage observe a reduced tum-on time from 71 50 for SONOSl
layer and a 4-nm blocking oxide. We can see the importance to 7 2 10 for SONOS2.
of controlling the tunnel oxide thickness and the trap density Previous MNOSBONOS scaling scenarios keep the
in the silicon nitride film since our devices can operate with electric field across the tunnel oxide or nitride nearly constant

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FRENCH et al.: DESIGN AND SCALING OF A SONOS MULTIDIELECTRIC DEVICE 395

0.4 detection
window

f5

anmtunneloxide
nmtunneloxide

-4 2 loo lo2 lo4 lo6

Fig. 12. Retention measurement of SONOSI with 1.8-nm tunnel oxide,

Fig. IO. Erase/write measurement of SONOSI with 1.8-nm tunnel oxide, 5-nm nitride, and 4-nm blocking oxide, and 2) SONOS2 with 1.1-nm tunnel
5-nm nitride, and 4-nm blocking oxide, and 2) SONOS2 with 1.1-nm tunnel oxide, 5-nm nitride, and 4-nm blocking oxide given a 5-V programming
oxide, 5-nm nitride, and 4-nm blocking oxide at f 5 V. The turn-on time is voltage and a 10-s erase and write time. The loss of charge begins earlier
decreased from 71 50 for SONOSI and 72 10 for SONOS2 when the tunnel oxide thickness is reduced

.I nm tunnel oxide 1.8 nm tunnel oxide The retention characteristics of SONOSl and SONOS2 are
programming programming
1 shown in Fig. 12 given a 5-V programming voltage and a 10-s
d
' erase and write time. The major difference between the two
devices is the onset of memory loss at 100 p s for the erase state
of the 1.1-nm tunnel oxide (SONOS2) in contrast with the 10-
ms comer for the 1.8-nm tunnel oxide (SONOSl), resulting
in a difference of two orders of magnitude due to the 0.7-nm
reduction in the tunnel oxide thickness. This difference is due
to an increase in back tunneling for the 1.1-nm tunnel oxide
over the 1.8-nm tunnel oxide. Thus, there is a tradeoff between
-2 the erase/write speed and memory retention in conventional,
scaled SONOS device structures. The reduction in memory
retention is manifested by a decrease in memory "sense"
Fig. Erase/write measurement of the 1.1-nm tunnel oxide device and window for long retention times. Given a 0.4-V detection
the 1.8-nm tunnel oxide device with a constant tunnel oxide electric field. By window, SONOSl retains the memory window for four days
scaling the tunnel oxide thickness 7 nm, we can decrease the programming
voltage from V to 8 V and reduce the erase time from 10 ms to 1 ms while while SONOS2 keeps the window for one hour. The 1.1-nm
maintaining a constant write speed. ultrathin tunnel oxide device (SONOS2) may no longer meet
the stringent retention requirements for the semiconductor
disk application but may be utilized in NVRAM's or neural
while the triple dielectric dimensions are scaled [ l l ] , [171.
networks. Other scaling approaches should be explored for
Therefore, we can compare devices with different tunnel oxide
applications which require extended retention times.
thicknesses using constant tunnel oxide electric field criteria.
Clearly there is room for further improvement in retention.
We have already examined the erase/write characteristics
Various methods of improving the retention characteristics
for a 9-V programming voltage on the 1.8-nm tunnel oxide
in MNOS/SONOS structures have been studied by previous
device in comparison to the SONOS transistors from Nozaki
researchers. Hu and White have used a buried channel structure
et al. (see Fig. 8). Assuming zero stored nitride charge, the
instead of a surface channel structure to eliminate the charge
initial electric field across the tunnel oxide is given by
back tunneling [23]. Severals investigators have examined the
VP possibility of tailoring the nitride traps by using a graded
E,,(O) nitride [15] or an oxynitride [21]. Finally, Maes et al. have
Xeff
incorporated a hydrogen anneal to reduce the interface trap
For the 1.8-nm tunnel oxide device (SONOSl) at a 9-V pro- density and improve the retention [5], [7]. We are in the
gramming voltage, the initial tunnel oxide field is 10.2 MV/cm. process of incorporating several of these methods on our
Thus, the programming voltage for the 1.1-nm tunnel oxide scaled SONOS structures to obtain fast erase/write times, low
device (SONOS2) should be 8 V to maintain a constant electric programming voltages, and improved retention and endurance
field across the tunnel oxide. When comparing the eraselwrite characteristics.
measurements for the two different tunnel oxide thicknesses Another alternative to scaling is to decrease the blocking
with the same tunnel oxide electric field, the speed of SONOS2 oxide thickness. The tum-on time is reduced from 71 10
is slightly faster than SONOSl (see Fig. 11) for a given to 7 2 1 p s by decreasing the blocking oxide thickness from 4
memory window. Thus, we can decrease the programming nm for SONOS2 to 3.3 nm for SONOS3 (see Fig. 13) since the
voltage from 9 V to 8 V and maintain the programming speed initial turn-on time, is smaller for a thinner blocking oxide
by scaling the tunnel oxide thickness 0.7 nm. thickness (see (8)). However, a smaller memory window is

r---

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396 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY-PART A, VOL. 17, NO. 3, SEPTEMBER 1994

demonstrated an 8-V electrically programmable nonvolatile

t5 programming voltage memory device with an extension towards 5-V programming.
e
c
which can be an ideal candidate for the next generation of
EEPROM’s for various applications such as semiconductor
w - disk, NVRAM, and neural networks.
m0,
c
0 REFERENCES
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initial stored charge is multiplied by a term involving the Semiconductor Memory (NVSM) Workshop, Monterey, CA, Aug. 1992.
N. Ajika, M. Ohi, H. Arima, T. Matsukawa, N. Tsubouchi, “A 5 volt only
blocking oxide thickness. Overall, scaling the blocking oxide 16M bit FLASH EEPROM cell with a simple stacked gate structure,”
does not improve the erase/write speed of the device. in IEDM Tech. Dig., 1990, pp. 115-118.
A. Roy, “Characterization and modeling of charge trapping and retention
in novel multi-dielectric nonvolatile semiconductor memory devices,”
Ph.D. dissertation, Lehigh Univ., Bethlehem, PA, 1989.
VI. CONCLUSIONS S.-I. Minami and Y. Kamigaki, “A novel MONOS nonvolatile memory
device ensuring IO-year retention after lo7 erasdwrite cycles,” IEEE
For the next generation of EEPROM’s, we must scale the Trans. Electron Devices, vol. 40,pp. 201 1-2017, Nov. 1993.
programming voltage while maintaining performance merits “New scaling guidelines for MNOS nonvolatile memory de-
such as programming speed, retention, and endurance for vices,” IEEE Trans. Electron Devices, vol. 38, pp. 2519-2526, Nov.
1991.
different applications. We have achieved low-voltage pro- T. Nozaki et al., “A 1-Mb EEPROM with MONOS memory cell for
grammability of the SONOS device to meet the low-voltage, semiconductor disk application,” IEEE J. Solid-state Circuits, vol. 26,
low-power requirements. We have also detailed the formation pp. 497-501, Apr. 1991.
T. Takeshima et al., “A 3.3 V single-power-supply 64Mb flash memory
of the multidielectric for both the scaled and the ultrathin with dynamic bit-line latch (DBL) programming scheme,” in ISSCC
tunnel oxide SONOS devices. Dig. Tech. Papers, 1994, pp. 148-149.
We have developed an analytical model for the transient U. Sharma, M. Woo, H. Kirsch, J. Hayden, and J. R. Yeargain, “A novel
technology for megabit density, low power, high speed NVRAMs,” in
characteristics that serves as a scaling guideline for the Proc. VLSI Technology Symp., Kyoto, Japan, May 1993.
SONOS nonvolatile memory transistor. The thicknesses of V. J. Kapoor, R. S. Bailey, and R. A. Tun, “Chemical composition,
charge trapping, and memory properties of oxynitride films for MNOS
the tunnel oxide, the nitride, and the blocking oxide have devices,” J. Electrochem. Soc., vol. 137, Nov. 1990.
significant impacts on the programming voltage, speed, and Y. Hu, A. Banerjee, and M. H. White, “Characterization of Si/Si02
retention. In the quest of increasing programming speed, the interface states in ultra-thin oxides,” in Proc. 23rd IEEE Semiconductor
Interjiace Specialist San Diego, CA, Dec. 1992.
retention characteristic may be degraded. Therefore, a delicate Y. Hu and M. H. White, “Charge retention in scaled SONOS nonvolatile
balance must be maintained between speed, retention, and semiconductor memory devices-modeling and characterization,” Solid-
endurance. Various methods of improving retention have been State Electron., vol. 36, pp. 1401-1415, Oct. 1993.
Y. Kamigaki, S.-I. Minami, K. Furusawa, K. Uchida, and T. Hagi-
discussed, including hydrogen anneal and buried channel wara, “Highly reliable 256-Kb MNOS EEPROM,” in Proc. loth IEEE
devices which reduce electron back tunneling. We have Nonvolatile Memory Semiconductor Workshop, Vail, CO, 1989.

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FRENCH al.: DESIGN AND SCALING OF A SONOS MULTIDIELECTRIC DEVICE 391

Margaret L. French (S’87-M’93) was bom in Marvin H. White (A’62-SM’71-F’74) received

Bethesda, MD, in 1965. She received the B.S., M.S., the A.S. degree in engineering from the Henry
and Ph.D. degrees in electrical engineering from Ford Community College, Dearbom, MI, in 1957,
Lehigh University, Bethlehem, PA, in 1987, 1990, the B.S.E. degree in physics and mathematics, and
and 1993, respectively. the M.S. degree in physics from the University of
From 1993 to July 1994, she was a Visiting Re- Michigan, Ann Arbor, in 1960 and 1961, respec-
search Scientist at Lehigh University. Currently, she tively, and the Ph.D. degree in electncal engineering
is an Assistant Professor in the Computer Science from The Ohio State University, Columbus, in 1969.
Department, Elizabethtown College, Elizabethtown, In 1978, he was a Fulbright Visiting Professor
PA. Her research interests include semiconductor in Microelectronics at the UniversitB Catholique de
device physics, with a special interest in the the Louvain, Louvain-la-Neuve, Belgium; from 1976 to
carrier transport and trapping of SONOS multidielectrics and the scaling and 1980 he served as a Professor (part-time) at the University of Maryland,
applications of nonvolatile memory devices. College Park. From 1961 to 1981 he was affiliated with Westinghouse
Dr. French is a member of Tau Beta Pi, Eta Kappa Nu, and an associate Electric Corporation, Advanced Technology Laboratories, Baltimore, MD, as
member of Sigma Xi. an Advisory Engineer in the area of low-power, custom integrated sensors,
devices, and circuits for advanced solid-state systems. He performed research
and development on silicon-diode camera tubes, electrooptical photodiode
imaging arrays, MOS and CMOS transistors, MNOS memory transistors,
bipolar and microwave transistors, and CCD’s for imaging, memory, and
Chun-Yu Chen (S’88) was born in Taipei, Taiwan. advanced discrete analog signal processing. In 1981, he joined the faculty at
in 1967. He received B.S. and M.S. degrees in Lehigh University, Bethlehem, PA, as a Sherman Fairchild Professor in Solid-
1988 and 1990, resFctivelY, and is currently a State Studies-Electrical and Computer Engineering. His research areas are
Ph.D. Candidate In the Department of Electrical En- focused on the influence of defects on the performance of solid-state devices
gineenng and Computer Science, Lehigh University and circuits, solid-state sensors and devices, and custom microelectronic
Bethlehem, PA. circuits. In particular, he has been involved with graduate education and
His research interests include novel solid-state research in nonvolatile semiconductor (SONOS) memory transistors and the
device Physics, nonvolatik memory devices, analog study of interface and bulk trapping phenomena in dielectrics.
CMOS integrated circuit design and fabrication, and Dr. White served as the Electron Devices Distinguished Guest Lecturer in
adaptive signal processing. 1982. During 1973 to 1976 he was the Electron Device National Newsletter
Mr. Chen is a member of Tau Beta pi, Eta Kappa Editor and is presently the Membership Chairperson for the Electron Devices
Nu, and an associate member of Sigma Xi. Society.

Harikaran Sathianathan (S’89) was bom in the

Maldive Islands in 1969. He received the B.S.
and M.S. degrees in electrical engineering from
Lehigh University, Bethlehem, PA, in 1991 and
1993, respectively.
Currently, he is a Research Assistant at Lehigh
University. His research interests include optimizing
nonvolatile memory device technology for high-
density EEPROM’s and the scaling of submicron
CMOS devices.
Mr. Sathianathan is a member of Tau Beta Pi.

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