IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY—PART A, VOL. 20, NO.

3, SEPTEMBER 1997 317

Coffin–Manson Fatigue Model

of Underfilled Flip-Chips
Vadim Gektin, Member, IEEE, Avram Bar-Cohen, Fellow, IEEE, and Jeremy Ames

Abstract— The fatigue life of an underfilled flip-chip package stress along the surfaces between the underfill and substrate
has been evaluated using the Coffin–Manson relation and finite as well as the underfill and chip.
element modeling (FEM)-computed solder shear strain for typ-
ical flip-chip structures. In the course of this effort, numerical
simulations were performed for underfill materials of varying II. ANALYTICAL BACKGROUND
thermo-structural properties, two chip sizes, and two solder
bump heights. The results were used to examine the parametric A. Coffin–Manson Relation
sensitivity of the thermal strain in the solder joints and the axial,
as well as shear, stress in the underfill material. The predicted The fatigue life of conventional solder joints has long
improvement in the number of cycles-to-failure of the underfilled been related to the induced cyclic shear strain via the Cof-
flip-chip was found to agree with empirical observation. However, fin–Manson relation (see, for example, [6]–[9])
the maximum improvement achievable by underfilling was found
to be limited by the adhesion strength of the underfill material. (1)
Index Terms— Coffin–Manson, fatigue, flip-chip, solder, ther-
mal strain, underfill. where is the number of cycles to failure, is a material
constant, is the cyclic plastic shear strain of a solder joint,
is the cyclic frequency, is the maximum temperature
I. INTRODUCTION
during the cycle, is the Boltzmann’s constant, is an

I N recent years, flip-chip technology has migrated to systems

using larger and much more powerful chips. Due to the
high input/output (I/O) density, low-cost assembly, and low
empirical constant, and may be thought of as an empirical
“activation energy.” The value of the constant , inversely
relating the cycles-to-failure to the shear strain, is reported in
“package” profile, flip-chip is the technology of choice in the literature to vary from 1.89 to 2.5 [10].
many current applications [1], [2]. However, the difference In light of the successful use of the Coffin–Manson equation
in the coefficients of thermal expansion (CTE) between the for predicting solder fatigue, it may be reasoned that the
chip and the ceramic substrate makes flip-chip configurations presence of an underfill material decreases the cyclic solder
vulnerable to thermally-induced strains and often results in strain—without affecting other terms—and, thereby, increases
solder joint fatigue. The use of “underfill” materials, which the number of cycles-to-failure of the attached flip-chip [5].
surround the solder bumps and fill the space between the To a first approximation it may thus be argued that the
chip and substrate, has typically resulted in a 5–10 times improvement in the fatigue life of solder joints, as expressed
improvement in package reliability, but solder fatigue remains in the ratio of cycles-to-failure with and without an underfill,
the major failure mechanism [3]. A recent study with gold can be simply related to the ratio of the solder shear strains,
bumps showed an even more dramatic effect, with a 200 times with and without the underfill, i.e.
improvement in the fatigue life of the underfilled joints [4].
Following previous work [5] that identified the theoretical (2)
basis for the improvement in the fatigue life of underfilled
solder joints, the present study uses finite element modeling where subscripts and correspond to underfill and air (no
(FEM) in conjunction with the Coffin–Manson relation, to underfill), respectively. However, restraining the movement of
more broadly examine the effect of underfill materials on the the chip relative to the substrate can produce a significant shear
thermally induced strain and life expectancy of flip-chips, for stress at the upper and lower surfaces of the underfill layer
a range of solder joint heights and chip sizes. Attention is giving rise to a new failure mode, underfill delamination and
devoted to both the shear strain in the solder and the shear rupture. Delamination of the underfill may not only reduce its
ability to restrain solder joint deformation but may also allow
moisture to accumulate at the interfaces, prompting additional
Manuscript received October 1, 1996; revised March 25, 1997. This work failure modes.
was supported in part by Northern Telecom.
V. Gektin is with Applied Materials, Santa Clara, CA 95050 USA.
A. Bar-Cohen is with the Deparment of Mechanical Engineering, University
B. Strain/Stress in Die-Attach
of Minnesota, Minneapolis, MN 55455 USA. To gain insight into the thermally induced axial and shear
J. Ames is with the Deparment of Mechanical Engineering, University of
California, Berkeley, CA 95437 USA. strain/stress behavior of a flip-chip underfill layer, it is conve-
Publisher Item Identifier S 1070-9886(97)04599-X. nient to consider a homogeneous underfill/solder layer and to
1070–9886/97$10.00  1997 IEEE

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318 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY—PART A, VOL. 20, NO. 3, SEPTEMBER 1997

where , accounting for the effect of the two adherends, is,

again, in the range 0 1. The first term on the right side
in (6) represents the axial compliance of the adhesive, while
the second and third terms represent the local axial compliance
of the adherends.
Following the pioneering work in this field and applying
a force and moment balance to the idealized tri-material
structure (Fig. 1), (3) and (5) can be solved simultaneously
for the shear and axial stresses in the die-attach layer [12],
[13]. The shear stress is found to follow a hyperbolic sine
dependence as

(7)

where is the CTE of the respective layer, is its

Fig. 1. Free body diagram of tri-material structure. temperature change and is given by

view the flip-chip configuration as a tri-material structure of (8)

cross-sectional length 2l, infinite depth, and overall thickness
, with a compliant middle layer of thickness This characteristic value, , is seen to depend on the interfacial
representing the homogeneous die-attach material (Fig. 1). shear stiffness as well as on the lateral compliance, , and
Using the idealized representation of an underfilled flip-chip, flexural rigidity, , of the two adherends. More specifically,
as shown in Fig. 1, the -directional, or axial, and shear
in (8), with defined as
stresses in the underfill/solder layer can be found as below.
Shear Stress: The shear stress in the die-attach is given by
(3)
is Young’s Modulus of the respective material, while
where and are the lateral displacements of the top with defined as
and bottom surfaces of the layer, and are assumed to equal the
displacement of adherends 1 and 2, respectively. Expanding
on a concept first proposed by Mirman [11], the interfacial
shear stiffness, or spring constant, of the adhesive layer, , Similarly, introducing parameters , the stress frequency
can be expressed as
(9)
(4)
and , the differential rigidity
where [equal to ] is its Shear Modulus,
—Young’s Modulus, —Poisson ratio, and accounts (10)
for the effect of the two adherends on the lateral stiffness of
the layer. The first term on the right side in (4) represents the the die-attach axial stress is found to follow the form [13], [14]
shear compliance of the die-attach, while the second and third
terms represent the local shear compliance of the adherends. (11)
The coefficient can be expected to range from values close where
to unity, representing a compliant die-attach (thick layer with
low Shear Modulus) to values close to zero, representing a
stiff die-attach (thin layer with high Shear Modulus).
Axial Stress: The axial stress in the die-attach layer is given
by
(5)
where is the axial stiffness or spring constant of the layer
[see (6)] and and are the vertical displacements of the
top and bottom surfaces of the die-attach, assumed again to
equal to the displacements of the respective adherends.
The axial stiffness, , is given by the following expression
[11]
with , the differential thermal expansion, presented as
(6)

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GEKTIN et al.: COFFIN–MANSON FATIGUE MODEL OF UNDERFILLED FLIP-CHIPS
Fig. 2. Analytical axial and shear stress plots.
Equations (7) and (11) are plotted in Fig. 2 for typical flip-
chip dimensions and properties for a post-underfill cool-down
of 125 C. Examining the form of this analytical solution, it
may be seen that the shear stress increases monotonically from
the center of the structure attaining its most severe value at
the edge, while the axial stress is tensile for approximately
three fourths of the distance to the edge and then reverses
sign, reaching a peak compressive value near the edge.
It should be noted that the sign of the axial stress,
dependent on the value of the differential rigidity, , as can
be seen from (10) and (11). In practice, this is an important
result, since the combination of the peel (positive axial) and
shear stress is more dangerous than combined compressive
and shear stress [15].
These analytical results (for an idealized tri-layer structure)
capture the essential thermo-structural behavior of the die-
attach layer. However, to more accurately capture the three-
dimensional thermally induced stress/strain in actual flip-chip
configurations, it is preferable to obtain similar relations for an
axisymmetric geometry. Based on the work of Mirman [16],
(7) and (11) can be extended to the desired axisymmetric
configuration by use of a modified Young’s Modulus and
coefficient of thermal expansion, as below
Due to the relatively small area fraction occupied by the
solder bumps ( 3%), the presence of the solder bumps can
be expected to weakly affect, and not fundamentally alter, the
thermo-structural behavior of the underfill material. However,
a far more complex model would be needed to calculate the
strain and stress in the solder joints. Yet, it is the solder
that is most vulnerable to failure. Consequently, an alternative
methodology must be sought for determining solder joint stress
and strain in an underfilled die-attach layer.
In the present study, a linear analysis FEM modeling
approach is used to determine the ratio of solder strain, with
and without an underfill material, and to thus determine the
improvement in fatigue life via (2). While in recent years
the nonlinear behavior of solder has been studied extensively
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319
TABLE I
FINITE-ELEMENT MODEL DESCRIPTION
Fig. 3. Axisymmetric structure used in FEM for 1A and 1B models. Di-
mensions in mm.
[17]–[19], nonlinear models are not yet available for the
polymeric underfill materials. In consideration of this situation,
as well as the fact that the temperature range studied is far from
the melting point of the solder, the present study is limited to
linear-elastic models. A subsequent paper will discuss a more
, is complete analytical approach to this problem.
III. FINITE-ELEMENT MODELING
To evaluate the effect of the underfill material on the fatigue
life of the solder joints, a number of finite-element models
was created for a 4.25 mm (170 mil) or 12.76 mm (510 mil)
square silicon die of 0.635 mm (25 mil) thickness converted
to 2.4 and 7.5 mm radius disks of the same thickness. The die
is attached to a ceramic substrate, approximately 5 mm (200
mil) or 15 mm (600 mil) square and 1.524 mm (60 mil) thick.
Two Pb/Sn solder bump heights were evaluated—0.127 mm
(5 mil) and 0.0635 mm (2.5 mil). The displacement boundary
condition used in the analysis is a point constraint at the center
of symmetry along the bottom surface, allowing substrate
flexing. To simplify reference to various chip sizes and solder
bump heights each specific configuration has been assigned an
alpha-numerical label, as shown in Table I.
Numerical analysis was performed using the structural finite
element program NIKEDP [20]. Calculations were performed
on a Sun Sparc 20 Workstation with a typical running time
of three minutes. The geometry of the plastic package was
transformed into an equivalent axisymmetric structure (Figs. 3
and 4), with the cross-sectional areas in the horizontal plane
remaining the same as in the original geometry. All the solder
bumps were combined to form a simple continuous ring (1A
and 1B models) or three continuous rings (2A and 2B models)
of solder, with a 0.127 by 0.2 mm or 0.0635 by 0.2 mm cross-
section, whose volume equals the volume of the solder joints.
The height of the ring is the same as that of a bump.
Meshing of the structure was done in such a way that
there were at least four elements in any modeled part of
the structure in any direction, generating a total of 3243
elements (Fig. 5). The mesh was significantly densified near
320 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY—PART A, VOL. 20, NO. 3, SEPTEMBER 1997

Fig. 6. Deformed flip-clip structure at steady state for 2A and 2B models.

TABLE III
MAXIMUM STRESSES AND STRAINS IN SOLDER WITH NO UNDERFILL PRESENT

Fig. 4. Axisymmetric structure used in FEM for 2A and 2B models. Di-

mensions in mm.

Fig. 5. FEM discretization of flip-chip structure for 2A and 2B models. lies between 10–16 GPa and coefficient of thermal expansion
(CTE) lies between 18–38 ppm/K, spanning the CTE value of
TABLE II the solder material. The numerical analysis was performed in
MATERIAL PROPERTIES USED IN FEM this range, with values of the strain and stress evaluated for
specific pairs of and within this range and then used to
create contours plots by the SURFER public-domain software
package.

IV. FINITE-ELEMENT MODELING RESULTS AND DISCUSSION

the solder ring (Fig. 5) to improve the accuracy of the results. A. Qualitative Results
It should be noted at the outset that the use of linear-
elastic models and an axisymmetric geometric representation The larger, deformed flip-chip structure, at steady state after
places some limitations on the precision of the computed a cool-down of 125 C with 13 GPa and 28 ppm/K,
strains and stresses. This approach can, however, be expected is shown in Fig. 6 with a 100 times magnification of the
to yield the correct trends and relative magnitudes of the deformations in the structure. The deformed structure, in this
thermally-induced deformation and stress, and, in particular, case, as well as for the smaller chip, is convex—reflecting
the relative benefits associated with the use of underfill flip- the higher CTE and hence larger contraction of the substrate
chip configurations. Previous results [21] have shown that relative to the die.
the use of an axisymmetric model minimizes the use of
computer resources without compromising the essential three- B. Quantitative Results
dimensional character of the results. As a baseline for later comparison it is useful to consider
To avoid possible singularities near the edge of the structure first the unconstrained case where no underfill was applied in
and, hence, unreliable FEM results near the edge, the reported the die-bond. For the 125 C temperature excursion and no
values of the axial and shear stress were taken one element underfill, the stress and strain encountered by the solder joints
away from the edge. Due to the lack of a detailed viscoelastic can be expected to be at their highest values. In Table III,
model for the underfill materials, a linear elastic model was the shear strain is seen to vary from 0.7 to 2.3%, rising with
used for all the flip-chip materials. The material properties used diameter and decreasing with height, and the axial strain to
in this analysis are shown in Table II and were taken from equal approximately 0.6%, for the geometries shown.
[3], [18], and [22]. Computed stresses for a double-density Similarly, it may be expected that the upper limit for the
mesh showed smoother transitions between the elements, but stresses in the underfill will be encountered when no solder
the same average result as obtained with the current element joints are present. The computed and analytically-determined
count. near-edge (maximum) shear stresses in the underfill for the
Following the underfilling procedure, the flip-chip can expe- models under consideration are presented in Table IV.
rience a 125 C cool-down to 25 C average room temperature It may be seen that there is only a modest change in the
and develop considerable residual stress. For purposes of shear stress between the small and large chip, with the same
determining the ratio of solder shear strain with and without layer thickness, but a more substantial decrease (approximately
underfill material, 125 C step was assumed to be the driving 30%) in the maximum shear stress from a thin to a thick layer.
force for fatigue. It may also be observed that the analytical value obtained
To cover a practical range of materials, it is assumed for via (7) is consistently higher, but only by 1–4 MPa, than the
this analysis that Young’s Modulus of the underfill material computed shear stresses in the underfill layer.

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GEKTIN et al.: COFFIN–MANSON FATIGUE MODEL OF UNDERFILLED FLIP-CHIPS 321

TABLE IV
MAXIMUM SHEAR STRESSES IN UNDERFILL WITH NO
SOLDER PRESENT ( 28 PPM/K, E 10 GPA) = =

Fig. 8. Contours of maximum shear strain in solder for various underfill

materials, m/m. Chip radius 2.4 mm, solder joint height 63.5 m.  in ppm/K.

Fig. 7. Contours of maximum shear strain in solder for various underfill

materials, m/m. Chip radius 2.4 mm, solder joint height 127 m.  in ppm/K.

C. Solder Shear Strain

As discussed in the earlier section, “load-sharing” by the un-
derfill material is expected to decrease the thermally-induced
strains in the solder joints. This reduction will depend on
the properties of the underfill material and particularly the
coefficient of thermal expansion and Young’s Modulus.
Evaluation of the change in the maximum shear strain of the
solder bumps caused by the use of the underfill material for the
four cases under consideration is presented in Figs. 7–10. The
plotted results, with an average shear strain of 0.3%, reflect a
dramatic decrease (approximately three times) in shear strain Fig. 9. Contours of maximum shear strain in solder for various underfill
materials, m/m. Chip radius 7.5 mm, solder joint height 127 m.  in ppm/K.
relative to the unconstrained, or underfill-free, configuration
(see Table III) and show a further 30% reduction in the solder
shear strain, for all four geometries, with increasing Young’s to a close approximation, the total computed strain may be
Modulus and a somewhat weaker influence of decreasing CTE considered equal to the plastic strain, making it possible to
of the underfill. Interestingly, for the configurations studied, directly apply the Coffin–Manson equation to this situation.
solder shear strain is practically independent of CTE of the Using the Engelmaier version of the Coffin–Manson equa-
underfill for low Young’s Modulus (less than 11 GPa)—lines tion [24]
of equal strain are almost vertical—and becomes independent
of Young’s Modulus of the underfill above 15 GPa—lines of (12)
equal strain are almost horizontal—making solder shear strain
a function of CTE of the underfill only. where is the fatigue ductility coefficient, taken to equal
0.325 [25], and, taking an average value of 2.3 [10], it is
D. Solder Fatigue possible to determine the fatigue life of the solder joints using
Examining the plotted and tabulated results, it may be (12) for the baseline case—with no underfill applied. Using the
observed that the total shear strain of the solder joints, caused FEM computed values with a 125 C temperature excursion
by a change in temperature of 125 C, leads to a minimum results in the cycles-to-failure prediction tabulated in Table V.
shear strain of 0.2%, which is over 10 times greater than the As anticipated, the predicted number of cycles-to-failure is
elastic limit strain of 0.02% at room temperature [23]. Hence, the largest for the flip-chip with a small chip diameter and a

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322 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY—PART A, VOL. 20, NO. 3, SEPTEMBER 1997

Fig. 10. Contours of maximum shear strain in solder for various underfill Fig. 11. Contours of increase in flip-chip fatigue life for various underfill
materials, m/m. Chip radius 7.5 mm, solder joint height 63.5 m.  in ppm/K. materials. Chip radius 2.4 mm, solder joint height 127 m.  in ppm/K.

TABLE V
FATIGUE LIFE PREDICTION FOR NO UNDERFILL CASES

large solder bump height (Model 1B), attaining a theoretical

endurance limit in excess of 5,000 cycles. Model 1A—a small
chip diameter with a small height appears capable of nearly
2,000 cycles-to-failure. The flip-chip configuration with a large
chip diameter showed smaller numbers of cycles-to-failure for
both small and large height.
Comparing the values for 1A and 2B it may be noted that
for the larger chips now coming to use, reliance on taller
solder bumps is at best only of marginal value in reversing
the decrease in cycles-to-failure relative to small chip. The Fig. 12. Contours of increase in flip-chip fatigue life for various underfill
materials. Chip radius 2.4 mm, solder joint height 63.5 m.  in ppm/K.
six to one ratio of the number of cycles-to-failure between the
small and large chip even with tall bumps, clearly points to the
need for an alternative solution, namely the use of underfill.
It is now possible to evaluate an increase in the number times for the large chip and short bumps. Approximately half
of cycles-to-failure caused by the application of an underfill these improvement ratios may be achieved for underfill with
material. Using (2) with 2.3 [10] and the shear solder CTE 38 ppm/K and 10 GPa.
strains, calculated from the FEM results, it is possible to deter- It is to be noted that based on these results, it would appear
mine the theoretical improvement in flip-chip fatigue life with that underfill makes it possible to operate large flip-chips
various underfill materials for the cases under investigation. reliably with short solder connections.
Figs. 11–14 display the theoretical improvement in the
fatigue life of the underfilled flip-chip for the appropriate E. Underfill Axial and Shear Stress
range of material properties. It may be observed that a very While the use of the underfill material thus appears to have
significant improvement in fatigue life can be achieved in the a most beneficial effect on solder strain and stress, successful
relevant range. The use of an underfill material with CTE of 18 implementation of this approach will require that the axial and
ppm/K and Young’s Modulus of 16 GPa yields approximately shear stresses in the underfill not compromise the integrity of
nine times the expected cycles-to-failure for the small flip-chip this material and/or lead to delamination.
and tall bump, 16.5 times for the small chip and short bump, The axial stress distribution along the underfill/silicon in-
84 times for the large chip and tall bumps, and almost 160 terface for the 7.5 mm chip with one and three solder rings

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GEKTIN et al.: COFFIN–MANSON FATIGUE MODEL OF UNDERFILLED FLIP-CHIPS 323

=
Fig. 15. Axial stress in underfill material with E 10 GPa,  = 28 ppm/K.
Chip radius 7.5 mm, solder joint height 63.5 m.

Fig. 13. Contours of increase in flip-chip fatigue life for various underfill
materials. Chip radius 7.5 mm, solder joint height 127 m.  in ppm/K.

=
Fig. 16. Shear stress in underfill material with E 10 GPa,  = 28 ppm/K.
Chip radius 2.4 mm, solder joint height 63.5 m.

three-ring and one ring cases show that the two stress profiles
are nearly indistinguishable from each other and agree closely
in the peak positive as well as negative values of the computed
Fig. 14. Contours of increase in flip-chip fatigue life for various underfill axial stress.
materials. Chip radius 7.5 mm, solder joint height 63.5 m.  in ppm/K.
Variation of the shear stress along the silicon/underfill
interface for the 2.5 mm radius flip-chip and the low solder
height of 63.5 m is shown in Fig. 16. The overall distribution
63.5 m high, using an underfill material of 10 GPa and
of the shear stress follows the classical pattern, as given by
28 ppm/K, are plotted as a function of distance from
(7), except in the vicinity of the simulated solder bump. As
the centerline in Fig. 15. The axial stress variation is seen previously noted for the axial stress, there is little difference
to follow the form of (11), reaching a rather large negative between the shear stress values for a no-ring and one solder
value of over 30 MPa and a fairly modest positive value of ring configuration.
less than 10 MPa. Generally similar results were obtained Contours of computed maximum shear stress, as a function
for the smaller flip-chip. Since it is the tensile axial stress of CTE and Young’s Modulus are shown in Figs. 17–20 and
that is most often thought to cause delamination or rupture, seen to range from 18–38 MPa for the configurations of
the large compressive value may not pose a severe danger interest. Analysis of the maximum shear stress in the underfill
to the integrity of the underfill. Alternately, the relatively material shows that in order to achieve the lowest shear stress
high underfill stresses adjacent to the outermost solder ring in the underfill, within the range of the material properties
may deserve closer scrutiny. Also shown in Fig. 15 is the given, it is necessary to select the lowest possible value
axial stress distribution for a model in which only one solder and the lowest possible CTE’s, except when dealing with small
ring—the outermost—is present. Comparison between the chips and higher solder bumps.

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324 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY—PART A, VOL. 20, NO. 3, SEPTEMBER 1997

Fig. 17. Contours of the maximum shear stress in underfill material, MPa. Fig. 19. Contours of the maximum shear stress in underfill material, MPa.
Chip radius 2.4 mm, solder joint height 127 m.  in ppm/K. Chip radius 7.5 mm, solder joint height 127 m.  in ppm/K.

Fig. 20. Contours of the maximum shear stress in underfill material, MPa.
Chip radius 7.5 mm, solder joint height 63.5 m.  in ppm/K.
Fig. 18. Contours of the maximum shear stress in underfill material, MPa.
Chip radius 2.4 mm, solder joint height 63.5 m.  in ppm/K.

While no fatigue model for polymeric adhesive is yet around CTE of 32 ppm/K for the range of Young’s Moduli
available, it is expected that a peak shear stress value below evaluated, with compressive values resulting from higher
the reported adhesion strength will minimize the probability of CTE’s and tensile stresses from lower CTE’s.
adhesive and cohesive failure of the underfill material. Results Due to its low resistance to deformation, the solder joint
in the literature suggest that the adhesion strength of typical could tolerate only a modest axial stress of typically up to 40
polymeric adhesives is on the order of 10–15 MPa [21], [26], gm/bump or approximately 0.5 MPa [28]. Alternately, large
and [27]. If underfill adhesion strengths are assumed to fall in negative values of the axial stress are also not desirable and
this range, it may prove difficult to maintain the integrity of may lead to solder creep or rupture. Consequently, CTE of
the underfill layer for high Young’s Modulus materials. the underfill material should be in range close to CTE of the
solder material.
F. Normal Stress in Solder
As may be seen in Fig. 21, in the underfilled die-attach V. CONCLUSION
layers, the axial stress is nearly independent of Young’s 1) Finite-Element thermo-structural simulation has re-
Modulus and depends only on the CTE of the underfill vealed the ability of underfill materials to significantly
material. Negligible stress values can be anticipated to occur reduce flip-chip solder joint shear strain.

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GEKTIN et al.: COFFIN–MANSON FATIGUE MODEL OF UNDERFILLED FLIP-CHIPS 325

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[17] S. Ling and A. Dasgupta, “A nonlinear multi-domain stress analysis
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[18] B. Z. Hong and L. G. Burrell, “Nonlinear finite element simulation of
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[1] G. O’Malley, J. Giesler, and S. Machuga, “The importance of material
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Comp., Technol. Conf., 1993, pp. 175–181. Vadim Gektin (M’96) received the M.S. and Ph.D.
[4] J. Kloeser, E. Zakel, F. Bechtold, and H. Reichl, “Reliability inves- degrees, both in mechanical engineering, from the
tigations of fluxless flip-chip interconnections on green tape ceramic University of Minnesota, Minneapolis, in 1993 and
substrates,” IEEE Trans. Comp., Packag., Manufact. Technol., vol. 19, 1997, respectively.
pp. 24–32, 1996. His research interests include thermal, thermo-
[5] V. Gektin, A. Bar-Cohen, and S. Witzman, “Thermo-structural behavior
structural, and fatigue behavior of microelectronics.
of underfilled flip-chips,” in Proc. 46th Electron. Comp., Technol. Conf.,
Dr. Gektin is a member of ASME International
1996, pp. 440–447.
and IMAPS.
[6] E. A. Johnson, W. T. Chen, and C. K. Lim, Principles of Electronic
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McGraw-Hill, 1989, ch. 6, pp. 159–195.

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326 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY—PART A, VOL. 20, NO. 3, SEPTEMBER 1997

Avram Bar-Cohen (M’85–SM’87–F’93) received the Ph.D. degree in me- Jeremy Ames received the B.S. degree from the
chanical engineering from the Massachusetts Institute of Technology, Cam- University of Minnesota, Minneapolis and is cur-
bridge, MA, in 1971. rently pursuing the M.S. degree at the University of
He is currently Professor and Director of the Thermodynamics and Heat California, Berkeley.
Transfer Division in the Mechanical Engineering Department and Associate His research interests include thermal design,
Director of the Center for the Development of Technological Leadership at the numerical modeling, and fluid mechanics.
University of Minnesota. His interests include thermal design, ebullient heat
transfer, and thermal phenomena in electronic systems, as well as engineering
education, technology forecasting, and management of technology. He served
as Executive Consultant for packaging and physical modeling at Control
Data Corporation, from 1984 to 1989, and held a succession of academic
appointments, from Lecturer to Professor, in the Department of Mechanical
Engineering at the Ben Gurion University of the Negev, Israel, from 1973
to 1988. He is co-author of Design and Analysis of Heat Sinks (1995) and
Thermal Analysis and Control of Electronic Equipment (1983). He also co-
edits the ASME Press Series Advances in Thermal Modeling of Electronic
Components and Systems, and the John Wiley series in Thermal Management
of Microelectronics and Electronic Systems. He has authored some 140
refereed Journal and Conference papers and 24 chapters in books.
Dr. Bar-Cohen was awarded the 1994 ASME Edwin F. Church Medal in
recognition of contributions to engineering education, continuing education,
and professional development on both national and international levels. He
was the General Chairman for the 1995 International Society Packaging
Conference, InterPack’95, and in 1988 was the Founding Chairman of the
ASM/IEEE Intersociety Conference on Thermal Phenomena in Electronic
Systems. For the past several years he has been an ASME Distinguished
Lecturer. He serves as the Editor-in-Chief of these TRANSACTIONS. He is a
Fellow of the ASME.

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