Security C –

TSMC Secret

Synopsys
Virtual Platforms

TSMC Reference Flow 11.0

TSMC Reference Flow 11.0

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What is It?
Abstraction technique to reduce hardware detail:
1. Higher level data types: C++ data types vs. pins
2. Reduced synchronization points: function calls vs.
indiv. clock phases
Abstraction-Levels
(LT) Loosely Timed – Instruction-Accurate Fct. call: Read(Address,Data)
• Coarse-graining timing functional
• No clock in un-timed system;
simulation kernel will execute one
potential ordering of concurrent processes
Multi-phase Fct. Call: Read(Address,Data)
(AT) Approximately Timed – Cycle
- Approximate / Cycle-Count Accurate
• TLM buses with timing
• Incorporates timing as functional labels Address Data
rather than executing waveform

(CA) Cycle Accurate

• Accurate at cycle boundaries
• (Clock-driven simulation)

TSMC Reference Flow 11.0

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Early (pre-RTL) SW Development SW-Driven Power Analysis

& HW/SW integration and Optimization
Camera USB
Virtual Platform
System-on-Chip System System
I/O I/O
P(f,V,mode)

Mem
CPU(s) TLM Bus
P(f,V,mode) Ctrl
Mem

P(f,V,mode)
ISS P(f,V,mode)

I$ D$ Slave
Periph Power Power

TLM Bus
Clock
Mgmt Mgmt
Module
Distribution Slave
Periph
IC
P(f,V,mode)

Flash
Memory
SRAM
Complete Device Model

SW-Driven Architecture Analysis SW-Driven System Validation

and Optimization
AT Bus Camera USB
Page tracking
Models / re-ordering
System
I/O
System
I/O
Virtual Platforms VCS MX™
Mem
CPU(s) TLM Bus
Ctrl
Mem

Instruction
$I Simulator
Set $D Slave
Wait SystemC
TLM Bus

Periph
Cycle- Slave
States
Approx ISS Periph
SoC
Access SystemVerilog
Flash
PMIC
Memory Timing System/Device

TSMC Reference Flow 11.0

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Apps
View
Application Development
80+ MIPS (Host Extension)

Untimed
40-60 MIPS TLM (LT)
Pre-silicon Software
Development & Integration

System Validation
& Arch. Exploration
1-10 MIPS Timed
Architectural Exploration TLM (AT)
& Real-Time SW Development Cycle Accurate
SystemC Models
Co-Emulation
1-100 KIPS RTL co-simulation

Functionally Cycle Cycle

Accurate Approximate Accurate
TSMC Reference Flow 11.0
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TSMC Secret

EARLY, PRE-RTL
SOFTWARE DEVELOPMENT

TSMC Reference Flow 11.0

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TSMC Secret

Design Challenges
 Profits of semiconductor companies now determined by “total”
solution, both hardware & software
 Software development is becoming dominant development
effort at 65 nm - typical SoC design effort is 40% HW and 60%
SW
 Growing software complexity, brought along by functionality
convergence & multi-core architectures
 Low development productivity: today’s 15-year old
technologies using physical development systems does allow
to keep up with growing complexity & time-to-market pressure
 Shortening time-to-market window, not matching well with a
sequential “first-hardware-then-software” development flow
TSMC Reference Flow 11.0
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Virtual Platform - Technology Requirements

 High simulation performance, typically several 10’s of MIPS,
allowing to run large software stacks, and to use these
platforms in a rapid edit-compile-debug cycle
 Binary compatible with the actual hardware target, to avoid
software porting effort when moving from a virtual to a physical
target
 Completeness, allowing to model a complete (embedded)
“system”, including SOC and board-level models, system I/O,
and system/device user interface
 Early availability, typically 9-12 months before silicon,
allowing maximum concurrent development between hardware
and software
 Integrate w/ existing embedded software tools & flows in
use in the software teams

TSMC Reference Flow 11.0

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Virtual Platform – RF 11 Example

TSMC Secret

TRACE32 ARM debugger

Virtual Platform model of DotAster

IPMate-MB-S3C2410X-001/002 Board
Linux Booting
TSMC Reference Flow 11.0
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TSMC Secret

Virtual Platform - Benefits

Available before chips come back from the fab

Available Early
and before boards have been built and debugged

Full visibility and control of multi-core platform

Enhanced Debugging
with non intrusive access to all components

No physical boards - minimal user ramp up time

Easy to Deploy
and logistical efforts to distribute and maintain

TSMC Reference Flow 11.0

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ARCHITECTURE
ANALYSIS & OPTIMIZATION

TSMC Reference Flow 11.0

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SoC Architecture Challenges

 Programmability & software complexity: required to achieve
the flexibility, which is required to support the diversity of
product use cases and to increase the time in market.
 Heterogeneity: mandatory to meet low power requirements.
Using only homogeneous processors is too inefficient for
extensive signal-processing in multimedia and wireless
communication applications.
 IP reuse: mandatory to meet time-to-market requirements.
 Complex SOC infrastructure: required to provide the required
communication bandwidth for all the IP blocks. For this
purpose, the SOC interconnect and memory subsystem include
complex mechanisms like distributed memory, cascaded
arbitration, Quality of Service (QoS), and so on.

TSMC Reference Flow 11.0

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SOC Design Challenges

 SOC infrastructure specialization: whereas many IP blocks can be reused from
the shelf, the SOC infrastructure needs to be customized to serve the specific
communication requirements of all IP blocks. Even for derivative designs, where
only one or two IP blocks change, the SOC infrastructure needs to be adjusted
and the overall performance needs to be validated.
 Large design space: due to the complexity and configurability of the SOC
infrastructure IP (interconnect, memory), tailoring the SOC infrastructure to the
specific needs of the product requirements is a nontrivial task.
 Varying & dynamic workloads: The workload on the SOC infrastructure is
difficult to estimate due to the multitude of different product use cases.
 High price of failure: A weakly-dimensioned SOC infrastructure leads to
insufficient product performance, which in turn may cause a missed market
opportunity.
 High potential for optimization: Typically, the SOC infrastructure either wastes
area and power due to overdesign, or fails to deliver the specified performance.
Hence there is a high potential for optimization to get it just right.
Common place approaches like (static) spreadsheet approaches breaking
down, an efficient model-based performance analysis methodology is
essential to meet today’s architecture & design SoC challenges

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Virtual Platforms - Technology Requirements

 Accuracy: the analysis methodology needs to be sufficiently accurate to give the
system architect the confidence to take design decisions.
 Product use-case analysis: the SOC infrastructure needs to deliver sufficient
communication bandwidth under all relevant product use cases. Therefore, the
system architect must be able to efficiently analyze the impact of the workload,
which is imposed by different use cases onto the interconnect and memory
architecture.
 Quick set-up time & early modeling: The time window to define or influence the
system architecture is typically very short, that is, in the order of a few months at
most. Hence, a performance analysis methodology needs to be set up and deliver
results within a few weeks.
 Quick turnaround time: Architecture optimization entails the investigation and
comparison of different design configurations. Since the number of design
parameters and product use cases is typically very large, it is mandatory that
architectural alternatives can be evaluated on a daily, if not hourly, basis.
 Visibility: It must be possible to obtain all relevant performance metrics (latency,
throughput, utilization, efficiency). These metrics enable the system architect to
evaluate architectural trade-offs and to come up with an optimum architecture.

TSMC Reference Flow 11.0

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Virtual Platform – Refinement Flow

Architecture
Analysis Focus Workload
• Critical masters, • Traffic generators

Model Refinement
• Early Work interconnects & mem. • Traces
load model ctrls. • Apps profile model

Architecture
• Control /traffic aspect
• Software
…

benchmark(s)
…

• Add data trans- • System software

• Complete formations & CPUs

Project Time
System Model • SW binary compati
-ble model

• Validate model • System software

Architecture assumptions & • RTL testbench
Validation RTL performance re-use & score
boarding

TSMC Reference Flow 11.0

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Virtual Platform – RF 11 Example

TSMC Secret

Dual Core ARM926 System

L1 Cache & AXI Bus Performance

TSMC Reference Flow 11.0

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 Architecture Analysis & Optimization Security C –

Virtual Platform – Benefits

TSMC Secret

 Provides deep insight into the internal details of

chosen architecture configurations to optimize
system performance and cost
 An optimized interconnect and memory architecture
can significantly lower area and hence the SOC
fabrication cost
 Its predictive bottleneck analysis allows to prevent
costly design iterations
 Provides insight into software performance and
provides a vehicle for performing detailed software
profiling and software optimization
TSMC Reference Flow 11.0
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TSMC Secret

POWER
ANALYSIS & OPTIMIZATION

TSMC Reference Flow 11.0

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 Power Analysis & Optimization Security C –
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Challenges
 Growing leakage power at smaller process
technology nodes (“static power”)
 Increasing dynamic power due to increased clock
frequencies & silicon integration (“dynamic power”)
 System-level power challenges:
 Battery life
 System cooling, Air-conditioning cost, and potentially complying
with new “Green” standards
 Reliability, and packaging cost
 Operating cost

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Virtual Platform - Technology Requirements

 The following power modeling aspects are supported by a TLM
platform:
1. Power management modeling, i.e. power control aspect:
 Clock modeling – gating, scaling freq(t), …
 Voltage distribution - power domains, scaling V(t) , …
 Power state control – power state sequencing (power down, retention, …)
2. Power estimation equations – fitted with process technology data & evaluated
at run-time, based on actual applied clock, voltage & power state
3. Power Dashboards – providing user insight in actual clocks, state, voltage &
power
 TLM Abstraction-level Support:
 “Loosely Timed” (LT) level
 Model provides Instantaneous power consumption, at each point in time
 “Approximately Timed” (AT) level
 Supports trade-off of performance vs. power
 Graphs: Power(t) & Energy(t)
 Improved accuracy for accounting for (memory) transactions power contribution

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Virtual Platform - Clock Modeling

Clock
Controller

Master1 Master2

Signal is used to transmit value of clock

CPU(s) frequency from controller to peripheral;
TLM Bus
Instruction
Set Simulator does not model actual clock waveform

Periph Periph

 Functional clock modeling

 Models functional operation of the clock controller, including:
 Clock distribution
 Includes its control over peripheral clock gating
 Registers, to model software control over clock frequencies
TSMC Reference Flow 11.0
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Virtual Platform - Voltage & Power State Control Modeling

Included functional models of:
1. On-chip Power Manager (SoC) 2. Power management chip (PMIC)
 Control of (internal) voltage  Voltage scaling of SoC
distribution & domains  SoC I2C control interface, power
sequencing, LDO regulators control,
 State control & sequencing DC/DC convertors, …
VDD (SoC voltage scaling)

Voltage Domains
VDD USB
VDD RF
PRCM LDOs
I2C
I2C
Voltage
Distribution
PM
Sequencer

System-on-Chip (SoC) Power Management Chip

TSMC Reference Flow 11.0

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Virtual Platform – Power Estimation Models

Parametrizable power model, consisting of:
1. Component power characteristics
2. Component power calc. equations
3. Power accumulator
Master2
Power
Manager LT / AT
Master1 Master2 TLM Model
Voltage Power Estimation
CPU(s) Frequency
TLM Bus Power State Equation
Instruction
Set Simulator

Power request /
response APIs
Power
Accumulator
Power
Power event
Accumulator
Logging (file)

Power Dashboard
TSMC Reference Flow 11.0
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 Power Analysis & Optimization Security C –

Virtual Platform – RF 11 Example

TSMC Secret

ARM926 power model fitted

with TSMC technology data

ARM926 Power
Estimation Model

Model of On-Chip
Clock & Power Manager

Dual Core ARM926 System

Power consumption & ARM926 power state

sequencing in the 40LP TSMC

TSMC Reference Flow 11.0

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Virtual Platform
IP

IP Power State Characterization

Dump Power Trace (TSMC Process Node/Frequency)

Translate Power Trace Format Encrypted Power State Data

TSMC PPA Model

TSMC Reference Flow 11.0

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TSMC Secret

Innovator

Dump Power Trace

Power Trace Format

Translate Power Trace file extension with <.synopsys.ptr>

TSMC Reference Flow 11.0
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TSMC Secret

Define IP Power State

Characterize IP Power State

Example of unencrypted
power data

TSMC Reference Flow 11.0

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 TSMC PPA Model Usage Security C –
TSMC Secret

Parameters Name Value

Select Ptrace Time Scale NS
GUI X-Axis Display Ratio Linear
File::Open TSMC Process Node File PPA_Synopsys_Arm926/arm926_core.data

File::Open Ptrace File PPA_Synopsys_Arm926/ptrace_core1_pm.synopsys.ptr

TSMC Process Node Selection 65lp

Frequency Selection 166m

Press <Draw Line>

TSMC Reference Flow 11.0

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Change TSMC Process Node

From 65LP to 40LP

TSMC Reference Flow 11.0

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 Power Analysis & Optimization Security C –

Virtual Platform – Benefits

TSMC Secret

 Provides unique insight in system power consumption,

including both hardware and software, and this at both the SoC
and system level. No other power estimation tools today bring
hardware and software together.
 Support the early development of “power management
software”, typical in today’s (mobile) operating-systems, which
can then begin even before RTL is available
 Analyze the effect on power of various design trade-offs
and different power schemes, utilizing the actual system
software executing on the processor(s).
 Enable power optimization & trend analysis: as part of
“Performance-Power-Area” trade-off, these models can run
experiments that guide the architectural partitioning of power-
related design features, such as number of power islands,
power management strategies, etc.

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SUMMARY

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Virtual Platforms / TLM Modeling

 Covers multiple uses cases
 From architecture analysis to power, to pre-silicon software
development, and to system verification & validation …
 Model re-uses enables highest “Return On Investment” (ROI)
 Benefits
 Architecture - Predictive bottleneck analysis, preventing design
iterations
 Power – Address hardware and software power consumption jointly
 Software
 Parallelize hardware and software development, reducing time to market
 Increase software development productivity, through advanced controlability
& visibility

 Reference Flow 11
 Refer to extensive tutorial & design examples provided as part of
Synopsys ESL contribution to TSMC Reference Flow 11

TSMC Reference Flow 11.0

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Tutorial Material

Please contact TSMC to get access

to the ESL Virtual Platform Tutorial material (tutorial
document & design files)

TSMC Reference Flow 11.0

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