A Phase-Frequency Detector and a Charge Pump

Design for PLL Applications

Sinisa Milicevic and Leonard MacEachern
Carleton University, Department of Electronics
1125 Colonel By Drive, Ottawa, Ontario
Canada K1S 5B6

Abstract— An improved phase frequency detector (PFD) and a

novel charge pump (CP) for phase locked loop (PLL) applications
are presented. Implemented in a CMOS 0.13μm technology, the
PFD and the CP dissipate 3.73mW and a 460μW DC power
from a 1V supply, respectively. The occupied chip area of the
PFD is 68x24μm2 , and that of the CP is 68x23μm2 . With a
spurious free dynamic range of a 80dBc, a phase noise of a
-95dBc/Hz at 100kHz offset, a low power and a small layout
area the presented PFD and CP are suitable for integrated radio
applications operating between 2.4GHz and 10GHz, such as
802.11 and WiMax for example.
Index Terms— phase frequency detector, PFD, Charge pump,
CP, loop filter, PLL, frequency synthesizer.

I. I NTRODUCTION

F IGURE 1 shows a block diagram of a phase locked

loop (PLL) type frequency synthesizer. The research
work presented in this paper is focused on the design and
performances of the PFD and the CP as building blocks of
a PLL system. The spurs and phase noise contribution due (a) PFD (b) Differential AND gate [1]
to these blocks is analyzed and presented. The design and Fig. 2. Phase frequency detector.
analysis of the other building blocks of the loop system can
be found in [1]–[6].
with a common source resistor. This topology was used to
minimize the layout area. However, it also helps to minimize
the low-frequency content of the noise coming from the circuit
[1]. The NOR gate is identical to the AND gate however with
swapped inputs.
Averaged output voltage

-4 -3 -2 -
0 2 3 4

Fig. 1. Block diagram of a charge pump based phase locked loop.

Phase error ( rad )

II. P HASE F REQUENCY D ETECTOR
The PFD considered with this work is shown in Figure 2(a).
It should be noted that the PFD is a fully differential and for
simplification it is drawn as a single-ended. There are two
building blocks of the PFD: an AND and a NOR gate. The AND
gate is depicted in Figure 2(b). The tail current source found
in a classical implementation of the CML gates is replaced
Fig. 3. Simulated PFD characteristic.
To obtain the PFD characteristic, two periodic square signals
with clock frequency of 20MHz are used to feed the PFD
inputs designated as “REF” and “LO”. The delay of the REF
signal is fixed to 0, while the delay of the LO is used as a

978-1-4244-1684-4/08/$25.00 ©2008 IEEE 1532

 36 Process & Mismatch
variable. A parametric analysis, as a part of the SpectreRF 34 N-channel Transistor
32
simulator, is used to monitor the average output voltage from mu = 63.4μA

Statistical Analysis Results

30 sd = 6.2μA
the PFD when the delay of the LO signal is varied from -100ns 28
26
N = 100
to +100ns. With a clock frequency of 20MHz that implies 24
22
that the phase of the LO signal is varied from -4π rad to +4π 20
rad. Figure 3 shows the simulated PFD characteristic. The plot 18
16
indicates that the PFD has no “dead” zone and has a liner 14
12
tracking characteristic over 2π radians of phase error. 10
8
6
III. C HARGE P UMP 4
2
Figure 4 shows the novel charge pump design used for 0
the research work reported herein. The implemented charge 50 55 60 65 70 75 80
Output Current ( μA )
pump has a differential input and a single-ended output. The
output signals from the phase frequency detector, designated Fig. 5. Monte Carlo simulation to analyze the output current from the n-
as “UP” and “Down”, are input to the charge pump. The UP channel transistor due to process and mismatch variation.
differential signals are fed to a p-type differential pair CMOS
transistors, while the Down differential signals are fed to an 20 Process & Mismatch
n-type differential pair CMOS transistors. P-channel Transistor
18 mu = 63.6μA

Statistical Analysis Results

16 sd = 4.7μA
N = 100
14
12
10
8
6
4
2
Fig. 4. Proposed design for a charge pump. 0
50.0 52.5 55.0 57.5 60.0 62.5 65.0 67.5 70.0 72.5

The function of the charge pump is to sink or source Output Current ( μA )

a current to a low pass filter (LPF). For this purpose, the
proposed charge pump uses two current sources denoted as
“IUP ” and “IDown ”. In this circuit, the input differential pairs
(P3-P4 for UP signals and M6-M7 for Down signals) steer
current either to a dummy load (M2 for UP signals and P8
for Down signals) or into the two current sources (M1 and
P9), respectively. The signal path from the current sources to
the charge pump output is equal for the both UP and Down
signals (two n-channel and two p-channel transistors).
The proposed charge pump is a modification of the charge
pump found in [8] pp. 212 and a bipolar version found in [9].
However, there are several important differences between the
proposed and referenced charge pumps.
The charge pumps in [8], [9] use one current source, while
the charge pump presented herein utilizes two current sources.
In the charge pumps [8], [9], the UP and Down signals,
coming from the PFD, are fed to n-channel differential pairs.
Consequently, there is an extra current direction for the Down
signals, which makes an issue of the current matching in
those designs. The charge pump proposed in this paper has
two complementary differential pairs for the UP and Down
signals. Providing equal values for IUP and IDown the current
matching is less of an issue for the new charge pump. Indeed,
the simulation results show that the proposed charge pump
exhibits better performance with respect to ripple on the
voltage controlled signal compared to [8], [9].
Fig. 6. Monte Carlo simulation to analyze the output current from the p-
channel transistor due to process and mismatch variation.
While not reported in this paper, the complementary current
sources may be adjusted via a calibration circuit to optimize
the charge pump characteristic behavior.
A Monte Carlo simulation was used to analyze the output
current from the transistors P6 and M4 due to process and
mismatch variation. The output voltage of the charge pump
was set so that the currents from P6 and M4 were equal.
The number of runs of the Monte Carlo simulation was set
to 100. Figures 5 and 6 show the results for the current
from M4 and P6, respectively. The standard deviation of the
current from the M4 transistor is 6.16μA, while the standard
deviation of the current from the P6 transistor is 4.7μA. The
average current from the M4 transistor is 63.4μA, while the
average current from the P6 transistor is 63.6μA. Thus, the
deviation between the two currents is -0.31% due to process
and mismatch variations.
Figure 7 shows the output currents from the n-channel and
p-channel transistor of the charge pump as a function of the
temperature. The worst deviation of a -0.5% (relative to 27◦
Celsius operation) is noticed at the upper region when the
temperature is set to 100◦ Celsius.

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 74 PMOS
2.7
2.5
72

Output noise ( pA/sqrt(Hz) )

NMOS
2.3
Output current ( μA )

2.1
70
1.9
68 1.7
1.5
66 1.3
1.1
64 0.9
0.7
62 0.5
0.3
60
0.1
0 10 20 30 40 50 60 70 80 90 100
1E+03 10E+03 100E+03 1E+06 10E+06
Temperature ( °C ) Frequency ( Hz )

Fig. 7. Plot of the output current from the n-channel and the p-channel
Fig. 8. Simulated output noise current from the CP block.
transistor due to temperature variation.

-70
-75
IV. N OISE C ONTRIBUTION -80

Phase Noise ( dBc/Hz )

-85 fn = 1MHz
The open loop noise from the PFD and the CP can be -90
expressed as, -95
in -100
NoisePFDCP = (1) -105
Kphase -110 fn = 100kHz
-115
where in is the output noise current from the CP, while Kphase -120
is the gain of the PFD. -125
To estimate the phase noise due to the PFD and the CP in -130
-135
a closed loop system, the transfer function of the feedback -140
system shown in Figure 1 can be written as, 1E+03 10E+03 100E+03 1E+06 10E+06

Hout (s) F (s) Kvco Kphase Frequency ( Hz )

= (2)
Hinput (s) s + F (s) Kvco Kphase N1 Fig. 9. Phase noise contribution from the PFD and the CP block for a 10GHz
VCO output frequency.
The loop system shown in Figure 1 is of third order. However,
because the capacitor C2 is sized to be 10-times smaller than
the capacitor C1 , the steady-state responses will be the same
as for the second-order loop [10]. Thus, the transfer function The phase noise contribution from the PFD and the CP in the
of the LPF can be simplified and expressed as, considered loop system expressed in dB is,
1   
F (s) = R + . (3)  Hout (ω) 
PNPFDCP = 20 log10    · NoisePFDCP . (8)
Hinput (ω) 
sC1
The transfer function of the PFD-CP system is,
ICP Figure 9 shows the phase noise contribution from the PFD
Kphase = . (4) and the CP for a damping constant of a 0.707, a division ratio
2π
of 500, a reference frequency of 20MHz, and two cases for the
If the expressions (3) and (4) are substituted into the expres- natural frequency (100kHz and 1MHz). As expected, a LPF
sion (2), and the following substitutions are performed, with a lower cut-off frequency will help to minimize the phase
ICP Kvco noise from the PFD and the CP. The output noise current from
2ξωn = R (5) the CP is shown in Figure 8.
2πN
ICP Kvco In order to find how the non-idealities of the PFD and the
ωn2 = (6) CP affect the output spectrum from the PLL, the voltage-
2πNC1
controlled oscillator (VCO) and the frequency divider are
where ξ and ωn are the damping constant and the natural replaced with VerilogA blocks so their noise contribution
frequency of the loop, respectively, then, is removed. The frequency synthesizer is programmed to
   generate a 2.4GHz signal. The DFT of the VCO signal is shown
 Hout (ω)   2  2
  = Nωn 1 + (RC1 ω) in Figure 10. The spurious free dynamic range (SFDR) in this
 Hinput (ω)  2 2 . (7)
(ωn2 − ω 2 ) + (2ξωn ) ω 2 case is 80dBc.

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 0 1.5
-10 1.4
-20 1.3
1.5
-30 1.2
Signal Power ( dB )

1.4
1.1 1.3
-40 1.2
1.0

Vctrl ( V )
-50 1.1

Vctrl ( V )
0.9 1.0
-60 0.9
0.8 0.8
-70 0.7
0.7 0.6
-80 0.5
0.6
-90 0.4
0.5 0.3
-100 0.2
0.4
-110 0 1 2 3 4 5 6 7
0.3 Time ( μs )
-120 0.2
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 0 100 200 300 400 500 600 700 800 900 1000
Frequency ( GHz ) Time ( ms )

Fig. 10. Frequency spectrum of the output signal from frequency synthesizer Fig. 12. Measured acquisition of the voltage controlled signal. The inset is
configured to generate a 2.4GHz signal. a magnified view of the lock-in period.

V. M EASURED R ESULTS The DC power dissipation from a 1V supply of the PFD and
A frequency synthesizer implementing the proposed PFD the CP is a 3.73mW and a 460μW, respectively. The SFDR
and CP was fabricated in CMOS 0.13μm technology. Figure due to the PFD and the CP is 80dBc, while the phase noise
11 shows the photograph of the fabricated chip. In order to at 100kHz offset is -95dBc/Hz. The occupied chip area of the
perform the measurements, the fabricated chip was bonded PFD is 1632μm2 , and of the CP is 1564μm2 .
to a printed circuit board (PCB). The reference signal was
generated from an Agilent 81134A 3.35GHz Pulse/Pattern ACKNOWLEDGMENT
Generator and the acquisition of the loop signal was monitored The authors wish to acknowledge the contributions and
by a Tektronix TDS 3032 300MHz 2.5GS/s. support of NSERC and Agilent Labs toward the realization
of the research reported herein.
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