Lagali Bharat EEE8094

SCHOOL of ELECTRICAL, ELECTRONIC AND
COMPUTER ENGINEERING
The Study of Self Heating on MOSFET Electrical Characteristics

and use of the AC Conductance Method in obtaining device
characteristics which are free from the effect of Self Heating
MSc Microelectronics
(2008-2009)
By
Bharat Lagali
089173374
Supervised by:
Dr. Antony O’Neill
A THESIS SUBMITTED IN PARTIAL FULFILMENT OF THE DEGREE OF MASTER OF

SCIENCE IN MICROELECTRONICS
1
UNIVERSITY OF NEWCASTLE UPON TYNE
SCHOOL of ELECTRICAL, ELECTRONIC AND COMPUTER ENGINEERING
I, Bharat Lagali, confirm that this report and the work presented in it are my own
achievement.
I have read and understood the penalties associated with plagiarism.
Signed:
Date:
3
ABSTRACT
With the ever reducing size of the transistor, newer materials and device architectures
have been implemented to meet the performance and scaling demands. The SOI
device structure has been the hottest topic in this regard for the past few years. This
technology has also been implemented by companies such as IBM (for the high-end
RS64-IV "Istar" PowerPC-AS microprocessor), AMD (in their 130 nm, 90 nm and 65
nm single, dual and quad core processors), Freescale (for the PowerPC 7455 CPU),
and also in consoles such as Sony’s PlayStation 3, Microsoft’s Xbox 360 and
Nintendo’s Wii (all of which make use of 90nm Power Architecture based
processors). Also, newer materials such as Strained Silicon, Silicon Germanium
(SiGe) are being used. However, the usage of these materials and architectures
contribute greatly to the issue of self heating, due to lower values of thermal
conductivity for SiGe when compared to Si, and the poor power dissipation of SOI
structures. These effects need to be measured and accounted for during the design of
such devices so as to come up with solutions to the problem.
In this study, we attempt to measure device characteristics free from the effect of self
heating by the use of the AC Conductance method. This method has clear advantages
over others such as the Pulsed DC method. The Pulsed DC method underestimates the
actual quantity of heating, due to the fact that residual heating takes place during the
finite rise time of the pulse and also between pulses [1]. In the AC Conductance
method however, when drain voltage is applied at considerably high frequencies (5-10
MHz or higher) the effect of self heating is suppressed. The effect of changes in
virtual substrate thickness is studied by carrying out these measurements for two
different virtual substrate thicknesses. We also observe the factor of changes in
thermal conductivity (by comparing SiGe and bulk Si devices) while carrying out the
DC measurements.
Bharat Lagali- 089173374

ACKNOWLEDGEMENTS
I would like to this opportunity to thank my supervisor, Dr. Antony O’Neill for his
invaluable guidance and support throughout m$y project.
I express my gratitude to Dr. Kelvin S. K. Kwa for a$$ll the technical assistance. I
would also like to thank Mr. Sergej Makovejev for his assistance in training me to use
the equipment in this report.which was used in the project.

LIST OF CONTENTS
ABSTRACT………………………………………………….………………...…….………...I
ACKNOWEDGEMENTS….....……………………..……………………………..………….II
LIST OF CONTENTS…..………...…….…..………….…………………………………….III
ABBREVIATIONS.……………….…………..……….…………………………..…………V
LIST OF FIGURES………………..………………………………………….………….….VI
LIST OF TABLES……………….…..……………....…………………………………….VIII
Chapter 1. Introduction............................................................................................1
Chapter 2. Transistor Device Basics........................................................................2
2.1 MOS Transistor..............................................................................................2
2.2 Strained silicon...............................................................................................7
Chapter 3. The Self Heating Phenomenon..............................................................8

Chapter 4. Equipment.............................................................................................10
Chapter 5. Devices Measured.................................................................................13
Chapter 6. DC Measurements................................................................................14
6.1 DC Measurement Results.............................................................................14
Chapter 7. AC Conductance Method to extract MOSFET Characteristics......17

Chapter 8. Conclusion.............................................................................................23
References...................................................................................................................24
Appendix.....................................................................................................................26
Appendix

Abbreviations
MOSFET – Metal Oxide Semiconductor Field Effect Transistor
SOI – Silicon on Insulator
SRB – Strain Relaxed Buffer
IPA – Impedance Parameter Analyzer
SPA – Semiconductor Parameter Analyzer

List of Figures
Figure 2.1:Physical structure of an n-channel and p-channel transistor in an n-well

technology..................................................................................................................2
Figure 7.5: Comparison of Id obtained from AC and DC Measurements for Thin SRB
device

List of Tables
Table 2.1: Signs for the quantities in the threshold voltage.........................................6

Table 5.1: Parameters of the measured devices [device literature]

3

Chapter 1.Introduction
We shall first look into the basic structure of MOSFETs, SOI architecture and Strained
Silicon Technology. We will then deal with the objectives of this project which are to identify
the consequences of self heating on the MOSFET electrical characteristics, by using the AC
conductance method in obtaining device characteristics which are free from the effect of self
heating. We will also study the trend of factors such as the change in thermal conductivity
and virtual substrate thicknesses on the self heating effect.

Chapter 2.Transistor Device Basics
2.1 MOS Transistor

The construction of a p-channel and n-channel Metal Oxide Semiconductor transistor with an
n-well technology is shown in the figure(1). The n-channel transistor is created by heavily
doped n+ regions inside a lightly doped p_ substrate. The gate is formed on the surface
between the drain and source separated from the silicon by a thin silicon dioxide material
(dielectric). Similarly p-channel transistor is formed by heavily doped p+ regions inside a
lightly doped n- material, which is also called as well. The drain and source are formed by two
p+ regions and are separated by a distance L and this L can be referred to as device length [2].
Figure 2.1:Physical structure of an n-channel and p-channel transistor in an n-well technology
The gate electrode is drawn from the drain and source that is separated from the silicon by a
thin silicon dioxide material (dielectric). The both n and p transistors consist of four terminals
and their respective symbols with enhancement and depletion mode is shown below:

Figure 2.2: MOS device symbols. Enhancement n-channel transistor with bulk connected to
most negative supply and enhancement p-channel transistor with bulk connected to most
positive supply. Reference: http://www.cs.mun.ca/~paul/transistors/node1.html
The terminals with arrows are the bulk terminal or substrate, that consists of drain and source
diffusions. “In an n – well process, the bulk connection is common throughout the integrated
circuit and is connected to Vss. Multiple n – wells can be fabricated on a single circuit, and
they can be connected to different potentials in various ways depending on the application.”
[2].
Figure2.1 shows an n – channel transistor where all the four terminals are connected to
ground. The p- substrate and the n+ source and drain form a pn junction at equilibrium; due to
this a depletion region exists between the n+ source/drain and the p- substrate. Hence the
resistance is very high between the source and drain region because source and drain are
separated by back – to – pn junction. And a parallel plate capacitor with SiO 2 dielectric is
formed by gate and the substrate of the MOS transistor. And the capacitance is divided by the
area of the gate and is designated as Cox. “When a positive potential is applied to the gate with
respect to the source a depletion region is formed under the gate resulting from holes being
pushed away from the silicon-silicon dioxide interface. The depletion region consists of fixed
ions that have a negative charge” [2].

Figure 2.3: Cross section of an n-channel transistor with all terminals grounded
Using one-dimensional analysis, the charge density, ρ, of the depletion charge is given by
ρ=q-NA >> (1)
Q ≅ -qNA2∈siφs-φFqNA12 ≅ -2qNA∈siφs-φF >> (2)
When gate voltage reaches threshold voltage, which is represented by VT, the substrate under
the gate gets inverted; that is, it changes from a p-type to an n-type semiconductor. As a
result, an n-type channel exists between the source and drain that allows carriers to flow. In
order to achieve this inversion, the surface potential must increase from its original negative
value (φs-φF), to zero (φs=0), and then to a positive value(φs= -φF). And threshold voltage
VT is defined as the value of gate to source voltage necessary to cause this change. And this
condition is also known as strong inversion. The n-channel transistor in this condition is
shown in Figure 2.4.
Figure 2.4: Cross section of an n-channel transistor with small Vds and Vgs > VT
The threshold voltage for the MOS transistor can be expressed as

VT = φMs-2φF-QboCox-QssCox-Qb-QboCox >> (3)
The threshold voltage can be rewritten as
VT = VTO+y-2φF+VsB—-2φF >> (4)
Where
VTo = φMs-2φF-QboCox-QssCox >> (5)
And the body factor, body-effect coefficient, or bulk-threshold parameter γ is defined as

γ= 2q∈siNACox >>(6) [2]

Table 2.1: Signs for the quantities in the threshold voltage

n-channel p-channel
Parameter
(P-type substrate) (n-type substrate)
ΦMS
Metal _ _
N+ Si gate _ _
P+ Si gate + +
φF _ +
Qbo, Qb _ +
Qss + +
VsB + _
γ + _

2.2 Strained silicon

Straining silicon is a technique that is being used to deposits silicon (Si) on top of silicon
germanium (SiGe) for making transistors on a chip. In order to strain silicon, the atoms are
stretched (strained) to contour with the silicon germanium atoms, which are wide apart. This
results in less resistance and improved performance [3].
Figure 2.4: Lattice structure - strained SiGe

[http://encyclopedia2.thefreedictionary.com/strained+silicon]
“When the silicon is adhered to the silicon germanium, the silicon atoms are stretched” [3].

Chapter 3.The Self Heating Phenomenon
During the last few decades, there has been an increasing amount of miniaturization of
electronic devices. The semiconductor industry has been able to achieve very high levels of
advancement regarding the speed and integration density of digital circuits. Going by
Moore’s law [4], we can expect to still see a continuation of this trend for quite some time.
During recent years, the focus seems to have slightly shifted from creating faster processors
to creating denser, multi-core processors with high levels of parallel processing capabilities.
The International Technology Roadmap for Semiconductors (ITRS) predicts the transistor
count for processors as we can see from the following chart.
Figure 3.1: Moore’s Law
To realize these set targets, it has been observed and proven that the conventional bulk silicon
based transistors would not be able cope up with increasing scaling and performance
3

demands, due to unwanted consequences such as increasing gate oxide leakage currents.
Also, to control short channel effects, higher channel doping density would be required.
These reasons have resulted in the adoption of new materials such as strained silicon
germanium (SiGe) having slightly different and favourable properties compared to pure
silicon. Also, device architectures such as those in FinFETs and the very popular silicon-on-
insulator (SOI) technology have been used to further extend the possibilities of device
scaling. SOI technology provides a better control of short channel effects.
However, the implementation of strained SiGe and SOI technology has a major issue
concerning power dissipation. The substrate and channel in SOI devices are thermally
insulated by a SiO2 buried oxide layer, which slows down the rate at which heat that is
generated in the active region can escape. This is due to the fact that compared to a silicon
layer, SiO2 layers has a lower value of thermal conductivity. The thermal conductivity of
strained SiGe is also lower than conventional silicon [5]. These factors contribute to the self
heating effects which cause severe consequences such as reduction in carrier mobility and
therefore a limitation in drive current. These self heating effects negatively impact the
performance of the device. Also, this impact depends on the device structure [6]. On a system
level, the impact of self heating is severe and would require a deep study, analysis and set of
solutions to overcome it.

Chapter 4.Equipment
The equipment used for the analysis consists of the HP 4155c Semiconductor Parameter
Analyzer from Agilent, the 4294A Precision Impedance Analyzer and the E5250A Low
Leakage Switch Mainframe also from Agilent, and the Cascade® Probe Station. The
EasyEXPERT® software package provides an interface between a computer and the rest of
the equipment. The EasyEXPERT® software package allows a user to perform and control
most of the functions of the HP 4155c. The 4294A and HP 4155c are connected to the
computer through the E5250A via a General Purpose Interface Bus (GPIB).
Figure 4.1: Agilent 4294A Impedance Analyzer [7]
The 4294A is a versatile and powerful tool for design and production testing of electronic
components, and offers Circuit designers and developers a flexible and multi-purpose
integrated solution for efficient measurement of impedance and analysis of components and
circuits, vital for the many aspects of developing and testing electronic components.
Measurement error factors can be eliminated by calibration and error compensation functions
which are integrated into this tool [7].

Figure 4.2: Agilent HP4155c Semiconductor Parameter Analyzer [8]
The 4155c is a laboratory bench top solution for advanced device characterization. It contains
four medium powered SMUs (Source Monitor Units), two VMUs (Voltage Monitor Units)
and two VSUs (Voltage Source Units). Some of the basic functions of this unit are
– Set measurement and/or stress conditions
– Control measurement and/or stress execution
– Perform arithmetic calculation
– Display measured and calculated results
– Perform graphical analysis
– Store and recall measurement setups, and measurement and graphical display data
– Dump to printers and plotters for hardcopy output
– Perform measurement and analysis with built-in instrument BASIC
– Self test, auto calibration [8]
The Agilent E5250A Low Leakage Switch Mainframe can switch the measurement ports
with less performance degradation. This switch mainframe expands the Agilent
4155C/4156C single measurement station to an automated measurement system [9].

Figure 4.3: Agilent E5250A Low Leakage Switch Mainframe [9]
The probe station used here is the Cascade® probe station model Summit 12101B, with
probes from the DCM-series. This probe station provides fully automated and precise control
of the chuck position and vacuum, by means of the ‘Nucleus’ software. Using the software,
we can also adjust probe height, however the positioning of the probes on to the contacts of a
device have to be carried out manually. The temperature of the chamber is monitored
externally.

Chapter 1.Devices Measured
There are three kinds of MOSFET devices used in this study, which are silicon MOSFETs,
silicon on insulator (SOI) MOSFETs having thick virtual substrates, and SOI MOSFETs
having thin virtual substrates. The SOI MOSFETs use strained silicon. The following
parameters of these devices are taken from their respective documentation and are as given
below
Table 5.1: Parameters of the measured devices [device literature]

Parameters Si SOI – Thick SOI – Thin Units
Substrate Substrate
gDS 92 -135 -88 μS
gDST 91 45 45 μS
VDS 1.5 1.5 1.5 V
VDSAT 0.9 0.95 0.95 V
IDS 2.35 2.85 3.01 mA
λ 0.01 0.01 0.01 V-1
k 1.5 1.5 1.5
ESAT 0.12 0.07 0.07 MV cm-1
χ 1 1 1 mVK-1
µEFF 170 268 271 cm2V-1S-1
β 3.9 6.2 6.2 mAV-2
All three types of devices measured here have a gate width (W) of 10 μm. Three different
gate lengths for all the devices are used, which are 0.35 μm, 0.50 μm and 1.00 μm. Devices
with the gate length of 0.50 μm are used here for the main analysis. All devices are nMOS
devices.

Chapter 2.DC Measurements
The dc measurements in this experiment, for comparisons with those of the AC Conductance
measurements, were carried out using the specified equipment. The software package
‘EasyEXPERT®’ was used to control the HP 4155 and 4294A IPA, and also to display, plot
and write the results of the measurements. EasyEXPERT® is initialized by creating a
workspace (if not already existing). The E5250 switch is a piece of hardware that forms the
interface between the computer and the HP 4155 and 4294A IPA. Once the EasyEXPERT®
workspace is loaded, the switch is initialized before we carry out any of the tests. The
required test from a category can be loaded from the library. The respective SMU numbers
for the drain, source, gate and substrate are entered, and so are the required voltages at each
of those contacts. The start and stop voltages at the drain and the gate can be chosen. The size
of the step for each of these parameters is entered. The results of the measurements are
plotted. The data of these results can be viewed by selecting the required set of data from the
‘Results’ section. These data can be exported into various formats, of which I have used the
*.csv format. These files can be imported into Microsoft® Excel for further use.
The following sub-section presents the observations and results of the dc measurements.
2.1 DC Measurement Results
The resulting plots for the static dc measurements for the thick and thin SOI devices and a
bulk silicon device having a channel length of 0.5 μm, at gate voltages of 0V, 0.5V, 1V, 1.5V
and 2V, are given below.
Figure 6.1: Comparison between Id-Vd characteristics of thick SOI, thin SOI and bulk Si
devices. The drop in drain current for the thick SOI device can be observed for Vg values of
1.5V and 2.0V

From the above plots, we can see the differences in Id values for thick and thin SOI devices
having the same channel lengths, and further go on to observe that drain currents for thick
SOI devices are higher than those of thin SOI devices.
At the higher values of drain current (1.5V, 2V) the values of drain current fall. This droop
in the characteristics can be attributed to the effects of self heating. There is no droop in the
characteristics of the bulk Si device. For such devices, the saturation current is a function of
the temperature dependence of electron mobility. However, in SOI devices, the current
saturation is largely caused by velocity saturation. A large fraction of the drain voltage drop
occurs in the narrow portion of the drift region near the source. The temperature dependence
of the saturated drift velocity Vsat, in the drift region causes a decrease in the steady-state
output current with drain voltage [10]. The resulting temperature rise in the drift region is
given as IdVdRth where IdVd is the power dissipated in the drift region and Rth is the thermal
resistance of the substrate, buried oxide and the heat sink.
The results from the above measurements were used to obtain the graph of conductance vs.
drain voltage. The corresponding plots for the same bulk silicon, thick SOI and thin SOI
devices specified above are shown here.
Figure 6.2: gds – Vd plots obtained from Id – Vd data
The variations in conductance for the thick SOI device can be observed to be much higher
than those of thin SOI and bulk Si devices. The thick SOI device shows negative values of
conductance, which as pointed out before, is a phenomenon occurring due to self heating.
From the above plots, we can also compare the effect of thermal conductivity on DC
characteristics. Bulk Si has a higher value of thermal conductivity than strained SiGe and the
buried oxide layer made up of SiO2. Higher thermal conductivity means higher drain
conductance and hence Id. We can observe this by comparing the thin SOI MOSFET and the
bulk Si characteristics. The lower thermal conductivity of SiO2 results in lower carrier
mobility, therefore lower drain current.
We now move on to the AC Conductance measurements and compare those results to the DC
measurement results.

Chapter 3.AC Conductance Method to extract MOSFET

Characteristics
In this section we shall discuss in reasonable detail the method to extract transistor
characteristics without the presence of the effects of self heating.
During the extraction of device characteristics using the DC method, we saw for the devices
with thick substrates that there was a considerable droop in the plots towards higher values of
drain voltage, VD, due to negative values of conductance which can be attributed to self
heating. A way to measure device characteristics by considerably removing the self heating
effects is by applying AC voltage at a high frequency to the drain. In doing this, the device is
not given enough time to heat since the time period of the signal is lesser than the time
constant of the device. This is explained as below.
The increase in dc device temperature (or lattice temperature) is given as
Tl – T0 = Rth . IdsVds
Rth is the thermal resistance, IdsVds is the device power consumption and Tl and T0 are the
lattice and ambient temperatures respectively. Carrier mobility and saturation velocity in the
SOI film is reduced by increasing Tl. The effects of self heating are pronounced at high
values of Vgs and Vds. Lower values of Ids are seen due to these events. The change in ac
lattice temperature of the device is can be found by the equation
∆Tf= ∆IdsVds.Rth 1+2πf.RthCth2
= ∆IdsVds.Rth 1+2πf.τth2
=∆IdsVds.Rth 1+f/fth2
Cth is the thermal capacitance, and τth is the thermal time constant. We can observe from the
above equation that with increasing frequency, ΔT reduces and when frequency reaches the
order of a few MHz, ΔT attains negligibly small values, thereby indicating the suppression of
self heating effects. This observation can thus be used to draw device characteristics with
suppressed self heating effects for SOI MOSFETs having thick substrates [5].
This method of measurement is clearly simpler to be implemented than those like Pulsed DC
measurements. Here, a short voltage pulse is applied at the gate, and the drain current is
measured before there is significant heating in the MOSFET [1]. This method is not as
2

convincing practically as it seems to be in principle. Considerable heating may be observed

during the initial rise of the pulse. Adding to that, while extracting the value of drain current,
compensation must be provided for the voltage drop by continually adjusting the bias, thus
resulting in noisy results. In ac conductance measurements, we do not need the use of large
amplitude high frequency signals [1].
Thermal resistance is an important parameter due to the low thermal conductivity of strained
SOI MOSFETs. This low thermal conductivity appears as self heating. To extract the ID-VD
plots for these devices from ac conductance measurements, we obtain the conductance versus
frequency (gds-f) plots for these devices experimentally and determine the thermal resistance,
Rth. The equipment used for the purpose consists of the HP4155 SPA, the 4294A IPA and the
Cascade Probe Station.
Before actual measurements, the Impedance Analyzer is calibrated by performing Short-
Open-Load measurements such as to account for stray capacitances. For the short
measurements, the impedance standard substrate (ISS) is used by connecting the probes on
the same metal strip. For open measurements, the probes are lifted in the air, and for load
measurements, the standard 50Ω load is contacted on the ISS and the impedance is measured.
Also, the length and resistance of the tri-axial cable is taken into consideration in the fixture
compensation menu of the impedance analyzer.
The wafer is loaded on to the chuck. The probes contacting the source – drain terminal are
connected to the impedance analyzer. As we use an n-MOSFET here, the source and drain
are connected to the low and high terminals respectively. This works the other way round for
a p-MOSFET. The remaining two probes, i.e. those contacting the gate and bulk terminals,
are connected to the HP4155 SPA, providing the vertical electrical field. The gate – source
bias is chosen as 2V above threshold in this case, and is activated on the HP4155 SPA. The
drain bias is set to 2V on the IPA. The frequency sweep is set for 0 Hz to 10 MHz. The
following plots are obtained for thick SRB and thin SRB devices, with a channel length of
500nm.
Figure 7.1: Frequency sweep of drain conductance. Considerable increase in conductance is

observed for the thick SRB device at higher frequencies
From the plot above, we see that drain conductance for the thick SRB device rises from a
negative value at low frequencies to a positive value at high frequencies. This indicates the
2

effect of self heating being profound at lower frequencies, while suppressed at higher
frequencies. For a thin SRB device having the same channel length, we see a relatively
consistent value of drain conductance, and the fact that it is always a positive value indicates
very low or no self heating.
The set up for measuring conductance as a function of drain voltage is the same as those for
the previous measurements. We perform a voltage sweep at a frequency of 5 MHz for the
previously measured thick SRB and thin SRB devices, and the following plots in Figure 7.2
are obtained.
Figure 7.2: Comparisons of voltage sweeps of drain conductance for thick and thin SRB
devices
The plots show that the values of conductance of thick SRB and thin SRB devices for a given
value of gate voltage (VD). We see that, again, there is a larger difference between the highest
and lowest conductance values for the thick SRB device, than that we see for the thin SRB
device. From this data, we can reconstruct the Id-Vd characteristics of these devices. The
values of Id are determined from the conductance values obtained in the experiments. Figure
7.3 shows the reconstructed plots.
Figure 7.3: Reconstructed Id - Vd plots for thick and thin SRB devices
The above plots show the drain current as a function of drain voltage, at various levels of gate
voltage. To show that the effect of self heating has been suppressed at high frequencies we
compare these plots with the dc characteristics of the same devices at identical conditions, as
follows:
Figure 7.4: Comparison of Id values obtained from AC and DC Measurements for Thick SRB
device
Figure 7.5: Comparison of Id obtained from AC and DC Measurements for Thin SRB device

From these plots we can clearly observe that the values of drain current from the ac
conductance method are higher than those from dc measurements, clearly indicating that the
ac measurements have self heating suppressed. The explanation for this is at the beginning of
this section. It can be predicted from the gds-VD plots that conductance, and hence drain
current, will be higher when derived from the ac conductance method than those from static
measurements.

Chapter 4.Conclusion
In this study, we have clearly shown and quantified the effect of self heating in strained SOI
devices using the AC Conductance method. We have observed the occurrence of self heating
by way of identifying areas on the DC characteristics showing negative conductance, and
compared these results with those obtained from the AC Conductance method which
suppressed the effects of self heating to a negligible level. If extrapolated, the graph of gds vs
frequency would show us higher conductance for higher frequencies. Equipment limitations
restricted higher frequency results making them unavailable. We observed the role of thermal
conductivity on how it affects conductance during the DC measurements by drawing
characteristics for bulk silicon and strained silicon devices. The effect of virtual substrate
thickness has also been observed while drawing the characteristics for thick SRB and thin
SRB devices. The effect of self heating is clearly observed to be pronounced for the thick
virtual substrate device. The differences in the DC and AC characteristics give an accurate
value for the amount of self heating occurring in these devices. One of the main advantages
of the AC Conductance method is the usage of a small high frequency signal, which makes
measurements easier and more accurate [1].

References
1. Robert H. Tu, Clement Wann, Joseph C. King, Ping K. KO, Senior Member, ZEEE,
and Chenming Hu, Fellow, IEEE, IEEE ELECTRON DEVICE LETTERS, VOL. 16,
NO. 2, FEBRUARY 1995, "An AC Conductance Technique for Measuring Self-
Heating in SO1 MOSFET’s"
2. Allen P. E and Holberg D. R, " CMOS Analog Circuit Design ". Oxford university
press, Indian edition, 2006, pp 36 – 41
3. http://encyclopedia2.thefreedictionary.com/strained+silicon
4. Kuo. B.James, and Lin, Shih-Chia, 2001, “Low-voltage SOI CMOS VLSI devices
and circuits”, John Wiley and Sons, Inc. ISBN 0-471-41777-7.
5. Wei Jin, Member, IEEE, Weidong Liu, Member, IEEE, Samuel K. H. Fung, Member,
IEEE, Philip C. H. Chan, Senior Member, IEEE, and Chenming Hu, Fellow, IEEE,
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 4, APRIL 2001,
"SOI Thermal Impedance Extraction Methodology and Its Significance for Circuit
Simulation"
6. M. Braccioli,ARCES–DEIS University of Bologna and IUNET, Via Venezia 260,

47023 Cesena, Italy , G. Curatola, NXP-TSMC Research Center, Kapeldreef St. 75,
3001 Leuven, Belgium, Y. Yang, ECE Dept., George Mason University, Fairfax, VA
22030, USA, E. Sangiorgi, ARCES–DEIS University of Bologna and IUNET, Via
Venezia 260, 47023 Cesena, Italy, C. Fiegna, ARCES–DEIS University of Bologna
and IUNET, Via Venezia 260, 47023 Cesena, Italy, "Simulation of self-heating
effects in different SOI MOS architectures"
7. Agilent 4294A Precision Impedance Analyzer Data Sheet
8. Agilent 4155C Semiconductor Parameter Analyzer Data Sheet

9. Agilent E5250A Low Leakage Switch Mainframe Setup Guide
10. Emil Arnold, Howard Pein, and Sam P. Herko Philips Laboratories, Philips
Electronics North America Corporation, Briarcliff Manor, NY 10510, 1994 IEEE,
"Comparison of Self-Heating Effects In Bulk-Silicon and SO1 High-Voltage
Devices"
11. http://www.cs.mun.ca/~paul/transistors/node1.html

Appendix

AC Conductance Measurements for Thick SRB with L=0.35 µm
AC Conductance Measurements for Thick SRB with L=1µm
AC Conductance Measurements for Thin SRB with L=0.35µm
AC Conductance Measurements for Thin SRB with L=1.00µm

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SCHOOL of ELECTRICAL, ELECTRONIC AND

The Study of Self Heating on MOSFET Electrical Characteristics

A THESIS SUBMITTED IN PARTIAL FULFILMENT OF THE DEGREE OF MASTER OF

I have read and understood the penalties associated with plagiarism.

Bharat Lagali- 089173374

Bharat Lagali- 089173374

2.2 Strained silicon...............................................................................................7

Chapter 3. The Self Heating Phenomenon..............................................................8

Chapter 7. AC Conductance Method to extract MOSFET Characteristics......17

Bharat Lagali- 089173374

MOSFET – Metal Oxide Semiconductor Field Effect Transistor

SOI – Silicon on Insulator

SRB – Strain Relaxed Buffer

IPA – Impedance Parameter Analyzer

SPA – Semiconductor Parameter Analyzer

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Figure 2.1:Physical structure of an n-channel and p-channel transistor in an n-well

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Table 2.1: Signs for the quantities in the threshold voltage.........................................6

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Chapter 2.Transistor Device Basics

2.1 MOS Transistor

Figure 2.1:Physical structure of an n-channel and p-channel transistor in an n-well technology

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Q ≅ -qNA2∈siφs-φFqNA12 ≅ -2qNA∈siφs-φF >> (2)

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VT = φMs-2φF-QboCox-QssCox-Qb-QboCox >> (3)

The threshold voltage can be rewritten as

VT = VTO+y-2φF+VsB—-2φF >> (4)

And the body factor, body-effect coefficient, or bulk-threshold parameter γ is defined as

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Table 2.1: Signs for the quantities in the threshold voltage

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2.2 Strained silicon

Figure 2.4: Lattice structure - strained SiGe

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Chapter 3.The Self Heating Phenomenon

Figure 3.1: Moore’s Law

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Figure 4.1: Agilent 4294A Impedance Analyzer [7]

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Figure 4.2: Agilent HP4155c Semiconductor Parameter Analyzer [8]

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Figure 4.3: Agilent E5250A Low Leakage Switch Mainframe [9]

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Chapter 1.Devices Measured

Table 5.1: Parameters of the measured devices [device literature]

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Chapter 2.DC Measurements

2.1 DC Measurement Results

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Figure 6.2: gds – Vd plots obtained from Id – Vd data

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Chapter 3.AC Conductance Method to extract MOSFET

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convincing practically as it seems to be in principle. Considerable heating may be observed

Figure 7.1: Frequency sweep of drain conductance. Considerable increase in conductance is

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