UNIT-II: ARCHITECTURE OF TMS320C5X

(Refer: Ch. No. 3 and 4 of Venkataramani)

INTRODUCTION

Leading manufacturers of DSP processors chips are:

i) Texas Instruments (TI) ii) Analog Devices iii) Motorola

This chapter deals with fifth generation TI TMS320C5X DSP processor (denoted as 5X).
The TMS320 DSP family:
•Two types of single-chip DSPs: 16-bit fixed-point and 32-bit floating-point.
• Has the operational flexibility of high-speed controllers and the numerical capability of
array processors.
•Inexpensive alternative to custom fabricated VLSI multitichip bit-slice processors.

The first five generations of TMS320 family are:

C1X, C2X, C3X, C4X and C5X.

•C1X, C2X, C2XX and C5X are 16-bit fixed- point processors.
C3X and C4X are 32-bit floating-point processors
Instruction sets of the higher generation fixed-point processors are upward compatible to the
lower generation fixed-point processors. For example C5X can execute the instructions of
both C1X and C2X.
The sixth generation C6X devices feature VelociTI™, an advanced very long instruction
word (VLIW) architecture developed by TI and can execute 1600 MIPS ( Mega Instructions
Per Second).
The eighth generation C8X devices, have, on a single piece of silicon, a number of advanced
DSPs (ADSPs) and a RISC master processor.
The TI DSP chips have IC numbers with the prefix TMS320. If the next letter is C (e.g.
TMS320C5X), it indicates that CMOS technology is used for the IC and the on-chip
non-volatile memory is a ROM. If it is E (e.g. TMS320E5X) it indicates that the
technology used is CMOS and the on-chip non-volatile memory is an EPROM. If it is
neither (e.g. TMS3205X), it indicates that NMOS technology is used for the IC and the
on-chip non-volatile memory is a ROM.

Architecture of TMS320C5X DSP ( Block diagram and description of

Architecture of TMS320C5X DSP)

The block diagram of the internal architecture of C5X is shown in Fig. 2.1. The 320C5X DSP
uses advanced Harvard architecture because they have separate memory bus structures for
program and data memory.

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 Fig. 2.1 Internal architecture of C5X
BUS STRUCTURE

Separate program and data buses allow simultaneous access to program instructions
and data, providing a high degree of parallelism. For example, while data is
multiplied, a previous product can be loaded into, added to or subtracted from the
accumulator and, at the same time, a new address can be generated. Such parallelism
supports a powerful set of arithmetic, logic and bit-manipulation operations that can
all be performed in a single machine cycle. The C5X architecture has four buses and
their functions are as follows:

Program bus (PB): It carries the instruction code and immediate operands from
program memory space to the CPU.
Program address bus (PAB): It provides addresses to program memory space for
both reads and writes.

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Data read bus (DB): It interconnects various elements of the CPU to data memory
space.
Data read address bus (DAB): It provides the address to access the data memory
space.

The program and data buses can work together to transfer data from on-chip data
memory and internal or external program memory to the multiplier for single-cycle
multiply/accumulate operations.

CENTRAL ARITHMETIC LOGIC UNIT (CALU)

It consists of the following elements: (16xl6)-bit parallel multiplier, arithmetic logic

unit (ALU), accumulator (ACC), accumulator buffer (ACCB), product register
(PREG) each with 32 bits and 0-16- bit left barrel shifter and right barrel shifter. One
of the operands for the ALU operation comes from ACC. The result of operations
performed in central ALU are stored in ACC. Either the higher order word or lower
order word of ACC can be loaded from memory. A 32-bit register denoted as ACCB
is used for temporary storage of ACC. The hardware multiplier unit in the C5X
processors performs 16 x 16 multiplication of numbers represented in 2’s
complement form. The 32-bit PREG holds the result of multiplication. The 16-bit
temporary register 0 (TREG0) holds the multiplicand. The other operand for the
multiplication can be specified using one of the addressing modes. A 0-16-bit left
barrel shifter and right barrel shifter in CALU permit the contents of memory to be
left shifted by 0 to 16 bits before they are either fed to ALU or stored from ALU to
memory. The CPU registers ACC and PREG can also be shifted using these shifters.
In this case they require two cycles. A 5-bit register TREG1 specifies the number of
bits by which the scaling shifter should shift either the incoming data to one of the
CPU registers or vice versa. When the incoming data to CPU is left shifted by the
scaling shifter the LSBs are filled with 0.

AUXILIARY REGISTER ALU (ARAU)

It consists of eight 16-bit auxiliary registers (ARs) AR0-AR7, a 3-bit auxiliary
register pointer (ARP) and an unsigned 16-bit ALU. ARAU calculates indirect
addresses by using inputs from ARs, 16-bit index register (INDX) and auxiliary
register compare register (ARCR). The ARAU can auto index the current AR while
the data memory location is being addressed and can index either by ± 1 or by the
contents of the INDX. As a result, accessing data does not require the CALU for
address manipulation; therefore, the CALU is free for other operations in parallel.

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This makes the instructions to be executed faster compared to the conventional
microprocessors. For example, let us consider the following sequence of 8085
instructions:

M0V A, M
INX H

These instructions enable the accumulator to be loaded using indirect addressing

mode and HL register used as the address pointer is incremented. These two
instructions can be replaced by a single 5X instruction LACC *+, 0. Further, any one
of the auxiliary registers can be used as the address pointer and incremented by the
above instruction. The register that will be used is specified by the content of the
ARP. The auxiliary registers AR0-AR7 may also be used as the general purpose
registers for holding the operands for arithmetic and logical operations in CALU.
Some of the other registers of ARAU and their functions are as follows:

INDEX REGISTER (INDX)

The 16-bit INDX is used by the ARAU as a step value (addition or subtraction by
more than 1) to modify the address in the ARs during indirect addressing. For
example, when the ARAU steps across a row of a matrix, the indirect address is
incremented by 1. However, when the ARAU steps down a column, the address is
incremented by the dimension of the matrix. The ARAU can add or subtract the
value stored in the INDX from the current AR as part of the indirect address
operation. INDX can also map the dimension of the address block used for bit-
reversal addressing.

AUXILIARY REGISTER COMPARE REGISTER (ARCR)

The 16-bit ARCR is used for address boundary comparison. The CMPR instruction
compares the ARCR to the selected AR and places the result of the compare in the
TC bit of ST1.

BLOCK MOVE ADDRESS REGISTER (BMAR)

The 16-bit BMAR holds an address value to be used with block moves and
multiply/accumulate operations. This register provides the 16-bit address for an
indirect-addressed second operand.

BLOCK REPEAT REGISTERS (RPTC, BRCR, PASR, PAER)

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All these registers are 16-bit wide. Repeat counter register (RPTC) holds the repeat
count in a repeat single-instruction operation and is loaded by the RPT and RPTZ
instructions. Block repeat counter register (BRCR) holds the count value for the
block repeat feature. This value is loaded before a block repeat operation is initiated.
Block repeat program address start register (PASR) indicates the 16-bit address
where the repeated block of code starts. The block repeat program address end
register (PAER) indicates the 16-bit address where the repeated block of code ends.
The PASR and PAER are loaded by the RPTB instruction.

PARALLEL LOGIC UNIT (PLU)

It performs Boolean operations or the bit manipulations required of high-speed

controllers. The PLU can set, clear, test or toggle bits in a status register control
register, or any data memory location. The PLU allows logic operations to be
performed on data memory values directly without affecting the contents of the ACC
or PREG. Results of a PLU function are written back to the original data memory
location.

MEMORY-MAPPED REGISTERS

The C5X has 96 registers mapped into page 0 of the data memory space. All C5X
DSPs have 28 CPU registers and 16 input/output (I/O) port registers but have
different numbers of peripheral and reserved registers. Since the memory-mapped
registers are a component of the data memory space, they can be written to and read
from in the same way as any other data memory location. The memory- mapped
registers are used for indirect data address pointers, temporary storage, CPU status
and control, or integer arithmetic processing through the ARAU.

PROGRAM CONTROLLER

The program controller contains logic circuitry that decodes the instructions,
manages the CPU pipeline, stores the status of CPU operations and decodes the
conditional operations. Parallelism of architecture lets the C5X perform three
concurrent memory operations in any given machine cycle: fetch an instruction, read
an operand and write an operand. The program controller consists of the following
elements:
16-bit program counter (PC)
16-bit status registers ST0, ST1,
Processor mode status register (PMST)
Circular buffer control register (CBCR)

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(8 x 16)-bit hardware stack
Address generation logic
Instruction register
Interrupt flag register and interrupt mask register

STATUS REGISTERS (Status registers ST0 and ST1 and their description)
A status register is a 16 bit register which contains status and control bits like
carry, overflow(OV) and auxiliary register pointer(ARP) etc.
The status registers can be stored into data memory and loaded from data memory,
thereby allowing the C5X status to be saved and restored for subroutines.

The bit assignment details for ST0 are given in Fig. 2.2.

Fig. 2.2 Bit assignment details for ST0

Significance of the various bits of ST0 is as follows:

ARP (Auxiliary Register Pointer): These bits select the AR to be used in indirect
addressing. When the ARP is loaded, the previous ARP value is copied to the
auxiliary register buffer (ARB) in ST1.

OV (Overflow) flag bit:This bit indicates that an arithmetic operation overflow in

the ALU.

OVM (Overflow Mode) bit: This bit enables/disables the accumulator overflow
saturation mode in the ALU.

INTM (Interrupt Mode) bit. This bit globally masks or enables all interrupts. The
INTM bit has no effect on the non-maskable RS and NMI interrupts.

DP (Data Memory Page Pointer) bits: These bits specify the address of the current
data memory page. The DP bits are concatenated with the 7 LSBs of an instruction
word to form a direct memory address of 16 bits.

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The bit assignment details for ST1 are given in Fig. 2.3.

Fig. 2.3 Bit assignment details for ST1

Significance of the various bits of ST1 is as follows:

ARB(Auxiliary Register Buffer): This 3-bit field holds the previous value contained
in the ARP in ST0. Whenever the ARP is loaded, the previous ARP value is copied to
the ARB, except when using the LST #0 instruction. When the ARB is loaded using
the LST #1 instruction, the same value is also copied to the ARP. This is useful when
restoring context (when not using the automatic context save) in a subroutine that
modifies the current ARP.

CNF ( On-chip RAM configuration control bit): This 1-bit field enables the on- chip
dual-access RAM block 0 (DARAM B0) to be addressable in data memory space or
program memory space. The CNF bit can be modified by the LST #1 instruction. If
CNF is 0, the on-chip DARAM block 0 is mapped into data memory space. The
CNF bit can be cleared by a reset or the CLRC CNF instruction. When CNF is 1, the
on-chip DARAM block 0 is mapped into program memory space. The CNF bit can
be set by the SETC CNF instruction.

TC (Test/control flag bit): This 1-bit flag stores the results of the ALU or parallel
logic unit (PLU) test bit operations. The status of the TC bit determines if the
conditional branch, call and return instructions are to be executed.

SXM (Sign-extension mode bit): This 1-bit field enables/disables sign extension of
an arithmetic operation. The SXM bit does not affect the operations of certain
arithmetic or logical instructions; the ADDC, ADDS, SUBB or SUBS instruction
suppresses sign extension, regardless of SXM.

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Sign extension

Description

1. Sign extension is the operation, in computer arithmetic, of increasing the number of

bits of a binary number while preserving the number's sign and value.

2.This is done by appending digits to the most significant side of the number,
following a procedure dependent on the particular signed number representation
used.

Case 1. Sign Extended (SXM =1)

Example 1. If six bits are used to represent the number " 00 1010 " (decimal positive
10) and the sign extend operation (i.e. SXM =1) increases the word length to 16 bits,
then the new representation is simply " 0000 0000 0000 1010 ".

Example 2. If ten bits are used to represent the value “ 11 1111 0001” (decimal
negative 15) using 2’s complement, and this is sign extended (i.e. SXM =1) to 16 bits
, the new representation is “1111 1111 1111 0001”. Thus, by appending ones on left
side of the number, the negative sign and the value of the original number are
maintained.

Case 2. Sign Extension Suppressed(SXM =0)

When SXM=0, the sign bit of the number is not extended i.e. Zeros or ones are not
appended before the number.

Example 3. Given the number 1234h. If the number is left shifted by 3 bits, find the
32 bit representation of the number for a) SXM =0 b) SXM=1.
Solution:
a) Given number 1234h= 0001 0010 0011 01002
Left shift by 3 bits: 1 0010 0011 0100 0002
For SXM=0 no bits are to be appended: Hence the result is: 91A0h
b) For SXM=1 sign should be extended i.e. Ones are to be appended.
Hence the number is 1111 1111 1111 1111 1001 0001 1010 00002 = FFFF91A0h

C (Carry bit): This 1-bit field indicates an arithmetic operation carry or borrow in the
ALU. The single bit shift and rotate instructions affect the C bit.
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M (Hold mode bit): This 1-bit field determines whether the central processing unit
(CPU) stops or continues execution when acknowledging an active HOLD signal.

XF (pin status bit): This 1-bit field determines the level of the external flag (XF)
output pin.

PM (Product shift mode bits): This 2-bit field determines the product shifter (P-
SCALER) mode and shift value for the PREG output into the ALU. Table 3.2 gives
the PM bits and the function performed.

Table 3.2 PM bits and the function performed

ON-CHIP MEMORY (Memory organization of TMS320C5X)

The C5X architecture contains a considerable amount of on-chip memory to aid in

system performance.It has

Program Read-Only Memory ( Program ROM)

Data/Program Dual-Access RAM (DARAM)
Data/Program Single-Access RAM (SARAM)

The C5X has a total address range of 224K words x 16 bits. The memory space is
divided into four individually selectable memory segments: 64K-word program
memory space, 64K-word local data memory space, 64K-word I/O ports and 32K-
word global data memory space.

Program ROM

All C5X DSPs carry a 16-bit on-chip maskable programmable ROM (see Fig. 2.1
for sizes). Some of the C5X DSPs have boot loader code resident in the on-chip
ROM, and the other C5X DSPs offer the boot loader code as an option. This

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memory is used for booting program code from slower external ROM or EPROM to
fast on-chip or external RAM. Once the custom program has been booted into RAM,
the boot ROM space can be removed from program memory space by setting the
MP/ bit in the processor mode status register (PMST). The on-chip ROM is
selected at reset by driving the MP/ pin low. If the on-chip ROM is not selected,
the C5X devices start execution from off-chip memory.

Data/Program Dual-Access RAM

All C5X DSPs carry a 1056-word x 16-bit on-chip dual-access RAM (DARAM).
The DARAM is divided into three individually selectable memory blocks: 512-
word data or program DARAM block B0, 512-word data DARAM block B1 and 32-
word data DARAM block B2. The DARAM is primarily intended to store data
values but, when needed, can be used to store programs as well. DARAM blocks B1
and B2 are always configured as data memory; however. DARAM block B0 can be
configured by software as data or program memory. DARAM improves the
operational speed of the C5X CPU. The CPU operates with a 4-deep pipeline.
In this pipeline, the CPU reads data on the third stage and writes data on the fourth
stage. Hence, for a given instruction sequence, the second instruction could be
reading data at the same time the first instruction is writing data. The dual data buses
(DB and DAB) allow the CPU to read from and write to DARAM in the same
machine cycle.

Data/Program Single-Access RAM

Almost all C5X DSPs carry a 16-bit on-chip single-access RAM (SARAM) of sizes
varying from 1- 9K (16–bits) words. Code can be booted from an off-chip ROM and
then executed at full speed once it is loaded into the on-chip SARAM. The SARAM
can be configured by software as data memory, as program memory or combination
of both data memory and program memory. The SARAM is divided into 1K- and/or
2K-word blocks contiguous in address memory space. All C5X CPUs support
parallel accesses to these SARAM blocks. However, one SARAM block can be
accessed only once per machine cycle. In other words, the CPU can read from or
write to one SARAM block while accessing another SARAM block.

ASSEMBLY LANGUAGE SYNTAX (AL Syntax)

For programming in the assembly language, the C5X assembler assumes the
following assembly language syntax. A source statement can contain four ordered
fields. The general syntax for source statements is as follows:

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[label] [:] mnemonic [operand list] [;comment ]
[ e.g. Loop1: ADD #20h ; add 20h to accumulator]

They in turn follow these guidelines:

1. All statements must begin with a label, a blank, an asterisk or a semicolon.
2. Labels are optional; if used, they must begin in column 1.
3. Labels may be placed either before the instruction mnemonic on the same line or
on the preceding line in the first column.
4. One or more blanks must separate each field. Tab characters are equivalent to
blanks.
5.Comments are optional. Comments that begin in column 1 can begin with an
asterisk or a semicolon (* or ;), but comments that begin in any other column must
begin with a semicolon.

The following types of operands are permitted:

0 ≤ dma ≤ 127 dma: Data Memory Address
0 ≤ pma ≤ 65535 pma: Program Memory Address
0 ≤ shift ≤ 15
0 ≤ shift2 ≤7
0 ≤n ≤ 7 n: AR no.
0 ≤ k ≤ 255 k: Short Constant
0 ≤ lk ≤ 65535 lk: Long Constant

Operands can be constants or assembly-time expressions that refer to memory, I/O ports,
register addresses, pointers, shift counts and a variety of other constants.

ADDRESSING MODES

C5X supports the following six addressing modes:

1. Direct addressing
2. Memory-mapped register adressing
3. Indirect addressing
4. Immediate addressing
5.Dedicated-register addressing
6.Circular addressing
Description of each addressing mode is given below:

Direct addressing
The data memory used with C5X processors is splited into 512 pages each of 128 words
long. The data memory page pointer (DP) in ST0 holds the address of the

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current data memory page. In the direct addressing mode of C5X, only lower-order 7
bits of the address are specified in the instruction. The upper 9 bits are taken from
the DP as shown in Fig. 2.4.

Fig. 2.4 16 bit address computation using direct addressing

Example 2.1 Explain direct addressing mode of 5X. Explain execution of the
instruction ADDC 20h with address generation process if content of DP =06h and
content of data memory location 0320h to 032fh are 20h.Take the content of ACC as
30h.

Solution. Explanation of execution of the instruction ADDC 20h:

The content of data memory address (dma) and the value of carry bit C are added to
the contents of accumulator(ACC) with sign extension mode suppressed. The result
is stored in the ACC. The carry bit C is set if result of addition generates a carry
otherwise it is cleared.

Address generation process: DP = 06h , INST = 20h

dma address = 9 bits from DP and 7 bits from Instruction

dma address = ( 0 0000 0110)2 ( 010 0000)2

9 bits of DP 7 bits of Inst.

Hence dma address is ( 0000 0011 0010 0000)2 = 0320h
Result of addition:
Hence, contents of dma 0320h ( i.e. 20h) is to be added to the contents accumulator
(i.e. 30h). The result of addition is 50h (assuming C = 0) and it is stoed in the
accumulator.

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Memory-mapped register addressing

The RAM area in page 0 is used for storing some of the registers, interrupt vector
addresses and so on. These locations can be accessed by specifying the actual
address or by the register name, (e.g., the AR0 can either be denoted by the actual
memory location (10h) used for storing its value or by the symbol AR0). Since these
memory locations can be interchangeably used with the register names, the registers
corresponding to page 0 are referred to as memory-mapped registers (MMRs). With
memory-mapped register addressing, the MMRs can be modified without affecting
the current data page pointer value. The memory- mapped register addressing mode
operates like the direct addressing mode, except that the 9 MSBs of the address are
forced to 0 instead of being loaded with the contents of the DP. This allows the
memory-mapped registers of data page 0 to be modified directly without the
overhead of changing the DP or auxiliary register. The following instructions operate
in the memory mapped register addressing mode. These instructions does not affect
the contents of the DP:

LAMM—Load accumulator with memory-mapped register

LMMR—Load memory-mapped register
SAMM—Store accumulator in memory-mapped register
SMMR—Store memory-mapped register

Example 2.2. The instruction LMMR AR0, #1500h loads AR0 with the content of
the location 1500h as shown in Fig. 2.5. Let the content of AR0 and the data
memory location 1500h be 2345h and 6789h, respectively, before executing the
instruction. After executing the instruction their contents become 6789h and 6789h.

Solution: Execution of LMMR AR0, #1500h instruction

Before execution After execution

Fig. 2.5

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Example 2.3 Let the content of AR0 and the data memory location be 2345h and
6789h, respectively, before executing the instruction SMMR AR0, # 1500h. After
executing the instruction their contents become 2345h and 2345h as shown in Fig.
2.6.

Solution: Execution of SMMR AR0, #1500h instruction

Before execution After execution

Fig.2.6
The SMMR does the reverse operation.

Indirect addressing

The ARs (AR0-AR7) are used for accessing data, using indirect addressing mode.
Out of the eight ARs the one which is currently used for accessing data is denoted by
the register ARP. The indirect addressing mode of C5X permits the AR used for the
addressing to be updated automatically either after or before the operand is fetched.
Hence a separate instruction is not required to update the AR. The manner in which
the memory address is computed and the manner in which the AR is altered after the
instruction depends on the instruction. This is indicated to the assembler by the
symbols *, *+, *–,*0+, *0–, *BR0+ and *BR0–. The symbol used to indicate the
indirect addressing mode and the action taken after executing the instruction are
given in Table 2.1.

Table 2.1 Various options in the indirect addressing mode of 5X

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Symbol Value of AR pointed by ARP after instruction execution
* AR unaltered
*+ AR incremented by 1
*- AR decremented by 1
*0+ AR incremented by the content of INDX
*0- AR decremented by the content of INDX
*BR0+ AR incremented by the content of INDX with reverse carry propagation
*BR0_ AR decremented by the content of INDX with reverse carry propagation

Example 2.4 Let the value of ARP, AR2 and INDX register be 2, 1250h and 2h,
respectively, and the content of the data memory location 1240h–1260h be filled
with the data 2345h. Let SXM be0. The value of ACC and AR2 after the following
sequence of LACC (load accumulator with shift) instructions are executed is shown
in Fig. 2.7.

LACC *, 0
LACC *+, 1
LACC *–, 2
LACC *0+, 4
LACC *0–, 3
Solution:

Instruction executed Contents of ACC and AR2 after execution

LACC *, 0 ACC 2345h AR2 1250h

LACC *+, 1 ACC 468Ah AR2 1251h

LACC *–, 2 ACC 8D14h AR2 1250h

LACC *0+, 4 ACC 3450h AR2 1252h

LACC *0–, 3 ACC 1A28h 1250h

AR2

Fig. 2.7

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Immediate addressing

In immediate addressing, the instruction word(s) contains the value of the immediate
operand. The C5X has both 1-word (8-bit, 9-bit and 13-bit constant) short immediate
instructions and 2-word (16-bit constant) long immediate instructions. This mode is
indicated by the symbol #.
Examples:
i)Short immediate instructions
e. g. ADD #567h ( adds 56h to ACC)
ii)Long immediate instructions
e. g. ADD # 4567h ( adds 4567h to ACC)

Dedicated-register addressing

The dedicated-registered addressing mode operates like the long immediate addressing
mode, except that the address comes from one of two special-purpose memory-mapped
registers in the CPU:
The block move address register (BMAR)
The dynamic bit manipulation register (DBMR)

The advantage of this addressing mode is that the address of the block of memory to be
acted upon can be changed during execution of the program.

Example 2.5 Let the content o f ARP, AR2 be 2 ,1250h respectively and the content of
data memory location( dma) 1249h-1250 be filled with data 2345h.Let SXM be
0. Find the values of ACC , AR2 and ARP after the execution of ADD *,2
instruction.

Solution: Explanation of execution of the instruction ADD *, 2:

This instruction uses indirect addressing mode. The content of dma pointed by the ARP
( here it is AR2) is added to the content of ACC. But before addition, the content must be
left shifted by 2 bits. The content of ARP and AR2 remain same after execution of the
instruction.

Content of AR2 = address of dma =1250h

Hence content of 1250h (i.e. 2345h) is to added to ACC.
Content of dma 1250h in binary = (0010 0011 0100 0101)2
Content of dma 1250h in binary with left of 2 bits = (1000 1101 0001 0100)2
Content of dma 1250h in hex = 8D14h
Hence addition of 8D14h and 0h( assuming initial content of ACC as 0) will be 8D14h
and it is stored in the ACC.
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Hence the values of ACC , AR2 and ARP after the execution of ADD *,2
instruction are:
ACC= 8D14h
AR2= 1250h
ARP=2

Example 2.6 Explain the following instructions:

i) LMMR AR0, 1500h (Correct instruction is LMMR AR0, #1500h)

ii)SMMR AR0, 1500h Correct instruction is SMMR AR0, #1500h)

Solution: See examples 2.2 and 2.3

Example 2.7 Explain the operations performed when the TMS320C5X issues the
following instructions
i) ADDC 20h ( see example 2.1)
ii) SMMR AR0, #1800( see example 2.6)
iii) BLDP 00h: Block move from data memory to program memory

The contents of the data memory address (dma) are copied to the program memory
address(pma) pointed by the block move address register (BMAR).The source and
destination blocks do not have to be entirely on-chip or off-chip.
Circular Addressing Mode ( Refer Ch. No. 4 Avtar Singh)

The provision of a circular buffer allows one to handle a continuous stream of

incoming data samples. In a circular buffer, successive data samples are stored in
sequential buffer locations until the end of the buffer is reached. After reaching the
end we start all over from the beginning of the buffer. This process can go on
forever as long as the data samples get processed in a timely manner at a rate faster
than the incoming data. To access a data sample from a circular buffer, a circular
addressing mode is of great help. The implementation of such an addressing mode
in hardware requires three registers: a pointer register (PNTR) to keep track of
current address, a start address register (SAR) to hold the start address of the buffer,
and an end address register (EAR) to hold the end address of the buffer. The pointer
register should have the capability of getting incremented/decremented. Different
forms of the indirect addressing mode for the pointer register are required in order
to update the pointer for different applications. The pointer updating algorithm is
given in Figure 2.8. The different cases that are encountered during the updating
process of the pointer are given below.
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 These cases are:

1. SAR < EAR, and updated PNTR > EAR

2. SAR < EAR, and updated PNTR < SAR
3. SAR > EAR, and updated PNTR > SAR
4. SAR > EAR, and updated PNTR < EAR

The buffer size in the first two cases = (EAR - SAR + 1) and in the last two it is
= (SAR - EAR + 1).

Pointer Updating Algorithm for the Circular Addressing Mode

Updated PNTR ← PNTR ± increment

If SAR < EAR

and if Updated PNTR >EAR, then

New PNTR ←Updated PNTR - Buffer size

and if Updated PNTR < SAR, then

New PNTR ← Updated PNTR + Buffer size

If SAR > EAR

and if Updated PNTR> SAR then

New PNTR ← Updated PNTR - Buffer size

and if Updated PNTR < EAR, then

New PNTR ← Updated PNTR + Buffer size

Else

New PNTR ← Updated PNTR

Figure 2.8 Register pointer updating algorithm for circular buffer addressing
mode. SAR = start address register contents, EAR = end address register
contents, PNTR = pointer
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 Low address

SAR

New PNTR

Equal
EAR

Updated PNTR

High address

Figure 2.9a) Case 1: SAR < EAR , and Updated PNTR > EAR

Low address

Updated PNTR

SAR

Equal

New PNTR

EAR

High address

Figure 2.9b) Case 2: SAR < EAR , and Updated PNTR < SAR

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 Low address

EAR

New PNTR

Equal
SAR

Updated PNTR

High address

Figure 2.9c) SAR > EAR , and Updated PNTR > SAR

Low address

Updated PNTR

EAR

Equal

New PNTR

SAR

High address

Figure 2.9d) SAR > EAR , and Updated PNTR < EAR

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Example 2.8 A DSP has a circular buffer with the start and the end addresses as 0200h
and 020Fh, respectively. What would be the new values of the address pointer of the
buffer if, in the course of address computation, it gets updated to (a) 0212h, (b) 0lFCh?

Solution: The buffer length = 020Fh - 0200h + 1 = 10h

a. The new value of the pointer is updated value - buffer length, i.e., 0212h- 0010h
0202h.
b. The new value of the pointer is updated value + buffer length, i.e. 0lFCh + 0010h =
020Ch.

Example 2.9 Repeat the problem of Example 2.8 if the start and end addresses of the
circular buffer are 0210h and 0201h, respectively.

Solution:
a. The new value of the pointer is the updated value - buffer length, i.e., 0212h - 0010h
=0202h.

b. The new value of the ,pointer is the updated value +buffer length, i.e., 0lFCh + 0010h
= 020Ch.

Note that these values are the same as those in the previous example. This shows that in
a circular buffer, the address pointer wraps around to point to an address inside the
buffer, irrespective of whether the buffer start address is higher or the end address is
higher.

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