18 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO.
1, JANUARY 2010
Analysis and Design of Voltage-Controlled Oscillator
Based Analog-to-Digital Converter
Jaewook Kim, Student Member, IEEE, Tae-Kwang Jang, Student Member, IEEE,
Young-Gyu Yoon, Student Member, IEEE, and SeongHwan Cho, Member, IEEE
Abstract—A voltage-controlled oscillator (VCO) based
analog-to-digital converter (ADC) is a time-based architecture
with a first-order noise-shaping property, which can be imple-
mented using a VCO and digital circuits. This paper analyzes the
performance of VCO-based ADCs in the presence of nonidealities
such as jitter, nonlinearity, mismatch, and the metastability of D
flip-flops. Based on this analysis, design criteria for determining
parameters for VCO-based ADCs are described. In addition, a
digital calibration technique to enhance the spurious-free dynamic
range degraded by the nonlinearity is also introduced. To verify
m
the theoretical analysis, a prototype chip is implemented in a
0.13- CMOS process. With a 500-MHz sampling frequency,
the prototype achieves a signal-to-noise ratio ranging from 71.8
mm
to 21.3 dB for an input bandwidth of 100 kHz–247 MHz, while
dissipating 12.6 mW and occupying an area of 0.078 2.
Index Terms—Analog to digital, analog-to-digital converter
(ADC), analysis, data converter, design, digital calibration, fre-
quency delta–sigma modulator, nonidealities, reconfigurable, time
based, voltage-controlled oscillator (VCO) quantizer, VCO based.
I. INTRODUCTION
N DEEP-SUBMICROMETER processes, the design of an
I analog-to-digital converter (ADC) based on voltage-do-
main signal processing is becoming more difficult due to the
low supply voltage that comes along with technology scaling.
However, for time-based architectures, time resolution is im-
proved from the reduced transition time of digital signals,
which is on the order of tens of picoseconds for 130-nm CMOS
processes and below [1].
An ADC based on a voltage-controlled oscillator (VCO) gen-
erates a time-based signal whose frequency is proportional to
the analog input. The frequency is then quantized by counting
the edges of the VCO output during a sampling period [2].
Since the VCO produces a continuous phase output, the quan-
tization noise of the previous sample affects that of the current
sample, and hence, an inherent first-order quantization noise-
shaping property can be achieved. However, unlike conventional
Manuscript received September 23, 2008; revised January 23, 2009.
First published March 24, 2009; current version published January 08,
2010. This work was supported by the Korean Government (MEST) under
the Korea Science and Engineering Foundation (KOSEF) under Grant
R01-2008-000-11892-0. This paper was recommended by Associate Editor S.
Pavan.
J. Kim and S. Cho are with the Department of Electrical Engineering and
Computer Science, Korea Advanced Institute of Science and Technology
(KAIST), Daejeon 305-701, Korea (e-mail: jaeuk83@gmail.com).
T. Jang is with Samsung Electronics Company Ltd., Giheung 449-711, Korea.
Y.-G. Yoon is with the Medical System Research Group, KAIST Institute,
Daejeon 305-701, Korea.
Digital Object Identifier 10.1109/TCSI.2009.2018928
1549-8328/$26.00 © 2010 IEEE
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delta–sigma ADCs that require complex analog building blocks
such as op-amps and digital-to-analog converters (DACs), the
VCO-based ADC can be implemented using only a VCO and
digital circuits. Since the operating frequency is limited by the
speed of the logic gates, it could easily reach up to gigasamples
per second in advanced CMOS processes.
Due to these attractive properties, there has recently been
some research on the VCO-based ADC. In [3], an energy-effi-
cient VCO-based architecture operating in the subthreshold re-
gion was implemented. In [4], a high-resolution and low-speed
Nyquist-rate ADC is realized for sensor application. In [5] and
[6], a third-order noise-shaping ADC is realized by employing
a feedback loop using two current DACs and an op-amp. In
[7], a time-based bandpass ADC is realized by time-interleaving
VCO-based ADCs. While these works have demonstrated the
potential of the VCO-based ADC, there has not been a thor-
ough analysis of its performance, which includes the effects
of nonidealities. In terms of performance, an open-loop VCO-
based ADC whose sampling frequency is over a few hundreds
of megasamples per second has not yet been reported.
In this paper, nonidealities of the VCO-based ADC are the-
oretically analyzed and verified in a prototype integrated cir-
cuit (IC) with a sampling frequency of 500 MHz using 0.13-
CMOS technology. From this analysis, the design criteria for
determining the sampling frequency and the number of VCO
delay cells is described. In addition, a digital calibration method
to enhance the spurious-free dynamic range (SFDR) is intro-
duced. This paper is organized as follows. In Section II, the op-
eration principle and the properties of the VCO-based ADC are
presented. Section III describes the effect of nonidealities, and
Section IV presents the design considerations for quantizers and
the digital calibration technique for VCO nonlinearity. Mea-
surement results are then presented in Section V, and conclu-
sions are drawn in Section VI.
II. VCO-BASED ADC
The basic architecture of a VCO-based ADC is shown in
Fig. 1. In previous works, this VCO–counter architecture
has been called a VCO–quantizer [5], [8], [9] or a frequency
delta–sigma modulator [3], [10]. In this paper, we will use
the term VCO–quantizer or VCO-based ADC to represent a
VCO–counter architecture. The VCO converts the analog input
signal from voltage domain to phase domain and generates
an output signal whose frequency is proportional to the average
analog input signal . The reset counter counts the edges of
the multiphase VCO outputs during a sampling clock period
and produces the digital output. Note that a sample-and-hold
(S/H) is absent in our analysis, which is in contrast to previous
analyses that assume S/H before the VCO [5], [8]. In addition,
KIM et al.: ANALYSIS AND DESIGN OF VCO-BASED ADC 19

Fig. 1. Block diagram of the VCO-based ADC including decimation filter.

CLKs represents sampling clock.

our analysis is generalized with a multiphase VCO rather than

a single-phase VCO. The signal waveform of a VCO–quantizer Fig. 2. Operation principle and waveforms of the VCO–quantizer.
is shown in Fig. 2, where the VCO has a differential output and
two counters count the rising edges of each output. Note that
the quantizer resolution will increase if multiple output phases For a general multiphase VCO with outputs, the counter
are available from the VCO. Since the residual phase (i.e., quantizes the VCO phase by . As shown in Fig. 2, quan-
quantization error ) of the previous sampling period tization error depends on the position of the sampling clock edge
inherently becomes the initial phase of the next period, in a VCO period. Since there is no correlation between the sam-
the output of the VCO–quantizer can be represented as pling clock and the VCO, quantization error can be assumed to
be random and uniformly distributed from 0 to . Hence,
(1) the quantization error power in the phase domain can be ob-
tained as follows, using a similar method to that of a conven-
where is the number of the VCO phase and is the tional first-order delta–sigma ADCs [11]:
VCO phase change due to the analog input. Taking the -trans-
form of (1) gives (6)

(2) where , represents the sampling frequency,

and represents the input frequency. From (5) and (6), the
theoretical SQNR can be calculated as follows:
It can be seen that the quantization error of the VCO–quan-
tizer is first-order shaped and, hence, is equivalent to a first-order
delta–sigma modulator. To obtain the signal-to-quantization
noise ratio (SQNR), is assumed to be a sinusoidal (7)
signal with an amplitude of and frequency of [i.e.,
]. The phase-domain input signal can where is the quantizer resolution, which can be represented
be described as as

(8)

where is the tuning range of the VCO .

(3) Note that the SQNR of the VCO–quantizer is different from the
conventional delta–sigma modulator in that the quantizer reso-
where lution is inversely proportional to the sampling frequency.
(4) By plugging (8) to (7), it can be seen that SQNR is enhanced by
10 dB/decade as the sampling frequency is increased. Another
where is the sampling period and and are the free- interesting property that cannot be seen from the prior analyses
running frequency and gain of the VCO, respectively. It can be [5], [8] is that SQNR is decreased with input-signal frequency
seen that the input-signal amplitude in the phase domain is a due to the absence of an S/H, i.e., the averaging nature of the
sinc function of the input frequency, where is defined as VCO results in the last term in (7) which has a low-pass filtering
. Hence, the input-signal power in the phase domain property with nulls at integer multiples of the sampling fre-
can be represented as quency. Hence, when the VCO–quantizer is operated at Nyquist
rate, the SQNR is reduced by 3 dB and signals near the integer
(5) multiples of are inherently filtered out.

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20 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 1, JANUARY 2010

where “ ” represents . Assuming that

is much smaller than the sampling period, and
can be approximated as the following:

(11)

(12)

Assuming that , the autocorrelation of

Fig. 3. Timing diagram of sampling clocks with and without jitter.  [n] and can be expressed as [14], [15]
 [n] represent absolute and period jitters of the nth sampling clock edge, re-
spectively.

III. NONIDEAL EFFECTS

Nonidealities such as jitter, nonlinearity, mismatch of the (13)
VCO, and metastability of D flip-flops (DFFs) degrade or limit
the performance of the VCO-based ADC. In this section, the where represents the autocorrelation of . It can be
effect of these nonidealities will be analyzed and simulated in seen that the power spectral density. (PSD) of , which is the
MATLAB and CppSim [12], which is a behavioral simulator Fourier transform of , is upconverted to the input fre-
that accurately models the phase noise and jitter of oscillators. quency at . Hence, a skirt around is expected in the output
Throughout the simulation, it is assumed that there is a 64-phase spectrum of the ADC. In order to consider a general case of ab-
ring VCO with a tuning range of 50–450 MHz and that the solute-jitter PSD, the total noise power of is obtained, and
sampling frequency is 500 MHz unless otherwise noted. a lower bound of the signal-to-noise ratio (SNR) is calculated.
The total noise power of the sampling-clock uncertainty can be
A. Sampling Clock Jitter obtained as
The sampling clock in the VCO-based ADC is not only used
for sampling the input signal but is also used as a time reference (14)
for integration. Hence, the effect of sampling clock jitter can be
divided into two parts: the sampling uncertainty caused by the
absolute jitter (i.e., aperture jitter) and the error in the integration (15)
time caused by the period jitter.
To analyze these effects, sampling clocks with and without
jitter are shown in Fig. 3 together with the input signal . where is the variance of the absolute jitter. Using the input-
In this analysis, absolute jitter is defined as the time dif- signal power of (5), the lower bound of can be obtained
ference between the th edge of an ideal and a practical sam- as follows:
pling clock. Period jitter is defined as the time difference
between the th period of an ideal and a practical clock [13]. (16)
The phase-domain input signal with sampling jitter can be rep-
resented as It can be seen that the effect of the absolute jitter on the
VCO-based ADC is the same as the conventional voltage-based
ADC. This result is quite natural, since the SNR degradation
(9) should not depend on how the error due to sampling uncertainty
is processed, whether in voltage or time domain.
By obtaining the autocorrelation of and taking the
discrete-time Fourier transform, the PSD due to integration-time
This equation can be decomposed into the ideal phase-do- error can be obtained as
main input signal , the phase error due to sampling un-
certainty , and the phase error due to integration time (17)
, which can be described as follows:

where represents the PSD of . It can be seen

that is equal to scaled by the tuning range
and the free-running frequency of the VCO. The lower bound
of the SNR can be obtained by calculating the total noise power
of , which can be expressed as

(10)
(18)

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KIM et al.: ANALYSIS AND DESIGN OF VCO-BASED ADC 21

Fig. 4. FFT result of the VCO-based ADC in CppSim simulation without and
with sampling jitter.

Fig. 5. FFT result of the VCO-based ADC in CppSim simulation with sam-
Hence, is obtained as pling jitter. (a) Sampling uncertainty is dominant. (b) Integration-time error is
dominant.

(19) B. VCO Phase Noise

Similar to the previous analysis, the effect of the VCO phase
noise on the phase domain input can be described by the fol-
Intuitively, the first term is natural since the period lowing:
jitter can be considered as the integration-time error. The sinc
function represents the effect of integration sampling on the
input signal. The last term shows up since a
VCO with high free-running frequency will have a larger phase
error than a VCO with low free-running frequency for the same
period jitter and tuning range. Hence, to minimize the effect of
period jitter, free running frequency should be reduced.
To verify the aforementioned theoretical analysis, CppSim
simulation is performed when the input frequency is 10 MHz. (20)
The fast-Fourier-transform (FFT) result of VCO-based ADC
with and without sampling jitter is shown in Fig. 4. As ex- where is the input referred noise of the VCO and is
pected, the skirt centered around the input frequency is shown the output phase noise of the VCO. Taking the -transform of
due to the sampling uncertainty, and the noise floor is raised at the aforementioned gives
low frequencies due to both the sampling uncertainty and in-
(21)
tegration-time error. Unfortunately, the effects of sampling un-
certainty and integration time cannot be easily distinguished in The noise power can be expressed as
this simulation, and the SNR described in (16) and (19) cannot
be confirmed. Hence, two different simulations are performed
under the conditions that exclude the effect of each other. First,
the number of VCO multiphases is increased to 1024 in order
to remove the effect of quantization noise. To make the effect of
sampling uncertainty dominant, the input frequency is increased
to 200 MHz. The FFT result is shown in Fig. 5(a) where the
rms absolute jitter is 68.1 ps and the resulting SNR is 22.2 dB.
This is very close to the theoretical value of 21.34 dB obtained
from (16). To make the effect of integration-time error domi- (22)
nant, input frequency is reduced to 1 MHz, and the free-running
frequency of the VCO is increased to 5 GHz. The FFT result is
shown in Fig. 5(b), where the rms period jitter is 1.98 ps and the where is the continuous-time PSD of the VCO phase noise.
resulting SNR is 29.6 dB. This is very close to the theoretical It can be seen that the phase noise of the VCO is first aliased due
value of 30.0 dB obtained from (19). to sampling and then shaped by the high-pass filter . If

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22 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 1, JANUARY 2010

Fig. 6. SNR versus VCO phase noise. The x-axis represents the phase noise
of a single-phase VCO that can be run in CppSim. This phase noise can be
converted to the phase noise of a multiphase VCO by subtracting 10 log N . Fig. 7. FFT result of the VCO-based ADC in CppSim simulation without and
For example, a 64-phase VCO with a tuning range of 400 MHz and a phase
0
noise of 120 dBc/Hz at a 1-MHz offset corresponds to a single-phase VCO
with VCO phase noise.
2 0
with a tuning range of 64 400 MHz and a phase noise of 60 dBc at 1 MHz.

C. Nonlinearity of VCO Tuning Characteristic

we assume that the VCO has a phase noise of L at a frequency
offset of and a slope of 20 dB/decade, then in When the VCO has a nonlinearity in its tuning curve, har-
continuous-time–frequency domain can be expressed as monic spurs are generated similar to a general voltage-based
ADC with nonlinearity. However, there is a difference in how
L the spurs show up, due to the absence of S/H in the VCO-
(23) based ADC, i.e., the harmonic spurs are sinc filtered just like
the signal. The input phase change due to the nonlinearity of
Applying (23) to (22), can be described as follows: the VCO can be represented as

L
(24)
(26)

Therefore, the SNR due to the VCO phase noise The power of the second-harmonic and third-harmonic (HD3)
can be obtained as the following: spurs can be obtained by the following:

(25)
L

where is the input-signal frequency. To verify the aforemen-

tioned theoretical analysis, the SNR due to the VCO phase noise
is obtained using CppSim when the VCO has a phase noise of
80 to 40 dBc at a 1-MHz offset. The SNR versus VCO phase
noise is shown in Fig. 6 with the theoretical result from (25),
where it can be seen that the theoretical-analysis result is about
2 dB higher than the simulation result. In Fig. 7, the FFT result
with the VCO phase noise of 60 dBc/Hz at a 1-MHz offset
is shown along with that using an ideal VCO. It can be seen
that the white noise from the VCO phase noise is added to the
first-order shaped quantization noise. Notice that the FFT plot
does not have a skirt around the input signal, which is in contrast
to the case of the sampling clock.
(27)
where it can be seen that the th harmonic spur is filtered by
nulls at integer multiples of . Note that, due to such filtering,
the intermodulation product can be much larger than the har-
monic spurs. An example is shown in Fig. 8 where the sampling
frequency is 600 MHz and the two-tone inputs are at 198 and
202 MHz. It can be seen that the power of the HD3 at 6 MHz
is 26 dB smaller than that of the the third intermodulation prod-
ucts (IM3s) at 194 and 206 MHz. In general, HD3 is 10 dB lower
than IM3 [16] but sinc filtering further reduces the power of the
HD3 by 16 dB.

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KIM et al.: ANALYSIS AND DESIGN OF VCO-BASED ADC 23

Fig. 10. (a) PSD of phase error due to the VCO mismatch ( (t)). PSD
(b) when  (t) is sampled by sampling clock and (c) when  (t) is
Fig. 8. FFT result of a two-tone test. Sampling frequency is 600 MHz, and the sampled and first-order noise shaped.
inputs are at 198 and 202 MHz.

When the analog input is not dc, the periods of the VCO and
are changed. In this analysis, to get an insight in the
PSD, both and the analog input ) are as-
sumed to be sinusoidal signals. Then, can be described
as

(29)

where is the amplitude of . The function

is periodic with frequency and,
hence, can be expanded in a Fourier series that can be described
Fig. 9. Three-stage ring VCO and effect of VCO mismatch in phase diagram. as

(30)
D. Mismatch of VCO Delay Cells where
The mismatch of the VCO delay cells (VCO mismatch) (31)
causes error in their propagation delay and adds the deter-
ministic phase error to the phase-domain input signal. A and is the Bessel function of the first kind of order and
multiphase ring VCO with mismatch is shown in Fig. 9, where argument [17]. Applying (30) to (29) and taking the real part
the analog input is constant and the rising and falling edges of gives
the delay-cell outputs are represented by upward and downward
arrows, respectively. It can be seen that, when the VCO has
(32)
a mismatch, the phase error is a periodic signal
whose period is half the VCO period because of the inherent
cycling structure of the ring oscillator. In the VCO–quantizer, where it can be seen that spurs are generated at twice the free-
the phase error sampled at the sampling clock edge running frequency and an infinite number of sidebands are sep-
is included as the quantization error, as shown in Fig. 9. Hence, arated from the by integer multiples of . The PSD of (32)
the output of the VCO–quantizer with the VCO mismatch can be obtained as follows and is shown in Fig. 10(a):
can be represented as

(28) (33)

where is the quantization error when the VCO is ideal.

It can be seen that the phase error due to the VCO mismatch is Since the phase error due to the VCO mismatch is sampled
sampled and then first-order noise shaped. and first-order noise shaped in the VCO–quantizer, as shown

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24 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 1, JANUARY 2010

in Fig. 10(b) and (c), the noise power can be expressed as the
following:

(34)

Therefore, the SNR due to the VCO mismatch can be ob-

tained as follows:

(35)

Although this analysis restricts the periodic phase error due

to the VCO mismatch to a sinusoidal signal, it provides useful
insights. From (33) and (34), it can be seen that should
be reduced in order to reduce the noise power due to mismatch.
Since is proportional to the number of VCO delay cells,
a small number of VCO delay cells is required, which means that Fig. 11. FFT result of VCO-based ADC and its magnified view in MATLAB
VCO operates at high speed. Another way to reduce the effect simulation with 3% VCO mismatch.
of the VCO mismatch is to control the free-running frequency.
It can be seen from (33) that spurs due to the VCO mismatch
are generated around the free-running frequency. Hence, spurs
can be removed if the free-running frequency is moved far away
from the desired frequency.
To verify aforementioned theoretical analysis, a MATLAB
simulation was performed as follows: A 514-phase ring VCO
has a tuning range of 6–55 MHz, the mismatch of VCO delay
cells is 3%, and the analog input frequency and sampling fre-
quency are 10 and 500 MHz, respectively. The FFT result and its
magnified view are shown in Fig. 11. Since the VCO free-run-
ning frequency is 30.5 MHz, dominant spurs are generated at
twice the free-running frequency of the VCO, at 61 MHz, and
the sidebands are separated by 10 MHz. Note that sideband
spurs are symmetrical around 61 MHz and low-frequency side-
bands are smaller than high-frequency sidebands due to the first-
order noise shaping. In Fig. 12, two FFT results with different
free-running frequencies are shown: 31 MHz for (a) and 87.5
MHz for (b). It can be seen that a VCO with higher free-run-
ning frequency moves the spurs in the desired bandwidth to high
frequencies. However, as described in Section III-A, the high
free-running frequency of the VCO increases the noise power
due to the period jitter of the sampling clock. Therefore, tradeoff Fig. 12. FFT result of VCO-based ADC in MATLAB simulation with 3% VCO
between the effect of sampling jitter and VCO mismatch exists. mismatch when free-running frequency is (a) 31 and (b) 87.5 MHz.

E. Metastability of DFF where is the ideal counter output captured by the first
DFF, is the error of the DFF due to metastability, and
The reset counter of the VCO–quantizer shown in Fig. 1 is is defined in (1). It can be seen that is also first-order
usually implemented by using DFFs and a subtractor, as shown shaped, similar to the error due to the quantization error. In this
in Fig. 13 [6]. The output of the counter is captured by the first analysis, we assume that occurs only at the LSB of the
DFF at every rising (or falling) edge of the sampling clock, counter output. Although it is possible that error occurs at other
which is then delayed by the second DFF before subtraction. bits, it will be shown in the next section that these errors can be
When the output of the counter is not stable at the sampling removed.
clock edges, an error may occur in the first DFF due to metasta- To observe and the corresponding SNR, we consider a
bility. The output of the VCO–quantizer that includes scenario where the VCO edges lie within the metastable window
the error from metastability can be described as the following: of the DFF, as shown in Fig. 13. We assume that the
metastable window is evenly split before and after the sam-
pling clock. When the output of the counter changes during the
(36) metastability window , the captured output of the DFF can

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KIM et al.: ANALYSIS AND DESIGN OF VCO-BASED ADC 25

Fig. 14. Block diagram of reset counter for multibit quantization. Second DFF
and subtractor are omitted.

The aforementioned analysis assumes that the error is uni-

formly distributed. However, in practical situations, errors have
a biased distribution rather than a uniform distribution, in which
Fig. 13. Effect of DFF metastability in timing diagram. case metastability may manifest itself as VCO mismatch and in-
troduces spurs.

be more or less than the ideal output. In general, de- IV. DESIGN OF VCO-BASED ADC
scribes the number of VCO edges during the metastable window
In this section, implementation issues regarding the number
that is incorrectly over- or undercounted. If we assume that the
of the delay cells and the digital calibration method for VCO
VCO has phases, can be expressed as the following:
nonlinearity will be described.

A. Multibit Quantization Versus 1-bit Quantization

When designing the VCO, one can either maximize the tuning
(37) range and reduce the number of phases or maximize the number
of phases and reduce the tuning range. For a given process, the
where means to round up and is the VCO period. minimum time resolution is fixed, and the ADC’s performance
Assuming that is uniformly distributed, the variance of is the same for both cases. However, when nonidealities such as
can be calculated as mismatch and metastability are considered, their performance
will be different. When the maximum output frequency of the
VCO is higher than the sampling frequency, the number of edges
(38)
during a sampling period can be more than one, thus requiring
a multibit quantizer. This is called a multibit quantization, as
To obtain the total noise power due to the metastability of opposed to a 1-bit quantization, where the output frequency of
DFF , the average of should be obtained because the VCO is always lower than the sampling frequency. Ideally,
it depends on the analog input signal and hence changes every the performance of the VCO-based ADCs that use either one
sampling period of these techniques are the same, but nonidealities such as the
metastability of DFF and the VCO mismatch cause differences.
(39) As described in Section III, the DFF that stores the counter
output at the sampling instance can cause errors because of
Since the error of DFF due to metastability is first-order metastability. Considering only one phase among the multi-
shaped, the noise power in the phase domain can be obtained phase VCO outputs, the maximum error due to metastability in
as follows: 1-bit quantization is just one. However, that of the multibit quan-
tization is more, and it can severely degrade the performance of
(40) the VCO-based ADC. Assuming that the metastability window
is narrower than the propagation delay of the VCO, the afore-
mentioned problem of a multibit quantizer can be solved by
Therefore, the theoretical limit of the SNR due to DFF
comparing the counter output of the neighborhood multiphase
metastability can be obtained as the following:
and replacing it when the difference is more than 1, as shown in
Fig. 14. Using this architecture, the maximum error of multibit
(41) quantization can be 1 bit, but the complexity and the power dis-
sipation of the reset counter are increased due to the comparator
For example, when the input bandwidth is 5 MHz and and multiplexer. On the other hand, 1-bit quantization can be re-
is 500 ps, the maximum theoretical SNR is 59.04 dB. This was alized with two DFFs and an XOR, as shown in Fig. 15. While it
verified using a MATLAB simulation whose SNR was 60.26 dB. achieves simple implementation for the reset counter, too many

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26 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 1, JANUARY 2010
Fig. 15. Block diagram of reset counter for 1-bit quantization.
Fig. 16. Basic concept and block diagram of digital calibration for VCO non-
linearity.
delay cells in the VCO can cause spurs from the mismatch of
the delay cells, as described in Section III.
B. Digital Calibration of VCO Nonlinearity
As described in Section III, the nonlinearity of the VCO
tuning characteristic generates harmonic spurs and degrades
the SNDR. The effect of nonlinearity is particularly more
severe when the input frequency is low, as the reduced SFDR
degrades the SNDR gained from oversampled noise shaping. In
order to improve the resolution, a calibration technique can be
employed, as shown in Fig. 16. When the ADC is in calibration
mode, a ramp signal is applied to the VCO–quantizer. In terms
of implementation, the ramp signal can be realized using a
digital 1-bit accumulator and a DAC or a resistive divider and
a switch. Note that the linearity of the DAC or the resistive
divider should be better than that of the VCO–quantizer. Next,
the digital output of the VCO–quantizer goes through
a moving average filter (MAF) that reduces the quantization
noise. The output of the MAF can be represented as
(42)
where is the width of the moving average window. In prac-
tical implementation, the MAF can be realized using a simple
adder, and can be removed by increasing the bit width of
the by bits. The output of the MAF is stored in a
lookup table (LUT) which, in effect, is the inverse transfer func-
tion of the VCO tuning curve. An example of the LUT is shown
in Fig. 17, where the solid line represents the ideal ADC transfer
curve and the bold dots represent the actual MAF output of the
ADC when a ramp is applied. When the ADC receives the ac-
tual input signal, the digital output (D3) is mapped in the LUT
to its corresponding address (011) and the calibrated output is
produced.
The complexity of the calibration circuitry depends on the
size of the LUT. When the duration of the ramp signal is
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Fig. 17. Example of the proposed digital calibration scheme.
Fig. 18. Implemented overall architecture.
and the quantizer resolution is , the size of the LUT can be
described as
(43)
For example, a ramp signal of , an of 2,
and result in a 150-byte mapping table, which is
enough to improve the SFDR from 30 to 65 dB. The proposed
calibration technique is verified by the experimental results in
the next section.
V. IMPLEMENTATION AND MEASUREMENT RESULTS
The VCO–quantizer shown in Fig. 18 was fabricated in a
0.13- CMOS technology. The VCO was implemented using
the 32-stage differential delay cell shown in Fig. 19 [18]. The
ring VCO is followed by 64 1-bit quantized reset counters and
a 64-bit adder. The reset counter consists of one divider, two
DFFs, and an XOR gate. The divider and the first DFF use a
sense-amplifier-based flip-flop (SAFF), shown in Fig. 20 [19],
for a small metastability window. The second DFF uses a true
single-phase clocked register (TSPC) for low power consump-
tion. The 64-bit adder is based on a carry–save architecture with
three-stage pipelining for a high-speed operation. The die pho-
tograph is shown in Fig. 21, where it can be seen that the active
area is 0.078 .
KIM et al.: ANALYSIS AND DESIGN OF VCO-BASED ADC 27

Fig. 21. Die photograph of the ADC. The chip was fabricated in a 0.13- m
CMOS process. The core area is 300 m 2 260 m
  .
Fig. 19. Delay-cell schematic of 64-phase ring VCO.

Fig. 22. Measured tuning characteristic of the ring VCO.

Fig. 20. SAFF schematic [19].

The measured tuning characteristic of the VCO is shown in

Fig. 22. In order to use the linear range of the tuning curve,
the full-scale analog input is set to 0–0.7 V, which corresponds
to 381–69 MHz of output frequency. The measured phase
noise of the ring VCO is 112 dBc/Hz at a 1-MHz offset.
The VCO–quantizer operates at a sampling clock of 500 MHz,
which has an absolute rms jitter of 83.9 ps when 1 million
samples are collected. For an input frequency of 1.1 MHz
and a peak-to-peak amplitude of 0.6 V, the FFT result of the Fig. 23. Measured power spectrum of ADC output. The peak-to-peak ampli-
VCO–quantizer is shown in Fig. 23, where the SNR is 64.25 tude of the input signal is 0.6 V.
dB. It can be seen that the skirt centered around the input
frequency reflects the effect of sampling jitter, particularly
sampling uncertainty. When input bandwidth is determined as mismatch and metastability of the DFF are represented as
dc to 2 MHz, the theoretical limit of the SNR due to sampling spurs that can be seen in Fig. 23. However, these spurs do not
uncertainty can be calculated as 64.73 dB from (16), which degrade the effective performance of the ADC because they
is close to the measured SNR of 64.25 dB. As expected in are located at high frequencies, i.e., when the ADC operates
Section III, the effect of other limiting factors such as VCO as an oversampling ADC, these spurs can be filtered out. For a

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28 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 1, JANUARY 2010
Fig. 24. Measured power spectrum of ADC output. The peak-to-peak ampli-
tude of the input signal is 13.4 mV.
Fig. 25. Measured power spectrum of ADC output before and after digital cal-
ibration for VCO nonlinearity.
Nyquist-rate ADC, harmonic spurs from VCO nonlinearity are
larger than these spurs.
To verify the analysis of the VCO phase noise, a small input
signal whose peak-to-peak amplitude of 13.4 mV was applied.
Since SNR degradation due to sampling uncertainty is not a
function of input-signal power, the small input signal reduces
the noise power due to sampling uncertainty which otherwise
overshadows the effect of the VCO phase noise. The measured
power spectrum of the VCO–quantizer is shown in Fig. 24,
where the SNR of 48.63 dB is close to the theoretical-analysis
result of 47.59 dB from (25). Note that, for noise-power calcu-
lation, the integration range is determined as 300 kHz–2 MHz
because that is where the VCO phase noise has the char-
acteristic assumed in (23)–(25).
To enhance the SFDR, the digital calibration method intro-
duced in Section IV was applied. For an input frequency of
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Fig. 26. SNR/SNDR/SNDR after calibration versus input power when the
input frequency is 1 MHz.
Fig. 27. SNR/SNDR/SNDR after calibration versus input bandwidth when the
0
input-signal power is 4.7 dBFS.
10 MHz, the FFT results of the VCO-based ADC before and
after calibration are shown in Fig. 25, where it can be seen that
the SFDR is improved from 32.2 to 61 dB due to calibration.
In this calibration, the width of the moving average is 2,
and the duration of the ramp signal is 203 ns (about 100
samples); hence, a 150-byte LUT is required. The MAF and the
LUT for the calibration and decimation filters are implemented
off-chip. The SNR, SNDR, and SNDR after calibration versus
the input-signal power at 1 MHz are shown in Fig. 26. It can
be seen that the SNR of the VCO-based ADC is proportional
to the input-signal power to the full-scale input, which is in
contrast to a conventional delta–sigma ADC whose SNR is de-
graded near the full-scale input due to stability. When the input
signal is small, the linearity of the VCO is better, and hence, the
SNDR is limited by the quantization noise rather than harmonic
spurs. As the analog input amplitude is larger than 20 dBFS,
the linearity of the VCO is severely degraded, and the SNDR is
reduced. However, the SNDR is improved to more than 60 dB
when calibration is used.
The SNR, SNDR, and SNDR after calibration versus the
analog input bandwidth are shown in Fig. 27, when the
input-signal power is 4.7 dBFS. As expected, the SNDR is
limited by the SFDR of 33.2 dB, and the SNR is limited by
KIM et al.: ANALYSIS AND DESIGN OF VCO-BASED ADC 29

TABLE I
ADC PERFORMANCE SUMMARY

verified using simulation and measurement. In addition, a dig-

ital calibration method for the VCO nonlinearity has been in-
troduced and proved using implemented IC and off-chip signal
processing. The implemented ADC achieves an SNR from 71.8
to 21.3 dB for an input bandwidth from 100 kHz to 247 MHz
and dissipates 12.6 mW. With the continued scaling of CMOS
processes, a VCO-based ADC is expected to gain higher perfor-
mance, as its resolution is determined by the speed of the logic
gate.

ACKNOWLEDGMENT
The authors would like to thank J. H. Lee and D. M. Park for
their invaluable advices.

Fig. 28. FOM versus input bandwidth.
the VCO phase noise for a low input bandwidth and by the
quantization noise in a high input bandwidth. The figure of
merit (FOM) of the VCO-based ADC versus the analog input
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Jaewook Kim (S’06) received the B.S. and M.S. de-
grees in electrical engineering from the Korea Ad-
vanced Institute of Science and Technology, Daejeon,
Korea, in 2006 and 2008, respectively, where he is
currently working toward the Ph.D. degree.
His research interests are time-based analog-to-
digital converters, digital RF receivers, and soft-
ware-defined radio.
Mr. Kim was the co-recipient of 2009 IEEE
TRANSACTIONS ON CIRCUITS AND SYSTEMS
Guillemon–Cauer Best Paper Award.
Authorized licensed use limited to: Amal Jyothi College of Engineering. Downloaded on July 07,2010 at 12:39:22 UTC from IEEE Xplore. Restrictions apply.
Tae-Kwang Jang (S’07) received the B.S. and M.S.
degrees in electrical engineering from the Korea Ad-
vanced Institute of Science and Technology, Daejeon,
Korea, in 2006 and 2008, respectively.
Since 2008, he has been with Samsung Elec-
tronics Company Ltd., Giheung, Korea, where
he is involved in analog-circuit design including
phase-locked loops and data converters for com-
munication systems and mobile processors. His
research interests include the low-power design of
analog and mixed-signal circuits.
Mr. Jang was the co-recipient of 2009 IEEE TRANSACTIONS ON CIRCUITS
AND SYSTEMS Guillemon–Cauer Best Paper Award.
Young-Gyu Yoon (S’08) received the B.S. and M.S.
degrees in electrical engineering from KAIST, Dae-
jeon, Korea, in 2007 and 2009, respectively.
Since 2009, he has been with KAIST Institute
(KI), Daejeon, for IT Convergence as a research engi-
neer. His research interests include analog-to-digital
converter, time-based signal processing, soft-
ware-defined radio and biomedical system.
Mr. Yoon was the recipient of 2009 IEEE
TRANSACTIONS ON CIRCUITS AND SYSTEMS
Guillemon–Cauer Best Paper Award.
SeongHwan Cho (S’94–M’03) received the B.S.
degree in electrical engineering from the Korea
Advanced Institute of Science and Technology
(KAIST), Daejeon, Korea, in 1995, and the M.S. and
Ph.D. degrees in electrical engineering and computer
science from the Massachusetts Institute of Tech-
nology, Cambridge, in 1997 and 2002, respectively.
During the summer of 1999, he was with the IBM
T. J. Watson Research Center, Yorktown Heights,
NY. In 2002, he joined Engim, Inc., where he was
involved in data converters, phased-locked loops,
and voltage-controlled-oscillator (VCO) design for IEEE 802.11(a)(b)(g) Wire-
less LANs. From 2003 to 2004, he was with the military of Korea as a Public
Service Agent. Since November 2004, he has been an Assistant Professor with
the Department of Electrical Engineering and Computer Science, KAIST.
His research interests include mixed-signal and analog circuits for low-power
communication systems and wireless sensor networks.
Dr. Cho has served as member of technical program committees (TPC) in sev-
eral IEEE conferences, including the International Solid-State Circuits Confer-
ence, the Asian Solid-State Circuits Conference, the Asia and South Pacific De-
sign Automation Conference, and the International Symposium on Low Power
Electronics and Design. He was the co-recipient of 2009 IEEE TRANSACTIONS
ON CIRCUITS AND SYSTEMS Guillemon–Cauer Best Paper Award.