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DEPARTMENT OF ECE
LAB OBSERVATION
Semester: ..................
GENERAL INSTRUCTIONS
SAFETY:
1. When students are doing experiment they have to be very care full.
2. Students should have the prior knowledge about the lab they are doing.
3. If any kind of wrong thing happened while doing the experiment. Students have to
immediately switch off power supply on the work table.
4. Wearing loose garments inside the lab is strictly prohibited.
ATTENDANCE:
1. Students have to come to the laboratory with proper dress code and ID Cards.
2. Students have to bring Observation note book , Record note book and calculators etc..
to the Laboratory.
3. Students have to sign in the log register after entering into the lab and before leaving
the laboratory.
4. Students have to show their observations with results after completion of their
experiments and they have to get is signed.
DOING EXPERIMENTS:
CALCULATION:
Calculate all required quantities and enter in the tabulation. Units are very, very
important. Draw the necessary graphs. Write the result. Show it to the staff for getting
Signature.
Course objectives:
To acquire skills in designing and testing analog integrated circuits
To expose the students to a variety of practical circuits using various analog ICs.
CONTENTS
1 Introduction 9
4 Schmitt Trigger 41
5 Difference Amplifier 45
INTRODUCTION
Operational Amplifier(op-amp)
The best known, and most common, linear IC is the operational amplifier which
consists of resistors, diodes, and transistors in a conventional analog circuit. An
operational amplifier is a direct-coupled, high gain amplifier consisting of one or more
differential amplifiers. it can be used to perform a variety of mathematical operations
such as addition,substraction,multiplication etc.Hence the name ’operational’ amplifier is
abbreviated as op-amp.
The input stage is the dual input,balanced output differential amplifier.This stage
generally provides most of the voltage gain of the amplifier and also establishes the input
resistance of the op-amp.The intermediate stage is usually another differential
amplifier,which is driven by the output of the first stage.In most amplifiers the
intermediate stage is dual input,unbalanced(single ended) output.Because direct coupling
is used ,the D.C voltage at the output of the inetrmediate stage is well above the ground
potential.
Therefore, generally, the level shifting stage is used after the intermediate stage to
shift the D.C level at the output of the intermediate stage downward to zero volts with
respect to ground.The final stage usually a push-pull complementory amplifier output
stage.The output stage increases the output voltage swing and raises the current supplying
capability of the op-amp.
Equivalent Circuit:
Pin diagram
IC µA 741
Parameters of op-amp:
Input offset voltage
It is the voltage that must be applied between the two input terminals of op-amp to null
the output.
Input offset current
The difference between the bias currents at the input terminals of the op-amp is
called as input offset current.
Common Mode Rejection Ratio(CMRR)
The relative sensitivity of an op-amp to a difference signal as compared to a
common –mode signal is called the common –mode rejection ratio. It is expressed in
decibels.
CMRR= Ad/Ac
Slew Rate
The slew rate is defined as the maximum rate of change of output voltage caused by a
step input voltage.An ideal slew rate is infinite which means that op-amp’s output voltage
should change instantaneously in response to input step voltage.
Applications of operational Amplifier:
* Summing Amplifier
* Integrating and Differentiating Amplifier
* Filtering etc.
The ideal op-amp
The ideal behaviour of an op-amp implies that
1. The output resistance is zero.
2. The input resistance is infinity.
3. op-amp has a zero voltage offsetie., for V1 = V2 = 0, output voltage VO = 0.
4. Common Mode Rejection Ratio (CMRR) is infinity.
5. Bandwidth is infinite i.e., Adis real and constant.
6. Slew rate is infinite.
Practical op-amp
1. Supply voltage:
a. µA 741A, µA 741, µA 741E ---------------- ±22V
b. µA 741C ---------------- ±18 V
2. Differential input voltage ---------------- ±30 V.
3. Input offset voltage ---------------- 1.0 mV.
4. Input Bias current ---------------- 80 nA.
5. Input resistance ----------------- 2MΩ.
6. CMMR ------------------ 90dB.
7. Output resistance ------------------ 75Ω.
8. Bandwidth ------------------ 1.0 MHz.
9. Slew rate ------------------ 0.5 V/µ sec.
Exp. No.1
1. a. INVERTING AMPLIFIER
AIM:
To design an Inverting Amplifier for the given specifications using Op-Amp IC 741.
APPARATUS REQUIRED:
THEORY:
The input signal Vi is applied to the inverting input terminal through R1 and the non-
inverting input terminal of the op-amp is grounded. The output voltage Vo is fed back to
the inverting input terminal through the Rf - R1 network, where Rf is the feedback
resistor. The input terminals of the opamp draws no current because of the large
differential input impedance. The potential difference across the input terminals of an
opamp is zero because of the large open loop gain. Due to these two conditions, the
inverting terminal is at virtual ground potential. So the current flowing through Ri and Rf
are the same.
Ii = If
i.e, Vin/Ri = - Vo /Rf
Therefore Vo/Vin = Av = - Rf/ Ri,
Here the –Ve sign indicates that the output will be an amplified wave with 1800 phase
shift (inverted output). By varying the Rf or Ri, the gain of the amplifier can be varied to
any desired value.
CIRCUIT DIAGRAM :
OBSERVATIONS:
MODEL GRAPH:
PROCEDURE:
DESIGN:
RESULT:
The design and testing of the inverting amplifier is done and the input and output
waveforms were drawn.
AIM:
To design a Non-Inverting Amplifier for the given specifications using Op-Amp IC 741.
APPARATUS REQUIRED:
THEORY:
The input signal Vi is applied to the non - inverting input terminal of the op-amp. This
circuit amplifies the signal without inverting the input signal. It is also called negative
feedback system since the output is feedback to the inverting input terminals. The Rf and
Ri are the feedback and input resistance of the circuit respectively.
Av = Vo / Vin = 1+ Rf/ Ri
Here the +Ve sign indicates that the output will be an amplified wave in phase with the
input. By varying the Rf or Ri, the gain of the amplifier can be varied to any desired
value.
PROCEDURE:
CIRCUIT DIAGRAM :
OBSERVATIONS:
MODEL GRAPH:
DESIGN:
RESULT:
The design and testing of the Non-inverting amplifier is done and the input and output
waveforms were drawn.
1. c. INTEGRATOR
AIM:
To design an Integrator circuit for the given specifications using Op-Amp IC 741.
APPARATUS REQUIRED:
THEORY:
A circuit in which the output voltage waveform is the integral of the input voltage
waveform is the integrator. Such a circuit is obtained by using a basic inverting amplifier
configuration if the feedback resistor Rf is replaced by a capacitor Cf . This circuit also
works as low pass filter. The expression for the output voltage is given as,
Vo = - (1/Rf C1) ∫ Vi dt
0
Here the negative sign indicates that the output voltage is 180 out of phase with the
input signal. The input signal will be integrated properly if the Time period T of the
signal is larger than or equal to Rf Cf. That is,
T ≥ Rf Cf
The integrator is most commonly used in analog computers and ADC and signal-wave
shaping circuits.
PROCEDURE:
CIRCUIT DIAGRAM :
OBSERVATIONS:
Output Voltage,Vo =
MODEL GRAPH:
4. By adjusting the amplitude and frequency knobs of the function generator, appropriate
input voltage (Vi= 2Vpp, 1KHz square wave) is applied to the inverting input terminal of
the Op-Amp.
5. The output voltage is obtained in the CRO and the input and output voltage
waveforms are plotted in a graph sheet.
DESIGN:
Given f =1 KHz
So T = 1/f = 1ms
Design equation is T = 2πRiC
Let C = 0.01μF
Then Ri = 15KΩ
Take Rf = 10Ri = 150KΩ
RESULT:
The design of the Integrator circuit was done and the input and output waveforms were
obtained.
1.d. COMPARATOR
AIM:
To design and setup a zero crossing detector circuit with OP AMP 741C and plot the
waveforms.
APPARATUS REQUIRED:
THEORY:
Comparator
Voltage Comparator: A comparator is a circuit which compares a signal voltage applied
at one input of an op-amp with output ±Vsat = (Vcc). If the signal is applied to the
inverting terminal of the op-amp it is called inverting comparator and if the signal is
applied to non-inverting terminal of the op-amp it is called non-inverting comparator. In
an inverting comparator if input signal is less than reference voltage, output will be
+Vsat. When input signal voltage is greater than reference voltage output will be –Vsat.
The vice-versa takes place in non-inverting comparator.
Zero Crossing Detector
Zero crossing comparator (ZCD) is an application of voltage comparator. The reference
voltage is set as zero volts. When the polarity of the input signal changes, output square
wave changes polarity. Here the signal is given the non-inverting terminal. So the output
signal is in phase with the input signal. Such a circuit is called non-inverting zero
crossing detector. In open loop configuration, the gain of the opamp is very high, so when
the input voltage is above zero voltage, output of the circuit goes to + Vsat which is
approximately +13V. Similarly when the input voltage is below zero voltage, the output
goes to - Vsat which is approximately -13V.
CIRCUIT DIAGRAM
OBSERVATIONS
Output Voltage,Vo =
MODEL GRAPH:
PROCEDURE:
RESULT:
The zero crossing detector circuit was done and the input and output waveforms were
obtained.
AIM: To design and setup a summing amplifier circuit with OP AMP 741C for a gain of
2 and verify the output.
APPARATUS REQUIRED:
THEORY:
Op-amp can be used to design a circuit whose output is the sum of several input signals.
Such a circuit is called a summing amplifier or an adder. Summing amplifier can be
classified as inverting & non-inverting summer depending on the input applied to
inverting & non-inverting terminals respectively. Circuit Diagram shows an inverting
adder (summing amplifier) with 2 inputs. Here the output will be amplified version of the
sum of the two input voltages with 1800 phase reversal.
Vo = - ( Rf/ Ri )(V1+V2)
PROCEDURE:
CIRCUIT DIAGRAM
OBSERVATIONS:
Output Voltage,Vo =
MODEL GRAPH:
DESIGN:
RESULT:
The design of the adder circuit was done and the input and output waveforms were
obtained.
Viva Questions
1. What is a comparator?
A comparator is a circuit which compares a signal voltage applied at one input of an
op-amp with known reference voltage at other input. It is basically an Op-amp with
output Vsat (»Vcc).
2. What is the difference between a basic comparator and ZCD?
Comparator has only one reference voltage whereas ZCD has zero reference voltage.
3. Give the gain expression for inverting and non inverting amplifier.
Inverting Amplifier = -Rf/Ri
Non inverting Amplifier = 1+( Rf/Ri)
4. State some linear and non linear applications of Op-amp.
Linear:
a) Adder
b) Subtractor
c) Instrumentation amplifier
5. Non linear:
a) Rectifier
b) Peak detector
c) Clippers and Clampers.
Exp.No. 2
APPARATUS REQUIRED:
An ideal op-amp draws no current from the source and its response is also independent of
temperature. However, a real op-amp does not work this way. Current is taken from the
source into op-amp inputs. Also the two inputs respond differently to current and voltage
due to mismatch in transistors.
CIRCUIT DIAGRAMS
To Measure CMRR
For 741, the bias current is 500nA or less. The smaller the input bias current, the
smaller will be the offset at the output voltage.
Input offset current
The input offset current is the difference between the two input currents driven from a
common source
|IOS| = 𝑰𝑰𝑩𝑩 + − 𝑰𝑰𝑩𝑩 −
It tells you how much larger one current is than the other. Bias current compensation
will work if both bias currents IB+ and IB- are equal. So, the smaller the input offset
current the better the OP amp. The 741 op-amps have input offset current of 20nA.
Input offset voltage
Ideally, the output voltage should be zero when the voltage between the inverting and
non-inverting inputs is zero. In reality, the output voltage may not be zero with zero input
voltage. This is due to un-avoidable imbalances, mismatches, tolerances, and so on inside
the op-amp. In order to make the output voltage zero, we have to apply a small voltage at
the input terminals to make output voltage zero. This voltage is called input offset voltage
.i.e., input offset voltage is the voltage required to be applied at the input for making
output voltage to zero volts. The 741 op-amp has input offset voltage of 5mV under no
signal conditions. Therefore, we may have to apply a differential input of 5mV, to
produce an output voltage of exactly zero.
Slew rate
Among all specifications affecting the ac operation of the op-amp, slew rate is the
most important because it places a severe limit on a large signals operation. Slew rateis
defined as themaximum rate at which the output voltage can change. The 741 op-amp has
a typical slew rate of0.5 volts per microsecond (V/µs). This is the ultimate speed of a
typical 741 its output voltage can change no faster than 0.5V/µs. If we drive a 741 with
large step input, it takes 20µs (0.5 V/µs*10V) for the output voltage to change from 0 to
10V.
CMRR
In an ideal different amplifier, differential gain Ad is infinite while common mode gain
AC must be zero. However, in a practical differential amplifier; Ad is very large and AC is
OBSERVATIONS:
very small. ie., the differential amplifier provides very large amplification for difference
signals and very small amplification for common mode signals. Many disturbance
signals/noise signals appear as a common input signal to both the input terminals of the
differential amplifier. Such a common signal should be rejected by the differential
amplifier. “The ability of a differential amplifier to reject a common-mode signal is
expressed by a ration called Common Mode Rejection Ratio, denoted as CMRR”. CMRR
is defined as the ratio of the differential voltage gain Ad to common mode voltage gain
AC. CMRR = Ad/AC Ideally AC is zero. Hence, the ideal value of CMRR is ∞.
PROCEDURE
e) CMRR
1. Connect the circuit as shown in Fig.
2. Give sine wave input (2Vp-p) from the signal generator and measure Vo. Calculate
𝑅𝑅 𝑓𝑓
𝑉𝑉𝑖𝑖 ( 𝑅𝑅 )
𝑖𝑖
CMRR using expression CMRR= .Express CMRR in dB using the expression
𝑉𝑉𝑜𝑜
20 log (Vo/Vi)
RESULT
The input bias current, input offset current, input offset voltage and slew rate of the op-
amp were determined.
Viva Questions
Exp. No. 3
SCHMITT TRIGGER
AIM:
To design and setup a Schmitt trigger, plot the input output waveforms and measure VUT
and VLT.
APPARATUS REQUIRED:
THEORY:
PROCEDURE:
CIRCUIT DIAGRAM
OBSERVATIONS:
MODEL GRAPH:
3. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.
4. Give V1 =10Vpp / 1 KHz sine wave.
5. Observe input and output on two channels of the oscilloscope simultaneously.
6. Note down and draw the input and output waveforms on the graph.
DESIGN:
RESULT:
The Schmitt trigger is done, plotted the input output waveforms and measured VUT and
VLT.
Viva Questions
Exp No.4
DIFFERENCE AMPLIFIER
AIM:
To design and setup a difference amplifier circuit with OPAMP IC 741C for a gain of 2
and verify the output.
APPARATUS REQUIRED:
THEORY:
A difference amplifier is a circuit that gives the amplified version of the difference of the
two inputs, Vo =A(V1-V2), Where V1 and V2 are the inputs and A is the voltage gain.
Here input voltage V1 is connected to non-inverting terminal and V2 to the inverting
terminal. This is also called as differential amplifier. Output of a differential amplifier
can be determined using super position theorem.
When V1=0, the circuit becomes an inverting amplifier with input V2 and the resulting
output is V02= -Rf /Ri (V2).
When V2=0, the circuit become a non-inverting amplifier with input V1 and the resulting
output is V01= Rf/Ri(V1).
Therefore the resulting output according to super position theorem is
Vo = V01+ V02 = Rf/Ri(V1-V2)
PROCEDURE:
CIRCUIT DIAGRAM
OBSERVATIONS:
Output Voltage,Vo =
MODEL GRAPH:
7. Note down and draw the input and output waveforms on the graph.
DESIGN:
Then Rf = 10KΩ
RESULT:
The design of the difference amplifier circuit was done and the input and output
waveforms were obtained.
Exp. No.5
ASTABLE AND MONOSTABLE MULTIVIBRATORS USING
OP AMP
5.a. SYMMETRICAL AND ASYMMETRICAL ASTABLE
MULTIVIBRATORS USING OP AMP
AIM:
To design and setup symmetrical and asymmetrical astable multivibrators using Opamp
APPARATUS REQUIRED:
THEORY:
In this circuit, the opamp is operated in saturation mode and the output swings between
+Vsat and –Vsat giving square wave output. This circuit is also called free running
oscillator or square wave generator . A positive feedback with feedback factor β = R1 /
(R1+R2) is provided to the non-inverting terminal. When Vo= +Vsat, the capacitor C
starts to charge to + Vsat through R. when the capacitor voltage crosses +βVsat, output
switches from +Vsat to –Vsat. Now the voltage appearing at the non-inverting terminal is
–βVsat and capacitor discharges through R towards -Vsat. When the capacitor voltage
crosses –βVsat, the output switches from –Vsat to + Vsat and this process continues to
generate square wave output with time period T=Ton + Toff= 2RC ln[(1+β)/(1-β)]. In
asymmetrical astable multivibrators, the charging and discharging time of capacitor is
made unequal to get asymmetrical square wave with different Ton and Toff.
CIRCUIT DIAGRAM :
OBSERVATIONS:
Output Voltage,Vo =
Time Period,T =
Voltage Across Capacitor,VC =
DESIGN
Given f = 1 KHz
So T = 1/f = 1ms
And β = R1 / (R1+R2)
Let R1 = 10KΩ , and R2 =10KΩ
Then β = 0.5
Therefore T= 2.2RC =1ms
Let C = 0.1μF
Then R = 4.7KΩ
Given f = 1 KHz
So T = Ton + Toff = 1/f = 1ms
Also Duty cycle = Ton/(Ton+Toff) = 0.66 or 66%
Solving above two equations, Ton = 0.66ms
Toff = 0.33ms
For β=0.5,
Ton= 1.1Rf1C = 0.66ms
Let C = 0.1μF
Then Rf1 = 6.2KΩ = 5.6KΩ (Std)
Similarly Toff = 1.1Rf2C = 0.33ms
Then Rf 2 = 3KΩ = 3.3 KΩ (Std
PROCEDURE:
MODEL GRAPH:
RESULT:
The design and testing of the astable multivibrator is done and the input and output
waveforms were drawn.
Viva Questions
1. What is multivibrator?
A multivibrator is an electronic circuit used to implement a variety of simple two-
state systems such as oscillators, timers and flip-flops. It is characterized by two
amplifying devices (transistors, electron tubes or other devices) cross-coupled by
resistors or capacitors.
2. What is quasi stable state?
Change from one state to another without any external trigger is termed as quasi
stable state.
3. What are the various modes of operation of multivibrator? Explain
Astable mode – 2 quasi stable state
Monostable – 1 quasi and on stable state.
Bistable – 2 stable states.
4. What is one-shot multivibrator?
The monostable is also called as one-shot multivibrator as it produces a single
pulse of specified duration in response to each external trigger signal. Only one
stable state exists. When an external trigger signal is applied the output changes
its state.
APPARATUS REQUIRED:
THEORY:
The monostable multivibrator is also called as one shot multivibrator. The circuit
produces a single pulse of specified duration in response to each external trigger pulse. It
always has one stable state (+Vsat). When an external trigger is applied, the output state
changes and the new state is called quasi stable state (-Vsat). The circuit remains in this
state for a fixed interval of time and then it returns to the original state after this interval.
This time interval is determined discharging of the capacitor from 0.7V to -βVsat.The
time period of quasi stable state or the delay is given by
T = 0.69RC
PROCEDURE:
CIRCUIT DIAGRAM :
MODEL GRAPH:
5. Observe trigger input , output and capacitor voltage on different channels of the
oscilloscope simultaneously.
6. Draw the waveforms on the graph.
7. Measure the time delay.
DESIGN:
OBSERVATIONS:
Output Voltage,Vo =
Time Period,T =
RESULT:
The design and testing of the monostable multivibrator is done and the input and output
waveforms were drawn.
Exp. No.6
RC PHASE SHIFT OSCILLATOR USING OP AMP
AIM:
To Design and setup a RC phase shift oscillator using Op-Amp 741 and (i) Plot the
output waveform (ii) Measure the frequency of oscillation.
APPARATUS REQUIRED:
THEORY:
RC phase shift oscillator uses op-amp, in inverting amplifier mode and the circuit
generates its own output signal. It consists of an op-amp as an amplifier and 3 RC
cascaded network as the feedback circuit. Since the op-amp is used in the inverting mode,
any signal that appears at the inverting terminal is shifted by 1800 at the output. An
additional 1800 phase shift required for oscillation is provided by the cascaded RC
network. Thus the total phase shift around the circuit is 3600 or 00 . At some specific
frequency, the phase shift of the cascaded RC network is exactly 1800 and feedback factor
is 1/29. If the gain of the amplifier is 29, the total loop gain of the circuit becomes 1. The
circuit will oscillate at this specific frequency and is given by
𝟏𝟏
f =
𝟐𝟐𝝅𝝅√𝟔𝟔𝑹𝑹𝑹𝑹
PROCEDURE:
CIRCUIT DIAGRAM :
OBSERVATIONS:
Output Voltage,Vo =
Time Period,T =
Frequency,F =
MODEL GRAPH:
4. The output voltage is obtained in the CRO and output voltage waveform is plotted
in a graph sheet.
DESIGN :
1
f =
2𝜋𝜋 √6𝑅𝑅𝑅𝑅
RESULT:
The design and testing of RC phase shift oscillator is done and the output waveform is
drawn.
Viva Questions
Exp. No. 7
To design and construct a Wien bridge oscillator using Op-Amp 741 and
(i) Plot the output waveform (ii) Measure the frequency of oscillation
APPARATUS REQUIRED:
THEORY:
It is the commonly used audio frequency oscillator which employs both positive and
negative feedback. The feedback signal is connected in the non-inverting input terminal
so that the amplifier is working in non-inverting mode. The Wien bridge circuit is
connected between amplifier input terminal and output terminal. The bridge has a series
RC network in one arm and a parallel RC network in the adjoining arm. In the remaining
two arms of the bridge, resistor R1 and Rf are connected. The phase angle criterion for
oscillation is that the total phase shift around the circuit must be zero. This condition
occurs when bridge is balanced. At resonance, the frequency of oscillation is exactly the
resonance frequency of balanced Wien bridge and is given by f0 = 1/ (2πRC). At this
frequency, the gain required for sustained oscillation is 3.It is provided by the non-
inverting amplifier with Gain = 1+ (Rf/R1) = 3
CIRCUIT DIAGRAM :
OBSERVATIONS:
Output Voltage,Vo =
Time Period,T =
Frequency,F =
MODEL GRAPH:
PROCEDURE:
DESIGN :
fosc = 1/2πRC
Let f = 1KHz , and C= 0.1μF
R=1.5KΩ
Gain=3
1+ (Rf/R1) =3
If R1 = 10KΩ ,Rf = 20KΩ Use 47KΩ pot
RESULT:
The design and testing of wein bridge oscillator is done and the output waveform is
drawn.
Viva Questions
Exp.No.8
To Design and setup a square wave and triangular wave generators using Op-Amp 741
and plot the output waveforms.
APPARATUS REQUIRED:
This experiment is about a triangular wave generator using opamp IC. Triangular wave is
a periodic, nonsinusoidal waveform with a triangular shape. The most important feature
of a triangular wave is that it has equal rise and fall times . The applications of triangular
wave include sampling circuits, frequency generator circuits, tone generator circuits etc.
There are many methods for generating triangular waves but here we focus on method
using opamps. This circuit is based on the fact that a square wave on integration gives a
triangular wave. The circuit uses an opamp based square wave generator for producing
the square wave and an opamp based integrator for integrating the square wave.
PROCEDURE:
CIRCUIT DIAGRAM
MODEL GRAPH
DESIGN:
Given f =1 KHz
So T = 1/f = 1ms
Design equation is T = 2πRiC
Let C = 0.01μF
Then Ri = 15KΩ
Take Rf = 10Ri = 150KΩ
RESULT
Designed and setup the circuit of a square wave generator and triangular wave
generator.Plotted the wave forms.
Exp. No. 9
PRECISION RECTIFIER
AIM:
APPARATUS REQUIRED:
THEORY:
CIRCUIT DIAGRAM:
OBSERVATIONS:
Output Voltage,Vo =
MODEL GRAPH:
RESULT:
The circuit of precision rectifier is done and the output waveform is drawn.
Viva Questions
Exp. No. 10
To design and setup symmetrical and asymmetrical astable multivibrators using IC 555
and (i) Plot the output waveform (ii) Measure the frequency of oscillation.
APPARATUS REQUIRED:
THEORY:
The 555 timer is a highly stable device for generating accurate time delay .The internal
structure of 555 is shown in which there are two comparators, a flip flop, an output stage,
a voltage divider network and a transistor. The comparator is a device whose output is
high when the non-inverting input voltage is greater than inverting input voltage and
output is low when inverting input voltage is greater than non-inverting input voltage.
The voltage divider network consist of three 5KΩ resistors and provides a trigger voltage
level of 1/3VCC and threshold voltage level of 2/3VCC.The control voltage is used for
changing the threshold and trigger voltages externally.
555 as Astable multivibrator: Astable multivibrator means it has no stable states. It has
two quasi stable states (high and low).In the figure given , there are 2 external resistors
RA and RB and a capacitor C. When the power is given to the circuit the capacitor C will
charge towards VCC through RA and RB ,when the capacitor voltage exceeds the level
of 2/3VCC (threshold voltage) the output of the comparator I goes high which resets the
flip flop so the output Q of the flip-flop becomes low and becomes high.
Now the transistor which is connected to becomes ON. The capacitor C started to
discharge through RB and transistor exponentially.
When voltage across capacitor reaches just below of 1/3VCC (trigger voltage) the output
of the comparator II becomes high and sets the flip flop, turning OFF the transistor since
it is connected to the of the flip flop. The capacitor C will begin to charge towards VCC
through RA and RB. when the capacitor voltage exceeds the level of 2/3VCC, the output
of the comparator I goes high which resets the flip-flop so the output Q of the flip flop
becomes low and becomes high. The cycle continues which gives a square wave at the
output (pin 3) and charging and discharging wave form across capacitor (pin 2&6).
555 as Symmetrical astable multivibrator:
Symmetrical astable multivibrator means the multivibrator has equal ON time & OFF
time (duty cycle =50%).we can achieve this by making the charging (towards 2/3 VCC)
and discharging (towards 1/3VCC) process of capacitor through equal resistance path. In
the circuit diagram the diode (1N 4001) is connected across the resistor RB so the
charging of capacitor above threshold voltage (2/3VCC) takes place through the resistor
RA and forward biased diode. The discharging below trigger voltage (1/3VCC) is
through the resistor RB. Since RA and RB have same value, charging and discharging
time of the capacitor will be same.
PROCEDURE:
CIRCUIT DIAGRAM :
MODEL GRAPHS:
RESULT
Designed and setup the circuit of astable multivibrator using IC555.Plotted the wave
forms.
Viva Questions
Exp. No. 11
To set up a low voltage regulator using IC723 and plot the regulation characteristics.
APPARATUS REQUIRED:
THEORY:
Type 723 is the most versatile of the monolithic voltage regulators. It can be used to
provide high and low positive regulated voltages .Current can be boosted to provide 5A
or more. It has short circuit protection. The input voltage of IC723 vary from 9.5V to
40V and provide output voltage from 2V to 37V. IC 723 regulator has two separate
sections. One section provides a fixed voltage of 7.15v at the terminal Vref, other section
consists of an error amplifier. These two sections are not internally connected. For
constructing low voltage regulator using 723, Vref point is connected through a
resistance to the non-inverting terminal and the output is feedback to the inverting
terminal of the error amplifier. If the output voltage becomes low, the voltage at the
inverting terminal of error amplifier also goes down. Thus make the output of the error
amplifier become more positive, there by driving transistor more into conduction. This
reduces the voltage across transistor and drives more current into the load, causing
voltage across the load to increase. Thus the initial decrease in the load voltage is
compensated. Similarly any increase in the load voltage gets regulated.
CIRCUIT DIAGRAM
PIN DIAGRAM
PROCEDURE:
DESIGN:
(Optional)
Let the regulated output voltage Vo = 6V
Vo = Vref x { R2 / (R1+R2)}
6 = 7.15 x R2/(R1+R2)
Let the current through resistor R1 and R2 I1 = 1mA
Then R1 = (Vref - Vo)/I1 = (7.15 – 6) /1ma = 1.1K = 1K (std)
Then R2 = 6 / 1.15 = 5.6K (std)
For room temp. Stability R3 = R1 || R2
As per data sheet 966 Ω< R3 < 3.52K
OBSERVATIONS:
MODEL GRAPH:
RESULT:
The circuit of low voltage regulator using IC723 is done and plotted the regulation
characteristics.
Viva Questions
1. What is a voltage regulator?
2. A voltage regulator is an electronic circuit that provides a stable DC voltage
independent of the load current, temperature and AC line voltage variations.
3. What is the main function of voltage regulator?
4. The main function of a voltage regulator is to provide a stable DC voltage for
processing other electronic circuits.
5. What are the different types of voltage regulators?
6. Fixed output voltage regulator (positive or negative)
7. Adjustable output voltage regulators (positive or negative)
8. Switching regulators.
9. Special regulators.
10. What are the four main parts of voltage regulators?
a) Reference voltage circuit
b) Error amplifier
c) Series pole transistor
d) Feedback Network.
11. What are the main advantages of voltage regulators?
a) Short circuit Protection.
b) Output Voltage can be varied.
12. Define line regulation or source regulation.
13. Line regulation is defined as the percentage change in the output voltage for a
change in the input voltage. It is usually expressed in millivolts or as percentage
of the input voltage.
14. Define Load regulation.
15. Load regulation is defined as the change in regulated output voltage for a change
in load current. It is usually expressed in millivolts or as a percentage of V0.
Exp. No.12
STUDY OF PLL IC
AIM:
To study phase lock loop and its capture range, lock range and free running VCO.
APPARATUS REQUIRED:
THEORY:
PLL has emerged as one of the fundamental building block in electronic technology.
It is used for the frequency multiplication, FM stereo detector , FM demodulator ,
frequency shift keying decoders, local oscillator in TV and FM tuner. It consists of a
phase detector, a LPF and a voltage controlled oscillator (VCO) connected together in
the form of a feedback system. The VCO is a sinusoidal generator whose frequency is
determined by a voltage applied to it from an external source. In effect, any frequency
modulator may serve as a VCO.
The phase detector or comparator compares the input frequency, fin , with feedback
frequency ,fout ,( output frequency). The output of the phase detector is proportional
to the phase difference between fin and fout . The output voltage of the phase detector
is a DC voltage and therefore m is often refers to as error voltage . The output of the
phase detector is then applied to the LPF , which removes the high frequency noise
and produces a DC lend. The DC level, in term is the input to the VCO.
The output frequency of the VCO is directly proportional to the input DC level. The
VCO frequency is compared with the input frequencies and adjusted until it is equal
to the input frequency.
PIN DIAGRAM:
CIRCUIT DIAGRAM:
OBSERVATIONS:
MODEL GRAPH:
In short, PLL keeps its output frequency constant at the input frequency. Thus, the PLL
goes through 3 states.
1. Free running state.
2. Capture range / mode
3. Phase lock state.
Before input is applied, the PLL is in the free running state.
Once the input frequency is applied, the VCO frequency starts to change and the PLL is
said to be the capture range/mode. The VCO frequency cantinues to change (output
frequency ) until it equals the input frequency and the PLL is then in the phase locked
state. When phase is locked, the loop tracks any change in the input frequency through its
repetitive action.
Lock Range or Tracking Range: It is the range of frequencies in the vicinity of f O over
which the VCO, once locked to the input signal, will remain locked .
Capture Range (f C) : Is the range of frequencies in the vicinity of ‘f O’ over which the
loop will acquire lock with an input signal initially starting out of lock .
PROCEDURE :
5. Now gradually decrease the input frequency till the PLL is again locked. This is the
frequency f3, the upper end of the capture range. Keep on decreasing the input frequency
until the loop is unlocked. This frequency f4 gives the lower end of the lock range.
6. The lock range ∆fL = (f2 – f4).Compare it with the calculated value of ± 7.8fo/12.
Also the capture range is ∆fc = (f3 – f1).Compare it with the calculated value of capture
range.
RESULT:
Thus the PLL circuit is constructed and its Characteristics were determined.
Viva Questions
b) Signal generation
c) Frequency shift keying
d) Frequency multipliers
8. What are the 3 stages of PLL characteristic?
a) Free running
b) Capture
c) Locking.
Exp. No. 13
D/A CONVERTER
AIM:
THEORY:
In weighted resistor type DAC, op-amp is used to produce a weighted sum of digital inputs
where weights are produced to weights of bit positions of inputs. Each input is amplified by a
factor equal to ratio of feed back resistance to input resistance to which it is connected.
VOUT = -RF/ /R (D3 +1/2 D2+ ¼ D1+1/8D0)
The R-2R ladder type DAC uses resistor of only two values R and2R.The inputs to
resistor network may be applied through digitally connected switches or from output pins of a
counter. The analogue output will be maximum, when all inputs are of logic high.
V=-Rf/R (1/2 D3+1/4D2+1/8D1+1/16D0)
In a 3 input ADC, if the analog signal exceeds the reference signal, comparator turns
on. If all comparators are off, analog input will be between 0 and V/4.If C1 is high and C2 is
low input will be between V/4 andV/2.If C1 andC2 are high and C3 is low input will be
between 3V/4 and V.
PROCEDURE:
1. Connect the circuit as shown in circuit diagram.
2. For various inputs, measure the outputs using multimeter.
Viva Questions
In weighted resistor, for higher order conversion the values of resistors become
very high which is overcome in R-2R ladder which has only R and 2R values of
resistors.
3. List the various types of ADC.
Direct type
a) Flash type
b) Counter
c) Successive Approximation Register
d) Tracking
4. Define resolution.
Smallest change in voltage which may be produced at output of the converter.
5. List the specifications of DAC and ADC.
a) Resolution
b) Linearity
c) Accuracy
d) Monotonicity
e) Settling time
f) Stability.