ESP32-S2

Hardware Design Guidelines

Version 1.0
Espressif Systems
Copyright © 2020

www.espressif.com
About This Document
The guidelines outline recommended design practices when developing standalone or add-on systems based on
the ESP32-S2 series of products, including ESP32-S2 SoCs, ESP32-S2 modules and ESP32-S2 development
boards.

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PROVIDED AS IS WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABIL-
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owners, and are hereby acknowledged.
Copyright © 2020 Espressif Systems (Shanghai) Co., Ltd. All rights reserved.
Contents

1 Overview 1

2 Schematic Checklist 2
2.1 Power Supply 3
2.1.1 Digital Power Supply 3
2.1.2 Analog Power Supply 4
2.2 Power-on Sequence and System Reset 5
2.2.1 Power-on Sequence 5
2.2.2 Reset 5
2.3 Flash (compulsory) and SRAM (optional) 5
2.4 Crystal Oscillator 6
2.4.1 External Clock Source (compulsory) 6
2.4.2 RTC (optional) 7
2.5 RF 8
2.6 UART 9
2.7 USB 9
2.8 ADC 9
2.9 Touch Sensor 9

3 PCB Layout Design 10

3.1 General Principles of PCB Layout 10
3.2 Positioning an ESP32-S2 Module on a Base Board 11
3.3 Power Supply 12
3.4 Crystal Oscillator 13
3.5 RF 14
3.6 Flash and PSRAM 15
3.7 UART 16
3.8 USB 16
3.9 Touch Sensor 16
3.10 Typical Layout Problems and Solutions 19
3.10.1 Q: The current ripple is not large, but the TX performance of RF is rather poor. 19
3.10.2 Q: The power ripple is small, but RF TX performance is poor. 19
3.10.3 Q: When ESP32-S2 sends data packages, the power value is much higher or lower than the
target power value, and the EVM is relatively poor. 20
3.10.4 Q: TX performance is not bad, but the RX sensitivity is low. 20

4 Hardware Development 21
4.1 ESP32-S2 Modules 21
4.2 ESP32-S2 Development Boards 21

Revision History 22
List of Figures
1 ESP32-S2 Schematic 2
2 ESP32-S2 Digital Power Supply Pins 3
3 ESP32-S2 Analog Power Supply Pins 4
4 ESP32-S2 Flash and SRAM 6
5 Schematic for ESP32-S2’s Crystal 7
6 Schematic for ESP32-S2’s Crystal Oscillator 7
7 Schematic for ESP32-S2’s External Crystal (RTC) 7
8 Schematic of External Oscillator 8
9 ESP32-S2 RF Matching Schematic 8
10 ESP32-S2 PCB Layout 10
11 ESP32-S2 Module Antenna Position on Base Board 11
12 Keepout Zone for ESP32-S2 Module’s Antenna on the Base Board 12
13 ESP32-S2 Power Traces in a Four-layer PCB Design 13
14 ESP32-S2 Crystal Oscillator Layout 14
15 ESP32-S2 RF Layout in a Four-layer PCB Design 15
16 ESP32-S2 PCB Stack-up Design 15
17 ESP32-S2 Flash and PSRAM Layout 16
18 A Typical Touch Sensor Application 17
19 Electrode Pattern Requirements 17
20 Sensor Track Routing Requirements 18
21 Shied Electrode and Protective Sensor 19
1. Overview

1. Overview
ESP32-S2 is a highly-integrated, low-power, 2.4 GHz Wi-Fi System-on-Chip (SoC) solution. With its state-of-the-
art power and RF performance, this SoC is an ideal choice for a wide variety of application scenarios relating to
Internet of Things (IoT), wearable electronics and smart home.

At the core of this chip is an Xtensa® 32-bit LX7 CPU that operates at up to 240 MHz. The chip supports application
development, without the need for a host MCU.

ESP32-S2 includes a Wi-Fi subsystem that integrates a Wi-Fi MAC, Wi-Fi radio and baseband, RF switch, RF balun,
power amplifier, low noise amplifier (LNA), etc. The chip is fully compliant with the IEEE 802.11b/g/n protocol and
offers a complete Wi-Fi solution.

ESP32-S2 also integrates advanced calibration circuitries that allow the solution to dynamically adjust itself to
remove external circuit imperfections or adjust to changes in external conditions. As such, the mass production
of ESP32-S2 solutions does not require expensive and specialized Wi-Fi test equipment.

For more information about ESP32-S2, please refer to ESP32-S2 Datasheet.

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 2. Schematic Checklist

2. Schematic Checklist
ESP32-S2’s integrated circuitry requires only 20 resistors, capacitors and inductors, one crystal and one SPI flash
memory chip. ESP32-S2 integrates a Wi-Fi MAC, Wi-Fi radio and baseband, RF switch, RF balun, power amplifier,
low noise amplifier (LNA), and advanced calibration circuitries.

ESP32-S2’s high integration allows for simple peripheral circuit design. This chapter details ESP32-S2 schematics.
ESP32-S2 schematic is shown in Figure 1.
5 4 3 2 1

GND

3
GND Y1 GND

GND

GND XOUT
The values of C1 and C4 vary with C1 C4
D D
the selection of the crystal.

XIN
TBD TBD
The value of R4 varies with the actual
PCB board.

2
VDD33

C2 C3 GND
R4
100pF 1uF
0 40MHz (±10ppm)
VDD33
GND GND CHIP_PU
GPIO46
GPIO45
C5 U0RXD
R3 499 U0TXD
0.1uF GPIO42
GPIO41
C GPIO40 C
VDD33 GND GND GPIO39

L1 2.0nH

C6 C7 C8 C9 C10 VDD33 VDD_SPI

57

56
55
54
53
52
51
50
49
48
47
46
45
44
43

10uF 1uF 0.1uF TBD 0.1uF

GND

CHIP_PU
GPIO46
VDDA
XTAL_P
XTAL_N
VDDA
GPIO45
U0RXD
U0TXD
MTMS

MTDO
MTCK
MTDI
VDD3P3_CPU

GND GND GND GND GND R8

10K(NC)

8
ANT2 1 42 GPIO38 U2
1 RF_ANT L2 TBD LNA_IN 2 VDDA GPIO38 41 GPIO37

VCC
2 3 LNA_IN GPIO37 40 GPIO36 SPICS0 1 5 SPID
4 VDD3P3 GPIO36 39 GPIO35 /CS DI
C11 C12
PCB ANT GPIO0 5 VDD3P3 GPIO35 38 GPIO34 SPICLK 6 2 SPIQ
TBD TBD GPIO1 6 GPIO0 GPIO34 37 GPIO33 CLK DO
GPIO2 7 GPIO1 GPIO33 36 R13 0 SPID SPIHD 7 3 SPIWP

GND
GPIO3 8 GPIO2 SPID 35 R14 0 SPIQ /HOLD /WP
GPIO4 9 GPIO3 SPIQ 34 R10 0 SPICLK
B GND GND GND B
GPIO5 10 GPIO4 SPICLK 33 SPICS0 FLASH-3V3

4
GPIO6 11 GPIO5 SPICS0 32 R15 0 SPIWP
The values of C11, L2 and C12 GPIO6 SPIWP
vary with the actual PCB board. GPIO7 12 31 R16 0 SPIHD NC: No component.
GPIO8 13 GPIO7 SPIHD 30 GND
VDD3P3_RTC_IO

GPIO9 14 GPIO8 VDD_SPI 29 GPIO26 SPICS1

VDD3P3_RTC

GPIO9 SPICS1 VDD_SPI

XTAL_32K_N
XTAL_32K_P

VDD_SPI
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

GPIO19
GPIO20

GPIO21
DAC_1
DAC_2

C13 C14
R9
U1 ESP32-S2 0.1uF 1uF
15
16
17
18
19
20
21
22
23
24
25
26
27
28

10K(NC) U3 8
VDD
GND GND SPICS1 1 5 SPID
VDD33 R11 10K VDD33 CS SI/SIO0
SPICLK 6 2 SPIQ
SCLK SO/SIO1
SPIHD 7 3 SPIWP
VSS

C15 C16 SIO3 SIO2

A A

0.1uF 0.1uF PSRAM-3V3 (Optional)

GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20

GPIO21

GND GND GND

5 4 Figure 1: ESP32-S2 Schematic 3 2 1

Any basic ESP32-S2 circuit design may be broken down into nine major sections:

• Power supply

• Power-on sequence and system reset

• Flash and SRAM (optional)

• Crystal oscillator

• RF

• UART

• USB

• ADC

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 2. Schematic Checklist

• Touch Sensor

2.1 Power Supply

For further details of using the power supply pins, please refer to Section Power Scheme in ESP32-S2 Datasheet.
4 3 2 1

2.1.1 Digital Power Supply

GND

Pin27 and pin45 are the power supply pins for RTC IO and CPU IO, in a voltage range of 3.0 V ~ 3.6 V and 2.8 V ~
4

3
GND
Y1 GND
3.6 V, respectively. We recommend adding extra 0.1 µF capacitors close to each digital power supply pin.
GND

GND XOUT
The values of C1 and C4 vary
VDD_SPI canwith
work asC1the power supply for the
C4
external device at either 1.8 V (when GPIO45 is 1 during boot),
the selection of the crystal.
XIN

TBD TBD
or 3.3 V (when GPIO45 is 0 and at default state during boot). We recommend adding extra 0.1 µF and 1 µF
The value of R4 varies with the actual
PCB board. capacitors close to VDD_SPI.
1

• When VDD_SPI operates at 1.8 V, it can be generated from ESP32-S2’s internal LDO. The maximum current
C3 GND
this LDO can offer is
R4
40 mA, and the output voltage range is 1.8 V ~ 3.6 V.
1uF
0 40MHz (±10ppm)
• When VDD_SPI operates at 3.3 V, it is driven directly by VDD3P3_RTC_IO through a 5 Ω resistor, therefore,
GND CHIP_PU
there will be some voltage drop from VDD3P3_RTC_IO. GPIO46
GPIO45
C5 U0RXD
VDD_SPI can also be driven by an external power supply. R3 499 U0TXD
0.1uF GPIO42
The schematic for ESP32-S2 digital power supply pins is shown in FigureGPIO41
2.
GPIO40
GND GND GPIO39

nH

C9 C10 VDD33 VDD_SPI

57

56
55
54
53
52
51
50
49
48
47
46
45
44
43

TBD 0.1uF
GND

CHIP_PU
GPIO46
VDDA
XTAL_P
XTAL_N
VDDA
GPIO45
U0RXD
U0TXD
MTMS

MTDO
VDD3P3_CPU

MTCK
MTDI

GND GND R8
10K(NC)

8
1 42 GPIO38 U2
D LNA_IN 2 VDDA GPIO38 41 GPIO37

VCC
3 LNA_IN GPIO37 40 GPIO36 SPICS0 1 5 SPID
4 VDD3P3 GPIO36 39 GPIO35 /CS DI
2
GPIO0 5 VDD3P3 GPIO35 38 GPIO34 SPICLK 6 2 SPIQ
D GPIO1 6 GPIO0 GPIO34 37 GPIO33 CLK DO
GPIO2 7 GPIO1 GPIO33 36 R13 0 SPID SPIHD 7 3 SPIW

GND
GPIO3 8 GPIO2 SPID 35 R14 0 SPIQ /HOLD /WP
GPIO4 9 GPIO3 SPIQ 34 R10 0 SPICLK
GND
GPIO5 10 GPIO4 SPICLK 33 SPICS0 FLASH-3V3
GPIO5 SPICS0 4
GPIO6 11 32 R15 0 SPIWP
GPIO7 12 GPIO6 SPIWP 31 R16 0 SPIHD
GPIO7 SPIHD NC: No component.
GPIO8 13 30 GND
VDD3P3_RTC_IO

GPIO9 14 GPIO8 VDD_SPI 29 GPIO26 SPICS1

VDD3P3_RTC

GPIO9 SPICS1 VDD_SPI

XTAL_32K_N
XTAL_32K_P

VDD_SPI
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

GPIO19
GPIO20

GPIO21
DAC_1
DAC_2

C13 C14
R9
U1 ESP32-S2 0.1uF 1uF
15
16
17
18
19
20
21
22
23
24
25
26
27
28

10K(NC)
8

U3
VDD

GND GND SPICS1 1 5 SPID

VDD33 R11 10K VDD33 CS SI/SIO0
SPICLK 6 2 SPIQ
SCLK SO/SIO1
SPIHD 7 3 SPIW
VSS

C15 C16 SIO3 SIO2

0.1uF 0.1uF PSRAM-3V3 (Optio

GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20

GPIO21

GND GND GND

Figure 2: ESP32-S2 Digital Power Supply Pins

4 3 2 1

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2. Schematic Checklist

Notice: When using VDD_SPI as the power supply pin for the external 3.3 V flash/PSRAM, the supply voltage should be
3.0 V or above, so as to meet the requirements of flash/PSRAM’s working voltage.

2.1.2 Analog Power Supply

Pin1, pin3, pin4, pin20, pin51, and pin54 are the analog power supply pins, working at 2.8 V ~ 3.6 V. It should be
noted that the sudden increase in current draw, when ESP32-S2 is in transmission mode, may cause a power rail
collapse. Therefore, it is highly recommended to add another 10 µF capacitor to the power trace, which can work
5 4 3 2

in conjunction with the 0.1 µF capacitor. In addition, a CLC filter circuit needs to be added near the power pins GND

(pin3 and pin4) so as to suppress high-frequency harmonics. The inductor’s rated current is
GNDpreferably 500 mA or

3
GND Y1
The values of C1 and C4 vary with

GND

GND XOUT
above. Refer to Figure 3 and place the appropriate decoupling
D
capacitor near
the selection of the crystal.
C1 each analog power
C4 pin.
The value of R4 varies with the actual

XIN
TBD TBD
PCB board.

2
VDD33

C2 C3 GND
R4
100pF 1uF
0 40MHz (±10ppm)
VDD33
GND GND CHIP_PU
GPIO46
GPIO45
C5 U0RXD
R3 499 U0TXD
0.1uF GPIO42
GPIO41
C GPIO40
VDD33 GND GND GPIO39

L1 2.0nH

C6 C7 C8 C9 C10 VDD33
57

56
55
54
53
52
51
50
49
48
47
46
45
44
43
10uF 1uF 0.1uF TBD 0.1uF
GND

CHIP_PU
GPIO46
VDDA
XTAL_P
XTAL_N
VDDA
GPIO45
U0RXD
U0TXD
MTMS

MTDO
MTCK
MTDI
VDD3P3_CPU
GND GND GND GND GND R8
10K(NC)
ANT2 1 42 GPIO38 U
1 RF_ANT L2 TBD LNA_IN 2 VDDA GPIO38 41 GPIO37
2 3 LNA_IN GPIO37 40 GPIO36 SPICS0 1
4 VDD3P3 GPIO36 39 GPIO35
C11 C12
PCB ANT GPIO0 5 VDD3P3 GPIO35 38 GPIO34 SPICLK 6
TBD TBD GPIO1 6 GPIO0 GPIO34 37 GPIO33
GPIO2 7 GPIO1 GPIO33 36 SPID SPIHD 7
GPIO3 8 GPIO2 SPID 35 SPIQ
GPIO4 9 GPIO3 SPIQ 34 R10 0 SPICLK
B GND GND GND
GPIO5 10 GPIO4 SPICLK 33 SPICS0
GPIO6 11 GPIO5 SPICS0 32 SPIWP
The values of C11, L2 and C12 GPIO6 SPIWP
vary with the actual PCB board. GPIO7 12 31 SPIHD NC: No compon
GPIO8 13 GPIO7 SPIHD 30
VDD3P3_RTC_IO

GPIO9 14 GPIO8 VDD_SPI 29 GPIO26 SPICS1

VDD3P3_RTC

GPIO9 SPICS1
XTAL_32K_N
XTAL_32K_P

VDD_SPI
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

GPIO19
GPIO20

GPIO21
DAC_1
DAC_2

C13 C14
R9
U1 ESP32-S2 0.1uF 1uF
15
16
17
18
19
20
21
22
23
24
25
26
27
28

10K(NC) U

GND GND SPICS1 1

VDD33 R11 10K VDD33
SPICLK 6

SPIHD 7
A C15 C16

0.1uF 0.1uF
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20

GPIO21

GND GND

Figure 3: ESP32-S2 Analog Power Supply Pins

5 4 3 2

Notice:

• The recommended voltage of the power supply for ESP32-S2 is 3.3 V, and its recommended output current is 500
mA or more.

• It is suggested that users add an ESD protection diode at the power entrance.

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2. Schematic Checklist

2.2 Power-on Sequence and System Reset

2.2.1 Power-on Sequence
ESP32-S2 uses a 3.3 V system power supply. The chip should be activated after the power rails have stabilized.
This is achieved by delaying the activation of CHIP_PU after the 3.3 V rails have been brought up. More details
can be found in Section Power Scheme in ESP32-S2 Datasheet.

Notice:
To ensure the power supply to the ESP32-S2 chip during power-up, it is advised to add an RC delay circuit at the
CHIP_PU pin. The recommended setting for the RC delay circuit is usually R = 10 kΩ and C = 0.1 µF. However,
specific parameters should be adjusted based on the power-up timing of the power supply and the power-up and
reset sequence timing of the chip.

2.2.2 Reset
CHIP_PU serves as the reset pin of ESP32-S2. The reset voltage (VIL_nRST ) should meet the requirements speci-
fied in Section DC Characteristics in ESP32-S2 Datasheet. To avoid reboots caused by external interferences, route
the CHIP_PU trace as short as possible, and add a pull-up resistor as well as a capacitor to the ground whenever
possible.

Notice:
CHIP_PU pin must not be left floating.

2.3 Flash (compulsory) and SRAM (optional)

ESP32-S2 can support up to 1 GB external flash and 1 GB external SRAM. The ESP32-S2-WROVER module
uses a 4 MB SPI flash and 2 MB PSRAM, powered by VDD_SPI. Make sure to select the appropriate flash and
PSRAM according to the power voltage on VDD_SPI. We recommend reserving a serial resistor (a 0 Ω resistor
can be used initially) on the SPI communication line, to lower the driving current, reduce interference to RF, adjust
timing, and improve anti-interference ability.

The schematic for ESP32-S2 flash and SRAM is shown in Figure 4.

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 GPIO45
U0RXD
R3 499 U0TXD
2. Schematic Checklist GPIO42
GPIO41
GPIO40 C
GPIO39

C10 VDD33 VDD_SPI

50
49
48
47
46
45
44
43

0.1uF
VDDA
GPIO45
U0RXD
U0TXD
MTMS

MTDO
VDD3P3_CPU

MTCK
MTDI

GND R8
10K(NC)

8
42 GPIO38 U2
GPIO38 41 GPIO37

VCC
GPIO37 40 GPIO36 SPICS0 1 5 SPID
GPIO36 39 GPIO35 /CS DI
GPIO35 38 GPIO34 SPICLK 6 2 SPIQ
GPIO34 37 GPIO33 CLK DO
GPIO33 36 R13 0 SPID SPIHD 7 3 SPIWP

GND
SPID 35 R14 0 SPIQ /HOLD /WP
SPIQ 34 R10 0 SPICLK B
SPICLK 33 SPICS0 FLASH-3V3

4
SPICS0 32 R15 0 SPIWP
SPIWP 31 R16 0 SPIHD
SPIHD NC: No component.
30 GND
VDD3P3_RTC_IO

VDD_SPI 29 GPIO26 SPICS1

VDD3P3_RTC

SPICS1 VDD_SPI
XTAL_32K_N
XTAL_32K_P

VDD_SPI
GPIO19
GPIO20

GPIO21
DAC_1
DAC_2

C13 C14
R9
ESP32-S2 0.1uF 1uF
21
22
23
24
25
26
27
28

10K(NC)

8
U3

VDD
GND GND SPICS1 1 5 SPID
R11 10K VDD33 CS SI/SIO0
SPICLK 6 2 SPIQ
SCLK SO/SIO1
SPIHD 7 3 SPIWP

VSS
C16 SIO3 SIO2
A

0.1uF PSRAM-3V3 (Optional)

GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20

GPIO21

GND GND

Figure 4: ESP32-S2 Flash and SRAM

3 2 1

2.4 Crystal Oscillator

There are two clock sources for the ESP32-S2, that is, an external crystal oscillator clock source and an RTC clock
source.

2.4.1 External Clock Source (compulsory)

Currently, the ESP32-S2 firmware only supports 40 MHz crystal oscillator. The specific capacitive values of C1 and
C4 depend on further testing of, and adjustment to, the overall performance of the whole circuit. It is recommended
that users reserve a series resistor (a 0 Ω resistor can be used initially) on the XTAL_P clock trace to reduce the
drive strength of the crystal, as well as to minimize the impact of crystal harmonics on RF performance. Note that
the accuracy of the selected crystal is ±10 ppm.

Figure 5 and Figure 6 show the schematics for crystal and crystal oscillator in ESP32-S2.

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 12

F
rd.

F
2. Schematic Checklist

TBD

TBD LAN_IN

2.0nH
C12
GND

GND

GND

GND

PCB board.
The value of R4 varies with the actual TBD

the selection of the crystal.

The values of C1 and C4 vary with
1uF
TBD

C9

0.1uF

C5

C3
Notice:
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0 • If an oscillator is used, its output should be connected to XTAL_P on the chip through a DC blocking capacitor

B
(about 50 pF). XTAL_N can be floating. Please make sure that the oscillator output is stable and its accuracy is
within ±10 ppm. It is also recommended that the circuit design for the oscillator is compatible with the use of

4
crystal, in case that if there is a defect in the circuit design, users can still use the crystal.
14
13
12
11
10
9
8
7
6
5
4
3
2
1

• Defects in the craftsmanship of the crystal oscillators (for example, large frequency deviation of more than ±10 ppm,
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
VDD3P3
VDD3P3
LNA_IN
VDDA

unstable performance within operating temperature range, etc) may lead to the malfunction of ESP32-S2, resulting

GND
57
in a decrease ofGND
the RF performance.

PCB ANT

ANT1
vary with
The values of C11, L2 and C12
56
CHIP_PU 55
GPIO46 54

2
1
C1
VDDA

GNDthe actual
53
5

XTAL_P 52

0
R4
XTAL_N 51

GND
RTC VDDA 50
_P GPIO45

GND
49 1 4

40MHz (±10ppm)
_N U0RXD 48 XIN GND

RF_ANT
U0TXD 47

Y1 selection
MTMS 46
MTDI CLK_32K C17 TBD GPIO15

GND
45 2 3
VDD3P3_CPU GND XOUT

TBD

C11
44
RTC_IO MTDO 43

GND
MTCK

3
GNDof a PCB board.

L2
VDD_SPI

GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
SPICS1

SPICS0
SPICLK

TBD

C4
SPIWP
SPIHD

SPIQ
SPID

Figure 5: Schematic for ESP32-S2’s Crystal

VDD33
29
30
31
32
33
34
35
36
37
38
39
40
41
42

TBD

TBD LAN_IN
C12
GND
R10

GND
R3

Y1
0.1uF

C10

VDD33
GPIO26

R4 0 4 3 C4 TBD R5 0 XTAL_P
VCC OUT
0

499

C1 1 2
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
NC GND
10nF
0.1uF
SPICS1

SPIHD
SPIWP
SPICS0
SPICLK
SPIQ
SPID
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38

GPIO39
GPIO40
GPIO41
GPIO42
U0TXD
U0RXD
GPIO45
GPIO46
CHIP_PU

40MHz(±10ppm)
VDD33

C15
4

GND

GND GND

Figure 6: Schematic for ESP32-S2’s Crystal Oscillator

14
13
12
11
10

28
9

7
6
5
4
3
2
1
U1
GPIO12
GPIO11

GPIO10

GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
VDD3P3
VDD3P3
LNA_IN
VDDA
NC: No component.

SPIHD

SPICLK

SPICS0

10K(NC)

2.4.2 RTC (optional)

R8

ESP32-S2 supports an external 32.768 kHz crystal or an external signal (e.g., an oscillator) to act as the RTC sleep
clock.
7

15
U2

GPIO10 C
/HOLD

CLK

/CS

Figure 7 shows the schematic for the external 32.768 kHz crystal. 16 GPIO11
17
18 GPIO12
VDD_SPI

VDD_SPI

19 GPIO13 X
GND

4 8
GND

GND VCC C17 TBD

20 GPIO14 X
R12
FLASH-3V3

GPIO15 21 VDD3P3_RTC
1

X1
/WP

GPIO16 22 XTAL_32K_P
DO

DI

32.768kHz 23 XTAL_32K_N
TBD
2

24 DAC_1
3

GND

C18 TBD 25 DAC_2

1

26 GPIO19
SPIWP

SPIQ

SPID

27 GPIO20 VDD3P
3

Figure 7: Schematic for ESP32-S2’s External28 VDD3P3_RTC_IO

Crystal (RTC)
GPIO21
VDD_SPI
ESP32-S2

GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
SPICS1

SPICS0
SPICLK
SPIWP

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SPIQ
SPID

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GPIO21
B

2
3
3
3
3
3
3
3
3
3
3
4
4
4
 2. Schematic Checklist

Notice: 5 4

• Please note the requirements for the 32.768 kHz crystal.

– Equivalent series resistance (ESR) ⩽ 70 kΩ. GN
– Load capacitance at both ends should be configured according to the crystal’s specification.

• The parallel resistor R12 is used for biasing the crystal circuit (5 MΩ < R12 ⩽ 10 MΩ). In general, users do not need

4
GND
to populate R12.

• If the RTC source is not required, then pin21 (XTAL_32K_P) and pin22 (XTAL_32K_N) can be used as general
The values of C1 and C4 vary with C1
D GPIOs.
the selection of the crystal.
TBD
The
18 value of R4 varies with the actual
Figure 8 shows the schematic of the external signal. PCB board.

1
VDD33 19 GPIO13
20 GPIO14
CLK_32K C17 TBD GPIO15 21 VDD3P3_RTC
C2 22 XTAL_32K_P
C3
23 XTAL_32K_N R4
100pF 24 DAC_1
1uF
0 40
Figure 8: Schematic of External DAC_2
25 Oscillator
VDD33
GND GND
The external signal can be input to XTAL_32K_P through a DC blocking capacitor (about 20 pF). XTAL_32K_N can
be floating. The signal should meet the following requirements: C5

XTAL_32K_P input 0.1uF(Vpp, unit: V)

Amplitude

C
Sine wave or square wave 0.6 < Vpp < VDD
VDD33 GND GND

L1 2.0nH
2.5 RF C6 C7 C8 C9

57

56
55
54
53
52
51
50
49
The impedance 10uF
matching point1uF
for the RF 0.1uF
pin (pin2) of ESP32-S2
TBDis (34+j5) Ω. A π-type matching network is
GND

CHIP_PU
GPIO46
VDDA
XTAL_P
XTAL_N
VDDA
GPIO45
essential for antenna matching in the circuit design. CLC structure is recommended for the matching network.
Figure 9 shows the RF matching schematic.
GND GND GND GND

ANT2 1
1 RF_ANT L2 TBD LNA_IN 2 VDDA
2 3 LNA_IN
4 VDD3P3
C11 C12
PCB ANT GPIO0 5 VDD3P3
TBD TBD GPIO1 6 GPIO0
GPIO2 7 GPIO1
GPIO3 8 GPIO2
GPIO4 9 GPIO3
B GND GND GND
GPIO5 10 GPIO4
GPIO6 11 GPIO5
The values of C11, L2 and C12 GPIO6
vary with the actual PCB board. GPIO7 12
GPIO8 13 GPIO7
GPIO9 14 GPIO8
VDD3P3_RTC

GPIO9
XTAL_32K_P

Figure 9: ESP32-S2 RF Matching Schematic

GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

Note:
The parameters of the components in the matching network are subject to the actual antenna andU1
PCB layout.
15
16
17
18
19
20
21
22

VDD33

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A C15
2. Schematic Checklist

2.6 UART
Users need to connect a 499 Ω resistor to the U0TXD line in order to suppress the 80 MHz harmonics. GPIO18
works as U1RXD and is in an uncertain state when the chip is powered on, which may affect the chip’s entry into
download boot mode. To solve this issue, add an external pull-up resistor.

2.7 USB
The ESP32-S2 has a full-speed USB OTG peripheral with integrated transceivers and is compliant with the USB
1.1 specification. GPIO19 and GPIO20 can be used as D- and D + of USB respectively. It is recommended to
reserve series resistor and capacitor to the ground on each line, and place them close to the chip side.

2.8 ADC
It is recommended that users add a 0.1 µF filter capacitor to a pad when using the ADC function.

2.9 Touch Sensor

When using the touch function, it is recommended to reserve a series resistor at the chip side to reduce the coupling
noise and interference on the line, and to strengthen the ESD protection. The recommended resistance is from
470 Ω to 2 kΩ, preferably 510 Ω. The specific value also depends on the actual test results of the product.

The ESP32-S2 touch sensor adopts a waterproof design. Note that only GPIO14 (TOUCH14) can drive the shield
electrode.

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3. PCB Layout Design

3. PCB Layout Design

This chapter introduces the key points of designing ESP32-S2 PCB layout with the example of ESP32-S2 mod-
ule.

While the high level of integration makes the PCB design and layout process simple, the performance of the system
strongly depends on system design aspects. To achieve the best overall system performance, please follow the
guidelines specified in this document for circuit design and PCB layout. All the common rules associated with
good PCB design still apply and this document is not an exhaustive list of good design practices.

The ESP32-S2 PCB layout design is shown in Figure 10.

Figure 10: ESP32-S2 PCB Layout

3.1 General Principles of PCB Layout

We recommend a four-layer PCB design.

• The first layer is the TOP layer for signal traces and components.

• The second layer is the GND layer without signal traces being routed so as to ensure a complete GND plane.

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3. PCB Layout Design

• The third layer is the POWER layer where a GND plane should be applied to better isolate the RF and crystal
oscillator part. It is acceptable to route signal traces on this layer, provided that there is a complete GND
plane under the RF and crystal oscillator.

• The fourth layer is the BOTTOM layer, where power traces are routed. Placing any components on this layer
is not recommended.

Below are the suggestions for a two-layer PCB design.

• The first layer is the TOP layer for traces and components.

• The second layer is the BOTTOM layer. Please do not place any components on this layer and keep traces
to a minimum. Ideally, it should be a complete GND plane.

3.2 Positioning an ESP32-S2 Module on a Base Board

If users adopt module-on-board design, they should pay attention to the layout of the module on the base board.
The interference of the base board on the module’s antenna performance should be minimized.

The module should be placed as close to the edge of the base board as possible. The PCB antenna area should
be placed outside the base board whenever possible. In addition, the feed point of the antenna should be closest
to the board, as Figure 11 shows.

1 2 3 ✅

Base Board

5 4 ✅

Figure 11: ESP32-S2 Module Antenna Position on Base Board

Note:
As is shown in Figure 11, the recommended position of ESP32-S2 module on the base board should be:
• Position 3, 4: Highly recommended;
• Position 1, 2, 5: Not recommended.

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3. PCB Layout Design

If the positions recommended are not feasible, please make sure that the module is not covered by any metal shell.
Besides, the antenna area of the module and the area 15 mm outside the antenna should be kept clean, (namely
no copper, routing, components on it) as shown in Figure 12.

Clearance

15 mm

15 mm

15 mm
Base Board

Figure 12: Keepout Zone for ESP32-S2 Module’s Antenna on the Base Board

If there is base board under the antenna area, it is recommended to cut it off to minimize its impact on the antenna.
When designing an end product, pay attention to the impact of enclosure on the antenna.

3.3 Power Supply

• Four-layer PCB design is recommended over two-layer design. Route the power traces on the fourth (bottom)
layer whenever possible. Vias are required for the power traces to go through the layers and get connected
to the pins on the top layer. There should be at least two vias if the main power traces need to cross layers.
The drill diameter on other power traces should be no smaller than the width of the power traces.

• The 3.3 V power traces, highlighted in yellow, are routed as shown in Figure 13. The width of the main power
traces should be at least 25 mil. The width of the power traces for pin3 and pin4 should be at least 20 mil.
The width of other power traces is preferably 10 mil.

• As shown in Figure 13, an ESD protection diode is placed close to the power port (marked in red circle). A
10 µF capacitor is required before the power trace connects the ESP32-S2 chip, to be used in conjunction
with a 0.1 µF capacitor. Then the power traces are divided into two ways from here and form a star-shape
topology, thus reducing the coupling between different power pins. Note that all decoupling capacitors
should be placed close to the power pin, and ground vias should be added adjacent to the ground pin for
the decoupling capacitors to ensure a short return path.

• The power supply for the PA is provided by pin3 and pin4. It is required to add GND isolation between this
power trace and the GPIO traces on the left, and place ground vias as much as possible.

• The ground pad at the bottom of the chip should be connected to the ground plane through at least nine
ground vias.

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3. PCB Layout Design

Note:
If you need to add a thermal pad EPAD under the chip on the bottom of the module, it is recommended to employ a
nine-grid on the EPAD, cover the gaps with ink, and place ground vias in the gaps, as shown in Figure 13. This can avoid
tin leakage when soldering the module EPAD to the substrate.

Figure 13: ESP32-S2 Power Traces in a Four-layer PCB Design

3.4 Crystal Oscillator

Figure 14 shows the reference design of the crystal oscillator. In addition, the following should be noted:

• The crystal oscillator should be placed far from the clock pin to avoid the interference on the chip. The gap
should be at least 2.0 mm. It is good practice to add high-density ground via stitching around the clock
trace for better isolation.

• There should be no vias for the clock input and output traces, which means the traces cannot cross layers.

• The external regulating capacitor should be placed on the near left or right side of the crystal oscillator, and
at the end of the clock trace whenever possible, to make sure the ground pad of the capacitor is close to
that of the crystal oscillator.

• Do not route high-frequency digital signal traces under the crystal oscillator. It is best not to route any signal
trace under the crystal oscillator. The vias on the power traces on both sides of the crystal clock trace
should be placed as far away from the clock trace as possible, and the two sides of the clock trace should
be surrounded by grounding copper.

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3. PCB Layout Design

• As the crystal oscillator is a sensitive component, do not place any magnetic components nearby that may
cause interference, for example large inductance component, and ensure that there is a clean large-area
ground plane around the crystal oscillator.

Figure 14: ESP32-S2 Crystal Oscillator Layout

3.5 RF
In a four-layer PCB design, the RF trace is routed as shown highlighted in pink in Figure 15.

• The RF trace should have 50 Ω single-ended characteristic impedance. The reference plane is the second
layer. A π-type matching circuitry should be reserved on the RF trace and placed close to the chip.

• Make sure to keep the width of the RF trace consistent, and do not branch the trace. The RF trace should
be as short as possible with dense ground via stitching around it for isolation.

• The RF trace should be routed on the outer layer without vias, i.e., should not cross layers. The RF trace
should be routed at a 135° angle, or with circular arcs if trace bends are required.

• The ground plane on the adjacent layer needs to be complete. Do not route any traces under the RF trace
whenever possible.

• There should be no high-frequency signal traces routed close to the RF trace. The RF antenna should be
placed away from high-frequency transmitting devices, such as crystal oscillators, DDR, and clocks, etc. In
addition, the USB port, USB to UART chip, UART signal lines (including traces, vias, test points, header pins,
etc.) must be as far away from the antenna as possible. It is good practice to add ground vias around the
UART signal line.

• When doing 50 Ω single-ended impedance control for the RF trace, please refer to the PCB stack-up design
shown in Figure 16.

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3. PCB Layout Design

Figure 15: ESP32-S2 RF Layout in a Four-layer PCB Design

Thickness (mm) Impedance (Ohm) Gap (mil) Width (mil) Gap (mil)

- 50 12.2 12.6 12.2

Base copper Thickness DK

Stack up Material
(oz) (mil)

SM 0.4 4

L1_Top Finished copper 1 oz 0.33 0.8

PP 7628 TG150 RC50% 8 4.39

L2_Gnd 1 1.2

Core Core Adjustable 4.43

L3_Power 1 1.2

PP 7628 TG150 RC50% 8 4.39

L4_Bottom Finished copper 1 oz 0.33 0.8

SM 0.4 4

Figure 16: ESP32-S2 PCB Stack-up Design

3.6 Flash and PSRAM

Place the reserved serial resistor on the SPI communication line close to the chip side. Route the SPI traces on
the inner layer (e.g., the third layer) whenever possible. Add ground vias around the clock and data traces of SPI
separately. The layout of the flash and PSRAM on ESP32-S2 is shown in Figure 17.

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3. PCB Layout Design

Figure 17: ESP32-S2 Flash and PSRAM Layout

3.7 UART
The series resistor on the U0TXD line needs to be placed as close to the chip and far from the crystal oscillator as
possible. The U0TXD and U0RXD traces on the top layer should be as short as possible. Employ vias around the
traces for isolation.

3.8 USB
Place the RC circuit reserved on the USB lines close to the chip. Route the USB traces on the inner layer (third
layer) whenever possible. Please use differential routing and make each trace the same length. Make sure there is
a complete reference ground plane. Note to surround the USB traces with ground copper.

3.9 Touch Sensor

ESP32-S2 offers up to 14 capacitive IOs that detect changes in capacitance on touch sensors due to finger contact
or proximity. The chip’s internal capacitance detection circuit features low noise and high sensitivity. It allows users
to use touch pads with smaller area to implement the touch detection function. Users can also use the touch panel
array to detect a larger area or more test points. Figure 18 depicts a typical touch sensor application.

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3. PCB Layout Design

Protective cover
Substrate

ESP32-S2

C
Electrode

Figure 18: A Typical Touch Sensor Application

In order to prevent capacitive coupling and other electrical interference to the sensitivity of the touch sensor system,
the following factors should be taken into account.

Electrode Pattern

The proper size and shape of an electrode improves system sensitivity. Round, oval, or shapes similar to a hu-
man fingertip is commonly applied. Large size or irregular shape might lead to incorrect responses from nearby
electrodes.

Figure 19: Electrode Pattern Requirements

Note:
The examples illustrated in Figure 19 are not of actual scale. It is suggested that users use a human fingertip as reference.

PCB Layout
The following are general guidelines to routing traces, as shown in Figure 20:

• The trace should be as short as possible and not exceed 300 mm.

• The trace width (W) can not be larger than 0.18 mm (7 mil).

• The alignment angle (R) should not be less than 90°.

• The trace-to-ground gap (S) should be in the range of 0.5 mm to 1 mm.

• The electrode diameter (D) should be in the range of 8 mm to 15 mm.

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3. PCB Layout Design

• Hatched ground should be added around the electrodes and traces.

• The traces should be isolated well and routed away from that of the antenna.

Figure 20: Sensor Track Routing Requirements

In addition, ESP32-S2 touch sensor adopts a waterproof design and features proximity sensor function. Figure 21
shows an example layout of a waterproof and proximity sensing design.

Note the following guidelines to better implement the above functions:

• It is recommended that the width of the shield electrode width is 2 cm.

• Employ a grid on the top layer with a trace width of 7 mil and a grid width of 45 mil (25% fill). The filled grid
is connected to the driver shield signal.

• Employ a grid on the bottom layer with a trace width of 7 mil and a grid width of 70 mil (17% fill). The filled
grid is connected to the driver shield signal.

• The protective sensor should be in a rectangle shape with curved edges and surround all other sensors.

• It is recommended that the width of the protective sensor is 2 mm.

• It is recommended that the gap between the protective sensor and shield sensor is 1 mm.

• The sensing distance of the proximity sensor is directly proportional to the area of the proximity sensor.
However, increasing the sensing area will introduce larger noise. Actual testing is needed for optimized
performance.

• It is recommended that the shape of the proximity sensor is a closed loop. The recommended width is 1.5
mm.

Note:
For more details on the hardware design of ESP32-S2 touch sensor, please refer to Touch Sensor Application Note.

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3. PCB Layout Design

Touch sensor (TOUCH1 ~ TOUCH14)

Protective sensor (TOUCH1 ~ TOUCH14)

Shied electrode

Figure 21: Shied Electrode and Protective Sensor

3.10 Typical Layout Problems and Solutions

3.10.1 Q: The current ripple is not large, but the TX performance of RF is rather poor.
Analysis:

The current ripple has a strong impact on the RF TX performance. It should be noted that the ripple must be
tested when ESP32-S2 is in the normal working mode. The ripple increases when the power gets high in a
different mode.

Generally, the peak-to-peak value of the ripple should be <80 mV when ESP32-S2 sends MCS7@11n packets,
and <120 mV when ESP32-S2 sends 11m@11b packets.

Solution:

Add a 10 µF filter capacitor to the branch of the power trace (the branch powering the ESP32-S2 analog power
pin). The 10 µF capacitor should be as close to the analog power pin as possible for small and stable current
ripples.

3.10.2 Q: The power ripple is small, but RF TX performance is poor.

Analysis:

The RF TX performance can be affected not only by power ripples, but also by the crystal oscillator itself. Poor
quality and big frequency offsets of the crystal oscillator decrease the RF TX performance. The crystal oscillator
clock may be corrupted by other interfering signals, such as high-speed output or input signals. In addition, high-
frequency signal traces, such as the UART trace under the crystal oscillator, could also result in the malfunction of
the crystal oscillator. Besides, sensitive components or radiation components, such as inductors and antennas,
may also decrease the RF performance.

Solution:

This problem is caused by improper layout and can be solved by re-layout. Please see Section 3 for details.

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3. PCB Layout Design

3.10.3 Q: When ESP32-S2 sends data packages, the power value is much higher or
lower than the target power value, and the EVM is relatively poor.
Analysis:

The disparity between the tested value and the target value may be due to signal reflection caused by the impedance
mismatch on the transmission line connecting the RF pin and the antenna. Besides, the impedance mismatch will
affect the working state of the internal PA, making the PA prematurely access the saturated region in an abnormal
way. The EVM becomes poor as the signal distortion happens.

Solution:

Match the antenna’s impedance with the reserved π-type circuit on the RF trace, so that impedance of the antenna
as seen from the RF pin matches closely with that of the chip. This reduces reflections to the minimum.

3.10.4 Q: TX performance is not bad, but the RX sensitivity is low.

Analysis:

Good TX performance indicates proper RF impedance matching. External coupling to the antenna can affect the
RX performance. For instance, the crystal oscillator signal harmonics could couple to the antenna. If the TX and
RX traces of UART cross over with RF trace, then, they will affect the RX performance, as well. If there are many
high-frequency interference sources on the board, signal integrity should be considered.

Solution:

Keep the antenna away from crystal oscillators. Do not route high-frequency signal traces close to the RF trace.
Please see Section 3 for details.

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4. Hardware Development

4. Hardware Development
Espressif designs and manufactures a large variety of modules and boards to help users evaluate functionality of
the ESP32-S2 chip.

4.1 ESP32-S2 Modules

For a list of ESP32-S2 modules please check Modules section of Espressif website.

To review module reference designs please check Documentation section of Espressif website.

Notes on Using Modules

• The module uses one single pin as the power supply pin. Users can connect the module to a 3.3 V power
supply that can drive at least 500 mA output current. The 3.3 V power supply works both for the analog
circuit and the digital circuit.

• The EN pin is used for enabling the module. Set the EN pin high for normal working mode. There is no RC
delay circuit on the module. It is recommended that users add an external RC delay circuit to the module.
For details please refer to Section 2.2.

• Lead the GND, RXD, TXD pins out and connect them to a USB-to-UART tool for firmware download, log-
printing and communication.

By default, the initial firmware has already been downloaded in the flash. If users need to re-download the firmware,
they should follow the steps below:

1. Set the module to UART Download mode by pulling IO0 (pulled up by default) and IO46 (pulled down by
default) low.

2. Power on the module and check through the serial terminal if the UART Download mode is enabled.

3. Download the firmware to flash, using the Flash Download Tool.

4. After downloading, pull IO0 high and enable the SPI Boot mode.

5. Power on the module again. The chip will read and execute the firmware during initialization.

Notice:

• During the whole process, users can check the status of the chip with the log printed through UART. If the firmware
cannot be downloaded or executed, users can check if the working mode is normal during the chip initialization by
looking at the log.

• The serial tool cannot be used for both the log-print and flash-download tools simultaneously.

4.2 ESP32-S2 Development Boards

For a list of the latest designs of ESP32-S2 boards please check Development Boards section of Espressif web-
site.

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Revision History

Revision History

Date Version Release notes

2020-05-07 V1.0 First release

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