La-A998p R01 Szso40 PDF

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1 1
2
Compal Confidential 2
SLC M/B Schematics Document

14": Tabo; 15.6" Pochacco
Intel Ivy Bridge ULV Processor with DDRIII + Panther Point
3 Date : 2013/11/13 3
Version 0.1
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A999P
Date: Friday, March 14, 2014 Sheet 1 of 58
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A B C D E
Intel 204pin DDR3L-SO-DIMM X2

Memory BUS(DDR3L) Dual Channel
NVIDIA N15V-GM (GB2-64) PEG x8 BANK 0, 1, 2, 3 page12,13
Gen2 / Gen3
Processor
595 ball BGA 23x23mm 1.35V DDR3L 1600MHz
1
Ivy Bridge 1
VRAM x 4 page 22~29

ULV Processor
FCBGA 1023
eDP
31mm*24mm
1 lane
FDI *8 DMI2 *4 Port 8 Port 9 Port 10

2.7GT/s 5GT/s USB WLAN Touch
Camera BT Combo Screen
eDP/LVDS LVDS page30 page33 page30
Conn.
page30 USB2.0
DDPB
HDMI Conn. Port 0 Port 1 Port 2
page31
Port 1 USB3.0 USB2.0 USB2.0
2 USB3.0 2
Conn.X1 Conn. Conn.

CRT Conn. VGA Intel page36 page36 page36
page 32
PCH
Debug port
Panther Point
PCIe SATA
FCBGA 989Balls
SATA III SATA I
GPP2 GPP1 GPP3 25mm x 25mm Port 0 Port2
Card Reader MINI Card Giga LAN HDD ODD
RTS5239 (WLAN/BT) RTL8151 Conn. Conn.
page35 page34 page34
page33 page35
HD Audio(AZ)
Card Reader
Transformer
3 Conn. 3
page35 RJ45
page35 page 14~22 Audio
Sub-borad SPI LPC ALC3227
page37
RTC CKT
USB/B BIOS (8M)
page24 ENE
POWER On/Off CKT KBC9012
Int. Speaker Combo Jacks
PWR BTN/B page41 Conn. page37 page37
page28
DC/DC Interface CKT
TP BTN/B
page27 Int.KBD Touch Pad FAN/LED
4 4
page38 page38 page39

2012/12/01 2013/07/10 Title
Issued Date Deciphered Date Block Diagrams
Size Document Number Rev
Custom 0.1
LA-A999P
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ZSO40/50 (LA-A998P/LA-A999 Ver:0.1) STATE

SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
BATT+ Battery power supply (12.6V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
1 +CPU_CORE Core voltage for CPU ON OFF OFF 1
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
ON OFF OFF
+VGFX_CORE Core voltage for UMA graphic ON OFF OFF
+0.675VS +0.675VP to +0.675VS switched power rail for DDR3L terminator ON OFF OFF
Power Plane Description S1 S3 S5
+1.05VS_VCCP +V1.05SP to +1.05VS_VCCP switched power rail for CPU ON OFF OFF +3VGS GPU power PX OFF OFF
+VCCP +VCCP (1.05V ) power for PCH ON OFF OFF
+VGA_CORE GPU power PX OFF OFF
+1.35V +1.35V_VDDQP to +1.35V power rail for DDR3L ON ON OFF
+1.5VS +1.5VS switched power rail ON OFF OFF +1.05VGS GPU power PX OFF OFF
+1.5VGS GPU power PX OFF OFF

+1.8VS (+3VALW ) to 1.8V LDO power rail to PCH ON OFF OFF
+3VALW +3VALW always on power rail ON ON ON*
+3VALW_EC +3VL to KBC ON ON ON*
+LAN_VDD_3V3 +3VALW to +LAN_VDD_3V3 power rail for LAN ON ON ON*
+3V_PCH +3VALW to +3V_PCH power rail for PCH (Short Jumper) ON ON ON*
EC SM Bus1 address PCH SM Bus address
+3VS +3VALW to +3VS power rail ON OFF OFF
Device Address
+5VALW +5VALWP to +5VALW power rail ON ON ON* Device Address
DDR DIMM0
+5V_PCH +5VALW to +5V_PCH power rail for PCH (Short resister) ON ON ON* Smart Battery
DDR DIMM1
+5VS +5VALW to +5VS switched power rail ON OFF OFF G-sensor 0x50/0x52
2 +RTCVCC RTC power ON ON ON Charger IC BQ24738 0xFFH 2
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. EC SM Bus2 address
Device Address
PCH SML1 CLKOUT DESTINATION
N15V-GE dGPU
PCI0 PCH_LPBACK
SMBUS Control Table
PCI1 PCI_LPC/TPM
WLAN BATT EC_SMB_CK2 PCH_SML1CLK
BATT TP SODIMM G-Sensor dGPU
SOURCE MIINI1 Charger EC_SMB_DA2 PCH_SML1DATA PCI2 None
EC_SMB_CK1 KB9012
EC_SMB_DA1
V V V PCI3 None
EC_SMB_CK2 KB9012
EC_SMB_DA2 V V PCI4 None
PCH_SMBCLK
PCH_SMBDATA
PCH
V USB Port Table
PCH_SML0CLK PCH 3 External
3
PCH_SML0DATA SATA DESTINATION USB 2.0 USB 1.1 Port 3
USB Port
PCH_SML1CLK
PCH_SML1DATA
PCH
V SATA0 JHDD1 UHCI0
0 USB2.0 (For USB3.0 Conn.)
1 USB2.0 (D/B)
SATA1 None 2 USB2.0 (D/B)
UHCI1
BY SKU 3 None
DIFFERENTIAL DESTINATION FLEX CLOCKS DESTINATION EHCI1
SATA2 JODD1 4 None
TPM 9635@ 9656@ UHCI2
5 None
CLKOUTFLEX0 None CPUUMA1@ 6
CLKOUT_PCIE0 mini WLAN SATA3 None UHCI3 None
CPU CPUUMA2@ 7 None
CLKOUTFLEX1 None CPUDIS@ 8 Camera
SATA4 None UHCI4
CARD READER 9 Mini Card(WLAN& BT)
X76@ SAM@
CLKOUT_PCIE1 CLKOUTFLEX2 None VRAM 10 Touch Screen
SATA5 None EHCI2 UHCI5
MIC@ HY@ 11 None
CLK CLKOUT_PCIE2 PCIE LAN CLKOUTFLEX3 DGPU_PRSNT# 12
UHCI6 None
13 None
CLKOUT_PCIE3 None
Symbol Note :
CLKOUT_PCIE4 None : means Digital Ground Option @ CONN@ SP@ PX@ UMA@ DIS@ USB 3.0 Port
2 External
USB Port
UMA X X V X V X
1 USB3.0 (left Side)
4 DIS X X V V X V 4
CLKOUT_PCIE5 None
: means Analog Ground 2
3
None
None
CLKOUT_PCIE6 None
4 None
Project ID UMA@ DIS@
CLKOUT_PCIE7 None
LA-A998P LA-A999P 2011/06/29 2011/06/29 Title
CLKOUT_PEG_B None PCB
Issued Date Deciphered Date
Notes List
14@ 15@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A999P
A B C D E
5 4 3 2 1
D D
C C
B B
A A
Security Classification Compal Secret Data

PROCESSOR(1/7) DMI,FDI,PEG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.1
5 4 3 2 1
5 4 3 2 1
UCPU1 CPUDIS01@
i5-2467M CPU
SA00004X000 PEG_ICOMPI and RCOMPO signals should be
Sandy Bridge: shorted and routed
Intel Core i5-2467M: SA00004X000 (4619HY32L01) with - max length = 500 mils - typical
UCPU1 CPUDIS02@ impedance = 43 mohms
i5-2367M CPU Ivy Bridge: +VCCP
PEG_ICOMPO signals should be routed with -
SA000051H20
UCPU1 CPUUMA3@ UCPU1 CPUUMA1@
1.5GHz GT2 ES2 QBP8: SA00005AZ10 (4619HZ32L01) max length = 500 mils
i5-2367M CPU 17W 1.5GHz GT2 ES2 QBP8 1.5GHz ES2 QBTP: SA00005AZ20(4619HZ32L02) - typical impedance = 14.5 mohms
SA000051H20 SA00005AZ10
D D
1
UCPU1 CPUDIS03@
i5-2367M CPU RC1
SA000051H20 UCPU1 CPUUMA4@ UCPU1 CPUUMA2@ 24.9_0402_1%
17W 1.7GHz GT2 ES2 QBP7 17W 1.5GHz no cnfg ES2 QBTP
SA00005B010 SA00005AZ20 UCPU1A @
2
G3 PEG_COMP
UCPU1 CPUDIS04@ PEG_ICOMPI G1
M2 PEG_ICOMPO G4
131204 Del CU65 by EMI requested
i5-3317U CPU <16> DMI_CRX_PTX_N0
SA00005K600 UCPU1 CPUUMA5@ P6 DMI_RX#[0] PEG_RCOMPO
<16> DMI_CRX_PTX_N1 DMI_RX#[1]
17W 1.7GHz no cnfg ES2 QBTQ P1
<16> DMI_CRX_PTX_N2 DMI_RX#[2]
SA00005B020 P10 H22
<16> DMI_CRX_PTX_N3 DMI_RX#[3] PEG_RX#[0] J21
N3 PEG_RX#[1] B22
<16> DMI_CRX_PTX_P0 DMI_RX[0] PEG_RX#[2]
P7 D21
DMI
P3 A19
P11 D17
<16> DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5] B14
K1 PEG_RX#[6] D13 PEG_GTX_C_HRX_N[0..7]
<16> DMI_CTX_PRX_N0 M8 DMI_TX#[0] PEG_RX#[7] A11 PEG_GTX_C_HRX_N7 PEG_GTX_C_HRX_N[0..7] <22>
<16> DMI_CTX_PRX_N1 N4 DMI_TX#[1] PEG_RX#[8] B10 PEG_GTX_C_HRX_P[0..7]
PEG_GTX_C_HRX_N6 <PEG>
<16> DMI_CTX_PRX_N2 R2 DMI_TX#[2] PEG_RX#[9] G8 PEG_GTX_C_HRX_N5 PEG_GTX_C_HRX_P[0..7] <22>
<16> DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] A8 PEG_GTX_C_HRX_N4
K3 PEG_RX#[11] B6 PEG_GTX_C_HRX_N3
<16> DMI_CTX_PRX_P0 M7 DMI_TX[0] PEG_RX#[12] H8 PEG_GTX_C_HRX_N2 PEG_HTX_C_GRX_N[0..7]
<16> DMI_CTX_PRX_P1 P4 DMI_TX[1] PEG_RX#[13] E5 PEG_HTX_C_GRX_N[0..7] <22>
PEG_GTX_C_HRX_N1
<16> DMI_CTX_PRX_P2 T3 DMI_TX[2] PEG_RX#[14] K7 PEG_GTX_C_HRX_N0 PEG_HTX_C_GRX_P[0..7]
<16> DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15] PEG_HTX_C_GRX_P[0..7] <22>
K22
PEG_RX[0] K19
PEG_RX[1] C21
U7 PEG_RX[2] D19
C <16> FDI_CTX_PRX_N0 W11 FDI0_TX#[0] PEG_RX[3] C19 C
<16> FDI_CTX_PRX_N1 W1 FDI0_TX#[1] PEG_RX[4] D16
<16> FDI_CTX_PRX_N2 AA6 FDI0_TX#[2] PEG_RX[5] C13
<16> FDI_CTX_PRX_N3 W6 FDI0_TX#[3] PEG_RX[6] D12
<16> FDI_CTX_PRX_N4 V4 FDI1_TX#[0] PEG_RX[7] C11 PEG_GTX_C_HRX_P7
eDP_COMPIO and ICOMPO signals
PCI EXPRESS -- GRAPHICS

<16> FDI_CTX_PRX_N5 Y2 FDI1_TX#[1] PEG_RX[8] C9 PEG_GTX_C_HRX_P6
should be shorted near balls <16> FDI_CTX_PRX_N6 AC9 FDI1_TX#[2] PEG_RX[9] F8 PEG_GTX_C_HRX_P5
<16> FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10]
Intel(R) FDI
and routed with typical PEG_RX[11]
C8 PEG_GTX_C_HRX_P4
C5 PEG_GTX_C_HRX_P3
impedance <25 mohms U6 PEG_RX[12] H6 PEG_GTX_C_HRX_P2
<16> FDI_CTX_PRX_P0 W10 FDI0_TX[0] PEG_RX[13] F6 PEG_GTX_C_HRX_P1
<16> FDI_CTX_PRX_P1 W3 FDI0_TX[1] PEG_RX[14] K6 PEG_GTX_C_HRX_P0
<16> FDI_CTX_PRX_P2 AA7 FDI0_TX[2] PEG_RX[15]
<16> FDI_CTX_PRX_P3 W7 FDI0_TX[3] G22
NOTE:eDP_COMPIO and eDP_ICOMPO <16> FDI_CTX_PRX_P4 T4 FDI1_TX[0] PEG_TX#[0] C23
should not be left floating even if Internal <16> FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1]
AA3 D23
Graphic is disabled since they are shared <16> FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2]
AC8 F21
with other interfaces <16> FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] H19
+VCCP AA11 PEG_TX#[4] C17
<16> FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
AC12 K15
<16> FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6] F17
U11 PEG_TX#[7] F14 PEG_HTX_GRX_N7 CU41 DIS@ 1 2 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N7
<16> FDI_INT FDI_INT PEG_TX#[8] A15 PEG_HTX_GRX_N6 CU42 DIS@ 1 2 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N6
PEG_TX#[9]
2
eDP@ AA10 J14 PEG_HTX_GRX_N5 CU43 DIS@ 1 2 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N5

<16> FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10]
RC88 RC2 AG8 H13 PEG_HTX_GRX_N4 CU44 DIS@ 1 2 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N4
<16> FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11]
1K_0402_5% 24.9_0402_1% M10 PEG_HTX_GRX_N3 CU45 DIS@ 1 2 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N3
PEG_TX#[12] F10 PEG_HTX_GRX_N2 CU46 DIS@ 1 2 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N2
PEG_TX#[13] D9 PEG_HTX_GRX_N1 CU47 DIS@ 1 2 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N1
1
PEG_TX#[14] J4 PEG_HTX_GRX_N0 CU48 DIS@ 1 2 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N0

EDP_COMP AF3 PEG_TX#[15] <PEG>
AD2 eDP_COMPIO F22
EDP_HPD# AG11 eDP_ICOMPO PEG_TX[0] A23
B <30> EDP_HPD# eDP_HPD# PEG_TX[1] D24 B
PEG_TX[2] E21
AG4 PEG_TX[3] G19
<30> EDP_CPU_AUX#_C AF4 eDP_AUX# PEG_TX[4] B18
<30> EDP_CPU_AUX_C eDP_AUX PEG_TX[5] K17
PEG_TX[6]
eDP
G17
AC3 PEG_TX[7] E14 PEG_HTX_GRX_P7 CU57 DIS@ 1 2 0.22U_0402_6.3V6K PEG_HTX_C_GRX_P7
<30> EDP_CPU_LANE_N0_C AC4 eDP_TX#[0] PEG_TX[8] C15 PEG_HTX_GRX_P6 1 2 PEG_HTX_C_GRX_P6
CU58 DIS@ 0.22U_0402_6.3V6K
AE11 eDP_TX#[1] PEG_TX[9] K13 PEG_HTX_GRX_P5 CU59 DIS@ 1 2 0.22U_0402_6.3V6K PEG_HTX_C_GRX_P5
AE7 eDP_TX#[2] PEG_TX[10] G13 PEG_HTX_GRX_P4 CU60 DIS@ 1 2 0.22U_0402_6.3V6K PEG_HTX_C_GRX_P4
eDP_TX#[3] PEG_TX[11] K10 PEG_HTX_GRX_P3 CU61 DIS@ 1 2 0.22U_0402_6.3V6K PEG_HTX_C_GRX_P3
AC1 PEG_TX[12] G10 PEG_HTX_GRX_P2 CU62 DIS@ 1 2 0.22U_0402_6.3V6K PEG_HTX_C_GRX_P2
<30> EDP_CPU_LANE_P0_C AA4 eDP_TX[0] PEG_TX[13] D8 PEG_HTX_GRX_P1 1 2 PEG_HTX_C_GRX_P1
CU63 DIS@ 0.22U_0402_6.3V6K
AE10 eDP_TX[1] PEG_TX[14] K4 PEG_HTX_GRX_P0 CU64 DIS@ 1 2 0.22U_0402_6.3V6K PEG_HTX_C_GRX_P0
AE6 eDP_TX[2] PEG_TX[15]
eDP_TX[3]
10/05 Change to 0.22uF.
<1111> Co-lay eDP function. IVY-BRIDGE_BGA1023
Typ- suggest 220nF. The change in AC capacitor

value from 180nF to 265nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)
A A

PROCESSOR(1/7) DMI,FDI,PEG
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8661P 0.1
5 4 3 2 1
5 4 3 2 1
+3VS Buffered reset to CPU Reset# signal is driven by the PCH to multiple agents on the platform.
PCH Reset# output DC levels are 0-V and 3.3 V,
processor Reset input DC levels are 0V and 1.0 V.
Processor high-voltage level is lower than PCH high voltage level,
+VCCP therefore a voltage level shifter is required on the Reset# signal.
1
CC1 In order for Reset# to meet the signal quality requirement at the input to
0.1U_0402_16V4Z the processor OD buffer must be placed on the motherboard between
1
2 the PCH and the processor.
RC3
75_0402_5%
5
UC1
2
1 RC4
P
NC 4 BUFO_CPU_RST# 2 1 BUF_CPU_RST#
D
PLT_RST# 2 Y 43_0402_1%
D
<17,22,33,35,40,41> PLT_RST# A
1
G
SN74LVC1G07DCKR_SC70-5
RC6 @
3
750_0402_1%
+3VS
Requires a series resistor of 43±5% between processor and PCH.
2
R375 @ It also a needs an Rtt of 75±5% to VCCP after the OD XDP_DBRESET# RC5 2 1 1K_0201_5%
0_0402_5% buffer and before the series resistor.
1 2
UCPU1B @
This pin is for compability with future SI2 change to 0201
platforms. A pull up resistor to VCCIO is
required if connected to the DF_TVS strap BCLK
J3
H2
CLK_CPU_DMI <15> 100MHz 12.19
BCLK# CLK_CPU_DMI# <15>
MISC
on the PCH.
CLOCKS
F49
<18> H_SNB_IVB# PROC_SELECT# AG3 CLK_EDP RC85 1 eDP@ 2 0_0402_5%
DPLL_REF_CLK CLK_R_EDP <15>
AG1 CLK_EDP# RC84 1 eDP@ 2 0_0402_5%
DPLL_REF_CLK# CLK_R_EDP# <15>
PROC_DETECT (Processor Detect): pulled to 1 2 C57
ground on the processor package. There is no @ RC7 10K_0201_5% PROC_DETECT# 131224
connection to the processor silicon for this SI2 change to 0201 If motherboard only supports external graphics or if it supports integrated graphic but without eDP:
signal. System board designers may use this Connect DPLL_REF_SSCLK on Processor to GND through 1K ± 5% resistor.
signal to determine if the processor is present 12.19 Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K ± 5% resistor
PAD T5 @ C49
+VCCP CATERR#
Processor Pullups
THERMAL
RC8 2 1 62_0402_5% PROCHOT# A48 AT30 H_DRAMRST#
<18,41> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>
1
BF44 SM_RCOMP0
SM_RCOMP[0]
DDR3
MISC
<41,46> PROCHOT# PROCHOT# 1 2 H_PROCHOT#_R C45 BE43 SM_RCOMP1 CC104
C295 RC10 56_0402_5% PROCHOT# SM_RCOMP[1] BG43 SM_RCOMP2
SM_RCOMP[2] 0.1U_0402_16V7K
1 2 2 @ESD@
RC11 2 1 10K_0201_5% H_CPUPWRGD_R Near CPU
10P_0402_50V8J 1 2 H_THEMTRIP#_R D45
<18> H_THRMTRIP# THERMTRIP#
C @ESD@ RC12 0_0402_5% PAD C
T35
Near CPU short@ PAD @
T39
N53 @
PRDY# N55
SI2 change to 0201 PREQ#
12.19 TCK
L56
L55
XDP_TCK
XDP_TMS
TMS
PWR MANAGEMENT
J58 XDP_TRST#
RC13 short@ TRST#
JTAG & BPM

1 2 0_0201_5% H_PM_SYNC_R C48 M60 XDP_TDI
<16> H_PM_SYNC PM_SYNC TDI L59 XDP_TDO
TDO
RC16 short@
1 2 0_0201_5% H_CPUPWRGD_R B46 short@ RC17
<18> H_CPUPWRGD UNCOREPWRGOOD
非CORE外外外OK
K58 XDP_DBRESET#_R 2 1 0_0201_5% XDP_DBRESET#
DBR# XDP_DBRESET# <16>
UNCOREPWRGOOD:
12/16:Change to 0201 for SI2
PM_SYS_PWRGD_BUF 1 2 PM_DRAM_PWRGD_R BE45 G58
RC18 130_0402_5% SM_DRAMPWROK BPM#[0] E55
BPM#[1] E59
BPM#[2] G55
SM_DRAMPWROK:DRAM power ok BPM#[3] G59 XDP_BPM#4_R T60 @ PAD
BUF_CPU_RST# D44 BPM#[4] H60 XDP_BPM#5_R T61 @ PAD
RESET# BPM#[5] J59 XDP_BPM#6_R T62 @ PAD
BPM#[6] J61 XDP_BPM#7_R T63 @ PAD
BPM#[7]
2011.10.18 delete all reserved XDP conponent.

Just reserve test point for XDP.
IVY-BRIDGE_BGA1023
+3VS
+3V_PCH
DDR3 Compensation Signals
2
B
RC81 +1.5V_CPU_VDDQ SM_RCOMP0 RC23 2 1 140_0402_1%
SI2 change to 0201 XDP_DBRESET#_R CC4 2 1 0.1U_0201_16V4Z B
1
10K_0402_5% CC2
0.1U_0402_16V4Z SM_RCOMP1 RC24 2 1 25.5_0402_1%
12.19
1
H_CPUPWRGD_R C118 1 2 220P_0402_50V7K

1
2 RC25 SM_RCOMP2 RC26 2 1 200_0402_1% C263 0.1U_0201_16V4Z

UC2 200_0402_5% XDP_TRST# 1 2
@ RC27 74AHC1G09GW_TSSOP5 C264 220P_0402_50V7K
SI2 change to 0201
5
0_0402_5% PLT_RST# 1 2 12.19

2
1 2 1 PU/PD for JTAG signals C265 @ 100P_0402_50V8J

P
<16> SYS_PWROK B 4 PM_SYS_PWRGD_BUF PM_SYS_PWRGD_BUF 1 2

2 O C266 220P_0402_50V7K
<16> PM_DRAM_PWRGD A
G
BUF_CPU_RST# 1 2
RC28
1
XDP_TMS T40 @ PAD 6/27 Add ESD solution

3
1 2 @
+3V_PCH
RC29 XDP_TDI T41 @ PAD
200_0402_5% 39_0402_5%
Part Number = SA00003Y000 XDP_TDO T42 @ PAD
1 2
D @ XDP_TCK T43 @ PAD

<43> SUSP SUSP 2 QC1
11.06 Change to +3V_PCH G 2N7002_SOT23 XDP_TRST# T46 @ PAD
S
3
2011.10.18 delete all reserved XDP conponent.

Just reserve test point for XDP.
A A

PROCESSOR(2/7) PM,XDP,CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
LA-8041P
5 4 3 2 1
5 4 3 2 1
UCPU1C @
UCPU1D @
<12> DDR_A_D[0..63]
AG6 <13> DDR_B_D[0..63]
DDR_A_D0
DDR_A_D1 AJ6 SA_DQ[0] AU36 DDR_B_D0 AL4
DDR_A_D2 AP11 SA_DQ[1] SA_CK[0] AV36 M_CLK_DDR0 <12> DDR_B_D1 AL1 SB_DQ[0] BA34
DDR_A_D3 AL6 SA_DQ[2] SA_CK#[0] AY26 M_CLK_DDR#0 <12> DDR_B_D2 AN3 SB_DQ[1] SB_CK[0] AY34 M_CLK_DDR2 <13>
DDR_A_D4 AJ10 SA_DQ[3] SA_CKE[0] DDR_CKE0_DIMMA <12> DDR_B_D3 AR4 SB_DQ[2] SB_CK#[0] AR22 M_CLK_DDR#2 <13>
AJ8 SA_DQ[4] AK4 SB_DQ[3] SB_CKE[0] DDR_CKE0_DIMMB <13>
DDR_A_D5 DDR_B_D4
D DDR_A_D6 AL8 SA_DQ[5] DDR_B_D5 AK3 SB_DQ[4] D
DDR_A_D7 AL7 SA_DQ[6] DDR_B_D6 AN4 SB_DQ[5]
DDR_A_D8 AR11 SA_DQ[7] DDR_B_D7 AR1 SB_DQ[6]
DDR_A_D9 AP6 SA_DQ[8] AT40 DDR_B_D8 AU4 SB_DQ[7]
DDR_A_D10 AU6 SA_DQ[9] SA_CK[1] AU40 M_CLK_DDR1 <12> DDR_B_D9 AT2 SB_DQ[8] BA36
AV9 SA_DQ[10] SA_CK#[1] BB26 M_CLK_DDR#1 <12> AV4 SB_DQ[9] SB_CK[1] BB36 M_CLK_DDR3 <13>
DDR_A_D11 DDR_B_D10
DDR_A_D12 AR6 SA_DQ[11] SA_CKE[1] DDR_CKE1_DIMMA <12> DDR_B_D11 BA4 SB_DQ[10] SB_CK#[1] BF27 M_CLK_DDR#3 <13>
DDR_A_D13 AP8 SA_DQ[12] DDR_B_D12 AU3 SB_DQ[11] SB_CKE[1] DDR_CKE1_DIMMB <13>
DDR_A_D14 AT13 SA_DQ[13] DDR_B_D13 AR3 SB_DQ[12]
DDR_A_D15 AU13 SA_DQ[14] DDR_B_D14 AY2 SB_DQ[13]
DDR_A_D16 BC7 SA_DQ[15] DDR_B_D15 BA3 SB_DQ[14]
DDR_A_D17 BB7 SA_DQ[16] BB40 DDR_B_D16 BE9 SB_DQ[15]
DDR_A_D18 BA13 SA_DQ[17] SA_CS#[0] BC41 DDR_CS0_DIMMA# <12> DDR_B_D17 BD9 SB_DQ[16] BE41
BB11 SA_DQ[18] SA_CS#[1] DDR_CS1_DIMMA# <12> BD13 SB_DQ[17] SB_CS#[0] BE47 DDR_CS0_DIMMB# <13>
DDR_A_D19 DDR_B_D18
DDR_A_D20 BA7 SA_DQ[19] DDR_B_D19 BF12 SB_DQ[18] SB_CS#[1] DDR_CS1_DIMMB# <13>
DDR_A_D21 BA9 SA_DQ[20] DDR_B_D20 BF8 SB_DQ[19]
DDR_A_D22 BB9 SA_DQ[21] DDR_B_D21 BD10 SB_DQ[20]
DDR_A_D23 AY13 SA_DQ[22] DDR_B_D22 BD14 SB_DQ[21]
DDR_A_D24 AV14 SA_DQ[23] AY40 DDR_B_D23 BE13 SB_DQ[22]
DDR_A_D25 AR14 SA_DQ[24] SA_ODT[0] BA41 M_ODT0 <12> DDR_B_D24 BF16 SB_DQ[23] AT43
AY17 SA_DQ[25] SA_ODT[1] M_ODT1 <12> BE17 SB_DQ[24] SB_ODT[0] BG47 M_ODT2 <13>
DDR_A_D26 DDR_B_D25
DDR_A_D27 AR19 SA_DQ[26] DDR_B_D26 BE18 SB_DQ[25] SB_ODT[1] M_ODT3 <13>
DDR_A_D28 BA14 SA_DQ[27] DDR_B_D27 BE21 SB_DQ[26]
DDR_A_D29 AU14 SA_DQ[28] DDR_B_D28 BE14 SB_DQ[27]
DDR_A_D30 BB14 SA_DQ[29] DDR_B_D29 BG14 SB_DQ[28]
BB17 SA_DQ[30] AL11 DDR_A_DQS#[0..7] <12> BG18 SB_DQ[29]
DDR_A_D31 DDR_A_DQS#0 DDR_B_D30
DDR_A_D32 BA45 SA_DQ[31] SA_DQS#[0] AR8 DDR_A_DQS#1 DDR_B_D31 BF19 SB_DQ[30] AL3 DDR_B_DQS#0 DDR_B_DQS#[0..7] <13>
DDR_A_D33 AR43 SA_DQ[32] SA_DQS#[1] AV11 DDR_A_DQS#2 DDR_B_D32 BD50 SB_DQ[31] SB_DQS#[0] AV3 DDR_B_DQS#1
DDR_A_D34 AW48 SA_DQ[33] SA_DQS#[2] AT17 DDR_A_DQS#3 DDR_B_D33 BF48 SB_DQ[32] SB_DQS#[1] BG11 DDR_B_DQS#2
DDR_A_D35 BC48 SA_DQ[34] SA_DQS#[3] AV45 DDR_A_DQS#4 DDR_B_D34 BD53 SB_DQ[33] SB_DQS#[2] BD17 DDR_B_DQS#3
DDR_A_D36 BC45 SA_DQ[35] SA_DQS#[4] AY51 DDR_A_DQS#5 DDR_B_D35 BF52 SB_DQ[34] SB_DQS#[3] BG51 DDR_B_DQS#4
DDR_A_D37 AR45 SA_DQ[36] SA_DQS#[5] AT55 DDR_A_DQS#6 DDR_B_D36 BD49 SB_DQ[35] SB_DQS#[4] BA59 DDR_B_DQS#5
DDR SYSTEM MEMORY A
C DDR_A_D38 AT48 SA_DQ[37] SA_DQS#[6] AK55 DDR_A_DQS#7 DDR_B_D37 BE49 SB_DQ[36] SB_DQS#[5] AT60 DDR_B_DQS#6 C
SA_DQ[38] SA_DQS#[7] SB_DQ[37] SB_DQS#[6]
DDR SYSTEM MEMORY B

DDR_A_D39 AY48 DDR_B_D38 BD54 AK59 DDR_B_DQS#7
DDR_A_D40 BA49 SA_DQ[39] DDR_B_D39 BE53 SB_DQ[38] SB_DQS#[7]
DDR_A_D41 AV49 SA_DQ[40] DDR_B_D40 BF56 SB_DQ[39]
DDR_A_D42 BB51 SA_DQ[41] DDR_B_D41 BE57 SB_DQ[40]
DDR_A_D43 AY53 SA_DQ[42] DDR_B_D42 BC59 SB_DQ[41]
DDR_A_D44 BB49 SA_DQ[43] DDR_B_D43 AY60 SB_DQ[42]
AU49 SA_DQ[44] AJ11 DDR_A_DQS[0..7] <12> BE54 SB_DQ[43]
DDR_A_D45 DDR_A_DQS0 DDR_B_D44
DDR_A_D46 BA53 SA_DQ[45] SA_DQS[0] AR10 DDR_A_DQS1 DDR_B_D45 BG54 SB_DQ[44]
DDR_A_D47 BB55 SA_DQ[46] SA_DQS[1] AY11 DDR_A_DQS2 DDR_B_D46 BA58 SB_DQ[45] AM2 DDR_B_DQS0 DDR_B_DQS[0..7] <13>
DDR_A_D48 BA55 SA_DQ[47] SA_DQS[2] AU17 DDR_A_DQS3 DDR_B_D47 AW59 SB_DQ[46] SB_DQS[0] AV1 DDR_B_DQS1
DDR_A_D49 AV56 SA_DQ[48] SA_DQS[3] AW45 DDR_A_DQS4 DDR_B_D48 AW58 SB_DQ[47] SB_DQS[1] BE11 DDR_B_DQS2
DDR_A_D50 AP50 SA_DQ[49] SA_DQS[4] AV51 DDR_A_DQS5 DDR_B_D49 AU58 SB_DQ[48] SB_DQS[2] BD18 DDR_B_DQS3
DDR_A_D51 AP53 SA_DQ[50] SA_DQS[5] AT56 DDR_A_DQS6 DDR_B_D50 AN61 SB_DQ[49] SB_DQS[3] BE51 DDR_B_DQS4
DDR_A_D52 AV54 SA_DQ[51] SA_DQS[6] AK54 DDR_A_DQS7 DDR_B_D51 AN59 SB_DQ[50] SB_DQS[4] BA61 DDR_B_DQS5
DDR_A_D53 AT54 SA_DQ[52] SA_DQS[7] DDR_B_D52 AU59 SB_DQ[51] SB_DQS[5] AR59 DDR_B_DQS6
DDR_A_D54 AP56 SA_DQ[53] DDR_B_D53 AU61 SB_DQ[52] SB_DQS[6] AK61 DDR_B_DQS7
DDR_A_D55 AP52 SA_DQ[54] DDR_B_D54 AN58 SB_DQ[53] SB_DQS[7]
DDR_A_D56 AN57 SA_DQ[55] DDR_B_D55 AR58 SB_DQ[54]
DDR_A_D57 AN53 SA_DQ[56] DDR_B_D56 AK58 SB_DQ[55]
DDR_A_D58 AG56 SA_DQ[57] DDR_B_D57 AL58 SB_DQ[56]
DDR_A_D59 AG53 SA_DQ[58] DDR_B_D58 AG58 SB_DQ[57]
DDR_A_D60 AN55 SA_DQ[59] DDR_B_D59 AG59 SB_DQ[58]
AN52 SA_DQ[60] BG35 DDR_A_MA[0..15] <12> AM60 SB_DQ[59]
DDR_A_D61 DDR_A_MA0 DDR_B_D60
DDR_A_D62 AG55 SA_DQ[61] SA_MA[0] BB34 DDR_A_MA1 DDR_B_D61 AL59 SB_DQ[60] BF32 DDR_B_MA0 DDR_B_MA[0..15] <13>
DDR_A_D63 AK56 SA_DQ[62] SA_MA[1] BE35 DDR_A_MA2 DDR_B_D62 AF61 SB_DQ[61] SB_MA[0] BE33 DDR_B_MA1
SA_DQ[63] SA_MA[2] BD35 DDR_A_MA3 DDR_B_D63 AH60 SB_DQ[62] SB_MA[1] BD33 DDR_B_MA2
SA_MA[3] AT34 DDR_A_MA4 SB_DQ[63] SB_MA[2] AU30 DDR_B_MA3
SA_MA[4] AU34 DDR_A_MA5 SB_MA[3] BD30 DDR_B_MA4
SA_MA[5] BB32 DDR_A_MA6 SB_MA[4] AV30 DDR_B_MA5
BD37 SA_MA[6] AT32 DDR_A_MA7 SB_MA[5] BG30 DDR_B_MA6
<12> DDR_A_BS0 BF36 SA_BS[0] SA_MA[7] AY32 DDR_A_MA8 BG39 SB_MA[6] BD29 DDR_B_MA7
B <12> DDR_A_BS1 BA28 SA_BS[1] SA_MA[8] AV32 <13> DDR_B_BS0 BD42 SB_BS[0] SB_MA[7] BE30 B
DDR_A_MA9 DDR_B_MA8
<12> DDR_A_BS2 SA_BS[2] SA_MA[9] BE37 <13> DDR_B_BS1 AT22 SB_BS[1] SB_MA[8] BE28
DDR_A_MA10 DDR_B_MA9
SA_MA[10] BA30 DDR_A_MA11 <13> DDR_B_BS2 SB_BS[2] SB_MA[9] BD43 DDR_B_MA10
SA_MA[11] BC30 DDR_A_MA12 SB_MA[10] AT28 DDR_B_MA11
BE39 SA_MA[12] AW41 DDR_A_MA13 SB_MA[11] AV28 DDR_B_MA12
<12> DDR_A_CAS# BD39 SA_CAS# SA_MA[13] AY28 DDR_A_MA14 AV43 SB_MA[12] BD46 DDR_B_MA13
<12> DDR_A_RAS# AT41 SA_RAS# SA_MA[14] AU26 <13> DDR_B_CAS# BF40 SB_CAS# SB_MA[13] AT26
DDR_A_MA15 DDR_B_MA14
<12> DDR_A_WE# SA_WE# SA_MA[15] <13> DDR_B_RAS# BD45 SB_RAS# SB_MA[14] AU22 DDR_B_MA15
<13> DDR_B_WE# SB_WE# SB_MA[15]
IVY-BRIDGE_BGA1023
IVY-BRIDGE_BGA1023
+1.35V
通通DIMM做reset @ RC35
1
CPU 0_0402_5%
1 2 RC36
1K_0402_5%
RC37
2
1K_0402_5%
3 1 1 2
S
H_DRAMRST# DDR3_DRAMRST#_R
<6> H_DRAMRST# DDR3_DRAMRST# <12,13>
QC2
2
BSS138_NL_SOT23-3
RC38 S0
G
2
4.99K_0402_1% DRAMRST_CNTRL_PCH hgih ,MOS ON

9/7 Folllow PAJ80 BOM by Light H_DRAMRST# HIGH,DDR3_DRAMRST# HIGH
del: SB501380020
1
A RC39 Dimm not reset A

add: SB00000QO00
0_0402_5% S3
1 2 DRAMRST_CNTRL DRAMRST_CNTRL_PCH Low ,MOS OFF
<10,15,41> DRAMRST_CNTRL_PCH
short@
H_DRAMRST# lo,DDR3_DRAMRST# HIGH
Dimm not reset
S4,5
1
CC3
DRAMRST_CNTRL_PCH Low ,MOS OFF
H_DRAMRST# lo,DDR3_DRAMRST# low Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title
0.047U_0402_16V4Z
2 Dimm reset
PROCESSOR(3/7) DDRIII
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-8041P
5 4 3 2 1
5 4 3 2 1
CFG Straps for Processor

PEG bus is reversed, need to PD.
11.01 CFG2
1
RC40 SI2 change to 0201
RC40
1K_0201_1% 12.19
2
D D
Change to part G.
PEG Static Lane Reversal - CFG2 is for the 16x
1: Normal Operation; Lane # definition matches

CFG2 * socket pin map definition
0:Lane Reversed
CFG4
1
RC41 eDP@
1K_0201_1%
Delete T12, T13, T10 UCPU1E @
2
12.21
CFG0 B50 N59
T9 CFG[0] BCLK_ITP CLK_RES_ITP <15>
CFG1 C51 N58
T6 CFG[1] BCLK_ITP# CLK_RES_ITP# <15>
CFG2 B54
CFG3 D53 CFG[2]
T11 CFG[3] Display Port Presence Strap
CFG4 A51 N42
CFG5 C53 CFG[4] RSVD30 L42
C CFG6 C55 CFG[5] RSVD31 L45 C
1 : Disabled; No Physical Display Port
T7
T8
CFG7
CFG8
H49
A55
CFG[6]
CFG[7]
CFG[8]
RSVD32
RSVD33
L47 CFG4 * attached to Embedded Display Port
CFG9 H51
T14 CFG[9]
CFG10 K49 M13 0 : Enabled; An external Display Port device is
T15 CFG[10] RSVD34
CFG11 K53 M14
T16
CFG12 F53 CFG[11] RSVD35 U14 connected to the Embedded Display Port
T47 CFG[12] RSVD36
2011.10.18 delete XDP resistor CFG13 G53 W14
T48 CFG[13] RSVD37
CFG14 L51 P13
just reserve test point for XDP. T58 CFG[14] RSVD38
CFG15 F51
T59 CFG[15]
CFG16 D52 CFG6
T17 CFG[16]
CFG17 L53 AT49
T18 CFG[17] RSVD39 K24 CFG5
RSVD40
RC48, RC49 SI2 change to 0201
1
1 249.9_0402_1%
VCC_VAL_SENSEH43
RESERVED
+CPU_CORE RC42
2 1 VSS_VAL_SENSEK43 VCC_VAL_SENSE AH2 12.19
RC43 49.9_0402_1% VSS_VAL_SENSE RSVD41 AG13 RC48 RC49
RSVD42 AM14 1K_0201_1% 1K_0201_1%
RC44 1 2 49.9_0402_1% VAXG_VAL_SENSE H45 RSVD43 AM15
+VGFX_CORE
2
2 1 VSSAXG_VAL_SENSE K45 VAXG_VAL_SENSE RSVD44
RC45 49.9_0402_1% VSSAXG_VAL_SENSE
N50 Change CFG[6:5] to 00= 1x8, 2x4 PCIe
F48 RSVD45
VCC_DIE_SENSE because AMD driver can't install issue
11.21
CPU_RSVD6 H48
CPU_RSVD7 K48 RSVD6
RSVD7 A4
DC_TEST_A4 PCIE Port Bifurcation Straps
1
C4
BA19 DC_TEST_C4 D3
B
@ RC46
1K_0201_1%
RC47 @
1K_0201_1%
AV19
AT21
BB21
RSVD8
RSVD9
RSVD10
DC_TEST_D3
DC_TEST_D1
DC_TEST_A58
D1
A58
A59
* 00
01
=
=
1 x 8, 2 x 4 PCI Express
reserved B
CFG[6:5]
2
BB19 RSVD11 DC_TEST_A59 C59 10 = 2 x 8 PCI Express

AY21 RSVD12 DC_TEST_C59 A61
RSVD13 DC_TEST_A61 11 = 1 x 16 PCI Express
BA22 C61
AY22 RSVD14 DC_TEST_C61 D61
AU19 RSVD15 DC_TEST_D61 BD61
AU21 RSVD16 DC_TEST_BD61 BE61
12/16:Change to 0201 for SI2 because standoff PAD
BD21 RSVD17 DC_TEST_BE61 BE59
BD22 RSVD18 DC_TEST_BE59 BG61
BD25 RSVD19 DC_TEST_BG61 BG59 12/16:Change to 0201 for SI2 because standoff PAD
BD26 RSVD20 DC_TEST_BG59 BG58
BG22 RSVD21 DC_TEST_BG58 BG4 CFG7
BE22 RSVD22 DC_TEST_BG4 BG3
RSVD23 DC_TEST_BG3
1
BG26 BE3
BE26 RSVD24 DC_TEST_BE3 BG1
BF23 RSVD25 DC_TEST_BG1 BE1 RC50 @
BE24 RSVD26 DC_TEST_BE1 BD1 1K_0201_1%
RSVD27 DC_TEST_BD1
2
IVY-BRIDGE_BGA1023
PEG DEFER TRAINING
CFG7 * 1: (Default) PEG Train immediately following

xxRESETB de assertion
A
0: PEG Wait for BIOS for training A

PROCESSOR(4/7) RSVD,CFG
5 4 3 2 1
5 4 3 2 1
UCPU1F POWER
+VCCP
+CPU_CORE AF46
VCCIO[1] AG48
VCCIO[3] AG50
A26 VCCIO[4] AG51
A29 VCC[1] VCCIO[5] AJ17
D A39 VCC[6] VCCIO[10] AK50 D
A42 VCC[7] VCCIO[11] AK51
C26 VCC[8] VCCIO[12] AL14
D27 VCC[15] VCCIO[19] AL48
D32 VCC[16] VCCIO[20] AM16
PEG IO AND DDR IO

E26 VCC[21] VCCIO[25] AN20
E37 VCC[25] VCCIO[29]
E38 VCC[26]
VCC[27]
CORE SUPPLY
F25
F26 VCC[28]
F28 VCC[29]
F32 VCC[30]
F34 VCC[31]
F37 VCC[32] AA14
F38 VCC[33] VCCIO[30] AA15
F42 VCC[34] VCCIO[31] AB17
G42 VCC[35] VCCIO[32] AB20
H25 VCC[36] VCCIO[33] AC13
H26 VCC[37] VCCIO[34] AD16
C H28 VCC[38] VCCIO[35] AD18 C
H29 VCC[39] VCCIO[36] AD21
H32 VCC[40] VCCIO[37] AE14
H34 VCC[41] VCCIO[38] AE15
H35 VCC[42] VCCIO[39] AF16
H40 VCC[45] VCCIO[42] AG15
J25 VCC[46] VCCIO[43] AG16
J32 VCC[50] VCCIO[47] AJ14
J34 VCC[51] VCCIO[48] AJ15
J35 VCC[52] VCCIO[49] +VCCP
J37 VCC[53]
J38 VCC[54]
J40 VCC[55] +VCCP
J42 VCC[56]
K26 VCC[57] W16 RC51
VCC[58] VCCIO50
1
K27 W17 1 2
K29 VCC[59] VCCIO51 RC52 @
K32 VCC[60] 75_0402_5%
K34 VCC[61] 0_0805_5%
K35 VCC[62]
2
K37 VCC[63]
K39 VCC[64] CPU EDS descript as follow:
VCC[66]
K42
L25 VCC[67] VCCIO_SEL
BC22 VCCP_PWRCTRL_R 110K_0402_5%
2 For Chief River platforms this pin
L28 VCC[68]
VCC[69]
choose low or high @ RC53 should not be used.
L33
L36 VCC[70] +VCCP
B L40 VCC[71] +1.05VS_VCCPQ B
N26 VCC[72] RC54 +VCCP
N30 VCC[73] AM25
QUIET
RAILS
N34 VCC[74] VCCPQE[1] AN22 1 2
VCC[75] VCCPQE[2]
1
N38 short@
VCC[76] 0_0805_5% RC56
1 2 75_0402_5%
CC73 1U_0402_6.3V6K
2
A44 H_CPU_SVIDALRT# RC57 1 2 43_0402_1%
VIDALERT# B43 VR_SVID_ALRT# <53>
H_CPU_SVIDCLK RC58 1 short@ 2 0_0402_5%
VIDSCLK VR_SVID_CLK <53>
SVID
C44 H_CPU_SVIDDAT RC59 1 short@ 2 0_0402_5%
VIDSOUT VR_SVID_DAT <53>
+CPU_CORE
Place the PU
1 2
RC60 100_0402_1% resistors close to CPU
F43 VCCSENSE_R RC61 1 short@ 2 0_0402_5%
VCC_SENSE VCCSENSE <53>
SENSE LINES
G43 VSSSENSE_R RC62 1 short@ 2 0_0402_5%

VSS_SENSE VSSSENSE <53>
1
RC63 1 2
+VCCP
10_0402_1% RC64 Place the PU
AN16 VCCIO_SENSE_R 100_0402_1%
VCCIO_SENSE AN17 VSS_SENSE_VCCIO VCCIO_SENSE <51> resistors close to VR
VSS_SENSE_VCCIO 1 VSS_SENSE_VCCIO <51>
2
A RC66 A
10_0402_1%
10/05 mount.
2
IVY-BRIDGE_BGA1023 (follow check list)

PROCESSOR(5/7) PWR,BYPASS
5 4 3 2 1
5 4 3 2 1
+1.5V_CPU_VDDQ +1.35V
‧ Can connect to GND if motherboard only
supports external graphics and if GFX VR is not
CC74 2 1 0.1U_0402_10V7K
‧
stuffed in a common motherboard design,
VAXG can be left floating in a common
CC75 2 1 0.1U_0402_10V7K +1.5V_CPU_VDDQ
motherboard design (Gfx VR keeps VAXG from RC67
floating) if the VR is stuffed 0_0402_5%
POWER
1
2 1
UCPU1G
+V_SM_VREF should RC68
have 20 mil trace width short@ 1K_0402_1%
+VGFX_CORE
D D
2
AY43 +V_SM_VREF_CNT 2 3 +V_SM_VREF
AA46 SM_VREF
VREF
VAXG[1]
1
AB47 1 @QC3
@ QC3
AB50 VAXG[2] BE7 +V_DDR_REFA_R CC79 AP2302GN-HF_SOT23-3 RC69
AB51 VAXG[3] SA_DIMM_VREFDQ BG7 +V_DDR_REFB_R 0.1U_0402_16V4Z 1K_0402_1%
AB52 VAXG[4] SB_DIMM_VREFDQ 1
AB53 VAXG[5] 2 RUN_ON_CPU1.5VS3
2
AB55 VAXG[6]
AB56 VAXG[7]
AB58 VAXG[8]
AB59 VAXG[9]
QC7 AC61 VAXG[10]
AD47 VAXG[11]
SB00000S700 AD48 VAXG[12] Check with Power Team
VAXG[13]
1
D AD50 +1.5V_CPU_VDDQ
BSS138W-7-F_SOT323-3
2 DRAMRST_CNTRL_PCH AD51 VAXG[14] AJ28 CC100 (330UF) can be taken off.
DRAMRST_CNTRL_PCH <15,41,7> VAXG[15] VDDQ[1]
- 1.5V RAILS
AD52 AJ33
+V_DDR_REFA S
G
AD53 VAXG[16] VDDQ[2] AJ36 5A 10.31
3
RC15 AD55 VAXG[17] VDDQ[3] AJ40

VAXG[18] VDDQ[4]
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 2 +V_DDR_REFA_R AD56 AL30
VAXG[19] VDDQ[5]
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
@ 0_0402_5% AD58 AL34 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VAXG[20] VDDQ[6]
CC85
CC86
CC87
CC88
CC89
CC90
CC91
CC92
1 RC14 2 AD59 AL38
VAXG[21] VDDQ[7]
CC93
CC94
CC95
CC96
CC97
CC98
CC99
QC8 @ 1K_0402_1% AE46 AL42
N45 VAXG[22] VDDQ[8] AM33
SB00000S700 P47 VAXG[23] VDDQ[9] AM36 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
VAXG[24] VDDQ[10]
1
D BSS138W-7-F_SOT323-3 P48 AM40

2 DRAMRST_CNTRL_PCH P50 VAXG[25] VDDQ[11] AN30
G P51 VAXG[26] VDDQ[12] AN34
+V_DDR_REFB P52 VAXG[27] VDDQ[13] AN38
S
QC4 Change to SA0000JA00 for small package +1.5V_CPU_VDDQ Source
3
RC82 P53 VAXG[28] VDDQ[14] AR26
DDR3
1 2 +V_DDR_REFB_R P55 VAXG[29] VDDQ[15] AR28
1016
GRAPHICS
C @ 0_0402_5% P56 VAXG[30] VDDQ[16] AR30 C
1 RC83 2 P61 VAXG[31] VDDQ[17] AR32
@ 1K_0402_1% T48 VAXG[32] VDDQ[18] AR34 +1.35V QC4 +1.5V_CPU_VDDQ
T58 VAXG[33] VDDQ[19] AR36 B+ AON6718L_DFN8-5
T59 VAXG[34] VDDQ[20] AR40 1
T61 VAXG[35] VDDQ[21] AV41 2
VAXG[36] VDDQ[22]
1
U46 AW26 +3VALW 5 3
VAXG[37] VDDQ[23]
2
V47 BA40
V48 VAXG[38] VDDQ[24] BB28 RC70 RC71
VAXG[39] VDDQ[25]
1
20K_0402_5%
V50 BG33 100K_0402_5% 470_0603_5%
4
VAXG[40] VDDQ[26]
1
For Chief River only V51 R78
2
V52 VAXG[41] RC72
1
V53 VAXG[42] 100K_0402_5% RUN_ON_CPU1.5VS3 @
VAXG[43]
3
M3 Circuit (Processor Generated SO-DIMM VREF_DQ) V55
2
VAXG[44]
6
V56
2
VAXG[45]
1
V58 RC74 1
V59 VAXG[46] 0_0402_5% RUN_ON_CPU1.5VS3# 5 2N7002DWH_SOT363-6
W50 VAXG[47] 1 2 CPU1.5V_S3_GATE_R QC5B 2 RUN_ON_CPU1.5VS3#
VAXG[48] <41> CPU1.5V_S3_GATE
6
W51 RC73 CC118
10/03 add +V_DDR_REFB
4
W52 VAXG[49] @ RC75
@RC75 330K_0402_5% 2 0.1U_0402_25V6 Q10A
1
W53 VAXG[50] 0_0402_5% 2N7002DWH_SOT363-6
W55 VAXG[51] 1 2 2 2N7002DWH_SOT363-6
W56 VAXG[52] <41,43,50,51,52,55,58> SUSP# QC5A
W61 VAXG[53] +1.5V_CPU_VDDQ
1
Y48 VAXG[54]
Y61 VAXG[55]
SI# BOM Change CC118 0.1u 25V form 0.1u 16V
VAXG[56]
+VGFX_CORE
131203 del RC76
Follow DG 0.71 page 6
RC86 1 2 100_0402_1%
QUIET RAILS
AM28
SENSE
LINES
B F45 VCCDQ[1] AN26 B

<53> VCC_AXG_SENSE G45 VAXG_SENSE VCCDQ[2]
<53> VSS_AXG_SENSE VSSAXG_SENSE 1U_0402_6.3V6K
1 2 1 2
RC87 100_0402_1%
<1119>check list. +1.35V +1.5V_CPU_VDDQ
+1.8VS RC77 CC119
1.8V RAIL
QC9 @
1 2 +1.8VS_VCCPLL BB3 1 14
VCCPLL[1] VIN1 VOUT1
10U_0603_6.3V6M
BC1 2 13
VCCPLL[2] +1.35V VIN1 VOUT1
1U_0402_6.3V6K
CC121
1U_0402_6.3V6K
CC122
0_0805_5% 1 1 1 BC4 @
short@ VCCPLL[3] CPU1.5V_S3_GATE_R 3 12 CC1361 2 100P_0402_50V8J
ON1 CT1
CC26
4 11
2 2 2 BC43 VBIAS GND
+VCCSA VDDQ_SENSE BA43 5 10
VSS_SENSE_VDDQ ON2 CT2
SENSE LINES
+VCCSA L17 6 9
L21 VCCSA[1] 7 VIN2 VOUT2 8
N16 VCCSA[2] VIN2 VOUT2
N20 VCCSA[3] 15
VCCSA[4] VCCSA_SENSE <52> GPAD
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1 1 1 1 1 N22
SA RAIL
P17 VCCSA[5] TPS22966DPUR_SON14_2X3-D

VCCSA[6]
CC23
CC20
CC22
CC21
CC24
P20 U10 VCCSA_SENSE 1 2

R16 VCCSA[7] VCCSA_SENSE @RC78
@ RC78 0_0402_5%
2 2 2 2 2 R18 VCCSA[8]
R21 VCCSA[9]
U15 VCCSA[10]
VCCSA VID
V16 VCCSA[11]
V17 VCCSA[12] D48 VCCSA_VID0
VCCSA_VID0 <52>
<1111>Reserve low power switch for +1.5V_CPU_VDDQ.
VCCSA[13] VCCSA_VID[0]
lines
V18 D49 VCCSA_VID1

V21 VCCSA[14] VCCSA_VID[1] VCCSA_VID1 <52>
A W20 VCCSA[15] VID[0] VID[1] 2011 2012 A
VCCSA[16]
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0 0 0.90 V Yes Yes

1 1 1 1 1 0 1 0.80 V Yes Yes
CC129
CC130
CC131
CC132
CC133
1 0 0.725 V No Yes
1 1 0.675 V No Yes
IVY-BRIDGE_BGA1023
2 2 2 2 2

Delete CC25 330U cap 10.19 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(6/7) PWR
(after check with power) DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8661P 0.1
5 4 3 2 1
5 4 3 2 1
UCPU1H
A13 AM38
A17 VSS[1] VSS[91] AM4
A21 VSS[2] VSS[92] AM42
A25 VSS[3] VSS[93] AM45
A28 VSS[4] VSS[94] AM48
A33 VSS[5] VSS[95] AM58
A37 VSS[6] VSS[96] AN1
A40 VSS[7] VSS[97] AN21
A45 VSS[8] VSS[98] AN25 UCPU1I
A49 VSS[9] VSS[99] AN28
D A53 VSS[10] VSS[100] AN33 D
A9 VSS[11] VSS[101] AN36
AA1 VSS[12] VSS[102] AN40 BG17 M4
AA13 VSS[13] VSS[103] AN43 BG21 VSS[181] VSS[250] M58
AA50 VSS[14] VSS[104] AN47 BG24 VSS[182] VSS[251] M6
AA51 VSS[15] VSS[105] AN50 BG28 VSS[183] VSS[252] N1
AA52 VSS[16] VSS[106] AN54 BG37 VSS[184] VSS[253] N17
AA53 VSS[17] VSS[107] AP10 BG41 VSS[185] VSS[254] N21
AB16 VSS[21] VSS[111] AR13 BG9 VSS[189] VSS[258] N36
AB18 VSS[22] VSS[112] AR17 C29 VSS[190] VSS[259] N40
AB61 VSS[25] VSS[115] AR48 D10 VSS[193] VSS[262] N48
AC10 VSS[26] VSS[116] AR61 D14 VSS[194] VSS[263] N51
AC14 VSS[27] VSS[117] AR7 D18 VSS[195] VSS[264] N52
AC46 VSS[28] VSS[118] AT14 D22 VSS[196] VSS[265] N56
AC6 VSS[29] VSS[119] AT19 D26 VSS[197] VSS[266] N61
AD17 VSS[30] VSS[120] AT36 D29 VSS[198] VSS[267] P14
AD61
AE13
VSS[33]
VSS[34] VSS VSS[123]
VSS[124]
AT52
AT58
D40
D43
VSS[201]
VSS[202]
VSS[270]
VSS[271]
P21
P58
AE8
AF1
VSS[35]
VSS[36]
VSS[37]
VSS[125]
VSS[126]
VSS[127]
AU1
AU11
D46
D50
VSS[203]
VSS[204]
VSS[205]
VSS VSS[272]
VSS[273]
VSS[274]
P59
P9
AF17 AU28 D54 R17
AF21 VSS[38] VSS[128] AU32 D58 VSS[206] VSS[275] R20
AF47 VSS[39] VSS[129] AU51 D6 VSS[207] VSS[276] R4
AF48 VSS[40] VSS[130] AU7 E25 VSS[208] VSS[277] R46
AF50 VSS[41] VSS[131] AV17 E29 VSS[209] VSS[278] T1
C AF51 VSS[42] VSS[132] AV21 E3 VSS[210] VSS[279] T47 C
AF55 VSS[45] VSS[135] AV40 F13 VSS[213] VSS[282] T52
AF59 VSS[48] VSS[138] AW13 F29 VSS[216] VSS[285] T56
AG10 VSS[49] VSS[139] AW43 F35 VSS[217] VSS[286] U13
AG14 VSS[50] VSS[140] AW61 F40 VSS[218] VSS[287] U8
AG18 VSS[51] VSS[141] AW7 F55 VSS[219] VSS[288] V20
AG47 VSS[52] VSS[142] AY14 G51 VSS[220] VSS[289] V61
AG52 VSS[53] VSS[143] AY19 G6 VSS[221] VSS[290] W13
AG61 VSS[54] VSS[144] AY30 G61 VSS[222] VSS[291] W15
AG7 VSS[55] VSS[145] AY36 H10 VSS[223] VSS[292] W18
AH4 VSS[56] VSS[146] AY4 H14 VSS[224] VSS[293] W21
AH58 VSS[57] VSS[147] AY41 H17 VSS[225] VSS[294] W46
AJ13 VSS[58] VSS[148] AY45 H21 VSS[226] VSS[295] W8
AJ16 VSS[59] VSS[149] AY49 H4 VSS[227] VSS[296] Y4
AJ26 VSS[62] VSS[152] AY9 J1 VSS[230] VSS[299] Y59
AJ30 VSS[63] VSS[153] BA1 J49 VSS[231] VSS[300] G48
AJ34 VSS[64] VSS[154] BA11 J55 VSS[232] VSS[301]
AJ38 VSS[65] VSS[155] BA17 K11 VSS[233]
AJ42 VSS[66] VSS[156] BA21 K21 VSS[234]
AJ45 VSS[67] VSS[157] BA26 K51 VSS[235]
AJ48 VSS[68] VSS[158] BA32 K8 VSS[236] A5
AJ7 VSS[69] VSS[159] BA48 L16 VSS[237] VSS_NCTF_1 A57
AK1 VSS[70] VSS[160] BA51 L20 VSS[238] VSS_NCTF_2 BC61
AK52 VSS[71] VSS[161] BB53 L22 VSS[239] VSS_NCTF_3 BD3
AL10 VSS[72] VSS[162] BC13 L26 VSS[240] VSS_NCTF_4 BD59
AL13 VSS[73] VSS[163] BC5 L30 VSS[241] VSS_NCTF_5 BE4
NCTF
B AL17 VSS[74] VSS[164] BC57 L34 VSS[242] VSS_NCTF_6 BE58 B
AL21 VSS[75] VSS[165] BD12 L38 VSS[243] VSS_NCTF_7 BG5
AL25 VSS[76] VSS[166] BD16 L43 VSS[244] VSS_NCTF_8 BG57
AL28 VSS[77] VSS[167] BD19 L48 VSS[245] VSS_NCTF_9 C3
AL33 VSS[78] VSS[168] BD23 L61 VSS[246] VSS_NCTF_10 C58
AL36 VSS[79] VSS[169] BD27 M11 VSS[247] VSS_NCTF_11 D59
AL40 VSS[80] VSS[170] BD32 M15 VSS[248] VSS_NCTF_12 E1
AL43 VSS[81] VSS[171] BD36 VSS[249] VSS_NCTF_13 E61
AL47 VSS[82] VSS[172] BD40 VSS_NCTF_14
AL61 VSS[83] VSS[173] BD44
AM13 VSS[84] VSS[174] BD48
AM20 VSS[85] VSS[175] BD52
AM22 VSS[86] VSS[176] BD56
AM26 VSS[87] VSS[177] BD8 IVY-BRIDGE_BGA1023
AM30 VSS[88] VSS[178] BE5
AM34 VSS[89] VSS[179] BG13
VSS[90] VSS[180]
IVY-BRIDGE_BGA1023
A A

PROCESSOR(7/7) VSS
5 4 3 2 1
5 4 3 2 1
DDR3 SO-DIMM A
+V_DDR_REFA +1.35V +1.35V
+1.35V
3.56A@+1.5V
RP15
+V_DDR_REFA 8 1
JDIMM1 7 2
All VREF traces should +V_DDR_REFA 1 2 +VREF_CA 6 3
D
3 VREF_DQ VSS1 4 DDR_A_D4 5 4 D
have 20 mil trace width VSS2 DQ4
0.1U_0402_16V7K
2.2U_0603_6.3V6K
CD2
DDR_A_D0 5 6 DDR_A_D5
<7> DDR_A_D[0..63] DQ0 DQ5
CD1
1 1 DDR_A_D1 7 8 1K_0804_8P4R_1%
9 DQ1 VSS3 10 DDR_A_DQS#0
<7> DDR_A_DQS[0..7] VSS4 DQS#0
11 12 DDR_A_DQS0
13 DM0 DQS0 14
<7> DDR_A_DQS#[0..7] 2 2 15 VSS5 VSS6 16
DDR_A_D2 DDR_A_D6
DDR_A_D3 17 DQ2 DQ6 18 DDR_A_D7
<7> DDR_A_MA[0..15] 19 DQ3 DQ7 20 +1.35V
DDR_A_D8 21 VSS7 VSS8 22 DDR_A_D12
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13 RP16
25 DQ9 DQ13 26 8 1
VSS9 VSS10 +V_DDR_REFB
DDR_A_DQS#1 27 28 7 2
DDR_A_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST# 6 3
DQS1 RESET# DDR3_DRAMRST# <13,7> +VREF_CB
31 32 5 4
DQ10 DQ14 1
DDR_A_D11 35 36 DDR_A_D15 @ESD@ 1K_0804_8P4R_1%
37 DQ11 DQ15 38 CD99
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21 2
0.1U_0402_16V7K
<1120>Swap assignment.
43 DQ17 DQ21 44
DDR_A_DQS#2 45 VSS15 VSS16 46
DDR_A_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_A_D22
DDR_A_D18 51 VSS18 DQ22 52 DDR_A_D23
DDR_A_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_A_D28
DDR_A_D25 59 DQ24 DQ29 60
63 VSS22 DQS#3 64 DDR_A_DQS3
65 DM3 DQS3 66
DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31
71 DQ27 DQ31 72
VSS25 VSS26
C C
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
<7> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <7>
75 76
77 VDD1 VDD2 78 DDR_A_MA15
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
<7> DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
Layout Note: 99 A1 A0 100
Place near JDIMM1.203 & JDIMM1.204 M_CLK_DDR0 101 VDD9 VDD10 102 M_CLK_DDR1
<7> M_CLK_DDR0 CK0 CK1 M_CLK_DDR1 <7>
M_CLK_DDR#0 103 104 M_CLK_DDR#1
<7> M_CLK_DDR#0 CK0# CK1# M_CLK_DDR#1 <7>
105 106
DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 <7>
DDR_A_BS0 109 110 DDR_A_RAS#
+0.675VS <7> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <7>
111 112
DDR_A_WE# 113 VDD13 VDD14 114 DDR_CS0_DIMMA#
<7> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <7>
<7> DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0 M_ODT0 <7>
117 CAS# ODT0 118
DDR_A_MA13 119 VDD15 VDD16 120 M_ODT1 +VREF_CA
A13 ODT1 M_ODT1 <7>
CD3
1U_0402_6.3V6K
CD4
1U_0402_6.3V6K
CD5
CD6
CD7
10U_0603_6.3V6M
CD8
10U_0603_6.3V6M
CD9
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
DDR_CS1_DIMMA# 121 122

<7> DDR_CS1_DIMMA# 123 S1# NC2 124
1 1 1 1 1 1 1 VDD17 VDD18
125 126 +VREF_CA
127 NCTEST VREF_CA 128
VSS27 VSS28
0.1U_0402_16V7K
DDR_A_D32 129 130 DDR_A_D36
2 2 2 2 2 2 2 DQ32 DQ36
2.2U_0603_6.3V6K
CD11
DDR_A_D33 131 132 DDR_A_D37
DQ33 DQ37
CD10
133 134 1 1
DDR_A_DQS#4 135 VSS29 VSS30 136
139 DQS4 VSS31 140 DDR_A_D38
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39 2 2
DDR_A_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_A_D44
B
DDR_A_D40 147 VSS34 DQ44 148 DDR_A_D45 B
DDR_A_D41 149 DQ40 DQ45 150
153 VSS36 DQS#5 154 DDR_A_DQS5
155 DM5 DQS5 156
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47
Layout Note: 161 DQ43 DQ47 162
Place near JDIMM1 DDR_A_D48 163 VSS39 VSS40 164 DDR_A_D52
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53
Layout Note: Place these 4 Caps near Command 167 DQ49 DQ53 168
and Control signals of DIMMA DDR_A_DQS#6 169 VSS41 VSS42 170
173 DQS6 VSS43 174 DDR_A_D54
+1.35V DDR_A_D50 175 VSS44 DQ54 176 DDR_A_D55
DDR_A_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_A_D60
DQ56 DQ61
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1 DDR_A_D57 183 184

DQ57 VSS47
CD12
CD13
CD14
CD15
CD16
CD17
CD18
CD19
CD20
CD21
1 1 1 1 1 1 1 1 1 1 185 186 DDR_A_DQS#7

+ CD22 187 VSS48 DQS#7 188 DDR_A_DQS7
330U_B2_2.5VM_R15M 189 DM7 DQS7 190
2 2 2 2 2 2 2 2 2 2 2 DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63
195 DQ59 DQ63 196
RD5 1 2 10K_0402_5% 197 VSS51 VSS52 198
199 SA0 EVENT# 200 PCH_SMBDATA
+3VS VDDSPD SDA PCH_SMBDATA <13,15>
2.2U_0603_6.3V6K
0.1U_0402_16V7K
201 202 PCH_SMBCLK

SA1 SCL PCH_SMBCLK <13,15>
CD24
SGA00004400 1 1 203 204

VTT1 VTT2 +0.675VS
1
CD23
10K_0402_5%
RD6
205 206
G1 G2
DDR3 SO-DIMM A 2 2 LCN_DAN06-K4406-0102 0.6A@+0.75VS
2
+1.35V
A A
Standard
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
CD26
CD27
CD28
CD25
1 1 1 1
<Address(SA1,SA0):00>
@ @ @ @
2 2 2 2
LA-A999P
DDRIII DIMM
SI# 8/16 Reserve 4 pcs 0.1uF for EMI noise issue C 0.1
LA-8661P
5 4 3 2 1
5 4 3 2 1
DDR3 SO-DIMM B
10/03 change to +V_DDR_REFB
+V_DDR_REFB +1.35V +1.35V
3.56A@+1.5V
JDIMM2
All VREF traces should +V_DDR_REFB 1 2
3 VREF_DQ VSS1 4 DDR_B_D4
have 20 mil trace width VSS2 DQ4
0.1U_0402_16V7K
2.2U_0603_6.3V6K
CD29
DDR_B_D0 5 6 DDR_B_D5
<7> DDR_B_D[0..63] DQ0 DQ5
CD50
1 1 DDR_B_D1 7 8
9 DQ1 VSS3 10 DDR_B_DQS#0
<7> DDR_B_DQS[0..7] VSS4 DQS#0
11 12 DDR_B_DQS0
D
13 DM0 DQS0 14 D
<7> DDR_B_DQS#[0..7] 2 2 15 VSS5 VSS6 16
DDR_B_D2 DDR_B_D6
DDR_B_D3 17 DQ2 DQ6 18 DDR_B_D7
<7> DDR_B_MA[0..15] 19 DQ3 DQ7 20
DDR_B_D8 21 VSS7 VSS8 22 DDR_B_D12
25 DQ9 DQ13 26
Delete DDR_B_DM[0..7] VSS9 VSS10
DDR_B_DQS#1 27 28
DDR_B_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <12,7>
31 32
37 DQ11 DQ15 38
43 DQ17 DQ21 44
DDR_B_DQS#2 45 VSS15 VSS16 46
DDR_B_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D22
DDR_B_D18 51 VSS18 DQ22 52 DDR_B_D23
DDR_B_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_B_D28
10/03 change to +V_DDR_REFB DDR_B_D24 57 VSS20
DQ24
DQ28
DQ29
58 DDR_B_D29
DDR_B_D25 59 60
63 VSS22 DQS#3 64 DDR_B_DQS3
65 DM3 DQS3 66
71 DQ27 DQ31 72
VSS25 VSS26
DDR_CKE0_DIMMB 73 74 DDR_CKE1_DIMMB
<7> DDR_CKE0_DIMMB CKE0 CKE1 DDR_CKE1_DIMMB <7>
75 76
77 VDD1 VDD2 78 DDR_B_MA15
DDR_B_BS2 79 NC1 A15 80 DDR_B_MA14
<7> DDR_B_BS2 BA2 A14
C 81 82 C
DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
Layout Note: 99 A1 A0 100
Place near JDIMM1.203 & JDIMM1.204 M_CLK_DDR2 101 VDD9 VDD10 102 M_CLK_DDR3
<7> M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 <7>
M_CLK_DDR#2 103 104 M_CLK_DDR#3
<7> M_CLK_DDR#2 CK0# CK1# M_CLK_DDR#3 <7>
105 106
DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <7>
DDR_B_BS0 109 110 DDR_B_RAS#
+0.675VS <7> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <7>
111 112
DDR_B_WE# 113 VDD13 VDD14 114 DDR_CS0_DIMMB#
<7> DDR_B_WE# WE# S0# DDR_CS0_DIMMB# <7>
<7> DDR_B_CAS# DDR_B_CAS# 115 116 M_ODT2 M_ODT2 <7>
117 CAS# ODT0 118
DDR_B_MA13 119 VDD15 VDD16 120 M_ODT3 +VREF_CB
A13 ODT1 M_ODT3 <7>
CD41
1U_0402_6.3V6K
CD51
1U_0402_6.3V6K
CD54
CD48
CD53
10U_0603_6.3V6M
CD52
10U_0603_6.3V6M
CD49
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
DDR_CS1_DIMMB# 121 122

<7> DDR_CS1_DIMMB# 123 S1# NC2 124
1 1 1 1 1 1 1 VDD17 VDD18
125 126 +VREF_CB
127 NCTEST VREF_CA 128
VSS27 VSS28
0.1U_0402_16V7K
DDR_B_D32 129 130 DDR_B_D36
2 2 2 2 2 2 2 DQ32 DQ36
2.2U_0603_6.3V6K
CD30
DDR_B_D33 131 132 DDR_B_D37
DQ33 DQ37
CD55
133 134 1 1
DDR_B_DQS#4 135 VSS29 VSS30 136
139 DQS4 VSS31 140 DDR_B_D38
DDR_B_D34 141 VSS32 DQ38 142 DDR_B_D39 2 2
DDR_B_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_B_D44
DDR_B_D41 149 DQ40 DQ45 150
153 VSS36 DQS#5 154 DDR_B_DQS5
155 DM5 DQS5 156
B
DDR_B_D42 157 VSS37 VSS38 158 DDR_B_D46 B
DDR_B_D43 159 DQ42 DQ46 160 DDR_B_D47
Layout Note: 161 DQ43 DQ47 162
Place near JDIMM1 DDR_B_D48 163 VSS39 VSS40 164 DDR_B_D52
DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D53
Layout Note: Place these 4 Caps near Command 167 DQ49 DQ53 168
and Control signals of DIMMA DDR_B_DQS#6 169 VSS41 VSS42 170
173 DQS6 VSS43 174 DDR_B_D54
+1.35V DDR_B_D50 175 VSS44 DQ54 176 DDR_B_D55
DDR_B_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_B_D60
DQ56 DQ61
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
47U 6.3V M B1 ESR70M
1 1 DDR_B_D57 183 184

DQ57 VSS47
CD37
CD46
CD45
CD40
CD42
CD56
CD44
CD43
CD47
CD39
1 1 1 1 1 1 1 1 1 1 185 186 DDR_B_DQS#7

VSS48 DQS#7
CD36
+ + CD57 187 188 DDR_B_DQS7

47U 6.3V M B1 ESR70M 189 DM7 DQS7 190
@ DDR_B_D58 191 VSS49 VSS50 192 DDR_B_D62
2 2 2 2 2 2 2 2 2 2 2 @ 2 DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D63
195 DQ59 DQ63 196
RD7 1 2 10K_0402_5% 197 VSS51 VSS52 198
199 SA0 EVENT# 200 PCH_SMBDATA
+3VS VDDSPD SDA PCH_SMBDATA <12,15>
2.2U_0603_6.3V6K
0.1U_0402_16V7K
201 202 PCH_SMBCLK

SA1 SCL PCH_SMBCLK <12,15>
CD38
1 1 203 204
VTT1 VTT2 +0.675VS
1
CD31
10K_0402_5%
RD9
205 206
G1 G2
DDR3 SO-DIMM B 2 2 +3VS LCN_DAN06-K4406-0102 0.6A@+0.75VS
2
+1.35V
10/05 change to PH. Standard

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
CD33
CD34
CD35
CD32
A
1 1 1 1
<Address(SA1,SA0):10> A
@ @ @ @
2 2 2 2
SI# 8/16 Reserve 4 pcs 0.1uF for EMI noise issue Security Classification Compal Secret Data Compal Electronics, Inc.
DDRIII-DDRH
0.1
LA-8661P
5 4 3 2 1
5 4 3 2 1
PCH_RTCX1
1 2 PCH_RTCX2
RH115 10M_0402_5%
YH1
1 2
32.768KHZ Q13FC1350000500
SJ10000EC00 <1111> Follow common 10ppm.
CH2 1 1
18P_0201_50V8J
CH3 This is needed to reduce leakage from
18P_0201_50V8J +RTCVCC Coin Cell Battery in G3 state
2 2
RH116 1 2 SM_INTRUDER#
D D
1M_0402_5% 9/7 SMT memo:Follow PM requirement change R1 p/n into PV BOM change to RP
R1: SA00004EES0
R3: SA00004QOB0 11.06
UH1A
+3VS
+RTCVCC PCH_RTCX1 A20 C38 LPC_AD0 RP17
1 RTCX1 FWH0 / LAD0 LPC_AD0 <40,41>
1
CH4 CMOS A38 LPC_AD1 BBS_BIT0_R 8 1
FWH1 / LAD1 LPC_AD1 <40,41>
LPC
1U_0402_6.3V6K CLRP1 PCH_RTCX2 C20 B37 LPC_AD2 EC and TPM. SATA_LED# 7 2
RTCX2 FWH2 / LAD2 C37 LPC_AD2 <40,41> 6 3 +RTCVCC
SHORT PADS LPC_AD3 HDDHALT_LED#
2
1 2 2 D20 FWH3 / LAD3 LPC_AD3 <40,41> 5 4
PCH_RTCRST# SERIRQ
RH117 20K_0402_5% RTCRST# D36 LPC_FRAME#
1 2 PCH_SRTCRST# G22 FWH4 / LFRAME# LPC_FRAME# <40,41> PCH_INTVRMEN RH124 2 1 330K_0402_5%
10K_0804_8P4R_5%
RH118 20K_0402_5% SRTCRST# E36
1 LDRQ0#
1
SM_INTRUDER# K22 K36 PCH_INTVRMEN RH126 2 1 330K_0402_5%
RTC
For EMI CH5 @
1U_0402_6.3V6K CLRP2 INTRUDER# LDRQ1# / GPIO23
131204 SWAP SHORT PADS PCH_INTVRMEN C17 V5 SERIRQ
：：
SERIRQ <40,41>
2
2 ME CMOS INTVRMEN SERIRQ
RP12 INTVRMEN
<37> HDA_BITCLK_AUDIO
8
7
1
2
HDA_BIT_CLK
HDA_RST#
CLP1 & CLP2 place near DIMM
RH506 AM3 +3VS * H Integrated VRM enable
L Integrated VRM disable
<37> HDA_RST_AUDIO# SATA0RXN SATA_PRX_DTX_N0 <34>
6 3 HDA_SYNC_R HDA_BIT_CLK 1 EMI@ 2 HDA_BIT_CLK_OUT N34 AM1
<37> HDA_SYNC_AUDIO HDA_BCLK SATA0RXP SATA_PRX_DTX_P0 <34>
5 4 HDA_SDOUT 0_0402_5% AP7 SATA HDD
SATA 6G
<37> HDA_SDOUT_AUDIO +5VS Prevent back drive issue. SATA0TXN SATA_PTX_DRX_N0 <34>
HDA_SYNC L34 AP5 HDA_SPKR RH139 2 @ 1 1K_0402_5%
HDA_SYNC SATA0TXP SATA_PTX_DRX_P0 <34>
33_0804_8P4R_5%
HDA_SPKR T10 AM10 LOW=Default
<37> HDA_SPKR SPKR SATA1RXN *
2
G
AM8 HIGH=No Reboot

QH1 HDA_RST# K34 SATA1RXP AP11
HDA_SYNC_R 3 1 HDA_SYNC HDA_RST# SATA1TXN AP10
SATA1TXP
S
SB00000S700 HDA_SDIN0 E34 AD7

<37> HDA_SDIN0 HDA_SDIN0 SATA2RXN SATA_PRX_DTX_N2 <34>
BSS138W-7-F_SOT323-3 AD5
SATA2RXP SATA_PRX_DTX_P2 <34>
G34 AH5 ODD
1 2 RH158 1 2 HDA_SDIN1 SATA2TXN AH4 SATA_PTX_DRX_N2 <34>
C34 SATA2TXP SATA_PTX_DRX_P2 <34>
1M_0402_5% RH122 @ 0_0402_5%
HDA_SDIN2 AB8
IHDA
7/12 SI add 1M pull down A34
HDA_SDIN3
SATA3RXN
SATA3RXP
SATA3TXN
AB10
AF3
AF1
HDA_SDO +3V_PCH
9/7 SMT memo:Follow intel ME update requirement SATA3TXP ME debug mode , this signal has a weak internal PD
C add: RH123 1 2 HDA_SDOUT HDA_SDOUT A36 C
<41> HDA_SDO HDA_SDO
RH123 0_0402_5% Y7 L=>security measures defined in the Flash HDA_SDOUT RH140 2 @ 1 1K_0402_5%
SATA
SATA4RXN Y5
C36 SATA4RXP AD3 Descriptor will be in effect (default) Low = Disabled
HDA_DOCK_EN# / GPIO33 SATA4TXN
SATA4TXP
AD1 * High = Enabled
N32 H=>Flash Descriptor Security will be overridden
HDA_DOCK_RST# / GPIO13 Y3
SATA5RXN Y1
SI2 delete RH128& RH127 200 ohm for CPU screw PAD SATA5RXP AB3
12.19 +3V_PCH PCH_JTAG_TCK J3
JTAG_TCK
SATA5TXN
SATA5TXP
AB1 RTC Battery
PCH_JTAG_TMS H7 Y11 +1.05VS_VCC_SATA
JTAG_TMS SATAICOMPO
1
JTAG
@ RH129
@RH129 PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2 +RTCBATT HDA_SYNC
JTAG_TDI SATAICOMPI RH130 37.4_0402_1% +RTCVCC
200_0402_5%
PCH_JTAG_TDO H1 1K_0402_5% 20mils This signal has a weak internal pull-down
JTAG_TDO AB12 +1.05VS_SATA3 On Die PLL VR is supplied by
2
SATA3RCOMPO RH148
PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI 20mils DH1 10mils 1.5V when smapled high
AB13 SATA3_COMP 1 2 2 2 1
SATA3COMPI 1.8V when sampled low
1
RH132 49.9_0402_1% W=20mils 1

RH133 RH134 RH135 RH507 3 Needs to be pulled High for Huron River platfrom
1 +3VL
100_0201_1% 100_0402_1% 100_0402_1% SPI_CLK_PCH 1 EMI@ 2SPI_CLK_PCH_OUT T3 AH1 RBIAS_SATA3 1 2 CH7 W=20mils
0_0402_5% SPI_CLK SATA3RBIAS RH137 750_0402_1% 1U_0402_6.3V6K BAV70W 3P C/C_SOT-323 +3V_PCH
SPI_SB_CS0# Y14 <1118> change to +3VL.
2
SPI_CS0# 2
T1 HDA_SYNC RH149 2 1 1K_0402_5%
SPI_CS1#
SPI
P3 SATA_LED#
SATALED# SATA_LED# <39>
Place CH95 close to PCH.
SPI_SI_PCH V4 V14 HDDHALT_LED#
SPI_MOSI SATA0GP / GPIO21
SPI_SO_PCH U3 P1 BBS_BIT0_R
SI2 change to RH133 0201 SPI_MISO SATA1GP / GPIO19
12.19 PANTHER-POINT_FCBGA989
2 1 PCH_JTAG_TCK +RTCBATT
51_0402_5% RH150
SPI BIOS Pinout SPI BIOS Pinout
RTC BAT conn
B
2 1
15mils B
(1)CS# (5)DIO (1)CS# (5)DIO
- +
(2)DO (6)CLK (2)DO (6)CLK
(3)WP# (7)HOLD# (3)WP# (7)HOLD#
(4)GND (8)VCC (4)GND (8)VCC
JRTC1
EON SA000046400 S IC FL 64M EN25Q64-104HIP SOP 8P W25X32 W25X32 LOTES_AAA-BAT-054-K01
SPI ROM 8M MXIC
WINBOND
SA00006N100
SA000039A30
S
S
IC
IC
FL
FL
64M
64M
MX25L6473EM2I-10G SOP 8P
W25Q64FVSSIQ SOIC 8P SPI ROM
CONN@
Micron SA00005L100 S IC FL 64M N25Q064A13ESEC0F SO8W 8P
(Share ROM)
place close to UH2
RPH17
EC_SPI_SO 8 1 SPI_SO_PCH_R
<41> EC_SPI_SO
EC_SPI_SI 7 2 SPI_SI_PCH_R
EC <41>
<41>
<41>
EC_SPI_SI
EC_SPI_CLK
EC_SPI_CS#
EC_SPI_CLK
EC_SPI_CS#
6
5
3
4
SPI_CLK_PCH_R
SPI_SB_CS0#_R
ROM
15_0804_8P4R_5%
RPH18
SPI_SO_PCH_R 8 1 SPI_SO_PCH
SPI_SI_PCH_R 7 2 SPI_SI_PCH
ROM
SPI_CLK_PCH_R
SPI_SB_CS0#_R
6
5
3
4
SPI_CLK_PCH
SPI_SB_CS0#
CPU
15_0804_8P4R_5%
+3V_PCH
+3V_PCH
A UH2 A
SPI_SB_CS0#_R 1 8
R127 1 2 SPI_WP# SPI_SO_PCH_R 2 CS# VCC 7 SPI_HOLD#
3.3K_0402_5% SPI_WP# 3 SO/SIO1 HOLD# 6 SPI_CLK_PCH_R
4 WP# SCLK 5 SPI_SI_PCH_R
R129 1 2 SPI_HOLD# GND SI/SIO0
3.3K_0402_5% EN25Q64-104HIP
<1111>Modified SPI ROM fix code. Security Classification Compal Secret Data Compal Electronics, Inc.
<1119>Add ROM socket. Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title
<1205>Del ROM socket. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (1/8) SATA,HDA,SPI, LPC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A999P
5 4 3 2 1
5 4 3 2 1
PV# 9/13 change power rail form +3VALW->+3V_PCH
10/03 change to PCIE port1. UH1B

+3V_PCH
+3V_PCH
Mini card WLAN <33> PCIE_PRX_DTX_N1 PCIE_PRX_DTX_N1 BG34 RH155 10K_0402_5%

PCIE_PRX_DTX_P1 BJ34 PERN1 E12 SMBALERT# 1 2 GPIO74 1 2
<33> PCIE_PRX_DTX_P1 PERP1 SMBALERT# / GPIO11
CH85 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N1 AV32 RH263 10K_0402_5%
<33> PCIE_PTX_C_DRX_N1 1 2 0.1U_0402_10V7K AU32 PETN1 H14 SMBCLK 1 2
CH84 PCIE_PTX_DRX_P1 DRAMRST_CNTRL_PCH
<33> PCIE_PTX_C_DRX_P1 PETP1 SMBCLK RH161 1K_0201_5%
PCIE_PRX_DTX_N2 BE34 C9 SMBDATA
<35> PCIE_PRX_DTX_N2 PERN2 SMBDATA
Card Reader PCIE_PRX_DTX_P2 BF34
<35> PCIE_PRX_DTX_P2 PERP2
<35> PCIE_PTX_C_DRX_N2 CH10 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N2 BB32
CH11 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P2 AY32 PETN2
<35> PCIE_PTX_C_DRX_P2 PETP2 A12 DRAMRST_CNTRL_PCH
SMBUS
SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH <10,41,7> +3V_PCH
<35> PCIE_PRX_DTX_N3 PCIE_PRX_DTX_N3 BG36
PCIE_PRX_DTX_P3 BJ36 PERN3 C8 SML0CLK
D <35> PCIE_PRX_DTX_P3 PERP3 SML0CLK D
PCIE LAN <35> PCIE_PTX_C_DRX_N3 CH46 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N3 AV34 RP24
CH27 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P3 AU34 PETN3 G12 SML0DATA SMBCLK 8 1
<35> PCIE_PTX_C_DRX_P3 PETP3 SML0DATA SMBDATA 7 2
BF36 SML1CLK 6 3
BE36 PERN4 SML1DATA 5 4
AY34 PERP4 C13 GPIO74
BB34 PETN4 SML1ALERT# / PCHHOT# / GPIO74 2.2K_0804_8P4R_5%
PETP4 E14 SML1CLK
BG37 SML1CLK / GPIO58 +3V_PCH
PCI-E*
BH37 PERN5 M16 SML1DATA
AY36 PERP5 SML1DATA / GPIO75 +3VS
BB36 PETN5 RP23
PETP5 SML0CLK 8 1
BJ38 SML0DATA 7 2
BG38 PERN6 PCH_SMBCLK 6 3
AU36 PERP6 M7 PCH_SMBDATA 5 4
Controller
AV36 PETN6 CL_CLK1
PETP6 2.2K_0804_8P4R_5%
BG40 T11
Link
BJ40 PERN7 CL_DATA1 +3V_PCH
PERP7
<1113>Swap.
AY40 <1118> add SML0 ; SMB2 removed.
BB40 PETN7 P10
PETP7 CL_RST1#
1
DIS@
BE38 RH8
BC38 PERN8
PERP8 10K_0402_5%
AW38
AY38 PETN8
2
PETP8
M10 PEG_CLKREQ#_R 2 DIS@ 1
PEG_A_CLKRQ# / GPIO47 GPU_CLKREQ# <22>
RH4 1 short@ 2 0_0402_5% PCIE_MINI1# Y40 0_0402_5% RH412
<33> CLK_PCIE_MINI1# 1 short@ 2 0_0402_5% PCIE_MINI1 Y39 CLKOUT_PCIE0N
MiniWLAN RH5
<33> CLK_PCIE_MINI1 CLKOUT_PCIE0P AB37 1 DIS@ 2 0_0402_5%
RH171 CLK_VGA# RH410
1 2 10K_0201_5% J2 CLKOUT_PEG_A_N AB38 1 DIS@ 2 0_0402_5% CLK_PCIE_GPU# <22>
MINI1_CLKREQ# CLK_VGA RH411
<1119>Change back to +3V_PCH. <22> 100MHz
CLOCKS
+3V_PCH PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P CLK_PCIE_GPU
<33> MINI1_CLKREQ#
RH178 1 short@ 2 0_0402_5% PCIE_CR# AB49 AV22 CLK_CPU_DMI#_PCH RH172 1 short@ 2 0_0402_5% CLK_CPU_DMI#
<35> CLK_PCIE_CR# 1 short@ 2 0_0402_5% AB47 CLKOUT_PCIE1N CLKOUT_DMI_N AU22 CLK_CPU_DMI_PCH 1 short@ 2 0_0402_5% CLK_CPU_DMI# <6>
C Card Reader RH179 PCIE_CR RH173 CLK_CPU_DMI 100MHz C
<35> CLK_PCIE_CR CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI <6>
RH181 2 1 10K_0201_5% CR_CLKREQ# M1 131127 SWAP Pin of RP9.1 & RP9.2 by layout requested
+3VS PCIECLKRQ1# / GPIO18 AM12
<35> CR_CLKREQ# CLKOUT_DP_N CLK_R_EDP# <6>
AM13 RP9 10K_0804_8P4R_5%
1 short@ 2 0_0402_5% PCIE_LAN# AA48 CLKOUT_DP_P CLK_R_EDP <6> 1 8
RH10 CLKIN_DMI2
<35> CLK_PCIE_LAN# 1 short@ 2 0_0402_5% PCIE_LAN AA47 CLKOUT_PCIE2N 2 7
PCIE LAN RH9 CLKIN_DMI2#
<35> CLK_PCIE_LAN CLKOUT_PCIE2P BF18 CLKIN_DMI# 3 6
131224 CLKIN_DMI#
RH182 1 2 10K_0201_5% LAN_CLKREQ# V10 CLKIN_DMI_N BE18 CLKIN_DMI For Integrated Graphics designs using eDP on Ivy Bridge. CLKIN_DMI 4 5
+3VS PCIECLKRQ2# / GPIO20 CLKIN_DMI_P
<35> LAN_CLKREQ# For designs not using eDP, can leave as No Connect
RP18 10K_0804_8P4R_5%
Y37 BJ30 CLKIN_DMI2# CLKIN_DOT96# 1 8
Y36 CLKOUT_PCIE3N CLKIN_GND1_N BG30 CLKIN_DMI2 CLKIN_DOT96 2 7
CLKOUT_PCIE3P CLKIN_GND1_P CLKIN_SATA# 3 6
RH180 2 1 10K_0402_5% A8 CLKIN_SATA 4 5
+3V_PCH PCIECLKRQ3# / GPIO25 G24 CLKIN_DOT96#
CLKIN_DOT_96N E24 CLKIN_DOT96 CLK_PCH_14M RH170 1 2 10K_0402_5%
Y43 CLKIN_DOT_96P
SI2 change to 0201 CLKOUT_PCIE4N
<1113>change to RP18.
Y45
CLKOUT_PCIE4P
12.19 RH177 2 1 10K_0201_5% L12 CLKIN_SATA_N
AK7 CLKIN_SATA#
AK5 CLKIN_SATA
If use extenal CLK gen, please place close to CLK gen
else, please place close to PCH
+3V_PCH PCIECLKRQ4# / GPIO26 CLKIN_SATA_P
V45 K45 CLK_PCH_14M +3VS

V46 CLKOUT_PCIE5N REFCLK14IN
CLKOUT_PCIE5P
+3V_PCH RH274 2 1 10K_0402_5% L14 H45 CLK_PCI_LPBACK
CLK_PCI_LPBACK <17>
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK
2
AB42 V47 XTAL25_IN 2N7002DWH_SOT363-6
SI2 change to 0201 AB40 CLKOUT_PEG_B_N XTAL25_IN V49 XTAL25_OUT
CLKOUT_PEG_B_P XTAL25_OUT
12.19 RH183 1 2 10K_0201_5% E6
SMBCLK 6 1
PCH_SMBCLK <12,13>
+3V_PCH PEG_B_CLKRQ# / GPIO56 QH2A
Change WL_OFF# to GPIO45 (pull-high) +3V_PCH Y47 XCLK_RCOMP 1 2
XCLK_RCOMP +1.05VS_VCCDIFFCLKN
2012.01.04 V40 RH184 90.9_0402_1% RH192 @
V42 CLKOUT_PCIE6N 1 2
<33> WL_OFF# CLKOUT_PCIE6P
5
+3VS 0_0402_5%
B B
RH185 1 2 10K_0402_5% WL_OFF# T13
+3V_PCH PCIECLKRQ6# / GPIO45 SMBDATA 3 4
PCH_SMBDATA <12,13>
2
XTAL25_IN V38 K43
V37 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
FLEX CLOCKS
RH318 2N7002DWH_SOT363-6
2 1 XTAL25_OUT CLKOUT_PCIE7P F47 UMA@ 10K_0402_5%
CLKOUTFLEX1 / GPIO65 QH2B
1M_0402_5% RH187 +3V_PCH RH189 1 2 10K_0402_5% K12 RH194
YH2 25MHZ_10PF_7V25000014 PCIECLKRQ7# / GPIO46 H47 1 2
1
RH190 2 @ 1 0_0402_5% CLK_BCLK_ITP# AK14 CLKOUTFLEX2 / GPIO66 0_0402_5%
<8> CLK_RES_ITP# CLKOUT_ITPXDP_N
1 3 RH191 2 @ 1 0_0402_5% CLK_BCLK_ITP AK13 K49 DGPU_PRSNT# @
1 3 <8> CLK_RES_ITP CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67
2
GND GND
SJ10000E500 PANTHER-POINT_FCBGA989 RH319 +3VS
2 4 131202 Follow 15" CRV DIS@ 10K_0402_5%
1 1
1
CH12 CH13
10P_0402_25V8K 10P_0402_25V8K
2 2
2
<1118>change to standard part. <1126>Del RH193/CH14/RH195/CH15 2N7002DWH_SOT363-6
SML1CLK 6 1
EC_SMB_CK2 <22,41>
QH6A
5
SML1DATA 3 4
EC_SMB_DA2 <22,41>
2N7002DWH_SOT363-6
A QH6B A
SI# 8/8 Add SML1CLK/SML1DATA for EC detect Thermal

PCH (2/8) PCIE, SMBUS, CLK
0.1
LA-A999P
5 4 3 2 1
5 4 3 2 1
UH1C
<5> DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0 FDI_CTX_PRX_N0 <5>

DMI_CTX_PRX_N1 BE20 DMI0RXN FDI_RXN0 AY14 FDI_CTX_PRX_N1
<5> DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 <5>
<5> DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2 FDI_CTX_PRX_N2 <5>
DMI_CTX_PRX_N3 BG20 DMI2RXN FDI_RXN2 BH13 FDI_CTX_PRX_N3
<5> DMI_CTX_PRX_N3 DMI3RXN FDI_RXN3 FDI_CTX_PRX_N3 <5>
BC12 FDI_CTX_PRX_N4 FDI_CTX_PRX_N4 <5>
DMI_CTX_PRX_P0 BE24 FDI_RXN4 BJ12 FDI_CTX_PRX_N5
<5> DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 <5>
<5> DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6 FDI_CTX_PRX_N6 <5>
DMI_CTX_PRX_P2 BJ18 DMI1RXP FDI_RXN6 BG9 FDI_CTX_PRX_N7
<5> DMI_CTX_PRX_P2 DMI2RXP FDI_RXN7 FDI_CTX_PRX_N7 <5>
<5> DMI_CTX_PRX_P3 DMI_CTX_PRX_P3 BJ20
DMI3RXP BG14 FDI_CTX_PRX_P0
FDI_RXP0 FDI_CTX_PRX_P0 <5>
DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1 FDI_CTX_PRX_P1 <5>
D <5> DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1 D
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2 FDI_CTX_PRX_P2 <5>
<5> DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2
DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 FDI_CTX_PRX_P3 <5>
DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4 FDI_CTX_PRX_P4 <5>
DMI
FDI
BG12 FDI_CTX_PRX_P5 FDI_CTX_PRX_P5 <5>
DMI_CRX_PTX_P0 AY24 FDI_RXP5 BJ10 FDI_CTX_PRX_P6
<5> DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 <5>
DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 FDI_CTX_PRX_P7 <5>
<5> DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7
DMI_CRX_PTX_P2 AY18
<5> DMI_CRX_PTX_P2 DMI2TXP
DMI_CRX_PTX_P3 AU18
<5> DMI_CRX_PTX_P3 DMI3TXP +3VS
AW16 FDI_INT
FDI_INT FDI_INT <5>
+VCCP BJ24 AV12 FDI_FSYNC0
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <5>
To VccIO. 1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1 RP14
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <5>
RH196 49.9_0402_1% 8 1 LCD_EDID_DATA
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0 7 2 LCD_EDID_CLK
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <5>
RH197 750_0402_1% 6 3 CTRL_CLK
4mil width and place BB10 FDI_LSYNC1 5 4 CTRL_DATA
FDI_LSYNC1 FDI_LSYNC1 <5>
within 500mil of the PCH 131204 SWAP
2.2K_0804_8P4R_5%
PCH_SUSWARN# 1 2 SUSACK#_R A18 DSWODVREN

RH198 @ 0_0201_5% DSWVRMEN
SI2 change to 0201 RH199 1 2 0_0201_5% PCH_RSMRST#
System Power Management

12.19 <41> SUSACK# 1 2 SUSACK#_R C12
SUSACK# DPWROK
E22 PCH_DPWROK PCH_DPWROK <41>
RH200 short@
0_0201_5% 1 2 AOAC_PME# <17,41><1111> Reserved for deep sleep. UH1D
RH504 0_0201_5%
<6> XDP_DBRESET# XDP_DBRESET# K3 B9 WAKE# 1 short@ 2 0_0402_5% PCH_PCIE_WAKE# <44> <41> ENBKL ENBKL J47 AP43
SYS_RESET# WAKE# RH201 M45 L_BKLTEN SDVO_TVCLKINN AP45
<30> PCH_ENVDD L_VDD_EN SDVO_TVCLKINP
<6> SYS_PWROK SYS_PWROK 1 short@ 2 P12 N3 PM_CLKRUN# PM_CLKRUN# <41> <30> DPST_PWM P45 AM42
RH202 0_0402_5% SYS_PWROK CLKRUN# / GPIO32 L_BKLTCTL SDVO_STALLN AM40
LCD_EDID_CLK T40 SDVO_STALLP
C
<30> LCD_EDID_CLK L_DDC_CLK C
<41> PCH_PWROK PCH_PWROK1 short@ 2 PM_PWROK_R L22 G8 SUS_STAT# T44 PAD <30> LCD_EDID_DATA LCD_EDID_DATA K47 AP39
RH203 0_0402_5% PWROK SUS_STAT# / GPIO61 LPCPD# pin of LPC devices may L_DDC_DATA SDVO_INTN AP40
be connected to PCH SUS_STAT# pin. CTRL_CLK T45 SDVO_INTP
1 short@ 2 L10 N14 SUSCLK T45 PAD CTRL_DATA P39 L_CTRL_CLK
RH204 0_0402_5% APWROK SUSCLK / GPIO62 <1111> Remove SUSCLK. L_CTRL_DATA
LVDS_IBG AF37 P38
LVD_IBG SDVO_CTRLCLK PCH_DDPB_CLK <31>
<6> PM_DRAM_PWRGD PM_DRAM_PWRGD B13 D10 PM_SLP_S5# PM_SLP_S5# <41> PAD T37 AF36 M39
DRAMPWROK SLP_S5# / GPIO63 LVD_VBG SDVO_CTRLDATA PCH_DDPB_DAT <31>
1 short@ 2 LVD_VREF AE48
PCH_RSMRST# 1 short@ 2PCH_RSMRST#_R C21 H4 PM_SLP_S4# RH207 0_0402_5% AE47 LVD_VREFH AT49
<41> PCH_RSMRST# RSMRST# SLP_S4# PM_SLP_S4# <41> LVD_VREFL DDPB_AUXN
RH206 0_0402_5% AT47
DDPB_AUXP AT40
DDPB_HPD PCH_DDPB_HPD <31>
<41> PCH_SUSWARN# PCH_SUSWARN# 1 2 SUSWARN#_R K16 F4 PM_SLP_S3# LVDS_CLKN AK39
SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# <41> <30> LVDS_CLKN LVDSA_CLK#
LVDS
0_0201_5% LVDS_CLKP AK40 AV42
RH208 short@ <30> LVDS_CLKP LVDSA_CLK DDPB_0N AV40
PCH_DPB_N2 <31> HDMI
DDPB_0P PCH_DPB_P2 <31>
1 short@ 2 PBTN_OUT#_R E20 G10 SLP_A# LVDS_TXN0 AN48 AV45
<41> PBTN_OUT#
RH209 0_0402_5% PWRBTN# SLP_A# SLP_A# <41> <30> LVDS_TXN0
LVDS_TXN1 AM47 LVDSA_DATA#0 HDMIDDPB_1N AV46
PCH_DPB_N1 <31>
<30> LVDS_TXN1 LVDSA_DATA#1 DDPB_1P PCH_DPB_P1 <31>
Digital Display Interface

LVDS_TXN2 AK47 AU48 PCH_DPB_N0 <31>
<30> LVDS_TXN2 LVDSA_DATA#2 DDPB_2N
<41,46,47,48> ACIN 1 2 ACIN_R H20 G16 PM_SLP_SUS# PM_SLP_SUS# <41> AJ48 AU47 PCH_DPB_P0 <31>
DH2 CH751H-40PT_SOD323-2 ACPRESENT / GPIO31 SLP_SUS# LVDSA_DATA#3 DDPB_2P AV47
DDPB_3N PCH_DPB_N3 <31>
LVDS_TXP0 AN47 AV49 PCH_DPB_P3 <31>
<30> LVDS_TXP0 LVDSA_DATA0 DDPB_3P
PM_BATLOW# E10 AP14 H_PM_SYNC LVDS_TXP1 AM49
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <6> <30> LVDS_TXP1 LVDSA_DATA1
LVDS_TXP2 AK49
<30> LVDS_TXP2 LVDSA_DATA2
AJ47 P46
GPIO29 PU to follow Intel request. RI# A10 K14 PCH_GPIO29 LVDSA_DATA3 DDPC_CTRLCLK P42
RI# SLP_LAN# / GPIO29 DDPC_CTRLDATA
11.04
AF40
PANTHER-POINT_FCBGA989 GPIO29 PU to follow Intel request. AF39 LVDSB_CLK# AP47
+3V_PCH LVDSB_CLK DDPC_AUXN AP49
11.04 DDPC_AUXP
RP25 +3V_DSW AH45 AT38
RI# 8 1 AH47 LVDSB_DATA#0 DDPC_HPD
PCH_GPIO29 7 2 AF49 LVDSB_DATA#1 AY47
B PM_BATLOW# 6 3 PCH_PWROK 2 1 PCH_RSMRST# AF45 LVDSB_DATA#2 DDPC_0N AY49 B
WAKE# 5 4 +RTCVCC DH30 CH751H-40PT_SOD323-2 LVDSB_DATA#3 DDPC_0P AY43
<1122>Reserved for deep Sx. AH43 DDPC_1N AY45
10K_0804_8P4R_5% AH49 LVDSB_DATA0 DDPC_1P BA47
DSWODVREN RH213 2 1 330K_0402_5% 1 2 AF47 LVDSB_DATA1 mDP DDPC_2N BA48
<49> SPOK LVDSB_DATA2 DDPC_2P
<1119>change to 10K. DH29 CH751H-40PT_SOD323-2 AF43 BB47
ACIN_R RH214 1 2 10K_0201_5% DSWODVREN RH215 2 1 330K_0402_5% LVDSB_DATA3 DDPC_3N BB49
@ DDPC_3P
PCH_SUSWARN# RH216 1 2 10K_0201_5%
*：
DSWODVREN - On Die DSW VR Enable CRT_B RH508 EMI@ 1 2 47NH_LQG15HS47NJ02D_0.2A_5% CRT_B_R N48 M43
：
<32> CRT_B CRT_BLUE DDPD_CTRLCLK
ACIN_R RH219 1 2 10K_0201_5% H Enable <32> CRT_G
CRT_G RH509 EMI@ 1 2 47NH_LQG15HS47NJ02D_0.2A_5% CRT_G_R P49 M36
@ L Disable CRT_R RH510 EMI@ 1 2 47NH_LQG15HS47NJ02D_0.2A_5% CRT_R_R T49 CRT_GREEN DDPD_CTRLDATA
<32> CRT_R CRT_RED
PCH_RSMRST# RH217 1 2 10K_0402_5% AT45
DDPD_AUXN
CRT
CRT_DDC_CLK T39 AT43
<32> CRT_DDC_CLK CRT_DDC_CLK DDPD_AUXP
SI2 change to 0201 RP20 CRT_DDC_DATA M40 BH41
<32> CRT_DDC_DATA CRT_DDC_DATA DDPD_HPD
8 1 CRT_B
12.19 7 2 CRT_G BB43
6 3 CRT_R M47 DDPD_0N BB45
CH268 <32> HSYNC CRT_HSYNC DDPD_0P
@ SI# 8/16 Reserve C268 100pF 5 4
<32> VSYNC
M49
DMC DDPD_1N BF44
PCH_PWROK 1 2 CRT_VSYNC BE44 +3VS
by ESD request DDPD_1P
150_0804_8P4R_1% BF42
CRT_IREF T43 DDPD_2N BE42
100P_0201_50V8J T42 DAC_IREF DDPD_2P BJ42
CRT_IRTN DDPD_3N
1
+3VS PM_CLKRUN# BG42
Max = 800 mils EC Request DDPD_3P
1
R560 R524
+3VS on 20110309 PANTHER-POINT_FCBGA989 2.2K_0402_5% 2.2K_0402_5%
RH220
1
1K_0402_0.5%
2
5
UH3 RH308
2
RH218 1 2 8.2K_0402_5% PM_CLKRUN# 10K_0402_5% CRT_DDC_CLK
VCC
PCH_PWROK 1 CRT_DDC_DATA
A IN1 4 SYS_PWROK @ A
2
2 OUT
GND
<53> VGATE IN2
MC74VHC1G08DFT2G_SC70-5 1 2 LVDS_IBG
3
RH222 2.37K_0402_1%
1 2 PCH_ENVDD
RH224 100K_0402_5%
RH223 2 1 10K_0402_5% SYS_PWROK 1 2 ENBKL
RH225 100K_0402_5% 2011/06/29 2011/06/29 Title
NOTE:It is recommended that SYS_PWROK
be asserted after both PWROK assertion and
PCH (3/8) DMI,FDI,PM,GFX,DP
CPU core VR powergood assertion. This needed Size Document Number Rev
to ensure a safe platform design which meets 0.1
the timing requirements for this signal.
LA-A999P
5 4 3 2 1
5 4 3 2 1
UH1E
AY7
RSVD1 AV7
BG26 RSVD2 AU3
BJ26 TP1 RSVD3 BG4
BH25 TP2 RSVD4
BJ16 TP3 AT10
BG16 TP4 RSVD5 BC8
AH38 TP5 RSVD6
AH37 TP6 AU2
AK43 TP7 RSVD7 AT4
AK45 TP8 RSVD8 AT3
C18 TP9 RSVD9 AT1
N30 TP10 RSVD10 AY3
H3 TP11 RSVD11 AT5
D AH12 TP12 RSVD12 AV3 D
AM4 TP13 RSVD13 AV1
AM5 TP14 RSVD14 BB1
Y13 TP15 RSVD15 BA3
K24 TP16 RSVD16 BB5
L24 TP17 RSVD17 BB3
AB46 TP18 RSVD18 BB7
AB45 TP19 RSVD19 BE8
TP20 RSVD20
RSVD
BD4
RSVD21 BF6
RSVD22
B21 AV5
M20 TP21 RSVD23 AV10
AY16 TP22 RSVD24
BG46 TP23 AT8
TP24 RSVD25
AY5
RSVD26 BA2
BE28 RSVD27
<36> USB3_RX1_N USB3Rn1
BC30 AT12
BE32 USB3Rn2 RSVD28 BF3
BJ32 USB3Rn3 RSVD29
BC28 USB3Rn4
<36> USB3_RX1_P USB3Rp1
BE30 USB DEBUG=PORT1 AND PORT9
BF32 USB3Rp2
BG32 USB3Rp3 C24 USB20_N0
USB3.0 x1 AV26 USB3Rp4 USBP0N A24 USB20_P0
USB20_N0 <36>
<36> USB3_TX1_N
BB26 USB3Tn1 USBP0P C25 USB20_P0 <36> To USB3.0 connector (Port 1)
USB20_N1
USB3Tn2 USBP1N USB20_N1 <36>
AU28 B25 USB20_P1 USB2.0
USB3Tn3 USBP1P USB20_P1 <36>
AY30 C26 USB20_N2
USB3Tn4 USBP2N USB20_N2 <36>
AU26 A26 USB20_P2 USB2.0
<36> USB3_TX1_P USB3Tp1 USBP2P USB20_P2 <36>
AY26 K28
AV28 USB3Tp2 USBP3N H28
C
AW30 USB3Tp3 USBP3P E28 C
USB3Tp4 USBP4N D28
USBP4P C28
HM76 not support USB2.0 for port 6-7
USBP5N A28
USBP5P C29
HM70 not support USB2.0 for port 4-7 &12 &13
USBP6N B29
PCI_PIRQA# K40 USBP6P N28
NM70 not support USB2.0 for port 4-7 &12 &13
PCI_PIRQB# K38 PIRQA# USBP7N M28
PIRQB# USBP7P
PCI
PCI_PIRQC# H38 L30 USB20_N8
G38 PIRQC# USBP8N K30 USB20_N8 <30>
PCI_PIRQD# USB20_P8 USB Camera
PIRQD# USBP8P USB20_P8 <30>
G30 USB20_N9
USBP9N USB20_N9 <33>
DGPU_HOLD_RST# C46 E30 USB20_P9 WLAN
<22,41> DGPU_HOLD_RST# REQ1# / GPIO50 USBP9P USB20_P9 <33>
USB
@ PAD T38 DGPU_SELECT# C44 C30 USB20_N10
REQ2# / GPIO52 USBP10N USB20_N10 <30>
<25,41,56> DGPU_PWR_EN DGPU_PWR_EN1 2 GPIO54 E40 A30 USB20_P10 Touch Screen
REQ3# / GPIO54 USBP10P USB20_P10 <30>
RH505 @ 0_0201_5% L32
GPIO51 D47 USBP11N K32
<1118>Follow HSW control by EC. GPIO53 E42 GNT1# / GPIO51 USBP11P G32
<1118>Re-assign USB 2.0 port. +3V_PCH
GPIO55 F46 GNT2# / GPIO53 USBP12N E32
GNT3# / GPIO55 USBP12P C32 RPH1
USBP13N A32 USB_OC0# 4 5
USBP13P <36> USB_OC0#
<40> ACCEL_INT# ACCEL_INT# G42 <36> USB_OC1# USB_OC1# 3 6
ODD_DA# G40 PIRQE# / GPIO2 USB_OC2# 2 7
<34> ODD_DA#
DP_CBL_DET C42 PIRQF# / GPIO3 C33 USBRBIAS
Within
1
500 2mils USB_OC3# 1 8
PIRQH# D44 PIRQG# / GPIO4 USBRBIAS# RH229 22.6_0402_1%
PIRQH# / GPIO5 10K_0804_8P4R_5%
B33 RPH2
AOAC_PME# K10 USBRBIAS USB_OC6# 4 5
<16,41> AOAC_PME# PME# USB_OC4# 3 6
PLT_RST#_PCH C6 A14 USB_OC0# USB_OC7# 2 7
PLTRST# OC0# / GPIO59 K20 USB_OC1# USB_OC5# 1 8
OC1# / GPIO40 B17 USB_OC2#
CLK_PCI_LPBACK RH230 2 EMI@ 1 22_0402_5% CLK_PCI0 H49 OC2# / GPIO41 C16 USB_OC3# 10K_0804_8P4R_5%
<15> CLK_PCI_LPBACK CLKOUT_PCI0 OC3# / GPIO42
B CLK_PCI_LPC RH231 1 EMI@ 2 22_0402_5% CLK_PCI1 H43 L16 USB_OC4# B
<40,41> CLK_PCI_LPC CLKOUT_PCI1 OC4# / GPIO43
J48 A16 USB_OC5#
K42 CLKOUT_PCI2 OC5# / GPIO9 D14 USB_OC6#
H40 CLKOUT_PCI3 OC6# / GPIO10 C14 USB_OC7#
CLKOUT_PCI4 OC7# / GPIO14
+3VS
PANTHER-POINT_FCBGA989
RPH3
ACCEL_INT# 1 8
PCI_PIRQD# 2 7
PCI_PIRQB# 3 6
PCI_PIRQC# 4 5
8.2K_0804_8P4R_5%
RPH4 @
GPIO51 1 8 +3VS 1 2
PIRQH# 2 7 RH232 0_0402_5%
GPIO53 3 6
2
DP_CBL_DET 4 5 @ +3VS
RH233
8.2K_0804_8P4R_5% 10K_0402_5%
5
UH4
1
RH7 1 PLT_RST#_PCH
P
PCI_PIRQA# 1 2 8.2K_0402_5% 4 IN1

<22,33,35,40,41,6> PLT_RST# O 2
IN2
G
ODD_DA# 1 RH6 2 8.2K_0402_5%

1
SN74AHC1G08DCKR_SC70-5
3
GPIO55 1 RH320 2 10K_0402_5% PD 100K@ KBC side @ RH234

100K_0402_5%
2
A A
DGPU_SELECT# 1 RH236 2 10K_0402_5%
GPIO54 1 RH237 2 10K_0402_5%
DGPU_HOLD_RST# @1 RH334 2 10K_0402_5%
Follow Powell reserve PU 10K

PCH (4/8) PCI, USB, NVRAM
0.1
LA-A999P
5 4 3 2 1
5 4 3 2 1
+3VS
2
<1119>ODD_PWR change to GPIO68.
UH1F RH330
10K_0402_5%
NMI_DBG#_CPU T7 C40 ODD_PWR
<41> NMI_DBG#_CPU BMBUSY# / GPIO0 TACH4 / GPIO68 ODD_PWR <34>
1
GPIO1 A42 B41
TACH1 / GPIO1 TACH5 / GPIO69
GPIO6 H36 C41 +3VS
<41> EC_SCI# EC_SCI# E38 A40

2
D D
GPIO28 EC_SMI# C10 RH238
GPIO8
10K_0402_5%
On-Die PLL Voltage Regulator LAN_PWR_EN C4 This signal should be connected to
<35> LAN_PWR_EN LAN_PHY_PWR_CTRL / GPIO12 the processor's UNCOREPWRGD
1
This signal has a weak internal pull up RH154 1 short@ 2 EC_LID_OUT#_R G2 P4 input to indicate when the processor power is valid.
* ：On-Die voltage regulator enable

<41> EC_LID_OUT# GPIO15 A20GATE GATEA20 <41>
0_0201_5%
H AU16 PCH_PECI_R 1 @ 2
L：On-Die PLL Voltage Regulator disable

PECI H_PECI <41,6>
RC124 1@ 2 0_0201_5% PCH_GPIO16 U2 0_0402_5% RH239
<24> DGPU_GC6_EN SATA4GP / GPIO16 P5 EC_KBRST# +1.8VS
RCIN# EC_KBRST# <41>
11.07 follow Lotus PU to +3VS
RC126 1@ 2 0_0201_5% DGPU_PWROK_R D40
GPIO
AY11
<25,56> DGPU_PWROK TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD <6>
1
+3V_PCH
CPU/MISC
131202 follow 15" CRV
RC125 1@ 2 0_0201_5% PCH_GPIO22 T5 AY10 H_THERMTRIP#_C 1 2 H_THRMTRIP# H_THRMTRIP# <6> RH226
1 2 SLP_ME_CSW_DEV# <41> EC_FB_CLAMP_TGL_REQ# SCLOCK / GPIO22 THRMTRIP# 390_0402_5% RH240 2.2K_0402_5%
RH267 10K_0402_5% PAD T49 PCH_GPIO24 E8 T14
GPIO24 INIT3_3V#
<1122>Reserved for deep Sx.
2
EC_PME# E16 AY1 NV_CLE 2 1 H_SNB_IVB# <6>
1 2 SLP_ME_CSW_DEV# <35,41> EC_PME# GPIO27 DF_TVS RH227 1K_0402_5%
RH241 1K_0402_5% SLP_ME_CSW_DEV# P8
<41> SLP_ME_CSW_DEV# GPIO28 Layout note: CLOSE TO THE BRANCHING POINT
@ AH8
PCH_GPIO34 K1 TS_VSS1 +3VS
STP_PCI# / GPIO34 AK11
PCH_GPIO35 K4 TS_VSS2
GPIO35 AH10 ODD_PWR 1 @ 2
ODD_PLUG# V8 TS_VSS3 RH310 10K_0402_5%
<34> ODD_PLUG# SATA2GP / GPIO36 AK10
PCH_GPIO37 M5 TS_VSS4 RP10
<30> TS_GPIO_CPU SATA3GP / GPIO37 PCH_GPIO16 1 8
PCH_GPIO37 GPIO38 N2 P37 EC_KBRST# 2 7
SLOAD / GPIO38 NC_1 131202 follow 15" CRV 3 6
FDI TERMINATION VOLTAGE OVERRIDE DGPU_PWROK_R
PCH_GPIO39 M3 PCH_GPIO22 4 5
C SDATAOUT0 / GPIO39 C
LOW - Tx, Rx terminated
* to same voltage PCH_GPIO48 V13
SDATAOUT1 / GPIO48 VSS_NCTF_15
BG2 10K_0804_8P4R_5%
(DC Coupling Mode)
GPIO49 V3 BG48
SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
+3VS HDD_DETECT# D6 BH3 +3VS
GPIO57 VSS_NCTF_17
BH47 RP11
RH245 2 @ 1 1K_0402_5% PCH_GPIO37 VSS_NCTF_18 GPIO38 1 8
A4 BJ4 PCH_GPIO39 2 7
VSS_NCTF_1 VSS_NCTF_19 131204 SWAP PCH_GPIO34 3 6
RH246 2 1 PCH_GPIO37 A44 BJ44 PCH_GPIO35 4 5
VSS_NCTF_2 VSS_NCTF_20
100K_0402_5% A45 BJ45 10K_0804_8P4R_5%
A46
NCTF
BJ46
A5 BJ5 +3V_PCH
GPIO27 A6
BJ6
NMI_DBG#_CPU 1
RP13
8
PCH_GPIO27 (Have internal Pull-High) B3 C2 HDD_DETECT# 2 7
VSS_NCTF_7 VSS_NCTF_25 EC_LID_OUT#_R 3 6
*High: VCCVRM VR Enable
Low: VCCVRM VR Disable
B47
C48 HDD_DETECT# 4 5
BD1 D1 10K_0804_8P4R_5%
+3V_DSW <1122>Reserved for deep Sx. BD49 D49
VSS_NCTF_10 VSS_NCTF_28 +3VS
BE1 E1
1 2 EC_PME# VSS_NCTF_11 VSS_NCTF_29 RP19
RH251 10K_0402_5% BE49 E49 GPIO1 1 8
B VSS_NCTF_12 VSS_NCTF_30 GPIO6 2 7 B
BF1 F1 PCH_GPIO48 3 6
1 2 EC_PME# VSS_NCTF_13 VSS_NCTF_31 GPIO49 4 5
@ RH250 10K_0402_5% BF49 F49
VSS_NCTF_14 VSS_NCTF_32 10K_0804_8P4R_5%
PANTHER-POINT_FCBGA989
LAN_PWR_EN 1 2
RH311 10K_0402_5%
DB# 10/20 Reserve GPIO 36 pull up resistor

and add pull down resistor
+3VS
10K_0402_5% 2 1 ODD_PLUG#
RH322
10K_0402_5% 2 1 EC_SMI#
RH255
A A

PCH (5/8) GPIO, CPU, MISC
0.1
LA-A999P
5 4 3 2 1
5 4 3 2 1
+VCCP PCH Power Rail Table

UH1G POWER +3VS S0 Iccmax
Voltage Rail Voltage Current (A)
0.01U_0201_16V7
1300mA LH1
AA23 U48 2 1
0.1U_0201_16V4Z
1mA VCCADAC +VCCADAC
VCCCORE[1]
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
AC23 1 1 1 BLM18PG181SN1D_2P V_PROC_IO 1.05 0.001
VCCCORE[2]
CH20
1 1 1 1 AD21
CRT
VCCCORE[3]
CH19
CH16
CH18
CH21
AD23 U47 CH22
AF21 VCCCORE[4] VSSADAC
CH17 10U_0603_6.3V6M V5REF 5 0.001
VCC CORE
10U_0603_6.3V6M AF23 VCCCORE[5] 2 2 2
D 2 2 2 2 AG21 VCCCORE[6] +3VS D
AG23 VCCCORE[7]
VCCCORE[8]
V5REF_Sus 5 0.001
AG24 1mA VCCALVDS AK36
AG26 VCCCORE[9]
AG27 VCCCORE[10] AK37 +1.8VS
VCCCORE[11] VSSALVDS
Vcc3_3 3.3 0.266
AG29 0.1UH_MLF1608DR10KT_10%_1608
2011.10.18 change all cap to small size: VCCCORE[12]
0.01U_0201_16V7
0.01U_0201_16V7
AJ23 Near AP43 LH2
VCCCORE[13]
22u& 10u to 0603
22U_0603_6.3V6M
AJ26 AM37 2 1
LVDS
+VCCTX_LVDS VccADAC 3.3 0.001
AJ27 VCCCORE[14] VCCTX_LVDS[1]
1 1 1
4.7u to 0402 VCCCORE[15]
CH23
CH24
AJ29 AM38 0.1uH inductor, 200mA
VCCCORE[16] VCCTX_LVDS[2]
CH25
AJ31 VccADPLLA 1.05 0.08
1u, 0.1u, 0.01u to 0201 VCCCORE[17]
60mAVCCTX_LVDS[3] AP36
2 2 2 9/8 SI build BOT limit 0.8, CH25
AP37 del:SE000008L80 VccADPLLB 1.05 0.08
+VCCP AN19 VCCTX_LVDS[4]
+VCCP VCCIO[28] add: SE000001120
VccCore 1.05 1.3
2 1 +VCCAPLLEXP BJ22 RH265
RH264 0_0603_5% VCCAPLLEXP
10U_0603_6.3V6M
1 V33 +3VS_VCC3_3_6 1 2 VccDMI 1.05 0.042
@ VCC3_3[6] +3VS
@ CH37
Place CH35 Near AP19 pin AN16
HVCMOS
short@
VCCIO[15] 0_0805_5%
1
AN17 VccIO 1.05 2.925
2 VCCIO[16] V34 CH26
VCC3_3[7]
0.1U_0201_16V4Z
+VCCP AN21 2 VccASW 1.05 1.01
VCCIO[17]
AN26
VCCIO[18]
RH297 VccSPI 3.3 0.02
1 2 +1.05VS_VCC_EXP AN27 2925mA AT16 +VCCAFDI_VRM
VCCIO[19] VCCVRM[3] +VCCP_VCCDMI
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
short@
+VCCP
10U_0603_6.3V6M
0_0805_5% 1 1 1 1 1 AP21 20mA RH266 VccDSW 3.3 0.003

C VCCIO[20] C
CH28
CH32
CH29
CH30
CH31
SI# 8/8 Add RH297 for
1U_0402_6.3V6K
power break down AP23 AT20 +VCCP_VCCDMI 1 2
VCCIO[21] VCCDMI[1]
1 short@ VccpNAND 1.8 0.19
2 2 2 2 2
DMI
CH33
AP24 0_0805_5%
VCCIO[22]
VCCIO
+3VS RH314
1U_0402_6.3V6K
AP26 AB36 +1.05VS_VCC_DMI_CCI 1 2 VccRTC 3.3 6 uA
VCCIO[23] VCCCLKDMI +VCCP 2
1 short@
CH34
AT24 0_0805_5%
VCCIO[24]
SI# 8/8 Change 10uH to 0805 0 ohm VccSus3_3 3.3 0.119
1
2
to follow compal common design
RH268 AN33
VCCIO[25]
0_0805_5% VccSusHDA 3.3 / 1.5 0.01
short@ AN34 AG16
VCCIO[26] VCCDFTERM[1] +VCCPNAND
2
RH269 VccVRM 1.8 / 1.5 0.16

+3VS_VCCA3GBG BH29 AG17 1 2
VCC3_3[3] VCCDFTERM[2] +1.8VS
DFT / SPI
1
0.1U_0402_10V7K
+VCCP 0_0805_5% VccCLKDMI 1.05 0.02
CH35 AJ16 1 short@
VCCDFTERM[3]
0.1U_0201_16V4Z 190mA
2
CH36
+VCCAFDI_VRM AP16 VccSSC 1.05 0.095
VCCVRM[2] AJ17
Place CH53 Near AP13,AP15 pin VCCDFTERM[4] 2
2 1 +1.05VS_VCCAPLL_FDI BG6 VccDIFFCLKN 1.05 0.055
RH270 0_0603_5% VccAFDIPLL
@ RH271
1 2 +1.05VS_VCCDPLL_FDIAP17 RH272 VccALVDS 3.3 0.001
+VCCP VCCIO[27]
short@ V1 +3V_VCCPSPI 1 2
FDI
VCCSPI +3V_PCH
0_0805_5% 20mA
AU20 1 0_0805_5% VccTX_LVDS 1.8 0.06
+VCCP_VCCDMI VCCDMI[2] short@
B
CH38 Change BIOS ROM power rail to +3V_PCH B
PANTHER-POINT_FCBGA989 1U_0402_6.3V6K
2 2014.01.21
+VCCAFDI_VRM
RH275
2 1 +VCCAFDI_VRM
+1.5VS
0_0603_5%
short@
A A

PCH (6/8) PWR
Size
Document Number Rev
0.1
LA-A999P
5 4 3 2 1
5 4 3 2 1
+3VALW +3V_DSW
1 2 <1122>Reserved for deep Sx.

RH312 0_0603_5%
+VCCP
VCC3_3 = 266mA detal waiting for newest spec
@ VCCDMI = 42mA detal waiting for newest spec
QH4 2 @ 1 +VCCACLK
AO3413L_SOT23-3 +3V_PCH RH276 0_0603_5%
UH1J POWER QH3
3 1 1 2
D
+3V_DSW RH277 @ 0_0603_5% AD49 N26 +1.05VS_VCCUSBCORE 2 1 +5VALW AO3413_SOT23 +5V_PCH
1 VCCACLK VCCIO[29] +VCCP
CH39 RH285 short@ 0_0603_5% RH278
G
1 2 P26 2 1 3 1
D
1
2
RH309 0_0603_5% 0.1U_0201_16V4Z +VCCPDSW T16 VCCIO[30] CH40
D <41> PCH_VREG_EN# 2 VCCDSW3_33mA P28 D
0.1U_0201_16V4Z
1U_0402_6.3V6K 0_0603_5%
VCCIO[31]
1
short@
G
1
2
+VCCP 2
CH41
LH3 +PCH_VCCDSW V12 T27 RH279
10UH_LB2012T100MR_20% DCPSUSBYP VCCIO[32] 20K_0402_5%
1
1 2 @ CH42 T29
VCCIO[33] <43> PCH_PWR_EN# 2
@ +3VS_VCC_CLKF33 T38
2
0.1U_0201_16V4Z VCC3_3[5] short@
1 2 T23 +3V_VCCPUSB 2 1
+VCCP 119mA VCCSUS3_3[7] +3V_PCH
BH23
0.1U_0201_16V4Z
@ CH43 +VCCAPLL_CPY_PCH RH281 0_0603_5%
10U_0603_6.3V6M VCCAPLLDMI2 T24 +3V_VCCAUBG 2 1
2 VCCSUS3_3[8] 1 +3V_PCH +5V_PCH +3V_PCH
CH44
1 2 AL29
0.1U_0201_16V4Z
+VCCDPLL_CPY RH282 short@ 0_0603_5%
RH283 short@ 0_0603_5% VCCIO[14] V23
VCCSUS3_3[9] 1
USB
CH47
2
2
1U_0402_6.3V6K
+VCCSUS1 AL24 V24 +VCCA_USBSUS DH3
DCPSUS[3] VCCSUS3_3[10]
1U_0402_6.3V6K
1 RH284
2
CH45
P24 1 100_0402_5%
VCCSUS3_3[6]
CH48
AA19 CH751H-40PT_SOD323-2
1
2@ VCCASW[1] T26 +1.05VS_VCCAUPLL 2 1 @ +PCH_V5REF_SUS
+VCCP VCCIO[34] +VCCP 2
AA21 1010mA RH286 short@ 0_0603_5% 1
VCCASW[2]
22U_0805_6.3V6M
22U_0805_6.3V6M
9/8 SI build BOT limit 0.8 CH49
2 @ 1 +1.05VM_VCCSUS del: SE000001120 AA24 M26 +PCH_V5REF_SUS RH287
VCCASW[3] 1mA V5REF_SUS
1U_0402_6.3V6K
RH407 0_0603_5% add: SE000001120 1 1 2 1 0.1U_0201_16V4Z

+3V_PCH 2
CH50
CH51
AA26
0.1U_0201_16V4Z
1 short@ 0_0603_5%
Clock and Miscellaneous

VCCASW[4]
CH262
AN23 +VCCA_USBSUS 1
DCPSUS[4]
CH52
AA27
2 2 VCCASW[5] AN24 +3V_VCCPSUS_1
2@ AA29 VCCSUS3_3[1]
VCCASW[6] 2
AA31 +5VS +3VS
RH307 VCCASW[7]
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2 1 +VCCP_VCCASW AC26 P34 +PCH_V5REF_RUN
+VCCP VCCASW[8] 1mA V5REF
2
C short@ RH289 DH4 C
1 1 1
CH53
CH54
CH55
0_0805_5% AC27 0_0603_5% RH288
VCCASW[9] N20 +3V_VCCPSUS 2 1 100_0402_5%
VCCSUS3_3[2] +3V_PCH
AC29 short@
PCI/GPIO/LPC
2 2 2 VCCASW[10] 1
SI# 7/29 Add RH307 for break N22 CH56 CH751H-40PT_SOD323-2
1
AC31 VCCSUS3_3[3] 1U_0402_6.3V6K +PCH_V5REF_RUN
down PCH VCCASW power VCCASW[11] +3VS
P20 1
+3VS AD29 VCCSUS3_3[4] 2 RH290 CH57
RH313 VCCASW[12] P22 +3VS_VCCPCORE 2 1 1U_0402_6.3V6K
2 1 AD31 VCCSUS3_3[5]
SI# 8/8 Add RH313 for follow VCCASW[13] 1 short@
short@ CH58 0_0805_5% 2
compal common design
0_0805_5% W21 AA16
VCCASW[14] VCC3_3[1] 0.1U_0201_16V4Z
W23 W16 2 RH292 +3VS
VCCASW[15] VCC3_3[8]
1U_0402_6.3V6K
LH4 1 2 +3VS_VCC_CLKF33 0_0603_5%

1 1 W24 T34 +3VS_VCCPPCI 2 1
VCCASW[16] VCC3_3[4]
CH61
10UH_LB2012T100MR_20% 1 short@
CH59 W26 CH60
@ VCCASW[17]
10U_0603_6.3V6M 2 2 W29 RH293 +3VS 0.1U_0201_16V4Z
VCCASW[18] 0_0603_5% 2
W31 AJ2 +VCC3_3_2 2 1
VCCASW[19] VCC3_3[2] short@ +1.05VS_SATA3
1
W33 RH294
VCCASW[20] AF13 CH62 2 1
VCCIO[5] +VCCP
2 1
+VCCRTCEXT N16 0.1U_0201_16V4Z CH63 0_0805_5% short@
DCPRTC AH13 1U_0402_6.3V6K
1 VCCIO[12]
CH64
+VCCAFDI_VRM Y49 AH14 +1.05VS_SATA3 2
+VCCP 0.1U_0201_16V4Z VCCVRM[4] VCCIO[13]
2
B 2 1 +VCCDIFFCLK AF14 LH5 B
RH296 short@ 0_0603_5% +1.05VS_VCCA_A_DPL BD47 VCCIO[6] 10UH_LB2012T100MR_20%
1 VCCADPLLA80mA AK1 1 2
SATA
CH65 +VCCSATAPLL
VCCAPLLSATA +VCCP
1U_0402_6.3V6K +1.05VS_VCCA_B_DPL BF47 +VCCAFDI_VRM @
VCCADPLLB80mA
2 1
+VCCP +1.05VS_VCCDIFFCLKN AF11 +VCCAFDI_VRM
AF17 VCCVRM[1] CH66 @
2 1 +1.05VS_VCCDIFFCLKN AF33 VCCIO[7] +1.05VS_VCC_SATA
VCCDIFFCLKN[1]
RH299 Place CH73 Near AK1 pin
RH298 short@ 0_0603_5% 1 AF34 55mA AC16 +1.05VS_VCC_SATA 2 1 2 10U_0603_6.3V6M
VCCDIFFCLKN[2] VCCIO[2] +VCCP
1U_0402_6.3V6K
CH67 AG34
1U_0402_6.3V6K VCCDIFFCLKN[3] AC17 0_0805_5%
VCCIO[3] 1
CH68
short@
+VCCP 2 +1.05VS_SSCVCC AG33 AD17
VCCSSC95mA VCCIO[4]
2 1 2
RH300 short@ 0_0603_5% 1 1 +VCCSST V16
CH69 CH70 DCPSST +VCCP
1U_0402_6.3V6K
0.1U_0201_16V4Z +1.05VM_VCCSUS T17 T21 SI# 8/8 Delet the RH301,RH302,RH304 for follow
2 2 V19 DCPSUS[1] VCCASW[22]
DCPSUS[2] compal common design
MISC
+VCCP V21
VCCASW[23]
CPU
2 1 BJ8
0.1U_0201_16V4Z
0.1U_0201_16V4Z
+V_CPU_IO
RH303 short@ 0_0603_5%
1mA
V_PROC_IO T19
1 1 1 VCCASW[21]
CH72
CH73
CH71 +RTCVCC
4.7U_0402_16V4Z
2 2 2 A22 P32 +VCCSUSHDA 2 1
RTC
VCCRTC 10mA VCCSUSHDA +3V_PCH

HDA
0.1U_0201_16V4Z
0.1U_0201_16V4Z
0.1U_0201_16V4Z
RH305 short@ 0_0603_5%

1 1 1 1
150_0402_1%
CH74
CH75
CH76
LH6 PANTHER-POINT_FCBGA989 CH77
1
A 10UH_LB2012T100MR_20% A
+VCCP 1 2 +1.05VS_VCCA_A_DPL 0.1U_0201_16V4Z All the CODEC I/O Voltages need to be at
2 2 2 2
RH306
@ the same level either 3.3 V or 1.5 V.
1 2 +1.05VS_VCCA_B_DPL
2
22U_0603_6.3V6M
22U_0603_6.3V6M
LH7
1U_0402_6.3V6K
1U_0402_6.3V6K
10UH_LB2012T100MR_20%
9/8 SI build BOT limit 0.8, CH78, CH80
1 1 1 1 Security Classification Compal Secret Data Compal Electronics, Inc.
CH78
CH79
CH80
CH81
del:SE000008L80
add: SE000001120 Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title
2 2 2 2
PCH (7/8) PWR
Size
Document Number Rev
0.1
7/8 CH78, CH80 220uF change to 22uF.
LA-A999P
5 4 3 2 1
5 4 3 2 1
UH1I
AY4 H46
AY42 VSS[159] VSS[259] K18
AY46 VSS[160] VSS[260] K26
AY8 VSS[161] VSS[261] K39
B11 VSS[162] VSS[262] K46
B15 VSS[163] VSS[263] K7
B19 VSS[164] VSS[264] L18
D UH1H B23 VSS[165] VSS[265] L2 D
H5 B27 VSS[166] VSS[266] L20
VSS[0] B31 VSS[167] VSS[267] L26
AA17 AK38 B35 VSS[168] VSS[268] L28
AA2 VSS[1] VSS[80] AK4 B39 VSS[169] VSS[269] L36
AA3 VSS[2] VSS[81] AK42 B7 VSS[170] VSS[270] L48
AA33 VSS[3] VSS[82] AK46 F45 VSS[171] VSS[271] M12
AA34 VSS[4] VSS[83] AK8 BB12 VSS[172] VSS[272] P16
AB11 VSS[5] VSS[84] AL16 BB16 VSS[173] VSS[273] M18
AC19 VSS[12] VSS[91] AL27 BB4 VSS[180] VSS[280] M4
AC2 VSS[13] VSS[92] AL31 BB46 VSS[181] VSS[281] M42
AC21 VSS[14] VSS[93] AL33 BC14 VSS[182] VSS[282] M46
AC24 VSS[15] VSS[94] AL34 BC18 VSS[183] VSS[283] M8
AC33 VSS[16] VSS[95] AL48 BC2 VSS[184] VSS[284] N18
AC34 VSS[17] VSS[96] AM11 BC22 VSS[185] VSS[285] P30
AC48 VSS[18] VSS[97] AM14 BC26 VSS[186] VSS[286] N47
AD10 VSS[19] VSS[98] AM36 BC32 VSS[187] VSS[287] P11
AD12 VSS[21] VSS[100] AM43 BC36 VSS[189] VSS[289] T33
AD26 VSS[25] VSS[104] AN2 BD46 VSS[193] VSS[293] P7
AD27 VSS[26] VSS[105] AN29 BD5 VSS[194] VSS[294] R2
AD33 VSS[27] VSS[106] AN3 BE22 VSS[195] VSS[295] R48
AD34 VSS[28] VSS[107] AN31 BE26 VSS[196] VSS[296] T12
C AD36 VSS[29] VSS[108] AP12 BE40 VSS[197] VSS[297] T31 C
AD37 VSS[30] VSS[109] AP19 BF10 VSS[198] VSS[298] T37
AD39 VSS[32] VSS[111] AP30 BF16 VSS[200] VSS[300] W34
AD43 VSS[36] VSS[115] AP42 BF26 VSS[204] VSS[304] V11
AD45 VSS[37] VSS[116] AP46 BF28 VSS[205] VSS[305] V17
AD46 VSS[38] VSS[117] AP8 BD3 VSS[206] VSS[306] V26
AD8 VSS[39] VSS[118] AR2 BF30 VSS[207] VSS[307] V27
AE2 VSS[40] VSS[119] AR48 BF38 VSS[208] VSS[308] V29
AE3 VSS[41] VSS[120] AT11 BF40 VSS[209] VSS[309] V31
AF10 VSS[42] VSS[121] AT13 BF8 VSS[210] VSS[310] V36
AF12 VSS[43] VSS[122] AT18 BG17 VSS[211] VSS[311] V39
AD14 VSS[44] VSS[123] AT22 BG21 VSS[212] VSS[312] V43
AD16 VSS[45] VSS[124] AT26 BG33 VSS[213] VSS[313] V7
AF16 VSS[46] VSS[125] AT28 BG44 VSS[214] VSS[314] W17
AF19 VSS[47] VSS[126] AT30 BG8 VSS[215] VSS[315] W19
AF24 VSS[48] VSS[127] AT32 BH11 VSS[216] VSS[316] W2
AF29 VSS[51] VSS[130] AT42 BH19 VSS[219] VSS[319] Y12
AF31 VSS[52] VSS[131] AT46 H10 VSS[220] VSS[320] Y38
AF38 VSS[53] VSS[132] AT7 BH27 VSS[221] VSS[321] Y4
AF4 VSS[54] VSS[133] AU24 BH31 VSS[222] VSS[322] Y42
AF42 VSS[55] VSS[134] AU30 BH33 VSS[223] VSS[323] Y46
AF46 VSS[56] VSS[135] AV16 BH35 VSS[224] VSS[324] Y8
AF5 VSS[57] VSS[136] AV20 BH39 VSS[225] VSS[325] BG29
AF7 VSS[58] VSS[137] AV24 BH43 VSS[226] VSS[328] N24
AF8 VSS[59] VSS[138] AV30 BH7 VSS[227] VSS[329] AJ3
AG19 VSS[60] VSS[139] AV38 D3 VSS[228] VSS[330] AD47
B AG2 VSS[61] VSS[140] AV4 D12 VSS[229] VSS[331] B43 B
AG31 VSS[62] VSS[141] AV43 D16 VSS[230] VSS[333] BE10
AG48 VSS[63] VSS[142] AV8 D18 VSS[231] VSS[334] BG41
AH11 VSS[64] VSS[143] AW14 D22 VSS[232] VSS[335] G14
AH3 VSS[65] VSS[144] AW18 D24 VSS[233] VSS[337] H16
AH36 VSS[66] VSS[145] AW2 D26 VSS[234] VSS[338] T36
AH39 VSS[67] VSS[146] AW22 D30 VSS[235] VSS[340] BG22
AH40 VSS[68] VSS[147] AW26 D32 VSS[236] VSS[342] BG24
AH42 VSS[69] VSS[148] AW28 D34 VSS[237] VSS[343] C22
AH46 VSS[70] VSS[149] AW32 D38 VSS[238] VSS[344] AP13
AH7 VSS[71] VSS[150] AW34 D42 VSS[239] VSS[345] M14
AJ19 VSS[72] VSS[151] AW36 D8 VSS[240] VSS[346] AP3
AJ21 VSS[73] VSS[152] AW40 E18 VSS[241] VSS[347] AP1
AJ24 VSS[74] VSS[153] AW48 E26 VSS[242] VSS[348] BE16
AJ33 VSS[75] VSS[154] AV11 G18 VSS[243] VSS[349] BC16
AJ34 VSS[76] VSS[155] AY12 G20 VSS[244] VSS[350] BG28
AK12 VSS[77] VSS[156] AY22 G26 VSS[245] VSS[351] BJ28
AK3 VSS[78] VSS[157] AY28 G28 VSS[246] VSS[352]
VSS[79] VSS[158] G36 VSS[247]
PANTHER-POINT_FCBGA989 G48 VSS[248]
H12 VSS[249]
H18 VSS[250]
H22 VSS[251]
H24 VSS[252]
H26 VSS[253]
H30 VSS[254]
H32 VSS[255]
H34 VSS[256]
F3 VSS[257]
VSS[258]
A PANTHER-POINT_FCBGA989 A

PCH (8/8) VSS
Size
Document Number Rev
0.1
LA-A999P
5 4 3 2 1
1 2 3 4 5
+3VGS
#9/2 , Add RV191 between.

UV1A GPU_PWR_LEVEL# RV62 1 DIS@ 2 100K_0402_5%
PEG_HTX_C_GRX_P0 AG6
Part 1 of 5 GPU_PWR_LEVEL# and GPU_THERMAL_DET# GPU_GPIO6 RV43 1 DIS@ 2 10K_0402_5%
<5> PEG_HTX_C_GRX_P0 PEX_RX0
PEG_HTX_C_GRX_N0 AG7 C6 GPU_GPIO0
<5> PEG_HTX_C_GRX_N0 PEX_RX0_N GPIO0
PEG_HTX_C_GRX_P1 AF7 B2 NVVDD_PSI RV44 1 DIS@ 2 10K_0402_5%
<5> PEG_HTX_C_GRX_P1 PEX_RX1 GPIO1
PEG_HTX_C_GRX_N1 AE7 D6
<CPU> <5> PEG_HTX_C_GRX_N1
PEG_HTX_C_GRX_P2 AE9 PEX_RX1_N GPIO2 C7 GPU_GPIO8 RV46 1 DIS@ 2 10K_0402_5%
PEG_HTX_C_GRX_N2 AF9 F9
PEG_HTX_C_GRX_P3 AG9 A3 GPU_GPIO9 RV48 1 DIS@ 2 10K_0402_5%
A PEG_HTX_C_GRX_N3 AG10 A4 GPU_GPIO6 A
PEG_HTX_C_GRX_P4 AF10 B6
GPIO
PEG_HTX_C_GRX_N4 AE10 A6 GPU_GPIO8
PEG_HTX_C_GRX_P5 AE12 F8 GPU_GPIO9
PEG_HTX_C_GRX_N5 AF12 C5
PEG_HTX_C_GRX_P6 AG12 E7 NVVDD_PWM_VID
<5> PEG_HTX_C_GRX_P6 PEX_RX6 GPIO11 NVVDD_PWM_VID <56>
PEG_HTX_C_GRX_N6 AG13 D7 GPU_PWR_LEVEL# RV191 1 DIS@ 2 0_0402_5%
<5> PEG_HTX_C_GRX_N6
PEG_HTX_C_GRX_P7 AF13 PEX_RX6_N GPIO12 B4 NVVDD_PSI
GPU_THERMAL_DET# <41> CHECK!! GPU_GPIO0 RV49 1 DIS@ 2 10K_0402_5%
<5> PEG_HTX_C_GRX_P7 PEX_RX7 GPIO13 NVVDD_PSI <56>
PEG_HTX_C_GRX_N7 AE13 B3
AE15 C3
AF15 NC GPIO15 D5
AG15 NC GPIO16 D4
AG16 NC GPIO17 C2
AF16 NC GPIO18 F7
AE16 NC GPIO19 E6
AE18 NC GPIO20 C4
AF18 NC GPIO21
AG18 NC
AG19 NC
AF19 NC AE3
AE19 NC
NC
DACA_HSYNC
DACA_VSYNC
AE4 #8/19 ,N15V-GM didn't support GC6,
AE21
AF21 NC AG3 unpop QV13 ,QV14.
DACA
AG21 NC DACA_RED AF3
AG22 NC DACA_BLUE AF4
NC DACA_GREEN
PEG_GTX_C_HRX_P0 CV1 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_P0 AC9 AE2
PCI EXPRESS
<5> PEG_GTX_C_HRX_P0 PEX_TX0 DACA_VREF
PEG_GTX_C_HRX_N0 CV2 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_N0 AB9 AF2
<5> PEG_GTX_C_HRX_N0 PEX_TX0_N DACA_RSET
PEG_GTX_C_HRX_P1 CV3 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_P1 AB10
<5> PEG_GTX_C_HRX_P1 PEX_TX1
PEG_GTX_C_HRX_N1 CV4 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_N1 AC10
<CPU> <5> PEG_GTX_C_HRX_N1
PEG_GTX_C_HRX_P2 CV5 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_P2 AD11 PEX_TX1_N
PEG_GTX_C_HRX_N2 CV6 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_N2 AC11 AE5 GPU_JTAG_TCK
<5> PEG_GTX_C_HRX_N2 PEX_TX2_N JTAG_TCK
PEG_GTX_C_HRX_P3 CV7 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_P3 AC12 AE6
<5> PEG_GTX_C_HRX_P3 PEX_TX3 JTAG_TDI T1402
PEG_GTX_C_HRX_N3 CV8 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_N3 AB12 AF6
<5> PEG_GTX_C_HRX_N3 PEX_TX3_N JTAG_TDO T1403
TEST
PEG_GTX_C_HRX_P4 CV25 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_P4 AB13 AD6
B <5> PEG_GTX_C_HRX_P4 PEX_TX4 JTAG_TMS T1404 B
PEG_GTX_C_HRX_N4 CV13 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_N4 AC13 AG4 GPU_JTAG_TRST
<5> PEG_GTX_C_HRX_N4 PEX_TX4_N JTAG_TRST_N
PEG_GTX_C_HRX_P5 CV15 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_P5 AD14
PEG_GTX_C_HRX_N5 CV14 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_N5 AC14 AD9 TESTMODE
<5> PEG_GTX_C_HRX_N5 PEX_TX5_N TESTMODE
PEG_GTX_C_HRX_P6 CV18 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_P6 AC15 131127 SWAP Pin of RV36.1, RV36.2 & RV36.4 by layout requested
PEG_GTX_C_HRX_N6 CV19 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_N6 AB15
<5> PEG_GTX_C_HRX_N6 PEX_TX6_N
PEG_GTX_C_HRX_P7 CV11 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_P7 AB16
PEG_GTX_C_HRX_N7 CV16 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_N7 AC16 B7 I2CA_SCL RV14 1 DIS@ 2 2.2K_0402_5%
<5> PEG_GTX_C_HRX_N7 PEX_TX7_N I2CA_SCL
AD17 A7 I2CA_SDA RV15 1 DIS@ 2 2.2K_0402_5%
AC17 NC I2CA_SDA #08/22,unused I2C change to pull-down.
AC18 NC C9 I2CB_SCL +3VGS DIS@ RV16
AB18 NC I2CB_SCL C8 I2CB_SDA I2CB_SDA 1 8
AB19 NC I2CB_SDA I2CB_SCL 2 7
I2C
AC19 NC A9 I2CC_SCL I2CC_SDA 3 6
AD20 NC I2CC_SCL B9 I2CC_SDA +3VGS DIS@ RV36 I2CC_SCL 4 5
AC20 NC I2CC_SDA GPU_CLKREQ#_R 1 8
AC21 NC D9 I2CS_SCL RV21 1 DIS@ 2 2.2K_0402_5% GPU_JTAG_TCK 2 7 2.2K_0804_8P4R_5%
AB21 NC I2CS_SCL D8 I2CS_SDA RV22 1 DIS@ 2 2.2K_0402_5% GPU_JTAG_TRST 3 6
AD23 NC I2CS_SDA TESTMODE 4 5
#08/22,unused I2C change to pull-down.
AE23 NC
NC Internal Thermal Sensor
AF24
AE24 NC A10 XTALSSIN RV23 1 DIS@ 2 10K_0402_5% 10K_0804_8P4R_5%
AG24 NC XTAL_SSIN
AG25 NC C10 XTALOUT RV25 1 DIS@ 2 10K_0402_5%
NC XTAL_OUTBUFF
CLK
AE8 B10 XTAL_OUT
<15> CLK_PCIE_GPU PEX_REFCLK XTAL_OUT
AD8
<CPU> <15> CLK_PCIE_GPU# PEX_REFCLK_N C11 XTALIN
1 DIS@ 2 PEX_TSTCLK_OUT AF22 XTAL_IN
RV26 200_0402_1% PEX_TSTCLK_OUT# AE22 PEX_TSTCLK_OUT
Differential signal PEX_TSTCLK_OUT_N +3VGS
1 2 PEX_TERMP AF25 AB6
RV27 DIS@ 2.49K_0402_1% PEX_TERMP NC
PLT_RST_VGA# AC7 D10 RV58 1 DIS@ 2 10K_0402_5%
PEX_RST_N NC
C GPU_CLKREQ#_R AC6 E9 C
PEX_CLKREQ_N NC
5
N15V-GM
QV2B DIS@
@DIS I2CS_SCL 4 3
EC_SMB_CK2 <15,41>
2N7002KDWH_SOT363-6
+3VGS
10K_0402_5% RV13 1 @ 2 0_0402_5%
+3VGS +3VGS RV182
DIS@
1 2
2
CV12
0.01U_0402_16V7K
1 QV2A DIS@
SI 11/05 change RV182.1 I2CS_SDA 1 6
EC_SMB_DA2 <15,41>
1
RV183 1 2 change to +3VGS from GPU_PWR_EN
DIS@
@ 0_0402_5% RV184 2N7002KDWH_SOT363-6
10K_0402_5% 2
@ RV20 1 @ 2 0_0402_5%
5
2
UV11
2
PLT_RST# 1 PU AT EC SIDE, +3VS AND 4.7K
G
P
<17,33,35,40,41,6> PLT_RST# B 4 PLT_RST_VGA#

DGPU_HOLD_RST# 2 Y 1 3 GPU_CLKREQ#_R
<17,41> DGPU_HOLD_RST# A <15> GPU_CLKREQ#
G
S
1
TC7SH08FUF_SSOP5 1
3
1
DIS@ RV186 @ CV17 QV10 DIS@ XTALDIS@
Controlled by EC "AND" PCH 10K_0402_5% 2N7002K_SOT23-3 RV187 RV24 1 2 10M_0402_5%
DIS@ 0.1U_0402_16V7K 10K_0402_5%
2 1 @ 2 @ XTALDIS@
2
YV1
2
RV188 0_0402_5%
XTALIN 1 3 XTAL_OUT
1 3
GND GND
1 1
D 2 4 D
CV9 CV10
10P_0402_25V8K 27MHZ 10PF X3G027000DA1H 10P_0402_25V8K
2 XTALDIS@ SJ10000GI00 2 XTALDIS@
SJ10000CV00 cost is better.

<1118>change to standard part.
Title
Compal Electronics, Inc.
Issued Date 2011/07/12 Deciphered Date 2012/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL N15V-GM
PCIE/DAC/GPIO Rev
Custom 0.1
Date:
LA-A999P
Friday, March 14, 2014 Sheet 22 of 58
1 2 3 4 5
1 2 3 4 5
UV1C
Part 3 of 5
AC3 D1 STRAP0
AC4 IFPA_TXC STRAP0 D2 STRAP0 <29>
STRAP1
STRAP
IFPA_TXC_N STRAP1 STRAP1 <29>
Y4 E4 STRAP2
Y3 IFPA_TXD0 STRAP2 E3 STRAP2 <29>
STRAP3
A IFPA_TXD0_N STRAP3 STRAP3 <29> A
AA3 D3 STRAP4
AA2 IFPA_TXD1 STRAP4 C1 STRAP4 <29>
AB1 IFPA_TXD1_N NC
AA1 IFPA_TXD2
AA4 IFPA_TXD2_N
AA5 IFPA_TXD3
IFPA_TXD3_N DIS@
GENERAL
D11 RV28 1 2 100K_0402_5%
AB5 BUFRST_N
AB4 IFPB_TXC E12
AB3 IFPB_TXC_N THERMDN F12
AB2 IFPB_TXD4 THERMDP
AD3 IFPB_TXD4_N
IFPB_TXD5
LVDS / TMDS
AD2
AE1 IFPB_TXD5_N DIS@
AD1 IFPB_TXD6 D12 ROM_CS RV29 1 2 10K_0402_5%
IFPB_TXD6_N ROM_CS_N +3VGS
AD4
AD5 IFPB_TXD7 C12 ROM_SCLK
IFPB_TXD7_N ROM_SCLK ROM_SCLK <29>
SERIAL
B12 ROM_SI
ROM_SI ROM_SI <29>
N4
N5 IFPC_AUX_I2CW_SCL A12 ROM_SO
T2 IFPC_AUX_I2CW_SDA_N ROM_SO ROM_SO <29>
T3 IFPC_L0
B IFPC_L0_N B
T1
R1 IFPC_L1 AA6
R2 IFPC_L1_N IFPAB_RSET
R3 IFPC_L2 T6
N2 IFPC_L2_N IFPC_RSET
N3 IFPC_L3 U6
IFPC_L3_N IFPD_RSET
K6
P3 NC
P4 IFPD_AUX_I2CX_SCL
V3 IFPD_AUX_I2CX_SDA_N
V4 IFPD_L0 AD10
U3 IFPD_L0_N NC AD7
U4 IFPD_L1 NC B19
T4 IFPD_L1_N NC
T5 IFPD_L2 G1
R4 IFPD_L2_N NC_G1 G2
R5 IFPD_L3 NC_G2 G3
IFPD_L3_N NC_G3 G4
NC_G4 G5
J2 NC_G5 G6
J3 IFPE_AUX_I2CY_SCL NC_G6 G7
N1 IFPE_AUX_I2CY_SDA_N NC_G7
M1 NC V1
C C
M2 NC NC_V1 V2
M3 NC NC_V2 V5
K2 NC NC_V5 V6
K3 NC NC_V6
K1 NC W1
J1 NC NC_W1 W2
NC NC_W2 W3
NC_W3 W4
H3 NC_W4
H4 IFPF_AUX_I2CZ_SCL
M4 IFPF_AUX_I2CZ_SDA_N
M5 NC
L3 NC E10
L4 NC NC F10
K4 NC NC
K5 NC
J4 NC
J5 NC
NC
N15V-GM
DIS@
D D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL N15V-GM LVDS/HDMI/DP/THM Rev
B 0.1
Date:
LA-A999P
1 2 3 4 5
1 2 3 4 5
+1.5VGS
UV1D
Part 4 of 5
B26 K10 +VGA_CORE
C25 FBVDDQ VDD K12
FBVDDQ VDD
CV28
0.1U_0402_10V7K
CV20
0.1U_0402_10V7K
CV21
1U_0402_6.3V6K
CV22
1U_0402_6.3V6K
CV23
4.7U_0603_6.3V6K
CV24
4.7U_0603_6.3V6K
CV29
10U_0603_6.3V6M
CV26
22U_0805_6.3V6M
E23 K14
E26 FBVDDQ VDD K16
1 1 1 1 1 1 1 1 FBVDDQ VDD
F14 K18
F21 FBVDDQ VDD L11
FBVDDQ VDD
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
G13 L13
2 2 2 2 2 2 2 2 G14 FBVDDQ VDD L15
G15 FBVDDQ VDD L17
G16 FBVDDQ VDD M10
G18 FBVDDQ VDD M12
G19 FBVDDQ VDD M14
Reference circuit: FBVDDQ VDD
A G20 M16 A
0.1uF *2 G21 FBVDDQ VDD M18
H24 FBVDDQ VDD N11
1 uF*2 FBVDDQ VDD
H26 N13
4.7uF*2 J21 FBVDDQ VDD N15
K21 FBVDDQ VDD N17
10uF*1 FBVDDQ VDD
L22 P10
22uF*1 L24 FBVDDQ VDD P12
L26 FBVDDQ VDD P14
M21 FBVDDQ VDD P16
N21 FBVDDQ VDD P18
R21 FBVDDQ VDD R11
T21 FBVDDQ VDD R13
V21 FBVDDQ VDD R15
W21 FBVDDQ VDD R17
FBVDDQ VDD
POWER
T10
AA10 VDD T12
+1.05VGS PEX_IOVDDQ VDD
AA12 T14
PEX_IOVDDQ VDD
CV51
1U_0402_6.3V6K
CV52
1U_0402_6.3V6K
CV53
4.7U_0603_6.3V6K
CV54
10U_0805_6.3V6M
CV55
10U_0805_6.3V6M
CV56
22U_0805_6.3V6M
CV57
22U_0805_6.3V6M
AA13 T16
AA16 PEX_IOVDDQ VDD T18
Reference circuit: 1 1 1 1 1 1 1 PEX_IOVDDQ VDD
AA18 U11
1uF *2 AA19 PEX_IOVDDQ VDD U13
PEX_IOVDDQ VDD
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
4.7uF*1 AA20 U15
2 2 2 2 2 2 2 AA21 PEX_IOVDDQ VDD U17
10uF*2 AB22 PEX_IOVDDQ VDD V10
AC23 PEX_IOVDDQ VDD V12
22uF*2 PEX_IOVDDQ VDD
AD24 V14
AE25 PEX_IOVDDQ VDD V16
AF26 PEX_IOVDDQ VDD V18 Power :VDD_SENSE & GND_SENSE
AF27 PEX_IOVDDQ VDD Differential signal
PEX_IOVDDQ F2 VCCSENSE_VGA
VDD_SENSE VCCSENSE_VGA <56>
CV58
1U_0402_6.3V6K
CV59
1U_0402_6.3V6K
CV60
4.7U_0603_6.3V6K
CV61
10U_0805_6.3V6M
CV62
10U_0805_6.3V6M
CV63
22U_0805_6.3V6M
CV69
22U_0805_6.3V6M
Reference circuit: AA22
AB23 PEX_IOVDD G10 short@ 1 RV30 2
1 1 1 1 1 1 1 +3VGS
1uF *2 PEX_IOVDD VDD33
CV64
0.1U_0402_10V7K
CV65
0.1U_0402_10V7K
CV66
0.1U_0402_10V7K
CV67
1U_0402_6.3V6K
CV68
4.7U_0603_6.3V6K
AC24 G12 0_0603_5%
AD25 PEX_IOVDD VDD33 G8
B 4.7uF*1 PEX_IOVDD VDD33 1 1 1 1 1 B
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
AE26 G9
10uF*2 2 2 2 2 2 2 2 AE27 PEX_IOVDD VDD33
PEX_IOVDD
DIS@
DIS@
DIS@
DIS@
DIS@
22uF*2 F11
NC 2 2 2 2 2
+PEX_3V3_NV AA8 AB8 +PEX_3V3_NV

AA9 PEX_PLL_HVDD PEX_SVDD_3V3
PEX_PLL_HVDD W6
IFPA_IOVDD Y6
<SI> LV1 use R_0402 footprint +PEXPLL_VDD AA14 IFPB_IOVDD P6
RV34 1 2 0_0402_5% +PEX_3V3_NV DIS@ AA15 PEX_PLLVDD IFPC_IOVDD R6
+3VGS PEX_PLLVDD IFPD_IOVDD
short@ LV1 +GPU_SP_PLLVDD N6 H6
VID_PLLVDD NC
CV70
0.1U_0402_10V7K
CV71
4.7U_0603_6.3V6K
CV72
4.7U_0603_6.3V6K
BLM18PG121SN1D_0603 M6 J6
1 2 +GPU_PLLVDD L6 SP_PLLVDD NC
1 1 1 +1.05VGS CORE_PLLVDD
+FB_PLLAVDD F16 V7 Remove IFPC_PLLVDD,IFPD_PLLVDD,IFPC_IOVDD,IFPD_IOVDD,IFPAB_PLLVDD,+DACA_VDD,IFPA_IOVDD
FB_PLLAVDD IFPAB_PLLVDD
CV73
0.1U_0402_10V7K
CV74
22U_0805_6.3V6M
#8/19,LV1 change to P22 W7
FB_PLLAVDD IFPAB_PLLVDD
DIS@
DIS@
DIS@
1 1 H22
2 2 2 Z=30 ohm , RDC=0.05 FB_DLLAVDD M7
SM01000F100 IFPC_PLLVDD N7
IFPC_PLLVDD
DIS@
DIS@
W5
PCB Footprint = R_0402 2 2 DACA_VDD R7
+FB_CAL_PD_VDDQ D22 IFPD_PLLVDD T7
FB_CAL_PD_VDDQ IFPD_PLLVDD
F3 J7
RV45 1 2 0_0402_5% +PEXPLL_VDD FB_CLAMP NC K7
+1.05VGS FB_CLAMP NC
short@
CV75
0.1U_0402_10V7K
CV76
1U_0402_6.3V6K
CV77
4.7U_0603_6.3V6K
RV47 1 2 0_0402_5%
<18> DGPU_GC6_EN
1 1 1 short@
DIS@
DIS@
DIS@
2 2 2 N15V-GM
DIS@
C C
DIS@
LV3
BLM18PG121SN1D_0603
+1.05VGS 1 2 +GPU_SP_PLLVDD
DG : LV3 ->Z=180 ohm , RDC=0.2 ohm.0603

CV82
0.1U_0402_10V7K
CV83
0.1U_0402_10V7K
CV84
4.7U_0603_6.3V6K
CV85
22U_0805_6.3V6M
1 1 1 1 DIS@
+1.5VGS 1 2 +FB_CAL_PD_VDDQ
RV50 40.2_0402_1%
DIS@
DIS@
DIS@
DIS@
2 2 2 2 #7/27 Follow DG to chenge

R1591 to 40.2 ohm
DG:LV4->Z=30 ohm , RDC=0.01 ohm.0603 +FB_PLLAVDD

LV4 DIS@
BLM18PG121SN1D_0603
1 2
+1.05VGS
CV91
0.1U_0402_10V7K
CV90
0.1U_0402_10V7K
CV88
0.1U_0402_10V7K
CV89
22U_0805_6.3V6M
1 1 1 1
DIS@
DIS@
DIS@
DIS@
2 2 2 2
D D

Title
POWER Rev
Custom 0.1
Date:
LA-A999P
1 2 3 4 5
1 2 3 4 5
UV1E
Part 5 of 5
AA7 L10
A2 GND GND L12
A26 GND GND L14
AB11 GND GND L16
AB14 GND GND L18
AB17 GND GND L2
AB20 GND GND L23
AB24 GND GND L25
AC2 GND GND L5
AC22 GND GND M11
AC26 GND GND M13
AC5 GND GND M15
A A
AC8 GND GND M17
AD12 GND GND N10
AD13 GND GND N12
AD15 GND GND N14
AD16 GND GND N16
AD18 GND GND N18
AD19 GND GND P11
GND
AD21 GND GND P13
AD22 GND GND P15
AE11 GND GND P17
AE14 GND GND P2 #8/20 : N15V-GM don't support GC6 function. UV20 unpop.
AE17 GND GND P23
AE20 GND GND P26
AF1 GND GND P5
AF11 GND GND R10
AF14 GND GND R12
AF17 GND GND R14
AF20 GND GND R16
AF23 GND GND R18
AF5 GND GND T11
AF8 GND GND T13
AG2 GND GND T15
AG26 GND GND T17
B1 GND GND U10
B11 GND GND U12
B14 GND GND U14
B17 GND GND U16
B20 GND GND U18
B23 GND GND U2
B27 GND GND U23
B5 GND GND U26
B8 GND GND U5
E11 GND GND V11
E14 GND GND V13
B
E17 GND GND V15 B
E2 GND GND V17
E20 GND GND Y2
E22
E25
E5
GND
GND
GND
GND
GND
GND
Y23
Y26
Y5
+1.05VGS=1.6A,4vias. J2 @
E8 GND GND AB7 2 1
GND GND +1.05V_GPU 2 1 +1.05VGS
H2
H23 GND C24 1 DIS@ 2 JUMP_43X79
H25 GND FB_CAL_PU_GND RV67 42.2_0402_1%
H5 GND B25 1 DIS@ 2
K11 GND FB_CAL_TERM_GND RV68 51.1_0402_1%
K13 GND F6 1 2 40.2K_0402_1%
K15 GND MULTI_STRAP_REF0_GND F4 RV70 @ #8/19.RV70 unpop , N15V-GM use binary mode. +3VALW to +3VGS
K17 GND NC F5
GND NC Contrl by power
GND_SENSE
F1 VSSSENSE_VGA
VSSSENSE_VGA <56> +1.05V to +1.05VGS +1.05V_GPU
N15V-GM
Power :VDD_SENSE & GND_SENSE
+3VALW +VCCP
DIS@ Differential signal DIS@
QV12
1 14
Power on 2 VIN1 VOUT1 13
RV92 VIN1 VOUT1
DGPU_PWROK DIS@ 3 12 CV181 1 2 680P_0402_50V7K
ON1 CT1
DGPU_PWR_EN +5VALW 20K_0402_5% 4 11 DIS@
VBIAS GND
<17,41,56> DGPU_PWR_EN DGPU_PWR_EN 5 10 CV182 1 2 100P_0402_50V8J
+3VGS
+1.5VGS=3.6A,8vias.
J3 @
6
7
ON2
VIN2 VOUT2
CT2
9
8
DIS@
C
+VGA_CORE +1.5VGS_GPU 2 1 +1.5VGS
VIN2 VOUT2
C
2 1 15
JUMP_43X118 GPAD
DGPU_PWROK #8/19.QV15 change to TPS22967 TPS22966DPUR_SON14_2X3-D
+3VGS
+1.05VGS +1.5V to +1.5VGS +3VGS=0.5A,2vias.

+1.5VGS_GPU
DIS@
+1.5VGS +1.5VS QV15
1 7 +1.05VGS
2 VIN VOUT 8
40us < Rt < 2ms 1
VIN VOUT +3VALW
DIS@ CV81 3 6
ON CT
2
1 1 1 DIS@ 1 DIS@ 1 DIS@
10U_0603_6.3V6M DIS@ CV80 CV79 CV86 CV87 RC370 DIS@
2 4 CV183 DIS@
+5VALW VBIAS 18_0402_5%
1
1U 6.3V K X5R 0402
5
GND 2 2 2 2 2
100P_0402_50V8J
10U_0603_6.3V6M
9 RV210 SD028180A80
47U_0805_6.3V6M
47U_0805_6.3V6M
1
GND DIS@
DIS@ 100K_0402_5%
3
<18,56> DGPU_PWROK DGPU_PWROK RV66 1 2 TPS22967DSGR_SON8_2X2
2
47K_0402_5% 1
#08/20 Don't support GC6,Add RV66. DIS@
CV78 @ 5 QV17B
Unpop QV16,RV41,RV42,CV78. 0.01U_0603_50V7K DMN66D0LDW-7_SOT363-6
6
2
4
DIS@
DGPU_PWROK 2 QV17A
DMN66D0LDW-7_SOT363-6
1
D D
PV# 2013.01.08 Add +1.05VGS discharge circuit

Title
VGA CORE, GND Rev
Custom 0.1
Date:
LA-A999P
1 2 3 4 5
1 2 3 4 5
PU for X16 mode

UV1B
Part 2 of 5
MDA0 E18 C27 CMDA0
<27> MDA0 FBA_D0 FBA_CMD0 CMDA0 <27>
A MDA1 F18 C26 Dummy A
<27> MDA1 FBA_D1 FBA_CMD1
MDA2 E16 E24 CMDA2 Note: DG use 1%
MDA3 F17 F24 CMDA3
MDA4 D20 D27 CMDA4
<27> MDA4 FBA_D4 FBA_CMD4 CMDA4 <27,28>
MDA5 D21 D26 CMDA5 DIS@
MDA6 F20 F25 CMDA6 2 RV169 1 CMDA2
MDA7 E21 F26 CMDA7 10K_0402_1%
MDA8 E15 F23 CMDA8 DIS@
<27>
<27>
MDA8
MDA9
MDA9 D15 FBA_D8
FBA_D9
FBA_CMD8
FBA_CMD9
G22 CMDA9
CMDA8
CMDA9
<27,28>
<27,28>
2 RV170 1 CMDA18 Mode D Command Mapping
MDA10 F15 G23 CMDA10 10K_0402_1%
MDA11 F13 G24 CMDA11 DIS@ RANK 0
MDA12 C13 F27 CMDA12 2 RV185 1 CMDA3
MDA13 B13 G25 CMDA13 10K_0402_1% Address 0..31 32..63
MDA14 E13 G27 Dummy DIS@
MDA15 D13 G26 CMDA15 2 RV189 1 CMDA19 FBx_CMD0 CS0#
MDA16 B15 M24 CMDA16 10K_0402_1%
MDA17 C16 M23 Dummy DIS@ FBx_CMD1
MDA18 A13 K24 CMDA18 2 RV190 1 CMDA5
MDA19 A15 K23 CMDA19 10K_0402_1% FBx_CMD2 ODT
MDA20 B18 M27 CMDA20
MDA21 A18 M26 CMDA21 FBx_CMD3 CKE
MDA22 A19 M25 CMDA22
MDA23 C19 K26 CMDA23 FBx_CMD4 A14 A14
MDA24 B24 K22 CMDA24
MDA25 C23 J23 CMDA25 FBx_CMD5 RST RST
<27> MDA25 CMDA25 <27,28>
MEMORY INTERFACE
MDA26 A25 FBA_D25 FBA_CMD25 J25 CMDA26
MDA27 A24 J24 CMDA27 FBx_CMD6 A9 A9
MDA28 A21 K27 CMDA28
MDA29 B21 K25 CMDA29 FBx_CMD7 A7 A7
MDA30 C20 J27 CMDA30
MDA31 C21 J26 FBx_CMD8 A2 A2
MDA32 R22
<28> MDA32 FBA_D32
MDA33 R24 FBx_CMD9 A0 A0
<28> MDA33 FBA_D33
MDA34 T22 D19 DQMA0
<28> MDA34 FBA_D34 FBA_DQM0 DQMA0 <27>
MDA35 R23 D14 DQMA1 FBx_CMD10 A4 A4
B <28> MDA35 FBA_D35 FBA_DQM1 DQMA1 <27> B
MDA36 N25 C17 DQMA2
MDA37 N26 C22 DQMA3 FBx_CMD11 A1 A1
MDA38 N23 P24 DQMA4
MDA39 N24 W24 DQMA5 FBx_CMD12 BA0 BA0
MDA40 V23 AA25 DQMA6
MDA41 V22 U25 DQMA7 FBx_CMD13 WE# WE#
MDA42 T23
<28> MDA42 FBA_D42
MDA43 U22 F19 DQSA#0 FBx_CMD14
<28> MDA43 FBA_D43 FBA_DQS_RN0 DQSA#0 <27>
MDA44 Y24 C14 DQSA#1
MDA45 AA24 A16 DQSA#2 FBx_CMD15 CAS# CAS#
MDA46 Y22 A22 DQSA#3
MDA47 AA23 P25 DQSA#4 FBx_CMD16 CS0#
MDA48 AD27 W22 DQSA#5
MDA49 AB25 AB27 DQSA#6 FBx_CMD17
MDA50 AD26 T27 DQSA#7
MDA51 AC25 FBx_CMD18 ODT
<28> MDA51 FBA_D51
MDA52 AA27 E19 DQSA0
<28> MDA52 FBA_D52 FBA_DQS_WP0 DQSA0 <27>
MDA53 AA26 C15 DQSA1 FBx_CMD19 CKE
MDA54 W26 B16 DQSA2
MDA55 Y25 B22 DQSA3 FBx_CMD20 A13 A13
MDA56 R26 R25 DQSA4
MDA57 T25 W23 DQSA5 FBx_CMD21 A8 A8
MDA58 N27 AB26 DQSA6
MDA59 R27 T26 DQSA7 FBx_CMD22 A6 A6
MDA60 V26
<28> MDA60 FBA_D60
MDA61 V27 D18 FBx_CMD23 A11 A11
<28> MDA61 FBA_D61 FBA_WCK01
MDA62 W27 C18
<28> MDA62 FBA_D62 FBA_WCK01_N
MDA63 W25 D17 FBx_CMD24 A5 A5
<28> MDA63 FBA_D63 FBA_WCK23 D16
D23 FBA_WCK23_N T24
T1405 FB_VREF_PROBE FBA_WCK45 FBx_CMD25 A3 A3
U24
CLKA0 D24 FBA_WCK45_N V24
<27> CLKA0 FBA_CLK0 FBA_WCK67 FBx_CMD26 BA2 BA2
CLKA0# D25 V25
<27> CLKA0# FBA_CLK0_N FBA_WCK67_N
FBx_CMD27 BA1 BA1
C CLKA1 N22 C
<28> CLKA1 FBA_CLK1
CLKA1# M22 F22 RV137 1 @ 2 60.4_0402_1% FBx_CMD28 A12 A12
<28> CLKA1# FBA_CLK1_N FBA_DEBUG0 +1.5VGS
J22 RV138 1 @ 2 60.4_0402_1%
FBA_DEBUG1
FBx_CMD29 A10 A10
FBx_CMD30 RAS# RAS#
N15V-GM
DIS@
D D

Title
MEM Interface Rev
Custom 0.1
Date:
LA-A999P
1 2 3 4 5
1 2 3 4 5
Memory Partition A RANK 0 MDA[0..63]
CMDA[30..0]
<26,28>
<26,28>
+1.5VGS
Data0~Data31
Rank 0 Rank 0
1
RV139
1.33K_0402_1%
DIS@ UV12 X76@ UV14 X76@
2
+FBA_VREF0 +FBA_VREF0 M8 E3 MDA19 +FBA_VREF0 M8 E3 MDA4
A
H1 VREFCA DQL0 F7 MDA21 H1 VREFCA DQL0 F7 MDA0 A
VREFDQ DQL1 VREFDQ DQL1
CV96
0.01U_0402_16V7K
F2 MDA16 F2 MDA5
DQL2 DQL2
1
CMDA9 N3 F8 MDA22 CMDA9 N3 F8 MDA2

RV140
1
CMDA11 P7 A0 DQL3 H3 MDA18 Group 2 CMDA11 P7 A0 DQL3 H3 MDA7
1.33K_0402_1% CMDA8 P3 A1 DQL4 H8 MDA23 CMDA8 P3 A1 DQL4 H8 MDA1 Group 0
A2 DQL5 A2 DQL5
DIS@
DIS@ CMDA25 N2 G2 MDA17 CMDA25 N2 G2 MDA6

2 CMDA10 P8 A3 DQL6 H7 MDA20 CMDA10 P8 A3 DQL6 H7 MDA3 Mode D Command Mapping
2
CMDA24 P2 A4 DQL7 CMDA24 P2 A4 DQL7

R8 A5 R8 A5
CMDA22
A6
CMDA22
A6 RANK 0
CMDA7 R2 D7 MDA10 CMDA7 R2 D7 MDA31
CMDA21 T8 A7 DQU0 C3 MDA13 CMDA21 T8 A7 DQU0 C3 MDA27 Address
A8 DQU1 A8 DQU1 0..31 32..63
CMDA6 R3 C8 MDA11 CMDA6 R3 C8 MDA30
CMDA29 L7 A9 DQU2 C2 MDA14 CMDA29 L7 A9 DQU2 C2 MDA25
A10/AP DQU3 Group 1 A10/AP DQU3 Group 3 FBx_CMD0 CS0#
CMDA23 R7 A7 MDA8 CMDA23 R7 A7 MDA28
CLKA0 CMDA28 N7 A11 DQU4 A2 MDA15 CMDA28 N7 A11 DQU4 A2 MDA26
A12 DQU5 A12 DQU5 FBx_CMD1
CMDA20 T3 B8 MDA9 CMDA20 T3 B8 MDA29
T7 A13 DQU6 A3 T7 A13 DQU6 A3
CMDA4
A14 DQU7
MDA12 CMDA4
A14 DQU7
MDA24 FBx_CMD2 ODT
1
M7 M7
A15/BA3 +1.5VGS A15/BA3 +1.5VGS
RV141 FBx_CMD3 CKE
162_0402_1%
DIS@ CMDA12 M2 B2 CMDA12 M2 B2 FBx_CMD4 A14 A14
CMDA27 N8 BA0 VDD D9 CMDA27 N8 BA0 VDD D9
2
CMDA26 M3 BA1 VDD G7 CMDA26 M3 BA1 VDD G7

BA2 VDD BA2 VDD FBx_CMD5 RST RST
CLKA0# K2 K2
VDD K8 VDD K8
VDD VDD FBx_CMD6 A9 A9
#8/19 , change CLK N1 N1
J7 VDD N9 J7 VDD N9
termination to 162 ohm. <26> CLKA0
CLKA0
CK VDD
CLKA0
CK VDD FBx_CMD7 A7 A7
CLKA0# K7 R1 CLKA0# K7 R1
<26> CLKA0# CK VDD CK VDD
CMDA3 K9 R9 CMDA3 K9 R9 FBx_CMD8 A2 A2
B
CKE/CKE0 VDD CKE/CKE0 VDD B
160 ohm:SD00000XP00 FBx_CMD9 A0 A0
CMDA2 K1 A1 CMDA2 K1 A1
CMDA0 L2 ODT/ODT0 VDDQ A8 CMDA0 L2 ODT/ODT0 VDDQ A8
CS/CS0 VDDQ CS/CS0 VDDQ FBx_CMD10 A4 A4
CMDA30 J3 C1 CMDA30 J3 C1
CMDA15 K3 RAS VDDQ C9 CMDA15 K3 RAS VDDQ C9
CAS VDDQ CAS VDDQ FBx_CMD11 A1 A1
CMDA13 L3 D2 CMDA13 L3 D2
WE VDDQ E9 WE VDDQ E9
VDDQ VDDQ FBx_CMD12 BA0 BA0
F1 F1
F3 VDDQ H2 F3 VDDQ H2
<26> DQSA2
DQSA2
DQSL VDDQ <26> DQSA0
DQSA0
DQSL VDDQ FBx_CMD13 WE# WE#
DQSA1 C7 H9 DQSA3 C7 H9
<26> DQSA1 DQSU VDDQ <26> DQSA3 DQSU VDDQ
FBx_CMD14
DQMA2 E7 A9 DQMA0 E7 A9 FBx_CMD15 CAS# CAS#
H:Group 1 <26> DQMA2
DQMA1 D3 DML VSS B3 L:Group 0 <26> DQMA0
DQMA3 D3 DML VSS B3
<26> DQMA1 DMU VSS <26> DQMA3 DMU VSS
E1 E1 FBx_CMD16 CS0#
L:Group 2 VSS G8 H:Group 3 VSS G8
G3 VSS J2 G3 VSS J2
<26> DQSA#2
DQSA#2
DQSL VSS <26> DQSA#0
DQSA#0
DQSL VSS FBx_CMD17
DQSA#1 B7 J8 DQSA#3 B7 J8
<26> DQSA#1 DQSU VSS <26> DQSA#3 DQSU VSS
M1 M1 FBx_CMD18 ODT
VSS M9 VSS M9
VSS P1 VSS P1
VSS VSS FBx_CMD19 CKE
CMDA5 T2 P9 CMDA5 T2 P9
RESET VSS T1 RESET VSS T1
VSS VSS FBx_CMD20 A13 A13
L8 T9 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
FBx_CMD21 A8 A8
1
1
J1 B1 J1 B1 FBx_CMD22 A6 A6
RV145 L1 NC/ODT1 VSSQ B9 RV150 L1 NC/ODT1 VSSQ B9
J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1
C
243_0402_1%
NC/CE1 VSSQ
243_0402_1%
NC/CE1 VSSQ FBx_CMD23 A11 A11 C
DIS@ L9 D8 DIS@ L9 D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 FBx_CMD24 A5 A5
2
2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ VSSQ FBx_CMD25 A3 A3
G1 G1
VSSQ G9 VSSQ G9
VSSQ VSSQ FBx_CMD26 BA2 BA2
96-BALL 96-BALL FBx_CMD27 BA1 BA1
SDRAM DDR3 SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96 FBx_CMD28 A12 A12
FBx_CMD29 A10 A10
FBx_CMD30 RAS# RAS#
+1.5VGS Closed to UV12
L
L
CV97
0.1U_0402_16V7K
CV98
0.1U_0402_16V7K
CV99
0.1U_0402_16V7K
CV100
0.1U_0402_16V7K
CV101
0.1U_0402_16V7K
CV102
1U_0402_6.3V6K
CV103
1U_0402_6.3V6K
CV104
1U_0402_6.3V6K
CV105
1U_0402_6.3V6K
CV106
1U_0402_6.3V6K
2 2 2 2 2 1 1 1 1 1
CV118
0.1U_0402_16V7K
CV119
0.1U_0402_16V7K
CV120
0.1U_0402_16V7K
CV121
0.1U_0402_16V7K
CV122
0.1U_0402_16V7K
CV123
1U_0402_6.3V6K
CV124
1U_0402_6.3V6K
CV125
1U_0402_6.3V6K
CV126
1U_0402_6.3V6K
CV127
1U_0402_6.3V6K
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
1 1 1 1 1 2 2 2 2 2
D D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL N15V-GM VRAM A Lower
Custom 0.1
Date:
LA-A999P
1 2 3 4 5
1 2 3 4 5
Memory Partition A RANK 0 32 bits MDA[0..63] <26,27>

+1.5VGS
CMDA[30..0] <26,27>
Rank 0
1
RV152
1.33K_0402_1%
DIS@ 2
Data32~Data63 Rank 0
A A
+FBA_VREF1 UV16 X76@ UV18 X76@
CV138
0.01U_0402_16V7K
+FBA_VREF1 M8 E3 MDA35 +FBA_VREF1 M8 E3 MDA52
VREFCA DQL0 VREFCA DQL0
1
1 H1 F7 MDA37 H1 F7 MDA49
RV153 VREFDQ DQL1 F2 MDA34 VREFDQ DQL1 F2 MDA53
1.33K_0402_1% CMDA9 N3 DQL2 F8 MDA39 CMDA9 N3 DQL2 F8 MDA50
A0 DQL3 A0 DQL3 Group 6
DIS@
DIS@ CMDA11 P7 H3 MDA32 CMDA11 P7 H3 MDA54

2 CMDA8 P3 A1 DQL4 H8 MDA38 Group 4 CMDA8 P3 A1 DQL4 H8 MDA48 Mode D Command Mapping
2
CMDA25 N2 A2 DQL5 G2 MDA33 CMDA25 N2 A2 DQL5 G2 MDA55

CMDA10 P8 A3 DQL6 H7 MDA36 CMDA10 P8 A3 DQL6 H7 MDA51
A4 DQL7 A4 DQL7 RANK 0
CMDA24 P2 CMDA24 P2
R8 A5 R8 A5
CMDA22
A6
CMDA22
A6
Address 0..31 32..63
CMDA7 R2 D7 MDA56 CMDA7 R2 D7 MDA44
CMDA21 T8 A7 DQU0 C3 MDA60 CMDA21 T8 A7 DQU0 C3 MDA40
A8 DQU1 A8 DQU1 FBx_CMD0 CS0#
CMDA6 R3 C8 MDA58 CMDA6 R3 C8 MDA46
CMDA29 L7 A9 DQU2 C2 MDA61 CMDA29 L7 A9 DQU2 C2 MDA41
A10/AP DQU3 Group 7 A10/AP DQU3 Group 5 FBx_CMD1
CMDA23 R7 A7 MDA57 CMDA23 R7 A7 MDA45
CMDA28 N7 A11 DQU4 A2 MDA63 CMDA28 N7 A11 DQU4 A2 MDA43
A12 DQU5 A12 DQU5 FBx_CMD2 ODT
CMDA20 T3 B8 MDA59 CMDA20 T3 B8 MDA47
CMDA4 T7 A13 DQU6 A3 MDA62 CMDA4 T7 A13 DQU6 A3 MDA42
A14 DQU7 A14 DQU7 FBx_CMD3 CKE
CLKA1 M7 M7
A15/BA3 +1.5VGS A15/BA3 +1.5VGS FBx_CMD4 A14 A14
1
CMDA12 M2 B2 CMDA12 M2 B2 FBx_CMD5 RST RST

RV154 CMDA27 N8 BA0 VDD D9 CMDA27 N8 BA0 VDD D9
162_0402_1% CMDA26 M3 BA1 VDD G7 CMDA26 M3 BA1 VDD G7
BA2 VDD BA2 VDD FBx_CMD6 A9 A9
DIS@ K2 K2
VDD K8 VDD K8 FBx_CMD7 A7 A7
2
VDD N1 VDD N1
CLKA1# CLKA1 J7
310mA VDD N9 CLKA1 J7 VDD N9
B
<26> CLKA1 CK VDD CK VDD FBx_CMD8 A2 A2 B
CLKA1# K7 R1 CLKA1# K7 R1
<26> CLKA1# CK VDD CK VDD
#8/19 , change CLK CMDA19 K9 R9 CMDA19 K9 R9 FBx_CMD9 A0 A0
CKE/CKE0 VDD CKE/CKE0 VDD
termination to 162 ohm. FBx_CMD10 A4 A4
CMDA18 K1 A1 CMDA18 K1 A1
CMDA16 L2 ODT/ODT0 VDDQ A8 CMDA16 L2 ODT/ODT0 VDDQ A8
CS/CS0 VDDQ CS/CS0 VDDQ FBx_CMD11 A1 A1
CMDA30 J3 C1 CMDA30 J3 C1
CMDA15 K3 RAS VDDQ C9 CMDA15 K3 RAS VDDQ C9
CAS VDDQ CAS VDDQ FBx_CMD12 BA0 BA0
CMDA13 L3 D2 CMDA13 L3 D2
WE VDDQ E9 WE VDDQ E9
VDDQ VDDQ FBx_CMD13 WE# WE#
F1 F1
DQSA4 F3 VDDQ H2 DQSA6 F3 VDDQ H2
<26> DQSA4 DQSL VDDQ <26> DQSA6 DQSL VDDQ FBx_CMD14
DQSA7 C7 H9 DQSA5 C7 H9
<26> DQSA7 DQSU VDDQ <26> DQSA5 DQSU VDDQ
FBx_CMD15 CAS# CAS#
DQMA4 E7 A9 DQMA6 E7 A9 FBx_CMD16 CS0#
L:Group 4 <26> DQMA4
DQMA7 D3 DML VSS B3 L:Group 6 <26> DQMA6
DQMA5 D3 DML VSS B3
<26> DQMA7 DMU VSS <26> DQMA5 DMU VSS
E1 E1 FBx_CMD17
H:Group 7 VSS G8 H:Group 5 VSS G8
DQSA#4 G3 VSS J2 DQSA#6 G3 VSS J2
<26> DQSA#4 DQSL VSS <26> DQSA#6 DQSL VSS FBx_CMD18 ODT
DQSA#7 B7 J8 DQSA#5 B7 J8
<26> DQSA#7 DQSU VSS <26> DQSA#5 DQSU VSS
M1 M1 FBx_CMD19 CKE
VSS M9 VSS M9
VSS P1 VSS P1
CMDA5 T2 P9 CMDA5 T2 P9
RESET VSS T1 RESET VSS T1
L8 T9 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
FBx_CMD22 A6 A6
1
1
C C
J1 B1 J1 B1 FBx_CMD23 A11 A11
RV155 L1 NC/ODT1 VSSQ B9 RV162 L1 NC/ODT1 VSSQ B9
243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1
NC/CE1 VSSQ NC/CE1 VSSQ FBx_CMD24 A5 A5
DIS@ L9 D8 DIS@ L9 D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 FBx_CMD25 A3 A3
2
2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
G1 G1
VSSQ G9 VSSQ G9
96-BALL 96-BALL FBx_CMD28 A12 A12
SDRAM DDR3 SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96 FBx_CMD29 A10 A10
FBx_CMD30 RAS# RAS#

L +1.5VGS
L Closed to UV18
CV139
0.1U_0402_16V7K
CV140
0.1U_0402_16V7K
CV141
0.1U_0402_16V7K
CV142
0.1U_0402_16V7K
CV143
0.1U_0402_16V7K
CV144
1U_0402_6.3V6K
CV145
1U_0402_6.3V6K
CV146
1U_0402_6.3V6K
CV147
1U_0402_6.3V6K
CV148
1U_0402_6.3V6K
CV160
0.1U_0402_16V7K
CV161
0.1U_0402_16V7K
CV162
0.1U_0402_16V7K
CV163
0.1U_0402_16V7K
CV164
0.1U_0402_16V7K
CV165
1U_0402_6.3V6K
CV166
1U_0402_6.3V6K
CV167
1U_0402_6.3V6K
CV168
1U_0402_6.3V6K
CV169
1U_0402_6.3V6K
2 2 2 2 2 1 1 1 1 1
2 2 2 2 2 1 1 1 1 1
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
1 1 1 1 1 2 2 2 2 2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
1 1 1 1 1 2 2 2 2 2
D D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL N15V-GM VRAM C Lower
Custom 0.1
Date:
LA-A999P
1 2 3 4 5
1 2 3 4 5
+3VGS Table 123

Strap pin Strap Mapping Resistance Polarity Logical
Name Strapping Bit0
Check Strap pin status ROM_SCLK SMB_ALT_ADDR 10K Pull-down to GND.
1
RV164 RV165 RV166 RV167 RV168 ROM_SI SUB_VENDOR 10K Pull-down to GND if no VBIOS ROM.
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
X76@ X76@ X76@ X76@ @ ROM_SO VGA_DEVICE 10K Pull-down to GND(no diaplay).
2
STRAP0 RAM_CFG[0] 10K
STRAP0
<23> STRAP0
STRAP1 STRAP1 RAM_CFG[1] 10K
<23> STRAP1
STRAP2
<23> STRAP2
STRAP3 STRAP2 RAM_CFG[2] 10K
<23> STRAP3
A STRAP4 A
<23> STRAP4
STRAP3 RAM_CFG[3] 10K
STRAP4 PCIE_MAX_SPEED 10K Pull-down to GND(PCIE Gen1).
1
RV171 RV172 RV173 RV174 RV175
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
X76@ X76@ X76@ X76@ DIS@ SMBUS_ALT_ADDR SUB_VENDOR
2
0 0x9E (Default) 0 Disable (Default)
1 0x9C (Multi-GPU usage) 1

+3VGS
VGA_DEVICE
Check SPI pin status 0
1 Non-Primary 3D Acceleration Device(Class Code 302h)(Default)
1
RV176 RV177 RV178
10K_0402_5% 10K_0402_5% 10K_0402_5% 1 Primary Display or VGA Device .
@ @ @
2
2
PCIE_MAX_SPEED
ROM_SI
<23> ROM_SI
ROM_SO 0 Limit to PCIE Gen1
<23> ROM_SO
ROM_SCLK
<23> ROM_SCLK
1 PCIE Gen 2/3 Capable
1
1
B B
ZZZ ZZZ ZZZ
RV179 RV180 RV181
10K_0402_5% 10K_0402_5% 10K_0402_5%
DIS@ DIS@ DIS@
2
SAM@ MIC@ HY@

1G SAMSUNG 1G MICRON 1G HYNIX
X7654132L21 X7654132L23 X7654132L22
ROM CFG setup

GPU Project VRAM size CH Description Compal VRAM P/N VRAM description [3...0] RAM_CFG R P/N
128M(X16) CHA DDR3 Hynix 128Mx16 1.5V SA00006H400 H5TC2G63FFR-11C 1000MHz 1100 RV171+RV172+RV167+RV166
ZSO40
ZSO50 128M(X16) CHA DDR3 Micron 128Mx16 1.5V SA000067500 MT41J128M16JT-093G:K 1000MHz 0001 RV164+RV172+RV173+RV174
N15V-GM (23x23) 64bit
(One CH single rank) 128M(X16) CHA DDR3 Samsung 128Mx16 1.5V SA000068U00 K4W2G1646E-BC1A 1000MHz 0101 RV164+RV172+RV166+RV174
#9/5 RAM_CFG follow RVL-06891-001 table 1.

Dule Rank layout with single Rank population. USER Straps
User[3:0]
C 1000-1100 Customer defined C
D D

Title
MISC Rev
Custom 1.0
Date:
LA-A999P
1 2 3 4 5
5 4 3 2 1
LVDS Power +3VALW

+3VS
W=60mils W=60mils
Touch Screen Power INVPWR_B+ B+
W=60mils UG1 W=60mils
1
5 1 RTS2 @EMI@
IN OUT +LCDVDD
100K_0402_5% 0_0805_5% 2 1 L1
2
GND
0.1U_0402_16V7K
@EMI@ 0_0805_5%
2
CG3
4 3 1 1 2 1 L2
SS EN
1
1 CG2
1
RTS1 D
1 1
D CG1 APL3512_SOT23-5 4.7U_0603_6.3V6K 1K_0402_5% QTS1 2 @EMI@ C117 C4620 SM010014520 3000ma D
2 2 TOUCH_ON# <41>
2N7002K_SOT23 G 680P_0402_50V7K 68P_0402_50V8J
1500P_0402_50V7K 2 CTS2
220ohm@100mhz
S
3
1 2 2 2 DCR 0.04
+VCC_TOUCH
2
0.047U_0402_16V7K
G
RG3 1 short@ 2 0_0402_5% 1 3
<16> PCH_ENVDD +3VS
S
0.1U_0402_16V4Z
1
CTS1
<1125>change power rail.
QTS2
S TR LP2301ALT1G 1P SOT-23-3
R2591 @ 2 INVTPWM 2
<41> EC_INVT_PWM
0_0402_5%
1
<16> DPST_PWM R258 1 short@ 2 0_0402_5% @
R163 Camera @EMI@
10K_0402_5% R170 1 2 0_0402_5%
L12 EMI@
D5
2
1 2 USB20_N8_R
<17> USB20_N8 1 2 2
USB20_P8_R C121 2 1 220P_0402_50V7K INVTPWM
1
4 3 USB20_P8_R USB20_N8_R 3 C122 2 1 220P_0402_50V7K DISPOFF#
1 2 <17> USB20_P8 4 3
C <41> EC_BKOFF# EC_BKOFF# DISPOFF# C
R166 33_0402_5% WCM-2012-900T_4P
PESD5V0U2BT_SOT23-3
1
R171 1 2 0_0402_5% @ESD@ SCA00000U10

R167 @EMI@
10K_0402_5%
LCD/LED PANEL Conn.
2
+LCDVDD
D3
D_MIC_L_CLK 2 CONN@
LVDS SKU D_MIC_L_DATA 3
1
1
JLVDS1
2 1 41
LCD_EDID_CLK R168 1 LVDS@ 2 0_0402_5% LCD_CLK LCD_CLK 3 2 G1 42
<16> LCD_EDID_CLK PESD5V0U2BT_SOT23-3 3 G2
LCD_EDID_DATAR169 1 LVDS@ 2 0_0402_5% LCD_DATA LCD_DATA 4 43
<16> LCD_EDID_DATA 4 G3
@ESD@ SCA00000U10 5 44
RP36 5 G4
LVDS@ SD309000080 LVDS_TXP0_CONN 6 45
4 5 LVDS_TXP0_CONN LVDS_TXN0_CONN 7 6 G5 46
<16> LVDS_TXP0 3 6 LVDS_TXN0_CONN 8 7 G6
<16> LVDS_TXN0 2 7 LVDS_TXP1_CONN 9 8
LVDS_TXP1_CONN
<16> LVDS_TXP1 1 8 LVDS_TXN1_CONN 10 9
LVDS_TXN1_CONN
<16> LVDS_TXN1 10
<DB>LA1/LA2 closed to Aduio codec 11
LVDS_TXP2_CONN 12 11
0_0804_8P4R_5% EMI@ LVDS_TXN2_CONN 13 12
B
RP37
LVDS@ SD309000080
131203 SWAP D_MIC_CLK
LA1
1
FBMA-L10-160808-301LMT_2P
2 D_MIC_L_CLK LVDS_CLKP_CONN
14
15
13
14
B
4 5 LVDS_TXP2_CONN <37> D_MIC_CLK D_MIC_DATA 1 short@ 2 D_MIC_L_DATA LVDS_CLKN_CONN 16 15
<16> LVDS_TXP2 <37> D_MIC_DATA 16
3 6 LVDS_TXN2_CONN LA2 0_0402_5% 17
<16> LVDS_TXN2 2 7 LVDS_CLKP_CONN USB20_N8_R 18 17
<16> LVDS_CLKP 1 8 LVDS_CLKN_CONN 19 18
USB20_P8_R
<16> LVDS_CLKN 20 19
USB20_P10_R 21 20
0_0804_8P4R_5% USB20_N10_R 22 21
TS_GPIO_CPUR2601 @ 2 TS_GPIO DISPOFF# 23 22
<18> TS_GPIO_CPU 23
0_0402_5% INVTPWM 24
TS_GPIO_EC R2611 short@ 2 TS_GPIO 25 24
<41> TS_GPIO_EC 25
0_0402_5% 26
eDP SKU INVPWR_B+
27
28
26
27
29 28
CC100 1eDP@ 2 .1U_0402_16V7K LVDS_TXP2_CONN 30 29
<5> EDP_CPU_LANE_P0_C +VCC_TOUCH 30
CC103 1eDP@ 2 .1U_0402_16V7K LVDS_TXN2_CONN 31
<5> EDP_CPU_LANE_N0_C 31
CC102 1eDP@ 2 .1U_0402_16V7K LCD_CLK 32
<5> EDP_CPU_AUX_C +3VS 32
CC101 1eDP@ 2 .1U_0402_16V7K LCD_DATA Touch Screen @EMI@ 33
<5> EDP_CPU_AUX#_C 1 2 0_0402_5% 34 33
R173
D_MIC_L_CLK 35 34
<1114>Follow AMD eDP pin assignment. D_MIC_L_DATA 36 35
L13 EMI@
D6 1 2 37 36
USB20_P10_R
USB20_N10_R 2 <17> USB20_P10 1 2 EDP_HPD_PANEL 38 37
1 39 38
EDP_HPD# USB20_P10_R 3 4 3 USB20_N10_R 40 39
<5> EDP_HPD# <17> USB20_N10 4 3 40
A eDP@ WCM-2012-900T_4P STARC_107K40-000001-G2 A
PESD5V0U2BT_SOT23-3
1
D
QTS3 2 EDP_HPD_PANEL @ESD@ SCA00000U10 R174 1 2 0_0402_5% 131202 Follow 15" CRV
2N7002K_SOT23 G @EMI@
S eDP@
3
RTS3 Security Classification Compal Secret Data Compal Electronics, Inc.

100K_0402_5% Issued Date 2013/02/26 Deciphered Date 2015/07/08 Title
LVDS Connector
2
LA-A992P 0.1
5 4 3 2 1
5 4 3 2 1
+3VS
PCH_DPB_P0 0.1U_0402_16V7K 1 2 CG27 PCH_DPB_P0_C
<16> PCH_DPB_P0
PCH_DPB_N0 0.1U_0402_16V7K 1 2 CG28 PCH_DPB_N0_C
<16> PCH_DPB_N0
<16> PCH_DPB_P1
<CPU> PCH_DPB_N1 0.1U_0402_16V7K 1 2 CG30 PCH_DPB_N1_C
<16> PCH_DPB_N1
1
RG47
<16> PCH_DPB_P2
PCH_DPB_N2 0.1U_0402_16V7K 1 2 CG32 PCH_DPB_N2_C 1M_0402_5%
<16> PCH_DPB_N2
2
<16> PCH_DPB_P3
2
D PCH_DPB_N3 0.1U_0402_16V7K 1 2 CG34 PCH_DPB_N3_C D
<16> PCH_DPB_N3
1 6 HP_DETECT
<16> PCH_DDPB_HPD
20K_0402_5%
QG1A 1
5
6
7
8
5
6
7
8
1
2N7002KDW _SOT363-6 CM17 @
5V Level RG56 220P_0402_50V7K
2N7002KDW _SOT363-6 2
QG1B
4
3
2
1
4
3
2
1
3 4
2
RP3 RP4
680_0804_8P4R_5% 680_0804_8P4R_5%
5
<1125>change to 680 ohm. +3VS
+3VS
@EMI@
PCH_DPB_P3_C RG59 1 2 0_0402_5% HDMI_R_CK+
4 3
C 4 3 C
5
EMI@ CMMI21T-900Y-N
SM070003K00 LM13 1 2 QG2B
1 2 PCH_DDPB_CLK 4 3 HDMI_SCLK
<16> PCH_DDPB_CLK
PCH_DPB_N3_C RG60 1 2 0_0402_5% HDMI_R_CK-
@EMI@ 2N7002DW H_SOT363-6
SB00000DH00
@EMI@ +3VS
PCH_DPB_N0_C RG61 1 2 0_0402_5% HDMI_R_D0-
1 2
EMI@ LM14 1 2
2
SM070003K00 CMMI21T-900Y-N
4 3
4 3 PCH_DDPB_DAT 1 6 HDMI_SDATA
<16> PCH_DDPB_DAT
PCH_DPB_P0_C RG63 1 2 0_0402_5% HDMI_R_D0+
@EMI@ 2N7002DW H_SOT363-6
+HDMI_5V_OUT SB00000DH00 QG2A
PCH_DPB_P1_C RG64 1 2
@EMI@ 0_0402_5% HDMI_R_D1+
4 3 +3VS
4 3 RG105
EMI@ CMMI21T-900Y-N 1 8 HDMI_SDATA
SM070003K00 LM15 1 2 2 7 HDMI_SCLK
1 2 3 6 PCH_DDPB_DAT
PCH_DPB_N1_C RG65 1 2 0_0402_5% HDMI_R_D1- 4 5 PCH_DDPB_CLK
@EMI@
2.2K_0804_8P4R_5%
PCH_DPB_P2_C RG66 1 2
@EMI@ 0_0402_5% HDMI_R_D2+
B B
4 3
4 3
EMI@ CMMI21T-900Y-N HDMI Conn.
SM070003K00 LM16 1 2
1 2
PCH_DPB_N2_C RG70 1 2 0_0402_5% HDMI_R_D2-
@EMI@ JHDMI1
HP_DETECT 19
SC300002800 18 HP_DET
+HDMI_5V_OUT +5V
@ESD@ DG1 17
1 1 DDC/CEC_GND
HP_DETECT 10 9 HP_DETECT HDMI_SDATA 16
HDMI_SCLK 15 SDA
2 2 SCL
W=40mils HDMI_SDATA 9 8 HDMI_SDATA 14
13 Reserved
FG1 +HDMI_5V_OUT CEC
HDMI_SCLK 4 4 7 7 HDMI_SCLK HDMI_R_CK- 12 20
@ @ 11 CK- GND 21
CK_shield GND
10P_0402_50V8J
10P_0402_50V8J
3 5 5 6 6 1 1 HDMI_R_CK+ 10 22
OUT CM26 CM27 HDMI_R_D0- 9 CK+ GND 23
1 3 3 8 D0- GND
+5VS IN D0_shield
1 HDMI_R_D0+ 7
2 8 2 2 HDMI_R_D1- 6 D0+
GND 5 D1-
CG46 IP4292CZ10-TB HDMI_R_D1+ 4 D1_shield
0.1U_0402_16V7K 2 HDMI_R_D2- 3 D1+
AP2330W-7_SC59-3 2 D2-
HDMI_R_D2+ 1 D2_shield
D2+
A
CONCR_099AKAC19NBLCNF A
CONN@

HDMI Conn/Level shift
0.1
LA-A999P
5 4 3 2 1
5 4 3 2 1
D D
<1125>change R to 2.2K.
+3VS
+HDMI_5V_OUT
@ESD@
DT4
SC300001G00
R4101 R4102 CRT_HSYNC_2 6 3 CRT_VSYNC_2
I/O4 I/O2
2
+HDMI_5V_OUT
2.2K_0402_5%
2.2K_0402_5%
5 2
VDD GND
1
CRT_DATA 4 1 CRT_CLK
I/O3 I/O1
2
SB00000DH00
CRT_DDC_DATA 1 6 CRT_DATA AZC099-04S.R7G_SOT23-6

<16> CRT_DDC_DATA
5
2N7002DWH_SOT363-6 @ESD@
DT3
QG3B QG3A SC300001G00
<16> CRT_DDC_CLK CRT_DDC_CLK 4 3 CRT_CLK CRT_R_2 6 3 CRT_G_2
I/O4 I/O2
2N7002DWH_SOT363-6 +HDMI_5V_OUT
SB00000DH00
5 2
VDD GND
4 1 CRT_B_2
I/O3 I/O1
AZC099-04S.R7G_SOT23-6
RGB Trace must less than 2000mils.

C C
CRB1.0 use 33ohm@100Mhz Bead CRT Connector

JCRT1
L4103 6
KC FBMA-L10-160808-600LMT 11
<16> CRT_R CRT_R 1 2 EMI@ CRT_R_2 1
L4104 7
KC FBMA-L10-160808-600LMT CRT_DATA 12
<16> CRT_G CRT_G 1 2 EMI@ CRT_G_2 2
L4105 8
KC FBMA-L10-160808-600LMT CRT_HSYNC_2 13
<16> CRT_B CRT_B 1 2 EMI@ CRT_B_2 3
+HDMI_5V_OUT +HDMI_5V_OUT 9
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
CRT_VSYNC_2 14
1 1 1 1 1 1 W=40mils 4
1 10 G 16
C4126
C4127
C4128
C4129
C4130
C4131
CRT_CLK 15 G 17
C4132
0.1U_0402_16V4Z
5
2 2 2 2 2 2 @
131126 SWAP RP22.1 & RP22.2 by layout requested 2 C-H_13-12201560CP
CONN@
RP22 DC060006E00
8 1 CRT_G
7 2 CRT_B
6 3 CRT_R
5 4
150_0804_8P4R_1%
+HDMI_5V_OUT
RT26 1 2 CRT_HSYNC_2
1 2 2 1 LT14 33_0402_5%
CT27 0.1U_0402_16V4Z
10K_0402_5% 1 2 CRT_VSYNC_2
1
UT2 LT15 33_0402_5% 1 1
74AHCT1G125GW_SOT353-5
OE#
B B
<16> HSYNC HSYNC 2 4 CRT_HSYNC_1 @ @
A Y CT26 CT28
G
10P_0402_50V8J 2 2 10P_0402_50V8J
3
+HDMI_5V_OUT
CT25 1 2 0.1U_0402_16V4Z
1
P
OE#
<16> VSYNC VSYNC 2 4 CRT_VSYNC_1
A Y
G
UT4
74AHCT1G125GW_SOT353-5
3
A A

Issued Date 2011/06/30 2013/06/30 Title
Deciphered Date
CRT
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-A999P
5 4 3 2 1
5 4 3 2 1
+3VS_WLAN
1
D +3VS_WLAN RN3 +1.5VS_WLAN +3VS_WLAN D
<44> MC_WAKE#
10K_0402_5%
RN13 JMINI1
2
2 short@ 0_0201_5%
short@1 1 2
<41> EC_PCIE_WAKE# 1 2
3 4
BT_ON_EC 5 3 4 6
7 5 6 8
<15> MINI1_CLKREQ# 7 8
9 10
11 9 10 12
<15> CLK_PCIE_MINI1# 11 12
13 14
<15> CLK_PCIE_MINI1 15 13 14 16
17 15 16 18
19 17 18 20 WL_OFF#
19 20 WL_OFF# <15>
21 22 PLT_RST#
21 22 PLT_RST# <17,22,35,40,41,6>
23 24 +3VS_WLAN
<15> PCIE_PRX_DTX_N1 25 23 24 26
<15> PCIE_PRX_DTX_P1 27 25 26 28
29 27 28 30
31 29 30 32
<15> PCIE_PTX_C_DRX_N1 31 32
<15> PCIE_PTX_C_DRX_P1 33 34
35 33 34 36
37 35 36 38 USB20_N9 <17>
37 38 USB20_P9 <17>
39 40
C 39 40 C
41 42
43 41 42 44
45 43 44 46 MINI1_LED# <41>
47 45 46 48
E51TXD_P80DATA 49 47 48 50
<41> E51TXD_P80DATA 51 49 50 52
E51RXD_P80CLK
<41> E51RXD_P80CLK 51 52
53 54
GND1 GND2
1
2
RN7
R216 BELLW_80053-1021 4.7K_0402_5%
100K_0402_5% CONN@
BT_ON_EC 1 RC160 2 E51RXD_P80CLK
<41> BT_ON_EC
2
1K_0402_1%
1
+3VS_WLAN
+1.5VS +1.5VS_WLAN
B RN1 @ B
1 2
1
0_0603_5% CN1
4.7U_0603_6.3V6K
2
@
+3VS_WLAN_R +3VS_WLAN
R271 @
1 2
0.1U_0402_16V7K
CN3
0_0805_5% 1@ 1
CN2
4.7U_0603_6.3V6K
2 2
A A

WLAN
Document Number Rev
0.1
LA-A999P
5 4 3 2 1
5 4 3 2 1
2.5" SATA HDD connector +5VS_HDD1

+5VS_ODD
10U_0603_6.3V6M
22U_0805_6.3V6M
1 1
C576
CC134
Change to dual load switch for ODD and WLAN
10U_0603_6.3V6M
0.1U_0402_16V7K
+5VS
+5VALW +5VS <MV>Add 22UF for RF suggestion ,4/10.
C150
+3VALW 1 1
2 2
C149
@ @ 0_0603_5%
Q22 R201 1 2
+5VS_HDD1
1 14 @ 0_0603_5%
2 VIN1 VOUT1 13 R212 1 2 2 2
VIN1 VOUT1
D D
ODD_PWR 3 12 C555 1 2 100P_0402_50V8J
<18> ODD_PWR ON1 CT1
4 11
VBIAS GND
WL_PWREN_EC 5 10 C558 1 2 680P_0402_50V7K
<41> WL_PWREN_EC ON2 CT2
6 9 JHDD1
7 VIN2 VOUT2 8 1 23
VIN2 VOUT2 SATA_PTX_R_DRX_P0 C155 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 2 GND GND 24
15 SATA_PTX_R_DRX_N0 C156 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 3 A+ GND
GPAD 4 A-
+3VS_WLAN_R GND
TPS22966DPUR_SON14_2X3-D SATA_PRX_R_DTX_N0 C153 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N0 5
SATA_PRX_R_DTX_P0 C154 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P0 6 B-
1 B+
10U_0603_6.3V6M
C571
7
GND
<SI>RS11 change to un pop
2 RS11 1 @ 2 0_0402_5% 8
+3VS VCC3.3
9
JHDD_P10 10 VCC3.3
11 VCC3.3
12 GND
13 GND
0_0804_8P4R_5% GND
14
Reserve SATA Redriver SATA_PRX_DTX_P0 1 8 SATA_PRX_R_DTX_P0 +5VS_HDD1
15 VCC5
VCC5
SATA_PRX_DTX_N02 7 SATA_PRX_R_DTX_N0 16
SATA_PTX_DRX_N03 6 SATA_PTX_R_DRX_N0 131203 SWAP pin of PR38 by layout requested 17 VCC5
SATA_PTX_DRX_P0 4 5 SATA_PTX_R_DRX_P0 ReSATA@ 18 GND
C RESERVED C
C157 1 2 0.01U_0402_16V7K SATA_PRX_R1_DTX_N0 19
+3VS +3VS_SATA_RE SD309000080 <14> SATA_PRX_DTX_N0 C158 1 2 0.01U_0402_16V7K SATA_PRX_R1_DTX_P0 20 GND
RP38 <14> SATA_PRX_DTX_P0 VCC12
NORESATA@ ReSATA@ 21
ReSATA@ ReSATA@ 22 VCC12
R103 1 2 0_0603_5% +3VS_SATA_RE C159 1 2 0.01U_0402_16V7K SATA_PTX_R1_DRX_P0 VCC12
+3VS_SATA_RE <14> SATA_PTX_DRX_P0
C160 1 2 0.01U_0402_16V7K SATA_PTX_R1_DRX_N0 SANTA_193202-1
<14> SATA_PTX_DRX_N0
ReSATA@ CONN@
2
ReSATA@
R136 1 2
10K_0402_5% @ C46 C4619
0.1U_0402_10V6K @
ReSATA@ 0.01U_0402_25V7K
1
U71 2 1
7 6 +5VS_ODD
EN VDD 16 Pleace near ODD Connector
SATA_PTX_R1_DRX_P0 1 VDD
SATA_PTX_R1_DRX_N0 2 A_INp 10 ReSATA@
A_INn NC
1000P_0402_50V7K
0.1U_0402_25V6K
10U_0805_10V6K
PCH side 20 1 R4610 2
SATA_PRX_R1_DTX_P0 5 REXT 4.99K_0402_1%
B_OUTp 1 1 1
SATA_PRX_R1_DTX_N0 4 9 A_PRE0
B_OUTn A_PRE0
CS13
CS16
CS12
8 B_PRE0
B_PRE1 17 B_PRE0
A_PRE1 19 B_PRE1 15 SATA_PTX_R_DRX_P0
11/25 add R4610 4.99k -> Parade review 2 2 2
A_PRE1 A_OUTp 14 SATA_PTX_R_DRX_N0
@ R143 2 1 10K_0402_5% 18 A_OUTn
+3VS_SATA_RE
3 TEST 11 SATA_PRX_R_DTX_P0
Connector side
B GND B_INp B
13 12 SATA_PRX_R_DTX_N0
21 GND B_INn JODD1
EPAD 1
PS8520BTQFN20GTR2_TQFN20_4X4 CS11 2 1 0.01U_0402_16V7K SATA_PTX_C_DRX_P1 2 GND
<14> SATA_PTX_DRX_P2 RX+
CS14 2 1 0.01U_0402_16V7K SATA_PTX_C_DRX_N1 3
<14> SATA_PTX_DRX_N2 RX-
4
CS15 2 1 0.01U_0402_16V7K SATA_PRX_C_DTX_N1 5 GND
<14> SATA_PRX_DTX_N2 CS18 2 1 0.01U_0402_16V7K SATA_PRX_C_DTX_P1 6 TX-
<14> SATA_PRX_DTX_P2 7 TX+
GND
8
+3VS_SATA_RE <18> ODD_PLUG# 9 DP
10 +5V
11/29 emphasis=1, 1==>R145/R152 ODD_DA# 11 +5V
<17> ODD_DA# 12 MD 14
13 GND GND1 15
GND GND2
2
ReSATA@ ReSATA@
R145 R147 @ R150 @ R152 <SI> Delete Q84, R954 OCTEK_SLS-13HCAB
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 1
CS17 CONN@
0.1U_0402_25V6K
1
B_PRE1 A_PRE1 A_PRE0 B_PRE0 ESD@

Need Vendor check value 2
2
Place CS17 close to JODD

R146 @ R149 @ R151 @ R153 @
A 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% A
1

ODD/SATA Conn
Custom 0.1
LA-A999P
5 4 3 2 1
5 4 3 2 1
JHW1 need to short LDO mode Switcing mode

JHW1
@ LL1 SMT @
1 2 RTL8151G (LDO mode)
1 2
+LAN_VDD_3V3 Rising time CL21 SMT @
JUMP_43X79
+3VALW
@ UG5 need>0.5mS and <100mS LL2 @ SMT
CL8 @ SMT +LAN_VDD_1V0
5 1 +LAN_VDD_3V3 LL1
IN OUT 1 2
2 short@
CL14 & CL15 close UL1 Pin22
GND 0_0603_5%
1@ RL35 20_0201_5% 1 4 3 @ LL2
CL26 & CL27 close UL1 Pin30
SS EN +LAN_REGOUT 1 2
1U_0402_6.3V6K
1U_0402_6.3V6K
@ CL28 2.2UH +-5% NLC252018T-2R2J-N
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
4.7U_0603_6.3V6K
APL3512_SOT23-5 1 1 1 1 1 1 1 1 1
0.1U_0402_16V7K
D 2 D
CL8
1500P_0402_50V7K @ CL12 CL13
CL23
1
CL11 CL14 CL15 CL26 CL27
CL21 @ @ 8161@ @8161@ 8166@ @8166@
@ 2 2 2 2 2 2 2 2 2
RL29 2 1 10K_0402_5%LAN_PWR_EN_R 2
<18> LAN_PWR_EN
Place CL11~CL13 close UL1 Pin 3, 8 , 22 EC_LAN_ISOLATEB# 2 1 +3VS

LL2, CL8, CL23 for 8161 1K_0402_5% RL5
1
2
+LAN_VDD_3V3 +VDDREG @ CL29
CL8 & CL18 close LL2 RL8
2
0.1U_0402_16V7K 8151/8166 Co-Lay 15K_0402_5%
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
+LAN_VDD_3V3=40mil
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1
1 1 1 1 1 1 8161@
@8161@ @ UL1 +LAN_VDD_1V0
CL10
CL16
CL20 CL19 CL9 CL5 L +VDDREG=40mil
@ @ +LAN_REGOUT=60mil
2 2 2 @ 2 2 2 LAN_MDIP0 1 3
LAN_MDIN0 2 MDIP0 AVDD10 8
LAN_MDIP1 4 MDIN0 AVDD10 30 +LAN_VDD_3V3 XTLI
LAN_MDIN1 5 MDIP1 AVDD10 22 +LAN_VDD_3V3
LAN_MDIP2 6 MDIN1 DVDD10 2 1 XTLO
LAN_MDIN2 7 MDIP2 11 1M_0402_5% RL7
MDIN2 AVDD33 +LAN_VDD_3V3
1
LAN_MDIP3 9 32 @
MDIP3 AVDD33 XTAL@
LAN_MDIN3 10 RL10 RL15
MDIN3 23 +VDDREG 1 2
CL9 & CL5 close to UL1: Pin 11,32 CL10& CL16 close to UL1: Pin 23 VDDREG(VDD33) 24 +LAN_REGOUT
10K_0402_5%
short@ short@
LAN_CLKREQ# 2 RL6 1 0_0201_5% LAN_CLKREQ#_R 12 REGOUT 0_0603_5%
CL19 close to UL1: Pin 32 <15> LAN_CLKREQ# RTL8111G
2
PLT_RST# 19 CLKREQB 21 LANWAKEB XTAL@
<17,22,33,40,41,6> PLT_RST# PERSTB LANWAKEB EC_PME# <18,41>
3
10P_0402_25V8J
10P_0402_25V8J
CL20 close to UL1: Pin 11 20 EC_LAN_ISOLATEB# YL1
CLK_PCIE_LAN 15 ISOLATEB XTAL@ 1 XTAL@ 1
OSC
OSC
<15> CLK_PCIE_LAN 16 REFCLK_P 27
CLK_PCIE_LAN# LED0 TH2 CL25 CL24
<15> CLK_PCIE_LAN# REFCLK_N LED0 26 LED1/GPO TH1
PCIE_PTX_C_DRX_P3 13 LED1/GPO 25 LED2 TH3
GND
GND
<15> PCIE_PTX_C_DRX_P3 14 HSIP LED2(LED1) 2 2
PCIE_PTX_C_DRX_N3
<15> PCIE_PTX_C_DRX_N3 HSIN
C PCIE_PRX_DTX_P3 CR11 1 2 0.1U_0402_10V7K PCIE_PRX_C_DTX_P3 17 28 XTLI C
<15> PCIE_PRX_DTX_P3 HSOP CKXTAL1
PCIE_PRX_DTX_N3 CR13 1 2 0.1U_0402_10V7K PCIE_PRX_C_DTX_N3 18 29 XTLO
<15> PCIE_PRX_DTX_N3
4
HSON CKXTAL2
RSET 31 33 25MHZ_20PF_FSX3M-25.M20FDO
RSET GND SJ10000E500
2
SP050005L00 Footprint
RL11
TSL1 8161@ 2.49K_0402_1% SA00005YT00
UL1 8166@
+V_DAC 1 24
<1118>change to standard part.
1
LAN_MDIN3 2 TCT1 MCT1 23 RJ45_TX3- RP5 SA000063500
LAN_MDIP3 3 TD1+ MX1+ 22 RJ45_TX3+ 1 8 RTL8166EH-CG QFN 32P E-LAN CTRL
TD1- MX1- 2 7 SANTA_130456-291 JLAN1 CONN@
4 21 3 6 RJ45_TX3- 8
LAN_MDIN2 5 TCT2
TD2+
MCT2
MX2+
20 RJ45_TX2- 4 5 (SA000063500) 10/100 8166@ PR4-
GND
10
LAN_MDIP2 6 19 RJ45_TX2+ RJ45_TX3+ 7 9
7
TD2- MX2-
18
75_0804_8P4R_1%
SD300002E80
(SA00005YT00) Giga 8151@ RJ45_RX1- 6
PR4+ GND
TCT3 MCT3 2 PR2-

LAN_MDIN1 8 17 RJ45_RX1- CL2
LAN_MDIP1 9 TD3+ MX3+ 16 RJ45_RX1+ SE167100J80 RJ45_TX2- 5
TD3- MX3- 10P_1808_3KV PR3-
10 15 1 RJ45_TX2+ 4
LAN_MDIN0 11 TCT4 MCT4 14 RJ45_TX0- PR3+ LANGND
LAN_MDIP0 12 TD4+ MX4+ 13 RJ45_TX0+ 1 EMI@ RJ45_RX1+ 3
TD4- MX4- PR2+
2
CL3
YSLC05CH_SOT23-3
ESD@ LANGND 120P_0402_50V8 RJ45_TX0- 2

2
DL1 PR1-
2 1 LANKO_LG-2446S-1 RJ45_TX0+ 1
@ @EMI@ SP050007M00 PR1+
CL1 CL4 S X’FORM_ LG-2446S-1 100/1000BASE-TX LAN
0.01U_0402_16V7K 0.1U_0402_16V7K
1 2
TSL1 8166@
1
SCA00000U10
SP050003P00
S X'FORM_ NS892404 ETHERNET 10/100
(SP050003P00) 10/100 8166@ 131127 SWAP Pin of DL1.2 & DL1.3 by layout requested
B B
(SP050007M00) Giga 8161@
RR1 short@
1 2 +3VS_CR
+3VS +3VS_CR
0_0603_5% 1 1 Card Reader Connector
4.7U_0402_6.3V6M
CR9
2
CR10
2 0.1U_0402_16V7K
RTS5239 RR4-RR9 close to chip CONN@
CR12-CR13 close to chip or socket JREAD1
UR1 SD_D3_R 1
PCIE_PTX_C_DRX_P2 1 12 SD_D1 1 2 SD_D1_R 208MHz DAT3
Close to Chip <15> PCIE_PTX_C_DRX_P2 HSIP SP1
RR2 short@ 0_0402_5%
PCIE_PTX_C_DRX_N2 2 13 SD_D0 RR4 1 short@ 2 0_0402_5% SD_D0_R @ CR12 SD_CMD_R 2
<15> PCIE_PTX_C_DRX_N2 HSIN SP2 +CR_VDD_3V3 CMD
CLK_PCIE_CR 3 14 SD_CLK EMI@ 1 RR5 2 33_0402_5% SD_CLK_R 1 2
<15> CLK_PCIE_CR 4 REFCLKP SP3 16 1 2 3
CLK_PCIE_CR# SD_CMD RR3 short@ 0_0402_5% SD_CMD_R Close to Conn
<15> CLK_PCIE_CR# REFCLKN SP4 VSS1
CL17 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_P2 5 17 SD_D3 RR6 1 short@ 2 0_0402_5% SD_D3_R 6.8P_0402_50V8C
<15> PCIE_PRX_DTX_P2 HSOP SP5
CL18 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_N2 6 18 SD_D2 RR7 1 short@ 2 0_0402_5% SD_D2_R +CR_VDD_3V3 4
<15> PCIE_PRX_DTX_N2 HSON SP6 VDD
0.1U_0402_16V7K
20 SD_WP
SP7
4.7U_0603_6.3V6M
1 SD_CLK_R 5
CLK
1
15 1 2 CR7 CR8
24 DV33_18 11 6
<15> CR_CLKREQ#
CR_CLKREQ#
CLKREQ# DV12_S
+DVDD12 CR14 1U_0402_6.3V4Z Close to Chip VSS2
PLT_RST# 23
2
22 PERST# 2 SD_D0_R 7
SD_CD# 21 MS_INS# 9 +3VS_CR DAT0
+3VS_CR 1 2 19 SD_CD# 3V3_IN 7 +AVDD12 SD_D1_R 8
10K_0402_5% RR8 GPIO AV12 10 DAT1
CARD_3V3 +CR_VDD_3V3
SD_D2_R 9
DAT2
6.2K_0402_1% 1 2 RR9 RREF 8 25 SD_CD# 10 12
RREF GND CD G1
RTS5239-GR_QFN24_4X4 SD_WP 11 13
RR9 close to chip WP G2
TAITW_PSDAT0-09GLBS1ZZ4H1
A A
+DVDD12 +DVDD12 +AVDD12 +AVDD12 Close to Chip

+3VS_CR
0.1U_0402_16V7K
0.1U_0402_16V7K
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
1 1
1
0.1U_0402_16V7K
CR1 CR2 CR3 CR4 1 1

CR5 CR6
2
2 2 4.7U_0402_6.3V6M @
2 2
LAN 8111G
0.1
LA-A999P
5 4 3 2 1
A B C D E
@EMI@
RS1 0_0402_5% USB3.0 need support 2.5A
USB3_TX1_P 2 1 CS1 USB3_TX1_C_P 1 2 USB3TXDP1_C_R change USB PWR SW SA00003TV00
<17> USB3_TX1_P
0.1U_0402_16V7K
CMMI21T-900Y-N low active
4 3 +5VALW +USB_VCCA
4 3
EMI@ US1 W=100mils
1 2 W=100mils 1 8
1000P_0402_50V7K
1 2 GND VOUT
0.1U_0402_16V7K
2 7
47U_0805_6.3V6M
LM1 SM070003K00 3 VIN VOUT 6
1 USB3_TX1_N 2 1 CS2 USB3_TX1_C_N 1 2 USB3TXDN1_C_R 4 VIN VOUT 5 1
<17> USB3_TX1_N EN FLG 1 1 1
0.1U_0402_16V7K RS2 0_0402_5% @
CS6
@EMI@ 1 G547I2P81U_MSOP8 CS5
CS4
CS3
@EMI@ 2 2 2
RS3 0_0402_5% 0.1U_0402_16V7K
2
1 2 USB3RXDP1_C
<17> USB3_RX1_P
CMMI21T-900Y-N @
4 3 USB_ON# 1 2 RS4
4 3 <41> USB_ON#
<EC> 0_0402_5% RS5 1 @ 2 USB_OC0# USB_OC0# <17>
EMI@ 0_0402_5%
1 2
1 2
LM2 SM070003K00
1 2 USB3RXDN1_C @ESD@
<17> USB3_RX1_N
RS6 0_0402_5% DM1 SCA00000U10
@EMI@ 2 USB20_N0_C
1
3 USB20_P0_C
YSLC05CH_SOT23-3
2
USB2.0/USB3.0 port 1 2
@EMI@
RS7 0_0402_5% SC300002800 +USB_VCCA
1 2 USB20_P0_C ESD@ DM2 JUSB1
<17> USB20_P0
USB3RXDN1_C 1 1 10 9 USB3RXDN1_C USB3TXDP1_C_R 9
LM3 1 SSTX+
1 2 2 2 VBUS
USB3RXDP1_C 9 8 USB3RXDP1_C USB3TXDN1_C_R 8
1 2 USB20_P0_C 3 SSTX-
EMI@ 4 4 D+
USB3TXDN1_C_R 7 7 USB3TXDN1_C_R 7
4 3 USB20_N0_C 2 GND 10
4 3 5 5 D- GND
USB3TXDP1_C_R 6 6 USB3TXDP1_C_R USB3RXDP1_C 6
SSRX+ GND
11
WCM-2012-900T_4P 4 12
1 2 USB20_N0_C 3 3 USB3RXDN1_C 5 GND GND 13
<17> USB20_N0 SSRX- GND
RS8 0_0402_5%
@EMI@ 8 ACON_TARA4-9K1311
CONN@
IP4292CZ10-TB
@EMI@
RS13 0_0402_5% 131126 reverse the JUSB2, follow haswell 14"
3 USB2.0 port x 2 <17> USB20_P1
1 2 USB20_P1_C 3
LM4
1 2 +USB_VCCB
+USB_VCCB 1 2 JUSB2
+5VALW
EMI@
US2 W=100mils 4 3 1
W=100mils 1 8 4 3 2 1
2 GND VOUT 7 WCM-2012-900T_4P 3 2
3 VIN VOUT 6 1 2 USB20_N1_C 4 3
4 VIN VOUT 5 <17> USB20_N1 5 4
RS14 @EMI@0_0402_5%
EN FLG 6 5
1 G547I2P81U_MSOP8 RS15 @EMI@0_0402_5% USB20_P1_C 7 6
1 2 USB20_P2_C USB20_N1_C 8 7
CS10 <17> USB20_P2 8
9
0.1U_0402_16V7K LM5 USB20_P2_C 10 9
2
1 2 USB20_N2_C 11 10 13
1 2 12 11 G1 14
EMI@ 12 G2
USB_ON# @RS10
@ 1
RS10 2 4 3
0_0402_5% RS9 1 @ 2 USB_OC1# 4 3
USB_OC1# <17>
0_0402_5% WCM-2012-900T_4P E-T_6916K-Q12N-00L
131126 SWAP DM4.2 & DM4.3 by layout requested 1 2 USB20_N2_C
<17> USB20_N2
RS16 0_0402_5%
4 @EMI@ 4
YSLC05CH_SOT23-3 ESD@
131203 SWAP pin of LM5 by layout requested
3 USB20_P1_C DM4 SCA00000U10
1 2 USB20_N2_C Security Classification Compal Secret Data Compal Electronics, Inc.
2 USB20_N1_C 1 2013/02/26 2015/07/08 Title
3 USB20_P2_C
DM3 SCA00000U10
USB 3.0/2.0 conn
ESD@ YSLC05CH_SOT23-3 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
B 0.1
131129 change DM3 & DM4 to pop by ESD requested
LA-A999P
A B C D E
5 4 3 2 1
UA1
+3VS +DVDD +DVDD_IO +3VS
20 1
MIC1_R DVDD +DVDD
19 9 1 @ 2 1 2
MIC1_L DVDD_IO +DVDD_IO
LA3
.1U_0402_16V7K
CA5
10U_0603_6.3V6M
CA6
.1U_0402_16V7K
CA7
10U_0603_6.3V6M
CA8
CA1 1 2 4.7U_0402_6.3V6M INT_MICR_C 18 26 RA2 SUPPRE_ KC FBMA-10-100505-101T 0402
MIC2_R AVDD1 +5VS_AVDD
INT_MIC RA3 1 2 1K_0402_5% CA4 1 2 4.7U_0402_6.3V6M INT_MICL_C 17 40 +1.5VS_AVDD 0_0603_5% 1 1 1 1 PCB Footprint = R_0402
MIC2_L AVDD2
31 41 131224: Change power rail from +1.5VS to +3VS
MIC1_VREFO_L PVDD1 +5VS_PVDD
MUTE_LED_CTR 30 46
29 MIC1_VREFO_R PVDD2 2 2 2 2
+MIC2_VREFO MIC2_VREFO
23 45 SPK_R+
24 LINE2_R SPK_OUT_R+ 44 SPK_R-
LINE2_L SPK_OUT_R-
Internal Speaker Place near Pin1 Place near Pin9

16 42 SPK_L+
D MONO_OUT SPK_OUT_L+ 43 SPK_L- D
PC_BEEP 12 SPK_OUT_L- +5VS_AVDD +5VS
PCBEEP LA4 +1.5VS_AVDD +1.5VS
+3VS 10 33 HPOUT_R RA4 1 2 75_0402_1% HP_OUTR 1 2
<14> HDA_SYNC_AUDIO SYNC HPOUT_R 32 HPOUT_L RA5 1 2 75_0402_1% HP_OUTL
Headphone FBMA-L11160808601LMA10T_2P 1 2
HPOUT_L
.1U_0402_16V7K
CA9
4.7U_0603_6.3V6K
CA10
HDA_RST_AUDIO# 11 LA5
<14> HDA_RST_AUDIO# RESET#
.1U_0402_16V7K
CA12
4.7U_0603_6.3V6K
CA13
1 2 600ohms @100MHz 1A SUPPRE_ KC FBMA-10-100505-101T 0402
2 CPVDD +3VS 1 @ 2 5 1 2 PCB Footprint = R_0402
SDATA_OUT 8 1 2 22_0402_5% HDA_SDOUT_AUDIO <14> P/N: SM01000BU00
RA6 SDATA_IN RA7
SDATA_IN HDA_SDIN0 <14>
CA17 4.7K_0402_5% CA11 1 2 10U_0603_6.3V6M ALDO_CAP 7
LDO3-CAP 6 2 1
4.7U_0603_6.3V6K BCLK HDA_BITCLK_AUDIO <14>
1 CA14 1 2 2.2U_0402_6.3V6M ACPVEE 34 2 1
CPVDD 36 CPVEE 22
CBN 35 CPVDD LINE1_L 21
1 2 2.2U_0402_6.3V6M 37 CBN LINE1_R 48
CA15 CBP
CBP SPDIFO/GPIO2
MIC_JD Place near Pin26
Place near Pin40
15 JDREF RA9 2 1 20K_0402_1% GNDA
2 JDREF 28 AVREF CA16 2 1 .1U_0402_16V7K GNDA
<30> D_MIC_DATA 3 GPIO0/DMIC_DATA VREF 27 1 2 10U_0603_6.3V6M
CA18
<30> D_MIC_CLK GPIO1/DMIC_CLK LDO1_CAP +5VS_PVDD +5VS
39 CA19 1 2 10U_0603_6.3V6M MUTE_LED <38>
LDO2_CAP LA6 600ohms @100MHz 2A
PLUG_IN# RA10 1 2 39.2K_0402_1% SENSEA 13 25 2 RA29 1 100K_0402_5% 1 2
14 SENSE_A AVSS1 38 @ FBMA-L11-201209601LMA20T_2P P/N: SM01000EE00
SENSE_B AVSS2
.1U_0402_16V7K
CA20
.1U_0402_16V7K
CA21
10U_0603_6.3V6M
CA22
10U_0603_6.3V6M
CA23
3
4 131202 Vender request GNDA 1 1 2 2
47 DVSS 49 DA8
PDB Thermal Pad
3
+1.5VS +DVDD YSLC05CH_SOT23-3
SCA00002900 Q4B
1
ALC3227-CG_MQFN48P_6X6 AVREFCA24 1 2 2.2U_0402_6.3V6M 2 2 1 1

2N7002KDW_SOT363-6
1
MUTE_LED_CTR 5
RA25
2.2K_0402_5% 1K_0402_5%
4
1
RA26 GNDA
2 2
1
<SI> QA2 change from NMOS to BJT GNDA
2
10K_0402_5%
B
RA12
E
HDA_RST_AUDIO# 3 1 PD#
2
C
C C
Part Number = SB000008E10 QA2
1
MMBT3904WH_SOT323-3
<41> EC_MUTE#
1 2 10K_0402_5% Power down (PD#) power stage for save power Internal SPK
<DB>Relace RA13/RA14/RA15/RA16 close to UA1
DA3 RA11 0V: Power down power stage
CH751H-40PT_SOD323-2 SM010008A00 JSPK1
3.3V: Power up power stage
2
SPK_R- EMI@ RA131 2 PBY160808T-300Y-N 0603 SPK_R-_CONN 1

SPK_R+ EMI@ RA141 2 PBY160808T-300Y-N 0603 SPK_R+_CONN 2 1
SPK_L- EMI@ RA151 2 PBY160808T-300Y-N 0603 SPK_L-_CONN 3 2 5
SPK_L+ EMI@ RA161 2 PBY160808T-300Y-N 0603 SPK_L+_CONN 4 3 GND 6
SM010008A00 4 GND
E-T_3703-Q04N-11R
wide 40 MIL Delete ESD Diode CONN@
220P_0402_50V7K
220P_0402_50V7K
220P_0402_50V7K
220P_0402_50V7K
1 1 1 1
@EMI@ C123
@EMI@ C124
@EMI@ C125
C126
SPK_R-_CONN SPK_L-_CONN
2 2 2 2
@EMI@
SPK_R+_CONN SPK_L+_CONN
3
DA1 @ESD@ DA2 @ESD@
SCA00002900 SCA00002900
L03ESDL5V0CC3-2_SOT23-3 L03ESDL5V0CC3-2_SOT23-3
PC Beep
1
1 2 PC_BEEP_R
EC Beep <41> EC_BEEP#
CA31 Reserve for ESD request.
.1U_0402_16V7K RA19 INT_MIC_R HP_OUTR_R HP_OUTL_R +MIC2_VREFO
B
47K_0402_5%
GNDA Jack detect B
3
SB Beep <14> HDA_SPKR
1 2 1 2 1 2 PC_BEEP Combo Mic = High
1
CA33 CA34 DA4
Normal HP = Low
1
.1U_0402_16V7K .1U_0402_16V7K YSLC05CH_SOT23-3 DA6

SCA00002900 YSLC05CH_SOT23-3 RA17
RA20 SCA00000U10 2.2K_0402_5%
10K_0402_5% ESD@
2
@ESD@ MIC_JD 1 2 INT_MIC
2
RA18
Close to Codec pin12
10U_0603_6.3V6M
CA32
22K_0402_5%
1
2
1
1
GNDA
COMBO AUDIO JACK

HPR, HPL, 15mil Keep 30mil
RA27 1 @ 2 0_0402_5% EMI@ JHP1
INT_MIC RA21 1 2 BLM15AG601SN1D_2P INT_MIC_R 3
6
RA28 1 @ 2 0_0402_5% EMI@
HP_OUTL RA22 1 2 BLM15AG601SN1D_2P HP_OUTL_R 1
1 2 EMI@ 2
CA40 @EMI@ HP_OUTR RA23 1 2 BLM15AG601SN1D_2P HP_OUTR_R 4
.1U_0402_16V7K
PLUG_IN#
5
100P_0402_50V8J
CA35
10P_0402_50V8J
CA36
10P_0402_50V8J
CA37
1 2 1 1 1
1
CA38 @EMI@
A .1U_0402_16V7K RA24 @EMI@ SINGA_2SJ-E960-001F A
@EMI@
@EMI@
22K_0402_5%
2 2 2 GNDA CONN@
1 2 Delete ESD Diode
2
CA39 @EMI@ Pin6 and Pin5

.1U_0402_16V7K Normal OPEN
1 2 GNDA GNDA GNDA GNDA
CA29 EMI@
.1U_0402_16V7K
1 2 Security Classification Compal Secret Data Compal Electronics, Inc.

CA30 EMI@ 2013/01/04 2015/01/04 Title
.1U_0402_16V7K
AUDIO ALC259-VC2-CG
C 0.1
GNDA DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-A999P
5 4 3 2 1
<41> KSI[0..7]
KSI7 Keyboard conn
KSI6
KSI5
KSI4
Touch pad conn KSI3
KSI2 CONN@ JKB1
KSI1 KSI1 1
KSI0 KSI7 2 1
KSI6 3 2
KSO9 4 3
KSI4 5 4
KSI5 6 5
<41> KSO[0..17]
KSO17 KSO0 7 6
KSO16 KSI2 8 7
KSO15 KSI3 9 8
KSO14 KSO5 10 9
ESD@ KSO13 KSO1 11 10
KSI0 C193 2 1 100P_0402_50V8J KSO12 KSI0 12 11
KSO11 KSO2 13 12
KSO10 KSO4 14 13
KSO9 KSO7 15 14
KSO8 KSO8 16 15
KSO7 KSO6 17 16
KSO6 KSO3 18 17
KSO5 KSO12 19 18
KSO4 KSO13 20 19
KSO3 KSO14 21 20
KSO2 KSO11 22 21
KSO1 KSO10 23 22
KSO0 KSO15 24 23
KSO16 25 24
KSO17 26 25
+5VS 27 26
CAP_LOCK# R203 1 2 3.3K_0402_5% 28 27
<41> CAP_LOCK#
<37> MUTE_LED MUTE_LED R207 1 2 3.3K_0402_5% 29 28
WL_WHIT 30 29
WL_AMBER 31 30 33
+5VS 32 31 G1 34
32 G2
ACES_50690-0320N-P01
+5VALW +5VALW
+3VALW
CONN@
JTP1
1
TP_CLK 2 1
<41> TP_CLK 3 2
TP_DATA
<41> TP_DATA 4 3 CAP_LOCK#
4 MUTE_LED
5
GND 6
GND
White
HB_A090420-SAHR21 1 1
1
Amber
2
CC135 CC123
DM5 R157 R158 100P_0402_50V8J 100P_0402_50V8J
3.3K_0402_5% 3.3K_0402_5% 2 2
YSLC05CH_SOT23-3 ESD@ ESD@
SCA00000U10 <1114> update footprint.
2
WL_AMBER WL_WHIT
@ESD@
2N7002KDW_SOT363-6
2N7002KDW_SOT363-6
6
3
Q20A
Q20B
1
2 5
<41> WLAN_OFF_LED# WLAN_ON_LED# <41>
4
KB/TP
B 0.1
LA-A999P
A B C D E
Powert Button Connector
1 +3VL 1
LID_SW#
White
LED10 +3VALW
1 220_0402_5% R2744
PWR_LED# 2 1 1 2
CC124 <41> PWR_LED#
JPWR1 100P_0402_50V8J
1 2 @ESD@ LTW-110DC5-C_WHITE
ESD@ 1
3
LID_SW# 2 1
<41> LID_SW#
ON/OFF# 3 2 5
remove at SI phase CS20 0.1U_0402_16V7K
<41> ON/OFF# 3 G1
4 6
4 G2 +3VL 2
E-T_6916K-Q04N-03R
White
CONN@ LED9 +3VS
R215
220_0402_5% R2743
ON/OFF# 2 1 SATA_LED# 2 1 1 2
<14> SATA_LED#
100K_0402_5% @ESD@ 1 LTW-110DC5-C_WHITE
3
remove at SI phase CS19 0.1U_0402_16V7K
<1205> update footprint. 2
2 2
<SI> Del New Lid SW conn
3 3
+FAN_POWER
40mil FAN conn +3VS

2.2U_0603_6.3V6K
1
+FAN_POWER
1
RE50
CE22 +5VS 10K_0402_5%
CE25
2 2.2U_0603_6.3V6K 40milCONN@ JFAN1
2
1 2 1
2 1
<41> FAN_SPEED1 3 2
UE3 3
1 8 1 4
2 VEN GND 7 5 GND
3 VIN GND 6 CE24 GND
4 VO GND 5 0.01U_0402_16V7K ACES_85204-0300N
<41> EN_DFAN1 VSET GND 2
APE8873M SOP 8P
4 4

PWRBTN/FAN
Document Number Rev
B 0.1
LA-A999P
A B C D E
5 4 3 2 1
ACCELEROMETER +3V_GSEN
0128 change power rail for NPCT421 co-lay
RH413 1 @ 2
+3VL +3V_GSEN
1
SLB9656@ +3VS 0_0402_5%
+3VS @ RH503
1 RH512 2 0_0402_5%
0_0402_5%
TPM1.2 +3VALW
2
@
1 RH511 2 SI# 2012.04.10 Change ACCEL_INT# to INT1
DH8
0.1U_0402_16V4Z 1 2
D 0_0402_5% +3V_GSEN ACCEL_INT# <17> D
1@ 1@ 1@ NPCT421@ ACCEL_INT#_R
C1060 C1059 C1058
@ CH751H-40PT_SOD323-2
1
0.1U_0402_16V4Z @ U25
2 2 2 C1061 * 1 9 +3V_GSEN
0.1U_0402_16V4Z 0.1U_0402_16V4Z Vdd_IO INT2 11
24
19
10
INT1
5
U70 2 EC_SMB_CK1 4 14
<41,47,48> EC_SMB_CK1 SCL/SPC VDD
EC_SMB_DA1 6
VDD
VDD
VDD
VSB
<41,47,48> EC_SMB_DA1 7 SDA/SDI/SDO 5
2 @ R208 1 8 SDO/SA0 GND 12
+3V_GSEN CS GND
LPC_AD0 26 28 short@ 10K_0402_5% 10
<14,41> LPC_AD0 LAD0 LPCPD# RES
1
LPC_AD1 23 9 BADD 1 2PLT_RST# 13 1 1
<14,41> LPC_AD1 LAD1 TESTB1/BADD RES
LPC_AD2 20 8 R1413 0_0402_5% R227 2 15 C231
<14,41> LPC_AD2 17 LAD2 TEST1 3 NC RES 16
LPC_AD3 0_0402_5% C232
<14,41> LPC_AD3 LAD3 NC RES
14 short@ 0.1U_0402_16V7K 10U_0603_6.3V6M
XTALO 13 2 2
XTALI HP3DC2TR
2
TPM
21 SLB 9656 TT 1.2 @ @ @
<17,41> CLK_PCI_LPC 22 LCLK 2
LPC_FRAME# T1406 PAD
<14,41> LPC_FRAME# LFRAME# GPIO2
1
PLT_RST# 16 6
<17,22,33,35,41,6> PLT_RST# LRESET# GPIO
SERIRQ 27 T1407 PAD R209 @
<14,41> SERIRQ 15 SERIRQ @
CLKRUN# 0_0402_5%
+3VS 1 @ 2 7 1
R1383 PP NC 3
2
4.7K_0402_5% NC 12
GND
GND
GND
GND NC
1
SLB 9656 TT 1.2

4
11
18
25
R1414
0_0402_5%
short@
2
C C
Screw Hole 131127 follow haswell 14"
H13 H14 H9 H10 H20 H19

H_5P0 H_5P0 H_5P0 H_5P0 H_3P0 H_2P8
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
@ @ @ @ @ @ FD3 FD4 FD2 FD1

1
@ @ @ @
1
H5 H22 H4 H7 H21 H8 H15 H3 H2 H1 H11 H12 H17 H23 H16 H18 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80
H_2P8 H_2P6X3P1 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_5P0 H_5P0 H_2P8 H_2P6X3P1 H_2P8 H_2P8
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
@ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @
1
B
1 B
A A

TPM/Screw hole
0.1
LA-A999P
5 4 3 2 1
5 4 3 2 1
+3VL +3VALW_EC
LK1 +3VALW_EC
15" DB SI PV MV 14" DB SI PV MV
FBMA-L11-160808-800LMT_0603 UMA UMA
0.1U_0402_16V7K
0.1U_0402_16V7K
1 2 RK57 +3VALW_EC 1 2 +EC_VCCA 12k ohm 20K ohm 0 ohm 15K ohm
33K ohm 56K ohm 27K ohm 43K ohm
2
RK13 RK13
CK2
CK3
0_0603_5% 1 1 1
RK6 DIS DIS
CK7 100K_0402_5% 160k ohm 240k ohm 330k ohm 560k ohm 130k ohm 200k ohm 270k ohm 430k ohm
RK13 RK13
ECAGND
0.1U_0402_16V7K
2 2 2
PV# 2013.01.29 Add CK4 for ESD protection
1
BOARD_ID Board ID control
+3V_EC_VDD
<DB>RK13 change to 160K ==>for 15" DIS
2
ESD@ RK12 short@
CK4
D 2 1 +3VL DIS@ <DB>RK13 change to 12K ===>for 15" UMA D
2 1 PLT_RST# RK13
0_0402_5% 240K_0402_1% UMA@
SD000001B80 RK13
1
0.1U_0402_16V7K
111
125
20K_0402_1% CH751H-40PT_SOD323-2
22
33
96
67
9
UK1 SD034200280 EC_ACIN 2 1 ACIN <16,46,47,48>
DK1
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
EC_VDD0
CK8 2 1 100P_0402_50V8J
+3VALW_EC RK15 2 1 330K_0402_5% EC_RST#
<18> GATEA20 GATEA20 1 21 GPU_HOT# <56>
1 2 EC_KBRST# 2 GATEA20/GPIO00 GPIO0F 23
<18> EC_KBRST# KBRST#/GPIO01 BEEP#/GPIO10 EC_BEEP# <37>
CK9 0.1U_0402_16V7K <14,40> SERIRQ SERIRQ 3 26 TS_GPIO_EC <30> short@ RK17
LPC_FRAME# 4 SERIRQ GPIO12 27 0_0402_5%
<14,40> LPC_FRAME# LPC_FRAME# ACOFF/GPIO13 AC_AND_CHAG <47>
LPC_AD3 5 VR_HOT# 1 2 PROCHOT# <46,6>
<14,40> LPC_AD3 LPC_AD3 <53> VR_HOT#
LPC_AD2 7 PWM Output
<14,40> LPC_AD2 LPC_AD2
LPC_AD1 8 63 B/I#
<14,40> LPC_AD1 LPC_AD1 BATT_TEMP/AD0/GPIO38 B/I# <46,47>
3
LPC_AD0 10 64 BOARD_ID
<14,40> LPC_AD0 LPC_AD0LPC & MISC AD1/GPIO39 65 ADP_I
ADP_I/AD2/GPIO3A ADP_I <46,48>
CLK_PCI_LPC 12 AD Input 66 USB_ON# USB_ON# <36>
<17,40> CLK_PCI_LPC CLK_PCI_EC AD3/GPIO3B
<17,22,33,35,40,6> PLT_RST# PLT_RST# 13 75 ADP_ID H_PROCHOT#_EC 5
PCIRST#/GPIO05 AD4/GPIO42 ADP_ID <46> <46> H_PROCHOT#_EC
EC_RST# 37 76 ENBKL
EC_SCI# 20 EC_RST# IMON/AD5/GPIO43 ENBKL <16> Q10B
<18> EC_SCI#
4
1 @ 2 PM_CLKRUN#_R 38 EC_SCII#/GPIO0E short@ 2N7002DWH_SOT363-6
<16> PM_CLKRUN# GPIO1D
<33> EC_PCIE_WAKE# RK59 1 2 0_0402_5% RK53 <PWR>
RK61 short@ 0_0402_5% 68 PCH_VREG_EN#_R 1 2 0_0201_5% <1120>Combine with Q10.
+3VALW_EC DAC_BRIG/GPIO3C 70 PCH_VREG_EN# <20>
<38> KSI[0..7] DA Output EN_DFAN1/GPIO3D EN_DFAN1 <39>
KSI0 55 71
KSI0/GPIO30 IREF/GPIO3E DGPU_HOLD_RST# <17,22>
KSI1 56 72 DRAMRST_CNTRL_PCH <10,15,7>
+3VS KSI2 57 KSI1/GPIO31 CHGVADJ/GPIO3F
KSI2/GPIO32
<1118> Remove SYS_PWROK.
KSI3 58 83
KSI3/GPIO33 EC_MUTE#/GPIO4A EC_MUTE# <37> +3VALW_EC
RP7 1 8 EC_SMB_CK1 KSI4 59 84 PM_SLP_S4# PM_SLP_S4# <16>
C
2 7 EC_SMB_DA1 KSI5 60 KSI4/GPIO34 USB_EN#/GPIO4B 85 WLAN_OFF_LED# C
KSI5/GPIO35 CAP_INT#/GPIO4C WLAN_OFF_LED# <38>
3 6 EC_SMB_CK2 KSI6 61 PS2 Interface 86
KSI6/GPIO36 EAPD/GPIO4D SLP_A# <16>
4 5 EC_SMB_DA2 KSI7 62 87 TP_CLK
<38> KSO[0..17] KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK <38>
KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <38>
KSO1 40
2.2K_0804_8P4R_5% KSO2 41 KSO1/GPIO21
KSO3 42 KSO2/GPIO22 97 EC_PME# EC_FB_CLAMP_TGL_REQ# RK60 1 DIS@ 2 10K_0402_5%
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 EC_PME# <18,35>
KSO4 43 98
KSO4/GPIO24 WOL_EN/GPXIOA01 WL_PWREN_EC <34>
KSO5 44 99 HDA_SDO
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VCIN0_PH
HDA_SDO <14>
KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 VCIN0_PH <46>
KSO7 46 SPI Device Interface
KSO8 47 KSO7/GPIO27 <SI> Update Pin119 and Pin120 net name
KSO9 48 KSO8/GPIO28 119 EC_SPI_SO
KSO9/GPIO29 SPIDI/GPIO5B EC_SPI_SO <14>
KSO10 49 120 EC_SPI_SI +3VALW
KSO10/GPIO2A SPIDO/GPIO5C EC_SPI_SI <14>
KSO11 50 SPI Flash ROM 126 EC_SPI_CLK
KSO11/GPIO2B SPICLK/GPIO58 EC_SPI_CLK <14>
KSO12 51 128 EC_SPI_CS# TP_CLK RK2 1 2 4.7K_0402_5%
KSO12/GPIO2C SPICS#/GPIO5A EC_SPI_CS# <14>
KSO13 52
KSO14 53 KSO13/GPIO2D TP_DATA RK4 1 2 4.7K_0402_5%
KSO15 54 KSO14/GPIO2E 73
KSO15/GPIO2F ENBKL/AD6/GPIO40 TOUCH_ON# <30>
KSO16 81 74 EC_FB_CLAMP_TGL_REQ# EC_FB_CLAMP_TGL_REQ# <18>
@ KSO17 82 KSO16/GPIO48 PECI_KB930/AD7/GPIO41 89 AOAC_PME#
KSO17/GPIO49 FSTCHG/GPIO50 AOAC_PME# <16,17>
+3VS RK36 1 2 10K_0402_5% EC_SCI# 90
BATT_CHG_LED#/GPIO52 BAT_CHG_LED <46>
91 CAP_LOCK#
CAPS_LED#/GPIO53 CAP_LOCK# <38>
EC_SMB_CK1 77 GPIO 92 PWR_LED#
<40,47,48> EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 PWR_LED# <39>
EC_SMB_DA1 78 93
<40,47,48> EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 WLAN_ON_LED# <38>
EC_SMB_CK2 RK39 1 short@ 2 0_0402_5% EC_SMB_CK2_R 79 SM Bus 95 SYSON
<15,22> EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON <43,50> +3VL
EC_SMB_DA2 RK40 1 2 0_0402_5% EC_SMB_DA2_R 80 121 VR_ON
<15,22> EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 VR_ON <53>
short@ 127 PCH_DPWROK
PM_SLP_S4#/GPIO59 PCH_DPWROK <16>
100P_0402_50V8J
CK10 RP8
<16> PM_SLP_S3# PM_SLP_S3# 6 100 PCH_RSMRST# 2 1 ECAGND PCH_PWR_EN 8 1
PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 PCH_RSMRST# <16>
<16> PM_SLP_S5# PM_SLP_S5# 14 101 PLT_RST# 7 2
PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# <18>
B <16> SUSACK# SUSACK# 15 102 VCIN1_PH VCIN1_PH <46> EC_ON 6 3 B
16 EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 103 H_PROCHOT#_EC EC_ACIN 5 4
<33> MINI1_LED# GPIO0A H_PROCHOT#_EC/GPXIOA06
PCH_SUSWARN# 17 104 MAINPWON
<16> PCH_SUSWARN# GPIO0B VCOUT0_PH/GPXIOA07 MAINPWON <49>
18 GPO 105 EC_BKOFF# EC_BKOFF# <30> 100K_0804_8P4R_5%
<18> SLP_ME_CSW_DEV# GPIO0C BKOFF#/GPXIOA08
CPU1.5V_S3_GATE 19 GPIO 106 PBTN_OUT# PBTN_OUT# <16>
<10> CPU1.5V_S3_GATE GPIO0D PBTN_OUT#/GPXIOA09
25 107 PCH_PWR_EN
<30> EC_INVT_PWM EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 PCH_PWR_EN <43>
FAN_SPEED1 28 108 SA_PGOOD SA_PGOOD <52> RK51
<39> FAN_SPEED1 PM_SLP_SUS# 29 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 VR_ON 1 2
<16> PM_SLP_SUS# EC_PME#/GPIO15
E51TXD_P80DATA 30 100K_0402_5%
<33> E51TXD_P80DATA EC_TX/GPIO16
E51RXD_P80CLK 31 110 EC_ACIN
<33> E51RXD_P80CLK EC_RX/GPIO17 AC_IN/GPXIOD01
PCH_PWROK 32 112 EC_ON
<16> PCH_PWROK
AC_LED# 34 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 114 ON/OFF#
EC_ON <49> <1112> Add it.
<46> AC_LED# SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 ON/OFF# <39>
36 GPI 115 LID_SW# LID_SW# <39>
<17,25,56> DGPU_PWR_EN NUM_LED#/GPIO1A LID_SW#/GPXIOD04 116 SUSP#
SUSP#/GPXIOD05 SUSP# <10,43,50,51,52,55,58>
117 NMI_DBG#
GPXIOD06 118 EC_PECI RK34 1 2
PECI_KB9012/GPXIOD07 H_PECI <18,6>
122
AGND/AGND
<22> GPU_THERMAL_DET# GPU_THERMAL_DET# 43_0402_1%

BT_ON_EC 123 XCLKI/GPIO5D 124 +V18R +3VALW_EC
GND/GND
GND/GND
GND/GND
GND/GND
<33> BT_ON_EC XCLKO/GPIO5E V18R

1
GND0
CK17
LID_SW# RK44 2 1 47K_0402_5%
4.7U_0603_6.3V6K
KB9012QF-A3_LQFP128_14X14 2
11
24
35
94
113
69
Part Number = SA00004OB30 20mil
LK2
ECAGND 2 1
FBMA-L11-160808-800LMT_0603
@ RK49 100K_0402_5% +3VALW_EC

1 2 PCH_DPWROK ECAGND <46>
@ RK50 100K_0402_5%
1
A A
1 2 PCH_PWROK
RK18
10K_0402_5%
2
NMI_DBG# 1 2
DK2
NMI_DBG#_CPU <18> Security Classification Compal Secret Data Compal Electronics, Inc.
CH751H-40PT_SOD323-2
EC ENE-KB9012
Custom 0.1
LA-A999P
5 4 3 2 1
5 4 3 2 1
D D
C C
Green CLK no reserved.
B B
A
BOM control A
Platform Silego P/N Compal PN 25MHz(A) 32.768KHz 25MHz(B) 27MHz 8MHz Remark
Intel CRV UMA SLG3NB244VTR SA000063300 1 1 1 X X GCLKUMA@

2013/06/10 2014/07/01 Title
Intel CRV Dis SLG3NB304VTR SA000057I00 1 1 1 1 X GCLKDIS@ Issued Date Deciphered Date
GCLK
0.1
Base on A32 32.768KHz use 10ppm, G-CLK 25MHz X'TAL use 10ppm. DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-A999P
5 4 3 2 1
A B C D E
+5VS_IN
J4 @
2 1
+5VS
+1.5V to +1.5VS
2 1
10U_0603_6.3V6M
22U_0805_6.3V6M
JUMP_43X118 1 1
C575
CC56
+3VALW +5VALW
2 2 @
<1111> Remove +1.5VS DCDC.
Q21
1 14
2 VIN1 VOUT1 13
+5VALW VIN1 VOUT1
SUSP# 3 12 C554 1 2 100P_0402_50V8J
1
ON1 CT1 1
4 11
VBIAS GND
SUSP# 5 10 C557 1 2 680P_0402_50V7K
ON2 CT2
6 9
7 VIN2 VOUT2 8 +3VS_IN
VIN2 VOUT2
15 J5 @
GPAD 2 1
2 1 +3VS
TPS22966DPUR_SON14_2X3-D
JUMP_43X118 1
10U_0603_6.3V6M
C570
2
<1111> 5V / 3V ?? pull high voltage +3VALW +3V_PCH

Q30
2 AO3413L_SOT23-3 2
+5VALW 3 1
D
40mils
G
2
2
R559 1
100K_0402_5% C590
1U_0402_6.3V6K
1
2
<20> PCH_PWR_EN# PCH_PWR_EN# SYSON# SUSP
SUSP <6>
3
Q18A Q18B
3
SYSON 2 5 SUSP#
0.1U_0402_16V7K
<41,50> SYSON SUSP# <10,41,50,51,52,55,58>
1
<41> PCH_PWR_EN PCH_PWR_EN 5
4
C591
@
Q17B
4
DMN66D0LDW-7_SOT363-6 2
+5VALW
3 RPH16 3
SYSON 8 1
SUSP 7 2
SYSON# 6 3
SUSP# 5 4
AO4430L 100K_0804_8P4R_5%
VGS Max=+/- 20V
VGS(Th) max=2.5V
Rds Max=5.5m @VGS=10V

Rds Max=7.5m @VGS=4.5V
+0.675VS +1.8VS +VCCP +1.35V
2
R182 R183 R184 @ R185
22_0603_5% 470_0603_5% 470_0603_5% 470_0603_5%
6 2
3 1
6 1
6 1
@
2 SUSP 5 SUSP 2 SUSP 2 SYSON#
Q15A Q15B Q17A Q113A

1
1
DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
4 4
AO4430L
VGS Max=+/- 20V Security Classification Compal Secret Data Compal Electronics, Inc.
VGS(Th) max=2.5V Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title
Rds Max=5.5m @VGS=10V THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
Rds Max=7.5m @VGS=4.5V Custom 0.1
LA-A999P
A B C D E
5 4 3 2 1
NGFF and WLAN
D D
+3VS +3VS_W LAN
2
@
RL25
100K_0402_5%
2
G
1
PCH_PCIE_W AKE# 1 3 MC_W AKE# MC_W AKE# <33>
<16> PCH_PCIE_W AKE#
S
@
QB8
2N7002H_SOT23-3
PV# 2013.01.23 Add QB8 abd RL25 to support OBFF

PV# 2013.02.22 Unpop QB4 and RL23 for not support OBFF
C C
B B
A A

Issued Date Title
Deciphered Date
WAKE and RST-1
Custom 0.1
LA-A999P
5 4 3 2 1
A B C D E
+V3P3S
+3VALW_EC
RP7 PU101
2.2K Charger IC
BQ24738
1
EC SM Bus1 address EC_SMB_CK1
1
EC_SMB_DA1
PJPB1 U25
Smart Battery G-sensor
HP3DC2TR
ENE +3V_PCH +3VS

KBC9012
+3VS +3V_PCH
RP24 RP23
2.2K 2.2K
RP7 RP24
2.2K 2.2K
level shift PCH_SMBCLK
2
SMBCLK PCH_SMBDATA
2
SML1CLK SMBDATA
EC SM Bus2 address EC_SMB_CK2 level shift SML1CLK
EC_SMB_DA2 SML1DATA SML1DATA
+3V_PCH JDIMM1
JDIMM2
+3VGS Intel
PCH
Panther Point RP24
RV21 2.2K
RV22
SML0CLK
2.2K
SML0DATA
NVIDIA N15V-GM (GB2-64) I2CS_SCL I2CS_SCL level shift

595 ball BGA 23x23mm I2CS_SDA I2CS_SDA
3 I2CC_SCL RV16 2.2K 3
I2CC_SDA
I2CB_SCL RV16 2.2K

I2CB_SDA
RV21
I2CA_SCL RV22 2.2K
I2CA_SDA
4 4

I2C Mapping
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-A999P
A B C D E
5 4 3 2 1
PL1 EMI@ VIN

ADPIN HCB2012KF-121T50_0805
1 2
PL2 EMI@
HCB2012KF-121T50_0805
1 2 @ PR2
0_0402_5%
@ PJP1 1 2 ACIN_LED
1000P_0402_50V7K
1000P_0402_50V7K
<41> AC_LED#
ACES_59012-0080N-002
100P_0402_50V8J
100P_0402_50V8J
2 1
2 1
1
EMI@ PC1
EMI@ PC2
EMI@ PC3
EMI@ PC4
D D
4 3
4 3 PR3
2
6 5 ADP_SIGNAL 100K_0402_5%
6 5
2
Charge_LED 8 7 ACIN_LED
8 7
PR1
10K_0402_5% PR5
ADP_SIGNAL 1 2 2K_0402_5%
ADP_ID <41> 1 2 Charge_LED
<41> BAT_CHG_LED
3
1
100P_0402_50V8J
1000P_0402_50V7K
1
GLZ3.6B_LL34-2
1
PR8
10K_0402_5%
PR7
@ PD3
@ PC5
PC6
100K_0402_5%
2
2
2
ESD@ PD1 ESD@ PD2
1
L30ESD24VC3-2_SOT23-3 L30ESD24VC3-2_SOT23-3
+3VL
+5VS
C +3VALW C
CD4148WN-1_1206-2
1
10K_0402_1%
47K_0402_1%
1
1
<41,6> PROCHOT# PR10 @ @ @
PR32
PR31
PD8
47K_0402_1% PR11 @
PROCHOT# 27,35
6
PU1A 10K_0402_1%
2
4
PQ2A @ PC8 LM393DR_SO8
2
L2N7002DW 1T1G_SC88-6 0.022U_0402_16V7K 2 @
2
2 1 2 1 - PR4 @
O
3
S
3 0_0402_5%
100P_0402_50V8J
+
1
1
P
ACIN
G
1 2 1 2 2 PQ5 @
1
PC9
PR12 @ 27,33,35,9 LBSS84LT1G_SOT23-3
PD4 @ PR13 @ 8 100K_0402_1% PC17 @ D
1
CD4148W N-1_1206-2 1.5M_0402_5% @ 0.022U_0402_16V7K
2
2
B/I# <41,47>
+5VS
ADP_I <41,48>
+3VALW +3VALW _EC

1
1
B B
PR17 PR26
47K_0402_1% PU1B PR18 PR25 5.9K_0402_1%
3
LM393DR_SO8 10K_0402_1% 10K_0402_1%

2
PQ2B PC12
2
2
L2N7002DW 1T1G_SC88-6 0.022U_0402_16V7K 5
P
5 1 2 7 + VCIN0_PH <41> VCIN1_PH <41>
0.1U_0402_16V7K
0.1U_0402_16V7K
O
1
1
6
100P_0402_50V8J
-
G
1
1
@ PC15
@ PC16
4
PR21 PH1 PR27 @ PR28

PC13
4
PD5 PR20 100K_0402_1% 100K_0402_1%_NCP15W F104F03RC 10K_0402_1% 10K_0402_1%

2
2
CD4148W N-1_1206-2 1.5M_0402_5%
2
2
ECAGND <41> H_PROCHOT#_EC <41>
2
ACIN <16,41,47,48>
A A

PWR-DC Conn
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-A998P 0.2
5 4 3 2 1
5 4 3 2 1
@ PJPB2
1 2
1 2
EMI@ PL3 JUMP_43X118
D HCB2012KF-121T50_0805 D
BATT++ 1 2 BATT+ BATT
PQ1 @
EMI@ PL4 SI4483ADY-T1-GE3_SO8
@ PJPB1 HCB2012KF-121T50_0805 1 8
1 1 2 2 7
1 2 3 6
2 3 5
3
1
4 EMI@ PC10 EMI@ PC11 @ PR14
4 5 1000P_0402_50V7K 0.01U_0402_25V7K 470K_0402_5%
4
5 6 1 2
2
6 7
7
1
8
8 9 PR15 @ PR16 @
GND 10
GND 470K_0402_5% 4.7K_0402_5%
PR19
OCTEK_BTJ-08FUAB 100_0402_5%
6 2
1 2
EC_SMB_DA1 <40,41,48>
PR22 PQ3A @
100_0402_5% L2N7002DW 1T1G_SC88-6
1 2 2
EC_SMB_CK1 <40,41,48>
1
100_0402_5%
+3VL
1
PR30
1
2
PR29 PR23 @
100K_0402_5% 220K_0402_5%
3
C 1 2 C
+3VL +3VL
2
B/I# <41,46>
5
3
1
PQ3B @
L2N7002DW 1T1G_SC88-6 PR24 @
6
220K_0402_5%
PQ4A @
L2N7002DW 1T1G_SC88-6
2
2
3
1
1
ESD@ PD6 ESD@ PD7
1
L30ESD24VC3-2_SOT23-3 L30ESD24VC3-2_SOT23-3 PC14 @

100P_0402_50V8J 5
ACIN <16,41,46,48>
2
PQ4B @
L2N7002DW 1T1G_SC88-6
4
AC_AND_CHAG <41>
Need to define "AC_AND_CHAG" signal with EC
B B
A A

PWR-BATT Conn
5 4 3 2 1
A B C D
1
D
2 PQ102
G 2N7002KW_SOT323-3
S
3
PR101 PR102
1 2 1 2
1M_0402_5% 3M_0402_5%
1 1
VIN P1 P2 B+
PQ101 PQ103 PR103 EMI@ PL101 PQ104
AON6414AL_DFN8-5 AON7506_DFN33-8-5 0.01_1206_1% 1.2UH_NRS4018T1R2NDGJ_2.6A_30% AON7506_DFN33-8-5
1 1 1 4 1 2 1
2 2 2
2200P_0402_50V7K
5 3 3 5 2 3 5 3
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
@EMI@ PC123
PC104
PC105
1
1
2200P_0402_50V7K
0.01U_0402_50V7K
1
1
VIN
PC101
PC102
4
PC107
2
2
1 2
2
2
3
2
PC106
0.1U_0402_25V6 PR104
ACDRV1_CHG 4.12K_0603_1%
0.1U_0402_25V6
PD101 BATDRV_CHG 1 2 BATDRV1_CHG
0.1U_0402_25V6
PC109
BAS40CW_SOT323-3
1
PC108
PC110
0.047U_0402_25V7K
2
1 2
5
10_1206_1%
PR105
1
2.2_0603_5%
PR106
PD102
RB751V-40_SOD323-2 @ PR107 PQ105
0_0603_5% AON7408L_DFN8-5
2
PC111 DH_CHG 1 2 4
2
1U_0603_25V6K
1 2
4.12K_0603_1%
4.12K_0603_1%
REGN_CHG
1
2 BATT 2
VCC_CHG
BST_CHG
PR108
PR109
DH_CHG
PC112 PL102
LX_CHG
3
2
1
1U_0603_25V6K 4.7UH_ETQP3W4R7WFN_5.5A_20% PR110
1 2 0.01_1206_1%
LX_CHG 1 2 CHG 1 4
2
@EMI@ PR111
2 3
4.7_1206_5%
20
19
18
17
16
PU101
CSON1
CSOP1
PQ106
RB551V-30_SOD323-2
BTST
PHASE
HIDRV
VCC
REGN
10U_0805_25V6K
10U_0805_25V6K
21 AON7506_DFN33-8-5
PAD
0.1U_0402_25V6
0.1U_0402_25V6
PC114
PC115
1 SNB_CHG 2
1
PD103
ACN_CHG 1 15 DL_CHG 4
ACN LODRV
PC113
PC116
1
2
2 14
680P_0603_50V8J
ACP_CHG PR112
2
ACP GND
@EMI@ PC117
0_0603_1%
3
2
1
2
BQ24738RGRR_QFN20_3P5X3P5 1 2 CSOP1
CMSRC_CHG 3 13 SRP_CHG
CMSRC SRP
2
PR113 PC118
ACDRV_CHG 4 12 SRN_CHG 0_0603_5% 0.1U_0603_16V7K
2
PR114 ACDRV SRN 1 2 CSON1
10K_0402_1%
1 2 5 11 BATDRV_CHG
+3VL ACPRES ACDET BATDRV
IOUT
SDA
SCL
ILIM
<16,41,46,47> ACIN
6
10
ACDET_CHG
IOUT_CHG
ILIM_CHG
3 3
PR115
357K_0402_1% +3VL
VIN 1 2
0.01U_0402_25V7K
100K_0402_1%
1
422K_0402_1%
PR116
PC119
1
1
PR117
2
2
2
Vin Dectector
EC_SMB_CK1 <40,41,47>
Min. Typ Max.
0.1U_0402_25V6
66.5K_0402_1%
1
H-->L 17.23V
PC120
PR118
1
EC_SMB_DA1 <40,41,47>
L-->H 17.63V
@ PR119
2
0_0402_5%
2
1 2
ILIM and external DPM ADP_I <41,46>
1
3.61A PC121 @ PC122

100P_0402_50V8J 0.1U_0402_10V7K
2
4
locate the RC Near EC chip 4

PWR-CHARGER
Custom 0.2
LA-A998P
Date: Sheet 48 of 58
A B C D
A B C D
PR302
165K_0402_1%
1 2
PR303
56K_0402_1%
1
1 2 1
PR304
@ PC302 143K_0402_1%
100P_0402_50V8J 1 2
1 2
PR301 PR305
14K_0402_1% 30K_0402_1%
1 2 1 2
B+ 3/5V_B+ 3/5V_B+
EMI@ PL301
HCB2012KF-121T50_0805
1 2 +3VALW PR306 PR307
2200P_0402_50V7K
20K_0402_1% 19.1K_0402_1%
ENTRIP_3V
ENTRIP_5V
1 2 1 2
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
1
TON_35V
@EMI@ PC318
PC303
PC307
1
1
PC304
PC308
FB_3V
FB_5V
PR318
10K_0402_1%
FB=2V
FB=2V
2
2
2
<16> SPOK
5
PQ301
FB2
ENTRIP2
ENTRIP1
FB1
TON
AON7408L_DFN8-5 21
PC305 PR309 6 PAD
0.1U_0402_10V7K 2.2_0402_1% PGOOD 20 PR310 PC306
4 1 2 BST1_3V 1 2 BYP1 2.2_0402_1% 0.1U_0402_10V7K
BST_3V 7 1 2 BST1_5V 1 2 4
BOOT2 19 BST_5V
2 BOOT1 PQ303 2
DH_3V 8 AON7408L_DFN8-5
1
2
3
PL303 UGATE2 18 DH_5V
3
2
1
UGATE1
Vo=3.4V 3.3UH_PCMB063T-3R3MS_6.5A_20% PL302
1 2 LX_3V 9 2.2UH_ETQP3W2R2WFN_8.5A_20% Vo=5.14V
+3VALWP PHASE2 17 LX_5V 1 2
PHASE1 +5VALWP
1
@EMI@ PR311
4.7_1206_5%
@EMI@ PR312
LG_3V 10
4.7_1206_5%
LGATE2
5
16 LG_5V
ENLDO
LGATE1
5
LDO5
LDO3
220U_C6_6.3V_M_R15
ENM
VIN
SNUB_3V 2
+
PC316
220U_C6_6.3V_M_R15
AON7506_DFN33-8-5
1
SNUB_5V 2
PU301
11
12
13
14
15
4 +
PC317
RT8243AZQW_WQFN20_3X3
2
PQ304
4
+5VLP
+3VLP
680P_0603_50V8J
PQ302
2
@EMI@ PC311
680P_0603_50V8J
AON7506_DFN33-8-5 PR313
1
+3VLP
@EMI@ PC312
499K_0402_1%
1
2
3
1
1 2 @ PJ301
3/5V_B+
3
2
1
JUMP_43X39
2
100K_0402_1%
1 2
1U_0603_10V6K
0.1U_0603_25V7K
+3VL
2
1 2
1
PC313
PR314
PC314
1
1
(100mA,40mils ,Via NO.= 2)
1
PC310
2
4.7U_0603_10V6K
2
PR315
2.2K_0402_1%
3
1 2 3
<41> EC_ON
@ PR316 @ PJ304
0_0402_5% JUMP_43X39
1 2 1 2
+VL
<41> MAINPWON 1 2
4.7U_0603_6.3V6K
(100mA,40mils ,Via NO.= 2)
1
@ PC315
1
1
@ PR317 PC309
100K_0402_5% 4.7U_0603_10V6K
2
2
2
@ PJ302
1 2
+3VALWP 1 2 +3VALW
JUMP_43X118
@ PJ303
1 2
+5VALWP 1 2 +5VALW
JUMP_43X118
4 4

PWR-3VALW/5VALW
Custom 0.2
LA-A998P
Date: Sheet 49 of 58
A B C D
5 4 3 2 1
EMI@
PLM1
HCB2012KF-121T50_0805 PCM2 PRM1
B+ 1 2 B+_DDR 0.22U_0402_10V6K 2.2_0402_1%
1 2 BST_DDR-1 1 2
D D
1
@EMI@
PCM13 PCM1 PCM3
2200P_0402_50V7K 4.7U_0805_25V6-K 4.7U_0805_25V6-K +1.35V_VDDQP
2
+0.6V_0.675VSP
BST_DDR
DH_DDR
LX_DDR
10U_0805_6.3V6K
10U_0805_6.3V6K
4
1
PCM4
PCM5
PQM1
AON7408L_DFN8-5
16
17
18
19
20
2
1
2
3
VLDOIN
PHASE
UGATE
BOOT
VTT
21
PAD
PLM2 DL_DDR 15 1
+1.35V_VDDQP 1.5UH_PCMC063T-1R5MN_9A_20% LGATE VTTGND
1 2
14 2
PGND VTTSNS
5
PRM3
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
@EMI@ 13.3K_0402_1%
1
1 2 13 3
PCM16
PCM17
PCM18
PCM19
PCM20
PCM21 PRM2 PQM2 CS_DDR PUM1

4.7_1206_5% AON7506_DFN33-8-5 CS RT8207PGQW _W QFN20_3X3 GND
2
2
4 12 4 VTTREF_DDRT
C PRM4 +5VALW VDDP VTTREF C
1SNB_DDR
5.1_0603_5%
1 2 VDD_DDR 11 5 +1.35V_VDDQP
+5VALW VDD VDDQ
PGOOD
1
2
3
1
TON
@EMI@ PCM8 PCM9 PCM10
FB
S5
S3
PCM7 1U_0603_10V6K 1U_0603_10V6K 0.033U_0402_16V7K
2
680P_0603_50V7K
FB=0.75V
2
10
6
FB_DDR
S5_DDR
S3_DDR
TON_DDR
PRM5
8.06K_0402_1%
1 2 +1.35V_VDDQP
Vo=1.3545V
1
PRM8
10K_0402_1%
2
PRM6
432K_0402_1%
B+_DDR 1 2
@ PRM9
B 0_0402_5% B
@ PJPM2 1 2
<41,43> SYSON
1 2
+1.35V_VDDQP 1 2 +1.35V
JUMP_43X118 @ PRM11
0_0402_5%
1 2
<10,41,43,51,52,55,58> SUSP#
@ PJPM1
JUMP_43X39
1
1 2
+0.6V_0.675VSP 1 2
+0.675VS @ PCM11 @ PCM12
0.1U_0402_10V7K 0.1U_0402_10V7K
2
A A

Title
PWR-1.35V/0.675VS
Custom 0.2
LA-A998P
5 4 3 2 1
5 4 3 2 1
EN pin don't floating

@ PRH1 If have pull down resistor at HW side, pls delete PR2
0_0402_5%
1 2
SUSP# <10,41,43,50,52,55,58>
D D
1
PRH2 @ PCH1
1M_0402_1% 0.22U_0402_10V6K
continuous 6A
2
2
peak 12A
@EMI@ @EMI@
PRH3 PCH2
EMI@ 4.7_1206_5% 680P_0603_50V7K
PLH1 PUH1 1 2 SNB_1.05V 1 2
HCB2012KF-121T50_0805 SY8206DQNC_QFN10_3X3
+1.05VSP +VCCP
B+ 1 2 B+_1.05V 8
IN EN
1 @ PRH4
0_0603_5%
PCH3
0.1U_0603_25V7K
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
PRH10 6 BST_1.05V 1 2 1
BST_1.05Vn 2 PLH2 @ PJH1
EMI@ PCH4
BS
1
1
10_0402_1% 1UH_PCMB063T-1R0MS_12A_20% Vo=1.05V JUMP_43X118
1 2 9 10 LX_1.05V 1 2 1 2
PCH6
PCH5
GND LX 1 2
2
330P_0402_50V7K
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
FB=0.6V
10_0402_1%
1
1
4 FB_1.05V
PCH8
PCH9
PRH11
PCH10
PCH11
FB
PCH7
ILMT_1.05V 3 7
PGND <9> VSS_SENSE_VCCIO +3VALW
2
ILMT BYP
4.7U_0603_6.3V6K
2
2 5 LDO_3V
put together
4.7U_0603_6.3V6K
PG LDO
PCH13
1
1 2
PCH12
C C
2
PRH5
1
PRH6 100K_0402_1%
10K_0402_5%
+3VS 1 2 PRH7
133K_0402_1%
@ PRH12
0_0402_5%
1 2
2
Pin 7 BYP is for CS. VCCIO_SENSE <9>
Common NB can delete +3VALW and PCH13
<52> VCCP_PWRGOOD
+3VALW
1
@ PRH8
0_0402_5%
2
ILMT_1.05V
1
B B
PRH9 @0@
0_0402_5%
2
The current limit is set to 6A, 9A or 12A when this pin

is pull low, floating or pull high
A A

Title
PWR-1.05VS_VCCP
Custom 0.2
LA-A998P
5 4 3 2 1
5 4 3 2 1
VID [0] VID[1] VCCSA Vout

0 0 0.9V
D D
0 1 0.85V
1 0 0.775V
1 1 0.75V
SY8037DDCC support CRV ULV VID table
1
EMI@ PCA9
680P_0603_50V7K
2 SNUB_+VCCSA
+VCCSAP (ULV)
TDC 3A
Peak Current 4A
2
EMI@ PRA1 OCP current 8A
4.7_1206_5%
1
EMI@ PLA1 PUA1 PLA2
HCB1608KF-121T30_0603 SY8037DDCC_DFN12_3x3 0.47UH_PCMB063T-R47MS_18A_20%
+3VALW 1 2 +VCCSA_PWR_SRC 12
PVIN LX
1 +VCCSA_PHASE 1 2 +VCCSAP
11 2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PCA3 PVIN LX
68P_0402_50V8J 10 3 PRA2 SA_PGOOD <41>
22U_0603_6.3V6M
22U_0603_6.3V6M
SVIN LX
1
100K_0402_5%
PCA5
PCA6
PCA7
PCA8
2200P_0402_50V7K
C 2
+VCCSAP_FB 1 9 4 2 1 C
2 FB PG +3VS
1
PCA1
PCA2
@EMI@ PCA10
2
8 5 +VCCSA_EN 1 2
VOUT EN
GND
2
2
1 7 6 @ PRA3
VID1 VID0 0_0402_5%
0.1U_0402_10V7K
13
PRA6
1
100_0402_5%
@ PCA4
2
2
<51> VCCP_PWRGOOD 2 1
1K_0402_5%
1K_0402_5%
PRA4
PRA5
2
@ PRA7
0_0402_5%
1
1 2
VCCSA_SENSE <10>
VCCSA_VID0 <10>
VCCSA_VID1 <10>
@ PJ305
1 2
+VCCSAP 1 2 +VCCSA
JUMP_43X118
The 1k PD on the VCCSA VIDs are empty.

These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.
B B
PU1801
EMI@ PL1801 4 5 PL1802

PGND NC
HCB1608KF-121T30_0603 2.2UH_MMD-04BZ-2R2M-X2_3A_20% Vo=1.8V
+3VALW 1 2 1.8V_B+ 3 6 1 2
IN LX +1.8VSP
22U_0603_6.3V6M
22U_0603_6.3V6M
2200P_0402_50V7K
2 7 1
22P_0402_50V8J
PG EN PR1804 Ipeak=1.308A
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
1 8 20K_0402_1%
@EMI@ PC1810
PC1801
PC1802
PC1809
PC1803
PC1806
FB=0.6V FB SGND 9 ILIM = 4A
PGND
F=1MHz
2
2
SY8003DFC_DFN8_2X2
1
4.7_1206_5%
1
@ PR1801 PR1805
@EMI@ PC1807 @EMI@ PR1802
0_0402_5% 10K_0402_1%
1 2 EN_1.8V
<10,41,43,50,51,55,58> SUSP#
2
2
1
@ PJ1801
1
PR1803 JUMP_43X79
@ PC1808 1M_0402_5% +1.8VSP 1 2 +1.8VS
680P_0402_50V7K
1 2
1
0.1U_0402_16V7K
2
A A
2

Title
PWR-VCCSAP/1.8VSP
C 0.2
LA-A998P
5 4 3 2 1
A B C D E
1
@ PCG9
1000P_0402_50V7K
VCC_AXG_SENSE
Layout Note
2
Reduce Acoustic Noise
1
PCG10
1. The AL bulk capacitor of B+ should be very
0.01UF_0402_25V7K close to CPU_CORE MOSFET.
2
VSS_AXG_SENSE 2. Input ceramic caps must place on symmetry +CPU_B+
same location on top side and bottom side.
PCG8
10U_0805_25V6K
10U_0805_25V6K
1 6800P_0402_25V7K 1
2200P_0402_50V7K
EMI@PCZ19
PCZ19
1 2
1
PCG1
PCG2
2K_0402_1%
1
EMI@
PCG11 PCG12
2
120P_0402_50V8J
470P_0402_50V7K
PRG7
1 2 1 2 1 2
Close GFX choke PRG11 PQG1 OCP setting=39.9~44.99A
PRG8 PCG13 499_0402_1% AON6932A_DFN5X6-8-7
2
PHG2 453_0402_1% 1000P_0402_50V8-J 3 0.22uH DCR= 0.97+-5% m ohm, Idc~Isat= 25~34A
VSUMG- 10K_0402_1%_ERTJ0EG103FA 1 2 1 2 1 2 1 2 @PRG1
@ PRG1 2 S2
PRG12 PRG13 0_0603_5% D1 4
Design Note S2
1
137K_0402_1% 2.55K_0402_1% UGA_GFX 1 2 UGA_GFX-1 1 PLG1 +VGFX_CORE
This circuit is for ULV 1+1 17W. G1 5 0.22UH_PCME064T-R22MS_28A_20%
S2
13K_0402_1%
.1U_0402_16V7K
CPU: IccMax=33A, TDC=16A(TDP NOM) PRG15 PHASEA_GFX 7 PHASEA_GFX 1 2
S1/D2
1
11K_0402_1%
PCG5
PRG14
0.033U_0402_25V7K
2K_0402_1% 6
0.1U_0402_25V6
G2
1
Loadline: -2.9 m V/A PCG3
1 2
1 2
1
1
5.1K_0402_1%
PCG7
0.1U_0603_25V7K
PRG10
PCG6
Output Cap. follow Intel PDDG
1
1
BOOTA_GFX 2 1 2
330uF/9m*1, 560uF/4.5m*1 22uF_0603*12, 2.2uF_0402*16 PCG14 PRG2
PRG9
+3VS
2
470P_0402_50V7K 2.2_0603_5% @EMI@ PRG3 PRG4
GFX(GT2): IccMax=33A, TDC=21.5A
2
LGA_GFX 4.7_1206_5% 3.65K_0603_1%
Loadline: -3.9 m V/A
1.91K_0402_1%
2
1 2
2
1
VSUMG+
Output Cap. follow Intel PDDG
560uF/4.5m*1, 22uF_0603*6, 10uF_0603*6 , 1uF_0402*11 BOOTA_GFX @EMI@ PCG4
680P_0402_50V7K
VSUMG+
UGA_GFX
VSUMG-
2
PHASEA_GFX
PRG16
LGA_GFX
Close GFX L/S MOS +5VS

PHG1
33
32
31
30
29
28
27
26
25
470K +-5% ERTJ0EV474J 0402
1 2
ISUMPG
ISUMNG
RTNG
FBG
COMPG
PGOODG
BOOTG
UGATEG
PAD
1U_0603_10V6K
2 2
PRG5 PRG6
1
61.9K_0402_1% 3.83K_0402_1%
1
1 2 NTCG_1 1 2 NTCG 1 24 PRZ7 VDD source use +5VS and PGOOD source use +3VS
PCZ5
@PRZ10
@ PRZ10 NTCG PHASEG @ PRZ6
@PRZ6 1_0603_5%
1 2 2 23 0_0603_5%
Please confirm power on and down sequence,
2
VR_ON VR_ON LGATEG make sure VGATE after CPU_CORE on.
2
2
0_0402_5% VR_SVID_CLK 3 22
<9> VR_SVID_CLK SCLK VCCP
PUZ1
VR_SVID_ALRT# 4 ISL95833HRTZ-T_TQFN32_4X4 21
<9> VR_SVID_ALRT# ALERT# VDD
1U_0603_10V6K
PCZ6
VR_SVID_DAT 5 20
<9> VR_SVID_DAT SDA PWM2
1
6 19 LG1_CPU
<41> VR_HOT# VR_HOT# LGATE1
2
NTC 7 18 PHASE1_CPU
NTC PHASE1
For VR_HOT#, already @PRZ11
@ PRZ11
1 2 8 17 UG1_CPU +CPU_B+
PGOOD
BOOT1
pull high at power side.
ISUMN
ISUMP
COMP
ISEN2 ISEN1 UGATE1 EMI@ PLZ2
RTN
1
54.9_0402_1%
BOOT_CPU
499_0402_1%
130_0402_1%
@ PCZ7 0_0402_5% FBMA-L11-322513-151LMA50T_1210
FB
1
47P_0402_50V8J 1 2
B+
10U_0805_25V6K
10U_0805_25V6K
PRZ12
PRZ13
PRZ14
+5VS
2
10
11
12
13
14
15
16
100U_25V_M
100U_25V_M
3.83K_0402_1%
1 1
1
2200P_0402_50V7K
PCZ21
PCZ22
1
1
PRZ16
PCZ1
PCZ2
EMI@PCZ20
PCZ20
+ +
2
VGATE <16> @
2
2 2
EMI@
2
+VCCP +3VS
470K +-5% ERTJ0EV474J 0402
1 2
NTC_1
1
1.91K_0402_1% PRZ9
61.9K_0402_1%
PQZ1
OCP setting=39.9~44.99A
1
@PCZ8
@ PCZ8 AON6932A_DFN5X6-8-7
PHZ1
PRZ15
0.1U_0402_16V7K 3 0.22uH DCR= 0.97+-5% m ohm, Idc~Isat= 25~34A

2
@PRZ1
@ PRZ1 2 S2
0_0603_5% D1 4 +CPU_CORE
UG1_CPU 1 2 UG1_CPU-1 1 S2 PLZ1
2
G1 5 0.22UH_PCME064T-R22MS_28A_20%
PRZ15 and PRG5 7 S2 1 2
PHASE1_CPU PHASE1_CPU
27.4K ohm for 100 degree S1/D2 6
Close CPU L/S MOS G2
680P_0402_50V7K 4.7_1206_5%
61.9K ohm for 110 degree
@EMI@ PRZ3
2.2_0603_5%
3 3
PRZ2 PCZ3
BOOT_CPU 1 2 1 2
1
0.1U_0603_25V7K
LG1_CPU
PRZ4
1
3.65K_0603_1%
@EMI@ PCZ4
2
PCZ9 PRZ17 PRZ18 VSUM+
2
2.61K_0402_1%
470P_0402_50V7K 2K_0402_1% 42.2K_0402_1%
1
1 2 1 2 1 2
PRZ25
11K_0402_1%
2K_0402_1%
0.033U_0402_25V7K
1
PRZ22
PCZ10 PRZ19 PCZ11 VSUM+

0.1U_0402_25V6
2
1
1
422_0402_1%
470P_0402_50V7K 499_0402_1% 100P_0402_50V8J

1
1
PRZ23
PCZ16
1 2 1 2 1 2
PCZ17
Close CPU choke

1
VSUM-
2
PRZ24
PHZ2
2
2
6800P_0402_25V7K
1
PCZ15
PRZ20 PRZ21 PCZ12 10K_0402_1%_ERTJ0EG103FA

1.91K_0402_1% 137K_0402_1% 1000P_0402_50V8-J
2
1 2 1 2 1 2
2
VSUM-
.1U_0402_16V7K
1
PCZ18
Layout Note <9> VCCSENSE @ PCZ13

SVID routing 330P_0402_50V7K
2
1 2
1. Alert# signal must be routed between
the Clock and Date lines to reduce the cross
talk between them. Signal order arrangement: 1 2 Cn = L/((Rntcnet*Rsum)/(Rntcnet+Rsum))*DCR)
mobile order is Clock-Alert-Date. PCZ14
If Cn is correctly selected, when the load current has a
4 4
0.01UF_0402_25V7K square change, the output voltage also has a square response.
2. SVID spacing requirement is 18mils(0.475mm).
<9> VSSSENSE
3. Maximum total microstrip routing length of

each SVID signal must not exceed 6000mils(152.4mm).
4. The SVID bus must be ground reference, It cannot be
referenced to input (Vbat or 12V) power plans as they can
couple noise into the SVID bus as power states change.
5. Avoid routing under noisy circuit, e.g. switch node ,
Gate driver, B+, Vin, high speed signal.
6. When SVID signal changes Layer, GND return path
PWR-CPU_CORE/GFX_CORE
may be changed also. We need add GND via for GND AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
0.2
reference.
LA-A998P
A B C D E
A
B
C
D
2
1
+
2 1 2 1 2 1 2 1
PCZ124 PCZ116 PCZ110 PCZ104

2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PCZ101
2 1 2 1 2 1 2 1
5
5
+CPU_CORE
330U_D2_2V_Y
2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
2
1
+
2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
CPU_CORE
2 1 2 1 2 1 2 1
PCZ102
330uF 9m *1
2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
22uF 0603 *12

560uF 4.5m *1
2.2uF 0402 *16

2 1 2 1 2 1 2 1
560U_D2_2VM_R4.5M

2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1

2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
PCZ130 PCZ122
2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
2 1 2 1
PCZ131 PCZ123
2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
4
4
560U_D2_2VM_R4.5M
PCG101
2 1 2 1 2 1
2
1
2
1
+
PCG121 PCG115 PCG109 PCG103

1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
2
1

+VGFX_CORE
1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
Issued Date
GFX_CORE
2
1

1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M 22U_0603_6.3V6M
Security Classification
1uF 0402 *11
10uF 0603 *6
22uF 0603 *6
2 1 2 1 2 1
560uF 4.5m *1
2
1

1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M 22U_0603_6.3V6M
3
3
2 1 2 1 2 1
2
1

1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M 22U_0603_6.3V6M
2013/08/07
2 1 2 1
2
1
PCG120 PCG114 PCG108

1U_0402_6.3V6K 10U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
Compal Secret Data

Deciphered Date
PCH123 PCH113
1U_0402_6.3V6K 1U_0402_6.3V6K
2 1 2 1
VCCP
PCH124 PCH114
1U_0402_6.3V6K 1U_0402_6.3V6K
1 2
2 1 2 1
2
2
10U_0603_6.3V6M PCH103
PCH125 PCH115
330uF 9m *2
2016/08/06
1U_0402_6.3V6K 1U_0402_6.3V6K 1 2
1uF 0402 *26
10uF 0603 *10
2 1 2 1 10U_0603_6.3V6M PCH104
PCH126 PCH116 1 2
1U_0402_6.3V6K 1U_0402_6.3V6K
10U_0603_6.3V6M PCH105
2 1 2 1 2 1
1 2
PCH133 PCH127 PCH117

1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M PCH106
Size
Title
Date:
2 1 2 1 2 1 1 2
PCH134 PCH128 PCH118 10U_0603_6.3V6M PCH107

1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
1 2
2 1 2 1 2 1
10U_0603_6.3V6M PCH108
Document Number
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1 2
2 1 2 1 2 1 10U_0603_6.3V6M PCH109
Friday, March 14, 2014
PCH136 PCH130 PCH120 1 2

330U_D2_2V_Y
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
LA-A998P
10U_0603_6.3V6M PCH110
2
1
+
2 1 2 1 2 1
1 2 PCH101
1
1
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M PCH111

330U_D2_2V_Y
Sheet
2 1 2 1 2 1 1 2
2
1
+
PCH102
PCH138 PCH132 PCH122 10U_0603_6.3V6M PCH112
54
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K

QFKAA
+VCCP
of
PWR-CPU_CORE DECOUPLING
58
Rev
0.2
A
B
C
D
A B C D
UMA@
PR1502
0_0402_5%
1 2
SUSP# <10,41,43,50,51,52,58>
1
1
1 @UMA@ UMA@ 1
PC1502 PR1503
.1U_0402_16V7K 1M_0402_5%
2
UMA@
2
PU1501
9
FB_1.5V 1 PGND 8
FB SGND UMA@ +1.5VSP +1.5VS
@ PJ1501 2 7 EN_1.5V PL1501 @ PJ1502
JUMP_43X79 PG EN 1UH_PH041H-1R0MS_3.8A_20% JUMP_43X79
+3VALW 1 2 VIN_1.5V 3 6 LX_1.5V 1 2 1 2
22U_0603_6.3V6M
1 2 IN LX 1 2
22U_0603_6.3V6M
22U_0603_6.3V6M
4 5
PGND NC
1
UMA@ PC1501
1
@EMIUMA@ UMA@ UMA@
UMA@ PC1504
UMA@ PC1505
SY8003DFC_DFN8_2X2 PR1504 PR1505 PC1503
2
4.7_0603_5% 30.1K_0402_1% 68P_0402_50V8J
2
2
2
continuous 3A
1
1
@EMIUMA@ UMA@
PC1506 PR1506
680P_0402_50V7K 20K_0402_1%
2
2 2
3 3
4 4

PWR-1.5VS
A B C D
5 4 3 2 1
D D
@VGA@
PRV1
1K_0402_5%
1 2 +3VGS
@VGA@
PRV2
0_0402_5%
1 2 NVVDD_PWM_VID <22>
GPU_B+
1
VGA@ @VGA@
1
PCV1 Rref1 PRV26 Operation phase Number PSI Voltage setting
1U_0402_6.3V6K VGA@ 1K_0402_5%
2
PRV3 1 2 +3VGS 1 phase with DEM 0V to 0.8V EMIVGA@

7.5K_0402_1% PLV1
@VGA@ HCB2012KF-121T50_0805 B+
C 1 phase with CCM 1.2V to 1.8V C
2
@VGA@ VGA@ PRV6 PSI Pull high on HW side 1 2
PRV4 PRV5 0_0402_5% Active phase with CCM 2.4V to 5.5V
2200P_0402_50V7K
0_0402_5% 27K_0402_1% 1 2
100U_25V_M
1
10U_0805_25V6K
10U_0805_25V6K
1 2 1 2 NVVDD_PSI <22>
EMIVGA@ PCV3
VGA@ PCV4
VGA@ PCV6
1
1
Rboot Rrefadj @VGA@ +
VGA@ PCV19
5
PRV28 @VGA@ PRV27
1
VGA@ 10K_0402_5% 1K_0402_5%
2
PCV8 1 2 1 2 @VGA@ 2
+3VGS
@VGA@ 5600P_0402_50V7K PRV10
2
PCV7 C VGA@ PRV9 Pull high on HW side 0_0603_5%
0.01U_0402_16V7K 1K_0402_5% U2_UGATE1 1 2 4
1 2 1 2 VGA@ +VGA_CORE
DGPU_PWR_EN <17,25,41>
GPU_VID
PQV1
GPU_FBRTN
VGA@ VGA@ SIR472DP-T1-GE3_POWERPAK8-5 EDP-Continuous 33.5A
Rref2 PRV7 PCV5 EDP-Peak 51.5A
3
2
1
VGA@ VGA@ 2.2_0603_5% 0.22U_0603_25V7K
OCP 66A
1
1 2 1 2
GPU_REFADJ
PRV8 PRV11 @VGA@ U2_BOOT1
U2_BOOT1
U2_UGATE1
6.2K_0402_1% 1.74K_0402_1% PCV9
1 2 1 2
GPU_PSI
0.1U_0402_25V6
GPU_EN
2
Reserve Location VGA@ PLV2 +VGA_CORE
0.22UH_PCME064T-R22MS_28A_20%
U2_PHASE1 1 2
1
@EMIVGA@
6
1
VGA@ PRV14
390U_2.5V_M
390U_2.5V_M
1 1
VGA@ PRV13 VGA@ 4.7_1206_5%
UGATE1
BOOT1
VID
PSI
EN
REFADJ
PRV12 340K_0402_1% PQV2 + +
VGA@ PCV12
VGA@ PCV10
100_0402_1% GPU_B+ 1 2 MDU1511RH_POWERDFN56-8-5
1SNB_VGA1 2
1 2 1 Rton GPU_REFIN 7 24 U2_PHASE1 U2_LGATE1 4
@VGA@ REFIN PHASE1 2 2
PCV14 GPU_VREF 8 23 U2_LGATE1
VREF LGATE1
1
@VGA@ 0.01UF_0402_25V7K
PRV16 2 GPU_TON 9 22 U2_PWM3 VGA@
3
2
1
<25> VSSSENSE_VGA 0_0402_5% TON VGA@ GND/PWM3 PRV15 @EMIVGA@
1 2 GPU_FBRTN 10 PUV1 21 12.7K_0402_1% PCV15
RGND RT8813AGQW_WQFN24_4X4 PVCC Rocset 680P_0603_50V7K
2
B B
TALERT/ISEN2
GPU_FB 11 20 U2_LGATE2
VSNS LAGTE2
1
TSNS/ISEN3
@VGA@
Co-Lay Co-Lay
VCC/ISNE1
@VGA@ PCV16 GPU_COMP 12 19 U2_PHASE2

SS PHASE2
UGATE2
PGOOD
PRV17 47P_0402_50V8J
BOOT2
2
0_0402_5% 1
GND
1 2 @VGA@ GPU_B+
PCV17
<24> VCCSENSE_VGA 0.01U_0402_16V7K
2200P_0402_50V7K
25
13
14
15
16
17
18
2 Css
10U_0805_25V6K
10U_0805_25V6K
VGA@
EMIVGA@ PCV20
VGA@ PCV21
VGA@ PCV22
1
1
PRV18
GPU_DSBL/ISEN1
GPU_TSNS/ISEN3
5
100_0402_1%
GPU_HOT#
1 2
GPU_PGOOD1
2
U2_UGATE2
@VGA@
U2_BOOT2
+VGA_CORE
PRV20
0_0603_5%
U2_UGATE2 1 2 4
VGA@
PQV3
VGA@ VGA@ SIR472DP-T1-GE3_POWERPAK8-5
PRV19 PCV18
3
2
1
2.2_0603_5% 0.22U_0603_25V7K
GPU_VREF U2_BOOT2 1 2 1 2
+3VGS
1
VGA@ VGA@ PLV3 +VGA_CORE

1. VSNS Soft-Start time (Internal) is 0.7ms (PCV17 un-pop) PRV21 0.22UH_PCME064T-R22MS_28A_20%
1
18.7K_0402_1% U2_PHASE2 1 2
Tss=(Css*Vrefin)/Iss+2.3ms VGA@
2
1
=0.01U*0.9V/5uA+2.3ms=4.1ms (PCV17 pop) PRV22
10K_0402_1% @EMIVGA@
390U_2.5V_M
1
1
5
PRV23
2
1
VGA@ VGA@ 4.7_1206_5% +
VGA@ PCV25
2. Switching frequency setting: PCV23 PHV1 +5VS VGA@
1SNB_VGA2 2
Fsw=(Vin-0.5)/(2*Vin*Rton*3.2p)=448Khz 1U_0402_6.3V6K 470K +-5% ERTJ0EV474J 0402 DGPU_PWROK <18,25> PQV4
2
MDU1511RH_POWERDFN56-8-5 2
2
A U2_LGATE2 4 A
3. Thermal monitoring: VGA@
PRV24
(VGPU_VREF-VTSNS)/PRV21=VTSNS/Rth 2.2_0603_5% @EMIVGA@
1 2 PCV26
3
2
1
680P_0603_50V7K
2
T_min T_typical T_max VGA@
PRV25
Co-Lay
1
100K_0402_1% VGA@
PRV21=18.7K 96.73C 100C 103.1C +3VS
1 2 PCV27
1U_0402_6.3V6K
2

PRV21=13K 106.38C 110C 113.4C <41> GPU_HOT# PWR-VGA_CORE
0.2
LA-A998P
5 4 3 2 1
A B C D E
+VGA_CORE
PLACE UNDER GPU

1 1
1
VGA@ VGA@ VGA@ VGA@ VGA@
PCV51 PCV52 PCV53 PCV54 PCV55
4.7U_0603_6.3V6M 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M
2
1
1
4.7U_0603_6.3V6M 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M
2
2
2 2
1
1
VGA@ VGA@ VGA@ VGA@
PCV61 PCV62 PCV63 PCV64
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
2
2
PLACE NEAR GPU
1
1
4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K
2
2
3 3
1
VGA@ VGA@
PCV70 PCV71
22U_0603_6.3V6M 47U_0805_6.3V6M
2
4 4

PWR-VGA CHIP DECOUPLING
Document Number Rev
B 0.2
LA-A998P
A B C D E
5 4 3 2 1
@VGA@
PRW 1
0_0402_5%
1 2
SUSP# <10,41,43,50,51,52,55>
1
D D
1
VGA@ @VGA@
PRW 2 PCW 1
1M_0402_1% 0.01UF_0402_25V7K
2
2
@EMIVGA@ @EMIVGA@
PRW 3 PCW 2
EMIVGA@ 4.7_1206_5% 680P_0603_50V7K
PLW 1
HCB2012KF-121T50_0805
VGA@
PUW 1 @VGA@ VGA@
1 2 SNB_VRAMPW R 1 2
+1.5VDIS +1.5VS
B+ 1 2 B+_VRAMPW R 8
IN EN
1 EN_VRAMPW R PRW 4
0_0603_5%
PCW 5
0.1U_0603_25V7K VGA@
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
6 BST_VRAMPW R1 2 BST_VRAMPW 1 Rn 2 PLW2 @ PJW 1
EMIVGA@ PCW3
VGA@ PCW4
VGA@ PCW6
BS
1
1.5UH_PCMC063T-1R5MN_9A_20% Vo=1.503V JUMP_43X118

9 10 LX_VRAMPW R 1 2 1 2
GND LX 1 2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2
1
FB=0.6V
PCW8
PCW9
VGA@ PCW10
VGA@ PCW11
1
1
4 FB_VRAMPW R VGA@ VGA@
FB PRW 5 PCW 7
3 7 30.1K_0402_1% 330P_0402_50V7K
+3VALW
2
ILMT BYP
VGA@
VGA@
2
2 5
PG LDO
1
VGA@
1
SY8206DQNC_QFN10_3X3 VGA@ PCW 12
PCW 13 4.7U_0603_6.3V6K
1
4.7U_0603_6.3V6K
2
C VGA@ C
PRW 6
19.6K_0402_1%
2
continuous 6A
peak 9A
B B
A A

Title
PWR-VRAM Power
Custom 0.2
LA-A998P
5 4 3 2 1

La-A998p R01 Szso40 PDF

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A B C D E

SLC M/B Schematics Document

Security Classification Compal Secret Data Compal Electronics, Inc.

Intel 204pin DDR3L-SO-DIMM X2

VRAM x 4 page 22~29

FDI *8 DMI2 *4 Port 8 Port 9 Port 10

Conn.X1 Conn. Conn.

Security Classification Compal Secret Data Compal Electronics, Inc.

ZSO40/50 (LA-A998P/LA-A999 Ver:0.1) STATE

Voltage Rails Full ON HIGH HIGH HIGH HIGH ON ON ON ON

+1.5VGS GPU power PX OFF OFF

Security Classification Compal Secret Data

PCI EXPRESS -- GRAPHICS

eDP@ AA10 J14 PEG_HTX_GRX_N5 CU43 DIS@ 1 2 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N5

PEG_TX#[14] J4 PEG_HTX_GRX_N0 CU48 DIS@ 1 2 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N0

Typ- suggest 220nF. The change in AC capacitor

Security Classification Compal Secret Data Compal Electronics, Inc.

JTAG & BPM

2011.10.18 delete all reserved XDP conponent.

H_CPUPWRGD_R C118 1 2 220P_0402_50V7K

2 RC25 SM_RCOMP2 RC26 2 1 200_0402_1% C263 0.1U_0201_16V4Z

0_0402_5% PLT_RST# 1 2 12.19

1 2 1 PU/PD for JTAG signals C265 @ 100P_0402_50V8J

<16> SYS_PWROK B 4 PM_SYS_PWRGD_BUF PM_SYS_PWRGD_BUF 1 2

XDP_TMS T40 @ PAD 6/27 Add ESD solution

D @ XDP_TCK T43 @ PAD

2011.10.18 delete all reserved XDP conponent.

Security Classification Compal Secret Data Compal Electronics, Inc.

DDR SYSTEM MEMORY B

4.99K_0402_1% DRAMRST_CNTRL_PCH hgih ,MOS ON

A RC39 Dimm not reset A

CFG Straps for Processor

PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane # definition matches

BB19 RSVD11 DC_TEST_A59 C59 10 = 2 x 8 PCI Express

PEG DEFER TRAINING

CFG7 * 1: (Default) PEG Train immediately following

Security Classification Compal Secret Data Compal Electronics, Inc.

PEG IO AND DDR IO

G43 VSSSENSE_R RC62 1 short@ 2 0_0402_5%

IVY-BRIDGE_BGA1023 (follow check list)

Security Classification Compal Secret Data Compal Electronics, Inc.

RC15 AD55 VAXG[17] VDDQ[3] AJ40

D BSS138W-7-F_SOT323-3 P48 AM40

RC82 P53 VAXG[28] VDDQ[14] AR26

B F45 VCCDQ[1] AN26 B

P17 VCCSA[5] TPS22966DPUR_SON14_2X3-D

P20 U10 VCCSA_SENSE 1 2

V18 D49 VCCSA_VID1

0 0 0.90 V Yes Yes

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

DDR_CS1_DIMMA# 121 122

1 DDR_A_D57 183 184

1 1 1 1 1 1 1 1 1 1 185 186 DDR_A_DQS#7

201 202 PCH_SMBCLK

SGA00004400 1 1 203 204

DDR_CS1_DIMMB# 121 122

47U 6.3V M B1 ESR70M

1 1 DDR_B_D57 183 184

1 1 1 1 1 1 1 1 1 1 185 186 DDR_B_DQS#7

+ + CD57 187 188 DDR_B_DQS7

201 202 PCH_SMBCLK

FDI 8 DMI2 4 Port 8 Port 9 Port 10