Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
July 2002
FDD2572 / FDU2572
N-Channel UltraFET® Trench MOSFET
150V, 29A, 54mΩ
Features Applications
• r DS(ON) = 45mΩ (Typ.), VGS = 10V, ID = 9A • DC/DC converters and Off-Line UPS
• Qg(tot) = 26nC (Typ.), VGS = 10V • Distributed Power Architectures and VRMs
• Low Miller Charge
• Primary Switch for 24V and 48V Systems
• Low Body Diode
• High Voltage Synchronous Rectifier
• UIS Capability (Single Pulse and Repetitive Pulse)
• Qualified to AEC Q101 • Direct Injection / Diesel Injection System
DRAIN SOURCE D
(FLANGE)
DRAIN
DRAIN GATE
GATE (FLANGE)
G
SOURCE
TO-252AA TO-251AA
FDD SERIES
FDU SERIES S
Thermal Characteristics
o
RθJC Thermal Resistance Junction to Case TO-251, TO-252 1.11 C/W
o
RθJA Thermal Resistance Junction to Ambient TO-251, TO-252 100 C/W
RθJA Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area 52 oC/W
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
Off Characteristics
BVDSS Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 150 - - V
VDS = 120V - - 1
IDSS Zero Gate Voltage Drain Current µA
VGS = 0V TC = 150o - - 250
IGSS Gate to Source Leakage Current VGS = ±20V - - ±100 nA
On Characteristics
VGS(TH) Gate to Source Threshold Voltage V GS = VDS, ID = 250µA 2 - 4 V
ID=9A, VGS=10V - 0.045 0.054
rDS(ON) Drain to Source On Resistance ID = 4A, VGS = 6V, - 0.050 0.075 Ω
ID=9A, VGS=10V, TC=175oC - 0.126 0.146
Dynamic Characteristics
CISS Input Capacitance - 1770 - pF
VDS = 25V, VGS = 0V,
COSS Output Capacitance - 183 - pF
f = 1MHz
CRSS Reverse Transfer Capacitance - 40 - pF
Qg(TOT) Total Gate Charge at 10V VGS = 0V to 10V - 26 34 nC
Qg(TH) Threshold Gate Charge VGS = 0V to 2V VDD = 75V - 3.3 4.3 nC
Qgs Gate to Source Gate Charge ID = 9A - 8 - nC
Qgs2 Gate Charge Threshold to Plateau Ig = 1.0mA - 5 - nC
Qgd Gate to Drain “Miller” Charge - 6 - nC
1.2 40
VGS = 10V
35
1.0
POWER DISSIPATION MULTIPLIER
30
0.6 20
0.4 15
10
0.2
5
0
0
0 25 50 75 100 125 150 175
25 50 75 100 125 150 175
TC , CASE TEMPERATURE (oC) TC, CASE TEMPERATURE (oC)
2.0
0.05
ZθJC, NORMALIZED
0.02
0.01
PDM
0.1
SINGLE PULSE t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
0.01
500
TC = 25oC
FOR TEMPERATURES
TRANSCONDUCTANCE ABOVE 25oC DERATE PEAK
MAY LIMIT CURRENT
IN THIS REGION CURRENT AS FOLLOWS:
IDM, PEAK CURRENT (A)
I = I25 175 - TC
150
100
VGS = 10V
20
10-5 10-4 10-3 10-2 10-1 100 101
t , PULSE WIDTH (s)
100 60
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
STARTING TJ = 25oC 50 VDD = 15V
IAS, AVALANCHE CURRENT (A)
STARTING TJ = 150oC
1 20 TJ = 25o C
TJ = -55oC
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) 10
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
0.1 0
0.001 0.01 0.1 1 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
tAV, TIME IN AVALANCHE (ms) VGS , GATE TO SOURCE VOLTAGE (V)
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 Figure 6. Transfer Characteristics
Figure 5. Unclamped Inductive Switching
Capability
60 60
PULSE DURATION = 80µs
TC = 25oC VGS = 10V DUTY CYCLE = 0.5% MAX
DRAIN TO SOURCE ON RESISTANCE (m Ω)
50
55 VGS = 6V
ID, DRAIN CURRENT (A)
40
VGS = 7V
VGS = 6V 50
30
VGS = 10V
20 VGS = 5V
45
10
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
40
0
0 1 2 3 4 5 0 10 20 30
VDS , DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
3.0 1.4
PULSE DURATION = 80µs VGS = VDS, ID = 250µA
DUTY CYCLE = 0.5% MAX
NORMALIZED DRAIN TO SOURCE
2.5
1.2
THRESHOLD VOLTAGE
NORMALIZED GATE
2.0
ON RESISTANCE
1.0
1.5
0.8
1.0
0.6
0.5
VGS = 10V, ID =9A
0 0.4
-80 -40 0 40 80 120 160 200 -80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC) TJ, JUNCTION TEMPERATURE (oC)
Figure 9. Normalized Drain to Source On Figure 10. Normalized Gate Threshold Voltage vs
Resistance vs Junction Temperature Junction Temperature
1.2 1000
ID = 250µA
NORMALIZED DRAIN TO SOURCE
COSS ≅ CDS + C GD
C, CAPACITANCE (pF)
1.1
CRSS = CGD
100
1.0
0.9 10
-80 -40 0 40 80 120 160 200 0.1 1 10 150
TJ , JUNCTION TEMPERATURE (oC) VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 11. Normalized Drain to Source Figure 12. Capacitance vs Drain to Source
Breakdown Voltage vs Junction Temperature Voltage
10
VDD = 75V
VGS , GATE TO SOURCE VOLTAGE (V)
WAVEFORMS IN
2
DESCENDING ORDER:
ID = 9A
ID = 4A
0
0 5 10 15 20 25 30
Qg, GATE CHARGE (nC)
VDS BVDSS
tP
VDS
L
IAS
VARY tP TO OBTAIN VDD
+
REQUIRED PEAK IAS RG
VDD
VGS -
DUT
tP
0V IAS 0
0.01Ω
tAV
Figure 14. Unclamped Energy Test Circuit Figure 15. Unclamped Energy Waveforms
VDS
VDD Qg(TOT)
VDS
L
VGS = 10V
VGS
+
VDD VGS
-
DUT VGS = 2V
0 Qgs2
Ig(REF)
Qg(TH)
Qgs Qgd
Ig(REF)
0
Figure 16. Gate Charge Test Circuit Figure 17. Gate Charge Waveforms
td(ON) td(OFF)
RL tr tf
VDS
90% 90%
+
VGS
VDD
10% 10%
- 0
DUT 90%
RGS
VGS 50% 50%
PULSE WIDTH
VGS 10%
0
Figure 18. Switching Time Test Circuit Figure 19. Switching Time Waveforms
RθJA (oC/W)
Equation 1 mathematically represents the relationship and
75
serves as the basis for establishing the rating of the part.
(T –T )
JM A (EQ. 1)
P D M = ----------------------------- 50
R θ JA
R
23.84
= 33.32 + -------------------------------------
θ JA (EQ. 2)
( 0.268 + Area )
Area in Inches Squared
R
154
= 33.32 + ----------------------------------
θ JA (EQ. 3)
( 1.73 + Area )
Area in Centimeters Squared
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*52),3))}
.MODEL MmedMOD NMOS (VTO=3.55 KP=3 IS=1e-40 N=10 TOX=1 L=1u W=1u RG=1.6)
.MODEL MstroMOD NMOS (VTO=4.0 KP=25 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=2.95 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=16 RS=0.1)
FDD2572
CTHERM1 TH 6 3.8e-3
CTHERM2 6 5 4.0e-3
CTHERM3 5 4 4.2e-3 RTHERM1 CTHERM1
CTHERM4 4 3 4.3e-3
CTHERM5 3 2 8.5e-3
CTHERM6 2 TL 3.0e-2
6
RTHERM1 TH 6 5.5e-4
RTHERM2 6 5 5.0e-3
RTHERM3 5 4 4.5e-2
RTHERM2 CTHERM2
RTHERM4 4 3 10.5e-2
RTHERM5 3 2 3.7e-1
RTHERM6 2 TL 3.8e-1
5
SABER Thermal Model
SABER thermal model FDD2572
template thermal_model th tl RTHERM3 CTHERM3
thermal_c th, tl
{
ctherm.ctherm1 th 6 =3.8e-3
4
ctherm.ctherm2 6 5 =4.0e-3
ctherm.ctherm3 5 4 =4.2e-3
ctherm.ctherm4 4 3 =4.3e-3
ctherm.ctherm5 3 2 =8.5e-3 RTHERM4 CTHERM4
ctherm.ctherm6 2 tl =3.0e-2
rtherm.rtherm1 th 6 =5.5e-4
rtherm.rtherm2 6 5 =5.0e-3 3
rtherm.rtherm3 5 4 =4.5e-2
rtherm.rtherm4 4 3 =10.5e-2
rtherm.rtherm5 3 2 =3.7e-1
RTHERM5 CTHERM5
rtherm.rtherm6 2 tl =3.8e-1
}
RTHERM6 CTHERM6
tl CASE
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™ FRFET™ PACMAN™ SuperSOT™-3
Bottomless™ GlobalOptoisolator™ POP™ SuperSOT™-6
CoolFET™ GTO™ Power247™ SuperSOT™-8
CROSSVOLT™ HiSeC™ PowerTrench® SyncFET™
DOME™ I2C™ QFET™ TinyLogic™
EcoSPARK™ ISOPLANAR™ QS™ TruTranslation™
E2CMOS™ LittleFET™ QT Optoelectronics™ UHC™
EnSigna™ MicroFET™ Quiet Series™ UltraFET®
FACT™ MicroPak™ SILENT SWITCHER ® VCX™
FACT Quiet Series™ MICROWIRE™ SMART START™
FAST® OPTOLOGIC® SPM™
FASTr™ OPTOPLANAR™ Stealth™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
Advance Information Formative or In This datasheet contains the design specifications for
Design product development. Specifications may change in
any manner without notice.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
www.datasheetcatalog.com