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A B C D E

1 1

Compal confidential 2

Schematics Document
ClawHammer AMD K8 with
3

nVIDIA Chrush K8 3

2003-10-15
REV:0.5

4 4

Compal Electronics, Inc.


Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 1 of 50
A B C D E
A B C D E

Compal confidential
File Name : LA-1811 Fan Control
page 4
Thermal Sensor
MAX6649
1 page 4 1

AMD K8
Memory BUS(DDR)
Claw Hammer Processor
DDR-SO-DIMM X2
CRT Connector page 4, 5, 6, 7 BANK 0, 1, 2, 3 page 8, 9,10
2.5V DDR- 200/266
page 18

HT 16x16 800 MHZ

TFT/HPA Panel
Interface USB2.0 USB conn
page 17 nVIDIA
MAP17 page 27

TV OUT
page 14, 15, 16 MDC & BT Conn
2
Connector
page 18 nVIDIA page 27 2

Crush K8 Audio CKT AMP & Audio Jack


AD1981B
IDSEL:AD18
(PIRQC#,GNT#3,REQ#3) 3.3V 33 MHz PCI BUS 708 BGA page 25 page 26

IDSEL:AD16 IDSEL:AD17 IDSEL:AD20 AC-LINK


(PIRQA#,GNT#0,REQ#0) (PIRQB#,GNT#1,REQ#1) (PIRQA#/B#,GNT#2,REQ#2)
ATA-100
Primary IDE
IEEE 1394 Mini PCI LAN CardBus Controller page 11, 12, 13
TSB43AB21A socket RTL 8101L Secondary IDE HDD
TI PCI1620 ATA-100
page 21 page 28 page 20 page 22 Connector
page 19

CDROM
RJ45/11 CONN Connector SPR CONN.
page 20
Slot 0/1 page 34
page 23 page 19
3 *RJ45 CONN 3

RTC CKT. LPC BUS *PS2 x2 CONN


*CRT CONN
*LINE IN JACK
*LINE OUT JACK
Power OK CKT. EC ENE VIA 1211 *1394 CONN
KB3910 Super I/O *SPDIF CONN
page 36
page 30 page 29 *DVI CONN
*DC JACK
*TVOUT CONN
Power On/Off CKT. Touch Pad Int.KBD PARALLEL FIR *PRINTER PORT
page 33 page 33 page 33 page 32 page 33 *COM PORT
*USB CONN x2
EC I/O Buffer BIOS FDD
DC/DC Interface CKT. page 31
page 31 page 32

page 37
4 4

Power Circuit DC/DC


page 38, 39, 40, 41, 42, 43, 44 Compal Electronics, Inc.
Title

Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Thursday, October 16, 2003 Sheet 2 of 50
A B C D E
A

Voltage Rails

+1.2V_HT
power
+1.2VS
plane +1.2VALW +1.25V
+1.5VS
+3VALW +2.5V
+2.5VS
+5VALW +3V
+3VS
State 12VALW +5V
+5VS

S0 O O O

S1 O O O
S3 O O X
S5 S4/AC O X X
S5 S4/AC don't exist
X X X
O MEANS ON
X MEANS OFF

PCI Devices

1
DEVICE PCI Device ID IDSEL # REQ/GNT # PIRQ 1

INTERNAL

USB 2.0 2 AD13 N/A G


AC97 MODEM 6 AD17 N/A M
AC97 6 AD17 N/A L
ATA 100 8 AD20 N/A
ETHERNET 5 AD16 N/A K
LPC I/F 1 AD12 N/A
SMBUS 1 AD12 N/A F

EXTERNAL
VGA 0 AD16 N/A E
1394 0 AD16 0 A
LAN 1 AD17 1 B
CARD BUS 4 AD20 2 A, B
Wireless LAN 2 AD18 3 C
Mini-PCI (no use) 3 AD19 4 D

Compal Electronics, Inc.


Title
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 3 of 50
A
A B C D E

H_CADIP[0..15] H_CADOP[0..15]
<11> H_CADIP[0..15] H_CADOP[0..15] <11>
H_CADIN[0..15] H_CADON[0..15]
<11> H_CADIN[0..15] H_CADON[0..15] <11>

LA-1851
U1A

4 BDW00
LA-1452 REV 0
Claw Hammer-DTR Fan Control Circuit 1 +5VS
4

H_CADIP15 T25 N26 H_CADOP15


H_CADIN15 R25 L0_CADIN_H15 L0_CADOUT_H15 N27 H_CADON15
H_CADIP14 U27 L0_CADIN_L15 L0_CADOUT_L15 L25 H_CADOP14

1
H_CADIN14 U26 L0_CADIN_H14 L0_CADOUT_H14 M25 H_CADON14 Q1
H_CADIP13 V25 L0_CADIN_L14 L0_CADOUT_L14 L26 H_CADOP13 +12VALW FMMT619_SOT23

1
H_CADIN13 U25 L0_CADIN_H13 L0_CADOUT_H13 L27 H_CADON13 1
H_CADIP12 W27 L0_CADIN_L13 L0_CADOUT_L13 J25 H_CADOP12 D1 C1

8
H_CADIN12 W26 L0_CADIN_H12 L0_CADOUT_H12 K25 H_CADON12

HTT Interface
H_CADIP11 AA27 L0_CADIN_L12 L0_CADOUT_L12 G25 H_CADOP11 @1SS355_SOD323 10U_1206_10V4Z

E
H_CADIN11 AA26 L0_CADIN_H11 L0_CADOUT_H11 H25 H_CADON11 EN_FAN1 3 R1 2
<30> EN_FAN1

2
H_CADIP10 AB25 L0_CADIN_L11 L0_CADOUT_L11 G26 H_CADOP10 +IN 1FAN1_ON 1 2

3
H_CADIN10 AA25 L0_CADIN_H10 L0_CADOUT_H10 G27 H_CADON10 2 1 2 OUT
2
H_CADIP9 AC27 L0_CADIN_L10 L0_CADOUT_L10 E25 H_CADOP9 -IN U2A 100_0402_5% C2

G
H_CADIN9 AC26 L0_CADIN_H9 L0_CADOUT_H9 F25 H_CADON9 R2 LM358A_SO8
H_CADIP8 AD25 L0_CADIN_L9 L0_CADOUT_L9 E26 H_CADOP8 10K_0402_5% 0.1U_0402_16V4Z FAN1

4
H_CADIN8 AC25 L0_CADIN_H8 L0_CADOUT_H8 E27 H_CADON8 1

1
H_CADIP7 T27 L0_CADIN_L8 L0_CADOUT_L8 N29 H_CADOP7 JP1
1 1
H_CADIN7 T28 L0_CADIN_H7 L0_CADOUT_H7 P29 H_CADON7 1 2 D2 C3 C612
H_CADIP6 V29 L0_CADIN_L7 L0_CADOUT_L7 M28 H_CADOP6 R3 8.2K_0402_5% 1
H_CADIN6 U29 L0_CADIN_H6 L0_CADOUT_H6 M27 H_CADON6 1N4148_SOT23 100P_0402_50V8K 2
H_CADIP5 V27 L0_CADIN_L6 L0_CADOUT_L6 L29 H_CADOP5 2 2 3

2
H_CADIN5 V28 L0_CADIN_H5 L0_CADOUT_H5 M29 H_CADON5 +12VALW ACES_85205-0300
H_CADIP4 Y29 L0_CADIN_L5 L0_CADOUT_L5 K28 H_CADOP4 R4 0.1U_0402_16V4Z
H_CADIN4 W29 L0_CADIN_H4 L0_CADOUT_H4 K27 H_CADON4 1 2
L0_CADIN_L4 L0_CADOUT_L4 +3VS
H_CADIP3 AB29 H28 H_CADOP3 C775
H_CADIN3 AA29 L0_CADIN_H3 L0_CADOUT_H3 H27 H_CADON3 10K_0402_5%
H_CADIP2 AB27 L0_CADIN_L3 L0_CADOUT_L3 G29 H_CADOP2 0.1U_0402_25V4K
3 L0_CADIN_H2 L0_CADOUT_H2 <30> FAN_SPEED1 3
H_CADIN2 AB28 H29 H_CADON2 1
H_CADIP1 AD29 L0_CADIN_L2 L0_CADOUT_L2 F28 H_CADOP1 C613
H_CADIN1 AC29 L0_CADIN_H1 L0_CADOUT_H1 F27 H_CADON1
H_CADIP0 AD27 L0_CADIN_L1 L0_CADOUT_L1 E29 H_CADOP0 1000P_0402_50V7K
H_CADIN0 AD28 L0_CADIN_H0 L0_CADOUT_H0 F29 H_CADON0 2
L0_CADIN_L0 L0_CADOUT_L0

H_CLKIP1 Y25 J26 H_CLKOP1


<11> H_CLKIP1 L0_CLKIN_H1 L0_CLKOUT_H1 H_CLKOP1 <11>
+1.2V_HT H_CLKIN1 W25 J27 H_CLKON1
<11> H_CLKIN1 L0_CLKIN_L1 L0_CLKOUT_L1 H_CLKON1 <11>
H_CLKIP0 Y27 J29 H_CLKOP0
<11> H_CLKIP0 L0_CLKIN_H0 L0_CLKOUT_H0 H_CLKOP0 <11>
H_CLKIN0 Y28 K29 H_CLKON0
<11> H_CLKIN0 L0_CLKIN_L0 L0_CLKOUT_L0 H_CLKON0 <11>
R5 1 2 49.9_0402_1% H_CTLIP1 R27 N25
R6 1 2 49.9_0402_1% H_CTLIN1 R26 L0_CTLIN_H1 L0_CTLOUT_H1 P25
<11> H_CTLIP0
H_CTLIP0
H_CTLIN0
T29
R29
L0_CTLIN_L1
L0_CTLIN_H0
L0_CTLOUT_L1
L0_CTLOUT_H0
P28
P27
H_CTLOP0
H_CTLON0
H_CTLOP0 <11> Fan Control Circuit 2 +5VS
<11> H_CTLIN0 L0_CTLIN_L0 L0_CTLOUT_L0 H_CTLON0 <11>

AF27 AJ27 LDTSTOP#


L0_REF1 LDTSTOP_L LDTSTOP# <11>
AE26

1
+1.2V_HT L0_REF0 1 2 +2.5VS Q2
FOX_PZ75403-2941-42 R7 1K_0402_5% FMMT619_SOT23

C
R8 44.2_0603_1%

1
2 1 LVREF1 1
U2B D3 C4
LVREF0

E
1 EN_FAN2 5 R9 @1SS355_SOD323 10U_1206_10V4Z
<30> EN_FAN2
1

C5 +IN 7FAN2_ON 1 2 2
1

2
R10 C6 2 1 6 OUT
2
2
1000P_0402_50V7K -IN 100_0402_5% C7
2
2 44.2_0603_1% 1000P_0402_50V7K R11
2 10K_0402_5% LM358A_SO8 0.1U_0402_16V4Z FAN2
2

1
1 1 JP2
1 2 D4 C8 C614
R12 8.2K_0402_5% 1
1N4148_SOT23 0.1U_0402_16V4Z 2
2 2 3

2
ACES_85205-0300
R13 10U_1206_10V4Z
1 2
Thermal Sensor +3VS

10K_0402_5%
+3VS

W=15mil
ADM1032 <30> FAN_SPEED2
1
C615
2
C610 1000P_0402_50V7K
THERMDA_CPU 2
THERMDA_CPU <6>
0.1U_0402_16V4Z
1

1 THERMDC_CPU
THERMDC_CPU <6>
R454
U3 1
@10K_0402_5% 1 2 THERMDA_CPU C611
VDD1 D+
2

6 3 THERMDC_CPU 2200P_0402_25V7K
ALERT# D- 2
1 4 8 EC_SMC_2 <30> 1
THERM# SCLK
5 7 EC_SMD_2 <30>
GND SDATA

ADM1032AR_SOP8
Compal Electronics, Inc.
Title
Claw Harmmer CPU (Host Bus)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 4 of 50
A B C D E
A B C D E

+1.25VREF_CPU
+2.5V U1B
50 mil width AG12
MEMVREF1
34.8_0603_1%
DDR_CLK5/5# & DDR_CLK7/7#
2 1 R16 MEMZN D14 Claw Hammer-DTR
34.8_0603_1% 2 1 R17 MEMZP C14 MEMZN route to nearest DIMM
MEMZP
<8> DDR_SDQ[0..63]
DDR_SDQ63 DDR_CKE0
DDR_CLK4/4# & DDR_CLK6/6#
A16 AE8 DDR_CKE0 <8>
DDR_SDQ62 B15 MEMDATA63 MEMCKEA AE7 DDR_CKE1 route to farthest DIMM
MEMDATA62 MEMCKEB DDR_CKE1 <8>
DDR_SDQ61 A12
1 DDR_SDQ60 B11 MEMDATA61 D10 DDR_CLK7 1
MEMDATA60 MEMCLK_H7 DDR_CLK7 <8>
DDR_SDQ59 A17 C10 DDR_CLK7#
MEMDATA59 MEMCLK_L7 DDR_CLK7# <8>
DDR_SDQ58 A15 E12 DDR_CLK6
MEMDATA58 MEMCLK_H6 DDR_CLK6 <9>
DDR_SDQ57 C13 E11 DDR_CLK6#
MEMDATA57 MEMCLK_L6 DDR_CLK6# <9>
DDR_SDQ56 A11 AF8 DDR_CLK5 DDR_CLK7 R18 1 2 120_0402_5% DDR_CLK7#
MEMDATA56 MEMCLK_H5 DDR_CLK5 <8>
DDR_SDQ55 A10 AG8 DDR_CLK5# DDR_CLK6 R19 1 2 120_0402_5% DDR_CLK6#
MEMDATA55 MEMCLK_L5 DDR_CLK5# <8>
DDR_SDQ54 B9 AF10 DDR_CLK4 DDR_CLK5 R20 1 2 120_0402_5% DDR_CLK5#
MEMDATA54 MEMCLK_H4 DDR_CLK4 <9>
DDR_SDQ53 C7 AE10 DDR_CLK4# DDR_CLK4 R21 1 2 120_0402_5% DDR_CLK4#
MEMDATA53 MEMCLK_L4 DDR_CLK4# <9>
DDR_SDQ52 A6 V3
DDR_SDQ51 C11 MEMDATA52 MEMCLK_H3 V4 within 1.00"
DDR_SDQ50 A9 MEMDATA51 MEMCLK_L3 K5 +2.5V
DDR_SDQ49 A5 MEMDATA50 MEMCLK_H2 K4
DDR_SDQ48 B5 MEMDATA49 MEMCLK_L2 R5 DDR_CLK1 R22 1 210K_0402_5%
DDR_SDQ47 C5 MEMDATA48 MEMCLK_H1 P5 DDR_CLK1# R23 1 210K_0402_5%
DDR_SDQ46 A4 MEMDATA47 MEMCLK_L1 P3 DDR_CLK0 R24 1 210K_0402_5%
DDR_SDQ45 E2 MEMDATA46 MEMCLK_H0 P4 DDR_CLK0# R25 1 210K_0402_5%
DDR_SDQ44 E1 MEMDATA45 MEMCLK_L0
DDR_SDQ43 A3 MEMDATA44 D8
DDR_SDQ42 B3 MEMDATA43 MEMCS_L7 C8
DDR_SDQ41 E3 MEMDATA42 MEMCS_L6 E8
DDR_SDQ40 F1 MEMDATA41 MEMCS_L5 E7
DDR_SDQ39 G2 MEMDATA40 MEMCS_L4 D6 DDR_SCS#3
MEMDATA39 MEMCS_L3 DDR_SCS#3 <9>
DDR_SDQ38 G1 E6 DDR_SCS#2
MEMDATA38 MEMCS_L2 DDR_SCS#2 <9>
DDR_SDQ37 L3 C4 DDR_SCS#1
MEMDATA37 MEMCS_L1 DDR_SCS#1 <8,9>

DDR Memory
DDR_SDQ36 L1 E5 DDR_SCS#0
MEMDATA36 MEMCS_L0 DDR_SCS#0 <8,9>
DDR_SDQ35 G3
DDR_SDQ34 J2 MEMDATA35 H5
MEMDATA34 MEMRASA_L DDR_SRASA# <8,9>
DDR_SDQ33 L2 D4
MEMDATA33 MEMCASA_L DDR_SCASA# <8,9>
DDR_SDQ32 M1 G5 +2.5V
2 MEMDATA32 MEMWEA_L DDR_SWEA# <8,9> 2
DDR_SDQ31 W1
DDR_SDQ30 W3 MEMDATA31 K3

A CHANGEL ADDRESS

1
MEMDATA30 MEMBANKA1 DDR_SBSA1 <8,9>
DDR_SDQ29 AC1 H3 R26
MEMDATA29 MEMBANKA0 DDR_SBSA0 <8,9>
DDR_SDQ28 AC3
DDR_SDQ27 W2 MEMDATA28 100_0402_1%
MEMDATA27 DDR_SMAA[0..13] <8,9>
DDR_SDQ26 Y1 E10 DDR_SMAA13 +1.25VREF_CPU
DDR_SDQ25 AC2 MEMDATA26 MEMADDA13 AE6 DDR_SMAA12

2
DDR_SDQ24 AD1 MEMDATA25 MEMADDA12 AF3 DDR_SMAA11
DDR_SDQ23 AE1 MEMDATA24 MEMADDA11 M5 DDR_SMAA10

1
DDR_SDQ22 AE3 MEMDATA23 MEMADDA10 AE5 DDR_SMAA9 R27 1 1
DDR_SDQ21 AG3 MEMDATA22 MEMADDA9 AB5 DDR_SMAA8 C11 C12
DDR_SDQ20 AJ4 MEMDATA21 MEMADDA8 AD3 DDR_SMAA7 100_0402_1%
DDR_SDQ19 AE2 MEMDATA20 MEMADDA7 Y5 DDR_SMAA6 1000P_0402_50V7K
DDR_SDQ18 AF1 MEMDATA19 MEMADDA6 AB4 DDR_SMAA5 2 2

2
DDR_SDQ17 AH3 MEMDATA18 MEMADDA5 Y3 DDR_SMAA4
DDR_SDQ16 AJ3 MEMDATA17 MEMADDA4 V5 DDR_SMAA3 0.1U_0402_10V6K
DDR_SDQ15 AJ5 MEMDATA16 MEMADDA3 T5 DDR_SMAA2
DDR_SDQ14 AJ6 MEMDATA15 MEMADDA2 T3 DDR_SMAA1
DDR_SDQ13 AJ7 MEMDATA14 MEMADDA1 N5 DDR_SMAA0
DDR_SDQ12 AH9 MEMDATA13 MEMADDA0
DDR_SDQ11 AG5 MEMDATA12 H4
DDR_SDQ10 AH5 MEMDATA11 MEMRASB_L F5
DDR_SDQ9 AJ9 MEMDATA10 MEMCASB_L F4
DDR_SDQ8 AJ10 MEMDATA9 MEMWEB_L
DDR_SDQ7 AH11 MEMDATA8 L5
B CHANGEL ADDRESS
DDR_SDQ6 AJ11 MEMDATA7 MEMBANKB1 J5
DDR_SDQ5 AH15 MEMDATA6 MEMBANKB0
DDR_SDQ4 AJ15 MEMDATA5 E9
DDR_SDQ3 AG11 MEMDATA4 MEMADDB_B13 AF6
3
DDR_SDQ2 AJ12 MEMDATA3 MEMADDB_B12 AF4
3
DDR_SDQ1 AJ14 MEMDATA2 MEMADDB_B11 M4
DDR_SDQ0 AJ16 MEMDATA1 MEMADDB_B10 AD5
MEMDATA0 MEMADDB_B9 AC5
R1 MEMADDB_B8 AD4
<8> DDR_SDM[0..7] MEMDQS17 MEMADDB_B7
DDR_SDM7 A13 AA5
DDR_SDM6 A7 MEMDQS16 MEMADDB_B6 AB3
DDR_SDM5 C2 MEMDQS15 MEMADDB_B5 Y4
DDR_SDM4 H1 MEMDQS14 MEMADDB_B4 W5
DDR_SDM3 AA1 MEMDQS13 MEMADDB_B3 U5
DDR_SDM2 AG1 MEMDQS12 MEMADDB_B2 T4
DDR_SDM1 AH7 MEMDQS11 MEMADDB_B1 M3
DDR_SDM0 AH13 MEMDQS10 MEMADDB_B0
T1 MEMDQS9
<8> DDR_SDQS[0..7] MEMDQS8
DDR_SDQS7 A14 N3
DDR_SDQS6 A8 MEMDQS7 MEMCHECK7 N1
DDR_SDQS5 D1 MEMDQS6 MEMCHECK6 U3
DDR_SDQS4 J1 MEMDQS5 MEMCHECK5 V1
DDR_SDQS3 AB1 MEMDQS4 MEMCHECK4 N2
DDR_SDQS2 AJ2 MEMDQS3 MEMCHECK3 P1
DDR_SDQS1 AJ8 MEMDQS2 MEMCHECK2 U1
DDR_SDQS0 AJ13 MEMDQS1 MEMCHECK1 U2
MEMDQS0 MEMCHECK0

4 4
FOX_PZ75403-2941-42

Title
Compal Electronics, Inc.
Claw Harmmer (MEMORY BUS)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 5 of 50
A B C D E
A B C D E

+1.25V Near Power Supply +1.25V Near Socket


470U_D2_2.5VM @220U_D2_2.5VM 100U_D2_10VM
U1C 1 1 1 1 1 1
TP_M_RESET# + C13 + C14 + C15 + C16 + C17 + C18
Claw Hammer-DTR AG10
NC E14
H_THERMTRIP# A20 NC D12
<11> H_THERMTRIP# THERMTRIP_L NC 2 2 2 2 2 2
Miscellaneous E13
1 H_RST# AF20 NC C12 470U_D2_2.5VM 330U_D_2VM_R15 100U_D2_10VM 1
<11> H_RST# RESET_L NC D22 TP_K8_D22
C20 H_PWRGD AE18 NC C22 TP_K8_C22 +1.25V
<11> H_PWRGD PWROK NC
3900P_0402_50V7K B13 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K
2 1 CLKIN AJ21 NC B7
<11> CPU_CLK 1 1 1 1 1 1 1 1 1

1
CLKIN# AH21 CLKIN_H NC C3 C21 C22 C23 C24 C25 C26 C27 C28 C29
R28 2 1 FBCLKOUT AH19 CLKIN_L NC K1 H_PWRGD
Clock
169_0402_1% R29 80.6_0402_1% FBCLKOUT# AJ19 FBCLKOUT_H NC R2
FBCLKOUT_L NC AA3 2 2 2 2 2 2 2 2 2
1
2 1 Place within 0.5" from CPU NC F3 C793 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K
2
<11> CPU_CLK# NC
Route as 80 Ohm DIFF impedence 8/5/20 C23
C30 3900P_0402_50V7K NC AG7 470P_0402_50V7K +1.25V
COREFB A23 NC AE22 2 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K
<44> COREFB COREFB_H NC
Place 169 Ohm within 0.5" from CPU COREFB# A24 C24 1 1 1 1 1 1 1 1 1
<44> COREFB# COREFB_L NC
Route as DIF 5/5/5/20 B23 A25 C31 C32 C33 C34 C35 C36 C37 C38 C39
Route as DIFF pair 10/5/10 CORE_SENSE NC C9
AE12 NC AE23 CLAW_ANALOG3
AF12 VDDIOFB_H NC AF23 CLAW_ANALOG2 2 2 2 2 2 2 2 2 2
L1 VDDIO_SENSE AE11 VDDIOFB_L NC AF22 CLAW_ANALOG1 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K
VDDIO_SENSE VDDIO_SENSE NC
LQG21F4R7N00_0805 AF21 CLAW_ANALOG0
+2.5VDDA 1 2 3300P_0402_50V7K +VDDA 50 mils width AH25 NC C1
1 AJ25 VDDA1 NC J3
VDDA2 NC R3
1 1 1
+ C40 C41 C42 C43 VID4 AG13 NC AA2
<44> VID4 VID4 NC
VID3 AF14 D3
<44> VID3 VID3 NC
100U_D2_10VM VID2 AG14 AG2
2 2 2 2 <44> VID2
VID1 AF15 VID2 NC B18
<44> VID1 VID1 NC
4.7U_0805_6.3V6K 0.22U_0603_10V7K VID0 AE15 AH1
<44> VID0 VID0 NC AE21
2 NC C20 2
DBRDY AH17 NC AG4
DBREQ# AE19 DBRDY NC C6
DBREQ_L Debug NC AG6
NC AE9
NC AG9 +2.5V U39
NC AF18
NC AJ23 BPSCLK R30 1 2 820_0402_5% +3VS 1 5 +2.5VDDA
NC AH23 BPSCLK# R31 1 2 820_0402_5% VIN VOUT
1 1
A26 NC AE24 TP_K8_AE24 C734 2 C735
<4> THERMDA_CPU THERMDA NC GND
A27 AF24 TP_K8_AF24
<4> THERMDC_CPU THERMDC NC C15 TP_K8_C15 1U_0603_10V6K 3 4 1U_0603_10V6K
+2.5VS NC AG18 TP_CPU_BP3 2 SD# BP 1 2
NC AH18 TP_CPU_BP2 C736
2 1 H_THERMTRIP# NC AG17 BP1 R32 1 2 680_0402_5% SI9183_SOT23-5
R37 1K_0402_5% NC AJ18 BP0 R33 1 2 680_0402_5% 0.01U_0402_16V7K
2 1 H_RST# TDO A22 NC C18 SINCHN R34 1 2 680_0402_5% 2
TDO NC <11,44> VR_ON
R38 330_0402_5% TMS E20 A19 BRN# R35 1 2 680_0402_5% +2.5VS
2 1 H_PWRGD TCK E17 TMS NC D20 SCANCLK1
R39 330_0402_5% TRST# B21 TCK NC C21 SCANCLK2
TRST_L JTAG NC
TDI A21 D18 SCANEN
TDI NC C19 SCANSHENB
NC B19 SCANSHENA R36 1 2 680_0402_5%
NC
0.22U_0603_10V7K 4.7U_0805_6.3V6K D29 AH29
VLDT0_A VLDT0_B +1.2V_HT
D27 AH27
H_RST# D25 VLDT0_A VLDT0_B AG28
1 1 1
C63 C64 C68 C28 VLDT0_A VLDT0_B AG26
C26 VLDT0_A VLDT0_B AF29
3
R563 B29 VLDT0_A VLDT0_B AE28
3
2 2 2 B27 VLDT0_A VLDT0_B AF25 RP1
@100_0402_5% 0.22U_0603_10V7K VLDT0_A VLDT0_B SCANCLK2 4 5
+1.25V D17 AG15 +1.25V SCANCLK1 3 6
A18 VTT_A VTT_B AF16 SCANEN 2 7
2

J3 B17 VTT_A VTT_B AG16 SCANSHENB 1 8


C17 VTT_A VTT_B AH16
JOPEN C16 VTT_A VTT_B AJ17 680_1206_8P4R_5%
1

VTT_A VTT_B AE13 VTT_SENSE


VTT_SENSE VTT_SENSE
TP_K8_A28 A28
TP_K8_AJ28 AJ28 KEY1
KEY0
FOX_PZ75403-2941-42

+2.5VS +1.2V_HT

@560_0402_5% @560_0402_5% 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K


R41 R44 250 mil
1
R46 1 1 1 1 1 1
1

@560_0402_5% + C59 C60 C61 C62 C65 C66 C67

R40 R43 +2.5VS


@560_0402_5%
@ @560_0402_5%
@ @ @ @ JP3 2 2 2 2 2 2 2
@ @ 100U_D2_10VM 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K
2

R42 R45 1 2
@560_0402_5% @560_0402_5% 3 4
DBREQ# 5 6
DBRDY 7 8
4 9 10 4
TCK
TMS 11 12
TDI 13 14
TRST# 15 16
TDO 17 18
19 20
21
23
22
24 Title
Compal Electronics, Inc.
26
ClawHarmmer ( MISC )
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
@SAMTEC_ASP-68200-07 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.5
@ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 6 of 50
A B C D E
A B C D E

U1E
B2 L28
AH20 VSS VSS R28
AB21 VSS VSS W28
W22 VSS VSS AC28
+CPU_CORE +2.5V M23 VSS VSS AF28
L24 VSS VSS AH28
U1D AG25 VSS VSS C29
L7 E4 AG27 VSS VSS F2 +CPU_CORE
AC15 VDD VDDIO G4 D2 VSS VSS H2
H18 VDD VDDIO J4 AF2 VSS VSS K2 330U_D_2VM_R15 330U_D_2VM_R15 330U_D_2VM_R15 330U_D_2VM_R15
B20 VDD VDDIO L4 W6 VSS VSS M2 1 1 1 1 1 1 1 1 1
E21 VDD VDDIO N4 Y7 VSS VSS P2
1 H22 VDD VDDIO U4 AA8 VSS VSS T2 + C69 + C70 + C71 + C72 + C73 + C74 + C76 + C77 + C78 1
J23 VDD VDDIO W4 AB9 VSS VSS V2
H24 VDD VDDIO AA4 AA10 VSS VSS Y2
F26 VDD VDDIO AC4 J12 VSS VSS AB2 2 2 2 2 2 2 2 2 2
N7 VDD VDDIO AE4 B14 VSS VSS AD2 330U_D_2VM_R15 330U_D_2VM_R15 330U_D_2VM_R15 @330U_D_2VM_R15 @330U_D_2VM_R15
L9 VDD VDDIO D5 Y15 VSS VSS AH2
V10 VDD VDDIO AF5 AE16 VSS VSS B4 +CPU_CORE
G13 VDD VDDIO F6 J18 VSS VSS AH4
K14 VDD VDDIO H6 G20 VSS VSS B6 @330U_D_2VM_R15 @330U_D_2VM_R15 @330U_D_2VM_R15 @330U_D_2VM_R15
Y14 VDD VDDIO K6 R20 VSS VSS G6 1 1 1 1 1 1 1 1 1
AB14 VDD VDDIO M6 U20 VSS VSS J6
G15 VDD VDDIO P6 W20 VSS VSS L6 + C79 + C80 + C81 + C82 + C83 + C84 + C85 + C86 + C87
J15 VDD VDDIO T6 AA20 VSS VSS N6
AA15 VDD VDDIO V6 AC20 VSS VSS R6
H16 VDD VDDIO Y6 AE20 VSS VSS U6 2 2 2 2 2 2 2 2 2
K16 VDD VDDIO AB6 AG20 VSS VSS AA6 @330U_D_2VM_R15 330U_D_2VM_R15 @330U_D_2VM_R15 @330U_D_2VM_R15 @330U_D_2VM_R15
Y16 VDD VDDIO AD6 AJ20 VSS VSS AC6
AB16 VDD VDDIO D7 D21 VSS VSS AH6
G17 VDD VDDIO G7 F21 VSS VSS F7 +CPU_CORE +CPU_CORE
J17 VDD VDDIO J7 H21 VSS VSS H7 10U_1206_6.3V7K 10U_1206_6.3V7K 10U_1206_6.3V7K
AA17 VDD VDDIO AA7 K21 VSS VSS K7 1 1 1 1 1 1 1 1
AC17 VDD VDDIO AC7 M21 VSS VSS M7 C89 C90 C91 C92 C93 C94 C95 C110
AE17 VDD VDDIO AF7 P21 VSS VSS P7
F18 VDD VDDIO F8 T21 VSS VSS T7 1000P_0402_50V7K 0.1U_0402_10V6K
K18 VDD VDDIO H8 V21 VSS VSS V7 2 2 2 2 2 2 2 2
Y18 VDD VDDIO AB8 Y21 VSS VSS AB7 10U_1206_6.3V7K 10U_1206_6.3V7K 10U_1206_6.3V7K
AB18 VDD VDDIO AD8 AD21 VSS VSS AD7
VDD VDDIO VSS VSS 4 in Socket Cavity,
AD18 D9 AG21 B8
AG19 VDD VDDIO G9 B22 VSS VSS G8 2 on backside under Socket
2 E19 VDD VDDIO AC9 E22 VSS VSS J8 2
G19 VDD VDDIO AF9 G22 VSS VSS L8

POWER
AC19 VDD VDDIO F10 J22 VSS VSS N8
AA19 VDD VDDIO AD10 L22 VSS VSS R8 +CPU_CORE +CPU_CORE
J19 VDD VDDIO D11 N22 VSS VSS U8 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K
F20 VDD VDDIO AF11 R22 VSS VSS W8 1 1 1 1 1 1 1 1 1 1 1 1 1
H20 VDD VDDIO F12 U22 VSS VSS AC8 C97 C98 C99 C100 C101 C102 C103 C104 C105 C106 C107 C108 C109
K20 VDD VDDIO AD12 AG29 VSS VSS AH8
M20 VDD VDDIO D13 AA22 VSS VSS F9
P20 VDD VDDIO AF13 AC22 VSS VSS H9 2 2 2 2 2 2 2 2 2 2 2 2 2
T20 VDD VDDIO F14 AG22 VSS VSS K9 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K
V20 VDD VDDIO AD14 AH22 VSS VSS M9
Y20 VDD VDDIO F16 AJ22 VSS VSS P9
Close to Socket In Socket Cavity
POWER

AB20 VDD VDDIO AD16 D23 VSS VSS T9


AD20 VDD VDDIO D15 F23 VSS VSS V9
G21 VDD VDDIO R4 H23 VSS VSS Y9
J21 VDD VDDIO +CPU_CORE K23 VSS VSS AD9
VDD VSS VSS Loop Bandwidth Bulk Cappacitance Total
L21 N28 P23 B10
N21 VDD VDD U28 T23 VSS VSS G10 KHz uF ESR
R21 VDD VDD AA28 V23 VSS VSS J10
VDD VDD VSS VSS 2.5m ohm
U21 AE27 Y23 L10
W21 VDD
VDD
VDD
VDD
R7 AB23 VSS
VSS
VSS
VSS
N10 20 23000 (AMD)
AA21 U7 AD23 R10
AC21 VDD VDD W7 AG23 VSS VSS U10 CPU Decouping Capacitor 0.9m ohm
F22 VDD
VDD
VDD
VDD
K8 E24 VSS
VSS
VSS
VSS
W10 50 9000
K22 M8 G24 AC10
M22 VDD VDD P8 J24 VSS VSS AH10
VDD VDD VSS VSS * 300 3300 1.5m ohm
P22 T8 N24 F11
T22 VDD VDD V8 R24 VSS VSS H11
3
V22 VDD VDD Y8 U24 VSS VSS K11
3

Y22 VDD VDD J9 W24 VSS VSS Y11


AB22 VDD VDD N9 AA24 VSS VSS AB11
AD22 VDD VDD R9 AC24 VSS VSS AD11
E23 VDD VDD U9 AG24 VSS VSS B12
G23 VDD VDD W9 AJ24 VSS VSS G12
L23 VDD VDD AA9 B25 VSS VSS AA12
N23 VDD VDD H10 C25 VSS VSS AC12
R23 VDD VDD K10 B26 VSS VSS AH12
U23 VDD VDD M10 D26 VSS VSS F13
W23 VDD VDD P10 H26 VSS VSS H13 +2.5V +2.5V
AA23 VDD VDD T10 M26 VSS VSS K13
AC23 VDD VDD Y10 T26 VSS VSS Y13 4.7U_0805_6.3V6K 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K
B24 VDD VDD AB10 Y26 VSS VSS AB13 1 1 1 1 1 1 1 1
D24 VDD VDD G11 AD26 VSS VSS AD13 C111 C112 C113 C114 C115 C116 C117 C118
F24 VDD VDD J11 AF26 VSS VSS AF17
K24 VDD VDD AA11 AH26 VSS VSS G14
M24 VDD VDD AC11 C27 VSS VSS J14 2 2 2 2 2 2 2 2
P24 VDD VDD H12 B28 VSS VSS AA14 4.7U_0805_6.3V6K 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K
T24 VDD VDD K12 D28 VSS VSS AC14
V24 VDD VDD Y12 G28 VSS VSS AE14
VDD VDD VSS VSS Near Socket
Y24 AB12 F15 D16
AB24 VDD VDD J13 H15 VSS VSS E15
AD24 VDD VDD AA13 AB17 VSS VSS K15
AH24 VDD VDD AC13 AD17 VSS VSS AB15
AE25 VDD VDD H14 B16 VSS VSS AD15
K26 VDD VDD AB26 G18 VSS VSS AH14
P26 VDD VDD E28 AA18 VSS VSS E16
V26 VDD VDD J28 AC18 VSS VSS G16
4 VDD VDD VSS VSS 4
D19 J16
F19 VSS VSS AA16
H19 VSS VSS AC16
FOX_PZ75403-2941-42 K19 VSS VSS AE29
Y19 VSS VSS AJ26
AB19 VSS VSS E18
AD19 VSS
VSS
VSS
VSS
F17
Title
Compal Electronics, Inc.
AF19 H17
VSS VSS
J20
L20 VSS VSS
K17
Y17
Claw Harmmer (Power & Ground)
VSS VSS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N20 Size Document Number Rev
VSS AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.5
FOX_PZ75403-2941-42
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 7 of 50
A B C D E
A B C D E F G H

+2.5V

RP2 RP3 +2.5V


JP4
DDR_SDQ1 1 8 DDR_DQ1 DDR_SDQ37 1 8 DDR_DQ37 1 2 20mil
VREF VREF +1.25VREF_MEM
DDR_SDQ5 2 7 DDR_DQ5 DDR_SDQ32 2 7 DDR_DQ32 3 4 1
DDR_SDQ4 3 6 DDR_DQ4 DDR_SDQ36 3 6 DDR_DQ36 DDR_DQ5 5 VSS VSS 6 DDR_DQ0
DDR_SDQ0 4 5 DDR_DQ0 DDR_SDQ33 4 5 DDR_DQ33 DDR_DQ1 7 DQ0 DQ4 8 DDR_DQ4 C119
9 DQ1 DQ5 10 0.1U_0402_10V6K
10_0804_8P4R_5% 10_0804_8P4R_5% DDR_DQS0 11 VDD VDD 12 DDR_DM0 2
DDR_DQ2 13 DQS0 DM0 14 DDR_DQ7
RP4 RP5 15 DQ2 DQ6 16
DDR_SDQS0 1 4 DDR_DQS0 DDR_SDQS4 1 4 DDR_DQS4 DDR_DQ6 17 VSS VSS 18 DDR_DQ3
1 DDR_SDM0 2 3 DDR_DM0 DDR_SDM4 2 3 DDR_DM4 DDR_DQ8 19 DQ3 DQ7 20 DDR_DQ12 DDR_DQ[0..63] 1
DQ8 DQ12 DDR_DQ[0..63] <9>
21 22
10_0404_4P2R_5% 10_0404_4P2R_5% DDR_DQ9 23 VDD VDD 24 DDR_DQ13 DDR_DQS[0..7]
DQ9 DQ13 DDR_DQS[0..7] <9>
RP6 RP7 DDR_DQS1 25 26 DDR_DM1
27 DQS1 DM1 28 DDR_DM[0..7]
VSS VSS DDR_DM[0..7] <9>
DDR_SDQ6 1 8 DDR_DQ6 DDR_SDQ38 1 8 DDR_DQ38 DDR_DQ14 29 30 DDR_DQ10
DDR_SDQ3 2 7 DDR_DQ3 DDR_SDQ34 2 7 DDR_DQ34 DDR_DQ15 31 DQ10 DQ14 32 DDR_DQ11
DDR_SDQ7 3 6 DDR_DQ7 DDR_SDQ35 3 6 DDR_DQ35 33 DQ11 DQ15 34
DDR_SDQ2 4 5 DDR_DQ2 DDR_SDQ39 4 5 DDR_DQ39 35 VDD VDD 36
<5> DDR_CLK5 CK0 VDD
<5> DDR_CLK5#
37 38
10_0804_8P4R_5% 10_0804_8P4R_5% 39 CK0# VSS 40
RP8 RP9 VSS VSS

DDR_SDQ13 1 8 DDR_DQ13 DDR_SDQ44 1 8 DDR_DQ44 DDR_DQ20 41 42 DDR_DQ17


DDR_SDQ9 2 7 DDR_DQ9 DDR_SDQ40 2 7 DDR_DQ40 DDR_DQ16 43 DQ16 DQ20 44 DDR_DQ21
DDR_SDQ8 3 6 DDR_DQ8 DDR_SDQ41 3 6 DDR_DQ41 45 DQ17 DQ21 46
DDR_SDQ12 4 5 DDR_DQ12 DDR_SDQ45 4 5 DDR_DQ45 DDR_DQS2 47 VDD VDD 48 DDR_DM2
DDR_DQ18 49 DQS2 DM2 50 DDR_DQ19
10_0804_8P4R_5% 10_0804_8P4R_5% 51 DQ18 DQ22 52
DDR_DQ22 53 VSS VSS 54 DDR_DQ23
RP10 RP11 DDR_DQ24 55 DQ19 DQ23 56 DDR_DQ29
DDR_SDQS1 1 4 DDR_DQS1 DDR_SDQS5 1 4 DDR_DQS5 57 DQ24 DQ28 58
DDR_SDM1 2 3 DDR_DM1 DDR_SDM5 2 3 DDR_DM5 DDR_DQ28 59 VDD VDD 60 DDR_DQ25
DDR_DQS3 61 DQ25 DQ29 62 DDR_DM3
10_0404_4P2R_5% 10_0404_4P2R_5% 63 DQS3 DM3 64
RP12 RP13 DDR_DQ26 65 VSS VSS 66 DDR_DQ27
DDR_DQ30 67 DQ26 DQ30 68 DDR_DQ31
DDR_SDQ15 1 8 DDR_DQ15 DDR_SDQ46 1 8 DDR_DQ46 69 DQ27 DQ31 70
DDR_SDQ14 2 7 DDR_DQ14 DDR_SDQ42 2 7 DDR_DQ42 71 VDD VDD 72
2 DDR_SDQ11 3 6 DDR_DQ11 DDR_SDQ47 3 6 DDR_DQ47 73 CB0 CB4 74 2
DDR_SDQ10 4 5 DDR_DQ10 DDR_SDQ43 4 5 DDR_DQ43 75 CB1 CB5 76
77 VSS VSS 78
10_0804_8P4R_5% 10_0804_8P4R_5% 79 DQS8 DM8 80
RP14 RP15 81 CB2 CB6 82
83 VDD VDD 84
DDR_SDQ19 1 8 DDR_DQ19 DDR_SDQ49 1 8 DDR_DQ49 85 CB3 CB7 86
DDR_SDQ20 DDR_DQ20 DDR_SDQ48 DDR_DQ48
Note: DU DU/RESET#
2 7 2 7 87 88
DDR_SDQ21 3 6 DDR_DQ21 DDR_SDQ53 3 6 DDR_DQ53 DDR_SMAA13 Recommend for AMD 89 VSS VSS 90
DDR_SDQ17 4 5 DDR_DQ17 DDR_SDQ52 4 5 DDR_DQ52 91 CK2 VSS 92
93 CK2# VDD 94
10_0804_8P4R_5% 10_0804_8P4R_5% DDR_CKE0_SR 95 VDD VDD 96 DDR_CKE0_SR
97 CKE1 CKE0 98
RP16 RP17 DDR_SMAA12 99 DU/A13 DU/BA2 100 DDR_SMAA11
DDR_SDQS2 1 4 DDR_DQS2 DDR_SDQS6 1 4 DDR_DQS6 DDR_SMAA9 101 A12 A11 102 DDR_SMAA8
DDR_SDM2 2 3 DDR_DM2 DDR_SDM6 2 3 DDR_DM6 103 A9 A8 104
DDR_SMAA7 105 VSS VSS 106 DDR_SMAA6
10_0404_4P2R_5% 10_0404_4P2R_5% DDR_SMAA5 107 A7 A6 108 DDR_SMAA4
RP18 RP19 DDR_SMAA3 109 A5 A4 110 DDR_SMAA2
DDR_SMAA1 111 A3 A2 112 DDR_SMAA0
DDR_SDQ22 1 8 DDR_DQ22 DDR_SDQ55 1 8 DDR_DQ55 113 A1 A0 114
DDR_SDQ18 2 7 DDR_DQ18 DDR_SDQ54 2 7 DDR_DQ54 DDR_SMAA10 115 VDD VDD 116 DDR_SBSA1
DDR_SDQ16 DDR_DQ16 DDR_SDQ50 DDR_DQ50 DDR_SBSA0 A10/AP BA1 DDR_SRASA# DDR_SBSA1 <5,9>
3 6 3 6 <5,9> DDR_SBSA0
117 118 DDR_SRASA# <5,9>
DDR_SDQ23 4 5 DDR_DQ23 DDR_SDQ51 4 5 DDR_DQ51 DDR_SWEA# 119 BA0 RAS# 120 DDR_SCASA#
<5,9> DDR_SWEA# WE# CAS# DDR_SCASA# <5,9>
DDR_SCS#0 121 122 DDR_SCS#1
<5,9> DDR_SCS#0 S0# S1# DDR_SCS#1 <5,9>
10_0804_8P4R_5% 10_0804_8P4R_5% DDR_SMAA13 123 124
RP20 RP21 125 DU DU 126
DDR_DQ33 127 VSS VSS 128 DDR_DQ32
DDR_SDQ28 1 8 DDR_DQ28 DDR_SDQ56 1 8 DDR_DQ56 DDR_DQ36 129 DQ32 DQ36 130 DDR_DQ37
3
DDR_SDQ24 2 7 DDR_DQ24 DDR_SDQ60 2 7 DDR_DQ60 131 DQ33 DQ37 132
3
DDR_SDQ25 3 6 DDR_DQ25 DDR_SDQ57 3 6 DDR_DQ57 DDR_DQS4 133 VDD VDD 134 DDR_DM4
DDR_SDQ29 4 5 DDR_DQ29 DDR_SDQ61 4 5 DDR_DQ61 DDR_DQ34 135 DQS4 DM4 136 DDR_DQ39
137 DQ34 DQ38 138
10_0804_8P4R_5% 10_0804_8P4R_5% DDR_DQ38 139 VSS VSS 140 DDR_DQ35
DDR_DQ40 141 DQ35 DQ39 142 DDR_DQ45
RP22 RP23 143 DQ40 DQ44 144
DDR_SDQS3 1 4 DDR_DQS3 DDR_SDQS7 1 4 DDR_DQS7 DDR_DQ44 145 VDD VDD 146 DDR_DQ41
DDR_SDM3 2 3 DDR_DM3 DDR_SDM7 2 3 DDR_DM7 DDR_DQS5 147 DQ41 DQ45 148 DDR_DM5
149 DQS5 DM5 150
10_0404_4P2R_5% 10_0404_4P2R_5% DDR_DQ42 151 VSS VSS 152 DDR_DQ43
RP24 RP25 DDR_DQ46 153 DQ42 DQ46 154 DDR_DQ47
Layout note DQ43 DQ47
155 156
DDR_SDQ30 1 8 DDR_DQ30 DDR_SDQ58 1 8 DDR_DQ58 157 VDD VDD 158
Place these resistors VDD CK1# DDR_CLK7# <5>
DDR_SDQ26 2 7 DDR_DQ26 DDR_SDQ63 2 7 DDR_DQ63 159 160
close to DIMM0, VSS CK1 DDR_CLK7 <5>
DDR_SDQ31 3 6 DDR_DQ31 DDR_SDQ59 3 6 DDR_DQ59 161 162
DDR_SDQ27 4 5 DDR_DQ27 DDR_SDQ62 4 5 DDR_DQ62 DDR_DQ48 163 VSS VSS 164 DDR_DQ52
all trace length<500 mil DQ48 DQ52
DDR_DQ49 165 166 DDR_DQ53
10_0804_8P4R_5% 10_0804_8P4R_5% 167 DQ49 DQ53 168
DDR_DQS6 169 VDD VDD 170 DDR_DM6
DDR_DQ54 171 DQS6 DM6 172 DDR_DQ51
173 DQ50 DQ54 174
DDR_DQ55 175 VSS VSS 176 DDR_DQ50
DDR_SDQS[0..7] DDR_DQ60 177 DQ51 DQ55 178 DDR_DQ61
<5> DDR_SDQS[0..7] DQ56 DQ60
179 180
DDR_SDQ[0..63] DDR_DQ56 181 VDD VDD 182 DDR_DQ57
<5> DDR_SDQ[0..63] DQ57 DQ61
1 2 DDR_CKE0_SR DDR_DQS7 183 184 DDR_DM7
<5> DDR_CKE0 DDR_CKE0_SR <9> DQS7 DM7
DDR_SDM[0..7] R47 10_0402_5% 185 186
<5> DDR_SDM[0..7] VSS VSS
DDR_DQ63 187 188 DDR_DQ62
4 DQ58 DQ62 4
DDR_SMAA[0..13] 1 2 DDR_CKE1_SR DDR_DQ58 189 190 DDR_DQ59
<5,9> DDR_SMAA[0..13] <5> DDR_CKE1 DDR_CKE1_SR <9> DQ59 DQ63
R48 10_0402_5% 191 192
193 VDD VDD 194
<9,12> DIMM_SMDATA SDA SA0
<9,12> DIMM_SMCLK 195 196
197 SCL SA1 198
+3VS VDD_SPD SA2
199 200
VDD_ID DU
Title
Compal Electronics, Inc.
AMP_1565918-1
DDR-SODIMM SLOT0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
SO-DIMM0 Size
Custom
Document Number Rev
0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS REVERSE LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 8 of 50
A B C D E F G H
A B C D E

+2.5V +2.5V
+1.25VREF_MEM
JP5
+1.25V +1.25V 1 2 50 mil width
3 VREF VREF 4 1
RP27 RP28 RP29 DDR_DQ0 5 VSS VSS 6 DDR_DQ5 +1.25V
DDR_DQ4 7 DQ0 DQ4 8 DDR_DQ1 C120 RP26
DDR_DQ0 8 1 1 8 DDR_DQ29 1 8 DDR_DQ52 9 DQ1 DQ5 10 0.1U_0402_10V6K DDR_SMAA7 8 1
DDR_DQ5 7 2 2 7 DDR_DQ24 2 7 DDR_DQ48 DDR_DQS0 11 VDD VDD 12 DDR_DM0 2 DDR_SMAA9 7 2
DDR_DQ4 6 3 3 6 DDR_DQ25 3 6 DDR_DQ53 DDR_DQ7 13 DQS0 DM0 14 DDR_DQ2 DDR_SMAA12 6 3
DDR_DQ1 5 4 4 5 DDR_DQ28 4 5 DDR_DQ49 15 DQ2 DQ6 16 DDR_SMAA11 5 4
DDR_DQ3 17 VSS VSS 18 DDR_DQ6
68_0804_8P4R_5% 68_0804_8P4R_5% 68_0804_8P4R_5% DDR_DQ12 19 DQ3 DQ7 20 DDR_DQ8 47_0804_8P4R_5%
1 21 DQ8 DQ12 22 1
RP31 RP32 RP33 DDR_DQ13 23 VDD VDD 24 DDR_DQ9 RP30
DDR_DM0 4 1 1 4 DDR_DM3 1 4 DDR_DM6 DDR_DQS1 25 DQ9 DQ13 26 DDR_DM1 DDR_SMAA4 8 1
DDR_DQS0 3 2 2 3 DDR_DQS3 2 3 DDR_DQS6 27 DQS1 DM1 28 DDR_SMAA6 7 2
DDR_DQ10 29 VSS VSS 30 DDR_DQ14 DDR_SMAA5 6 3
68_0402_4P2R_5% 68_0402_4P2R_5% 68_0402_4P2R_5% DDR_DQ11 31 DQ10 DQ14 32 DDR_DQ15 DDR_SMAA8 5 4
RP35 RP36 RP37 33 DQ11 DQ15 34
35 VDD VDD 36 47_0804_8P4R_5%
<5> DDR_CLK4 CK0 VDD
DDR_DQ7 8 1 1 8 DDR_DQ27 1 8 DDR_DQ51 37 38
<5> DDR_CLK4# CK0# VSS
DDR_DQ2 7 2 2 7 DDR_DQ31 2 7 DDR_DQ54 39 40 RP34
DDR_DQ3 6 3 3 6 DDR_DQ26 3 6 DDR_DQ50 VSS VSS DDR_SMAA0 8 1
DDR_DQ6 5 4 4 5 DDR_DQ30 4 5 DDR_DQ55 DDR_SMAA2 7 2
DDR_DQ17 41 42 DDR_DQ20 DDR_SMAA1 6 3
68_0804_8P4R_5% 68_0804_8P4R_5% 68_0804_8P4R_5% DDR_DQ21 43 DQ16 DQ20 44 DDR_DQ16 DDR_SMAA3 5 4
RP39 RP40 RP41 45 DQ17 DQ21 46
DDR_DQS2 47 VDD VDD 48 DDR_DM2 47_0804_8P4R_5%
DDR_DQ12 8 1 1 8 DDR_DQ32 1 8 DDR_DQ61 DDR_DQ19 49 DQS2 DM2 50 DDR_DQ18
DDR_DQ13 7 2 2 7 DDR_DQ33 2 7 DDR_DQ57 51 DQ18 DQ22 52
DDR_DQ8 6 3 3 6 DDR_DQ36 3 6 DDR_DQ60 DDR_DQ23 53 VSS VSS 54 DDR_DQ22 DDR_SMAA13 1 2
DDR_DQ9 5 4 4 5 DDR_DQ37 4 5 DDR_DQ56 DDR_DQ29 55 DQ19 DQ23 56 DDR_DQ24 R479 47_0402_5%
57 DQ24 DQ28 58 DDR_SMAA10 1 2
68_0804_8P4R_5% 68_0804_8P4R_5% 68_0804_8P4R_5% DDR_DQ25 59 VDD VDD 60 DDR_DQ28 R480 47_0402_5%
DDR_DQS3 61 DQ25 DQ29 62 DDR_DM3
RP43 RP44 RP45 63 DQS3 DM3 64 RP42
DDR_DM1 4 1 1 4 DDR_DQS4 1 4 DDR_DQS7 DDR_DQ27 65 VSS VSS 66 DDR_DQ26 DDR_SCS#1 8 1
DQ26 DQ30 <5,8> DDR_SCS#1
DDR_DQS1 3 2 2 3 DDR_DM4 2 3 DDR_DM7 DDR_DQ31 67 68 DDR_DQ30 DDR_SCS#3 7 2
69 DQ27 DQ31 70 DDR_SCASA# 6 3
68_0402_4P2R_5% 68_0402_4P2R_5% 68_0402_4P2R_5% 71 VDD VDD 72 DDR_SCS#0 5 4
CB0 CB4 <5,8> DDR_SCS#0
RP47 RP48 RP49 73 74
2 75 CB1 CB5 76 47_0804_8P4R_5% 2
DDR_DQ10 8 1 1 8 DDR_DQ34 1 8 DDR_DQ63 77 VSS VSS 78
DDR_DQ11 7 2 2 7 DDR_DQ39 2 7 DDR_DQ58 79 DQS8 DM8 80 RP46
DDR_DQ14 6 3 3 6 DDR_DQ38 3 6 DDR_DQ62 81 CB2 CB6 82 DDR_SCS#2 8 1
DDR_DQ15 5 4 4 5 DDR_DQ35 4 5 DDR_DQ59 83 VDD VDD 84 DDR_SWEA# 7 2
85 CB3 CB7 86 DDR_SBSA0 6 3
68_0804_8P4R_5% 68_0804_8P4R_5% 68_0804_8P4R_5% 87 DU DU/RESET# 88 DDR_SRASA# 5 4
RP51 RP52 89 VSS VSS 90
91 CK2 VSS 92 47_0804_8P4R_5%
DDR_DQ17 8 1 1 8 DDR_DQ45 93 CK2# VDD 94
DDR_DQ20 7 2 2 7 DDR_DQ40 DDR_CKE1_SR 95 VDD VDD 96 DDR_CKE1_SR
<8> DDR_CKE1_SR CKE1 CKE0
DDR_DQ21 6 3 3 6 DDR_DQ41 97 98 DDR_SBSA1 1 2
DDR_DQ16 5 4 4 5 DDR_DQ44 DDR_SMAA12 99 DU/A13 DU/BA2 100 DDR_SMAA11 R481 47_0402_5%
DDR_SMAA9 101 A12 A11 102 DDR_SMAA8
Note: A9 A8
68_0804_8P4R_5% 68_0804_8P4R_5% Layout note 103 104 DDR_CKE0_SR 1 2
DDR_SMAA13 Recommend VSS VSS <8> DDR_CKE0_SR
DDR_SMAA7 105 106 DDR_SMAA6 R482 68_0402_5%
RP54 RP55 for AMD. DDR_SMAA5 107 A7 A6 108 DDR_SMAA4
Place these resistor A5 A4
DDR_DQS2 4 1 1 4 DDR_DQS5 DDR_SMAA3 109 110 DDR_SMAA2 DDR_CKE1_SR 1 2
DDR_DM2 3 2 2 3 DDR_DM5 closely DIMM1, DDR_SMAA1 111 A3 A2 112 DDR_SMAA0 R483 68_0402_5%
all trace 113 A1 A0 114
68_0402_4P2R_5% 68_0402_4P2R_5% DDR_SMAA10 115 VDD VDD 116 DDR_SBSA1
RP57 RP58
length<=800mil DDR_SBSA0 A10/AP BA1 DDR_SRASA#
DDR_SBSA1 <5,8>
<5,8> DDR_SBSA0
117 118 DDR_SRASA# <5,8>
DDR_SWEA# 119 BA0 RAS# 120 DDR_SCASA#
<5,8> DDR_SWEA# WE# CAS# DDR_SCASA# <5,8>
DDR_DQ19 8 1 1 8 DDR_DQ43 DDR_SCS#2 121 122 DDR_SCS#3
<5> DDR_SCS#2 S0# S1# DDR_SCS#3 <5>
DDR_DQ18 7 2 2 7 DDR_DQ47 DDR_SMAA13 123 124
DDR_DQ22 6 3 3 6 DDR_DQ42 125 DU DU 126
DDR_DQ23 5 4 4 5 DDR_DQ46 DDR_DQ32 127 VSS VSS 128 DDR_DQ33
DDR_DQ37 129 DQ32 DQ36 130 DDR_DQ36
68_0804_8P4R_5% 68_0804_8P4R_5% 131 DQ33 DQ37 132
3
DDR_DQS4 133 VDD VDD 134 DDR_DM4
3
DDR_DQ39 135 DQS4 DM4 136 DDR_DQ34
137 DQ34 DQ38 138
DDR_DQ35 139 VSS VSS 140 DDR_DQ38
DDR_DQ45 141 DQ35 DQ39 142 DDR_DQ40
143 DQ40 DQ44 144
DDR_DQ41 145 VDD VDD 146 DDR_DQ44
DDR_DQS5 147 DQ41 DQ45 148 DDR_DM5
149 DQS5 DM5 150
DDR_DQ43 151 VSS VSS 152 DDR_DQ42
DDR_DQ47 153 DQ42 DQ46 154 DDR_DQ46
155 DQ43 DQ47 156
157 VDD VDD 158
VDD CK1# DDR_CLK6# <5>
159 160 DDR_CLK6 <5>
161 VSS CK1 162
+2.5V DDR_DQ52 163 VSS VSS 164 DDR_DQ48
DDR_DQ53 165 DQ48 DQ52 166 DDR_DQ49
DQ49 DQ53 Layout note
167 168
1

R49 DDR_DQS6 169 VDD VDD 170 DDR_DM6


DQS6 DM6 Place these resistor
DDR_DQ51 171 172 DDR_DQ54
100_0402_1% 173 DQ50 DQ54 174 close by DIMM1,
DDR_DQS[0..7] +1.25VREF_MEM DDR_DQ50 175 VSS VSS 176 DDR_DQ55 all trace length
<8> DDR_DQS[0..7] DQ51 DQ55
DDR_DQ61 177 178 DDR_DQ60
Max=0.8"
1 2

DDR_DQ[0..63] 179 DQ56 DQ60 180


<8> DDR_DQ[0..63] VDD VDD
R50 1 1 DDR_DQ57 181 182 DDR_DQ56
DDR_DM[0..7] C122 DDR_DQS7 183 DQ57 DQ61 184 DDR_DM7
<8> DDR_DM[0..7] DQS7 DM7
100_0402_1% C121 185 186
DDR_SMAA[0..13] 1000P_0402_50V7K DDR_DQ62 187 VSS VSS 188 DDR_DQ63
<5,8> DDR_SMAA[0..13] 2 2 DQ58 DQ62
DDR_DQ59 189 190 DDR_DQ58
4 4
2

0.1U_0402_10V6K 191 DQ59 DQ63 192


193 VDD VDD 194
<8,12> DIMM_SMDATA SDA SA0 +3VS
<8,12> DIMM_SMCLK
195 196
197 SCL SA1 198
+3VS 199 VDD_SPD SA2 200
VDD_ID DU

Title
Compal Electronics, Inc.
AMP_1565917-1
DIMM1 DDR-SODIMM SLOT1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
STANDARD Custom
LA-1851 0.5

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 9 of 50
A B C D E
A B C D E

+2.5V

470U_D_4VM @220U_D2_4VM 4.7U_0805_6.3V6K


1 1 1 1
1 1
1
+ C123 + C124 + C125 + C126 C127 C128 1

2 2 2 2 2 2
470U_D_4VM 470U_D_4VM 4.7U_0805_6.3V6K
Near DIMMs

Layout note :
Place one cap close to every 2 pull up resistors termination to
+1.25VS
+1.25V

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K


1 1 1 1 1 1 1 1 1 1 1 1
C131 C132 C133 C134 C135 C136 C137 C138 C139 C140 C141 C142

2 2 2 2 2 2 2 2 2 2 2 2

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K


2 2

+1.25V

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K


1 1 1 1 1 1 1 1 1 1 1 1

C143 C144 C145 C146 C147 C148 C149 C150 C151 C152 C153 C154

2 2 2 2 2 2 2 2 2 2 2 2

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K

+1.25V +1.25V

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 10U_1206_6.3V7K


1 1 1 1 1 1 1 1 1 1
1 1
C155 C156 C157 C158 C159 C160 C161 C162 C163 C164 C165 C166

2 2 2 2 2 2 2 2 2 2
2 2
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 10U_1206_6.3V7K

+1.25V

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K


3 3
1 1 1 1 1 1 1 1 1 1 1 1
C167 C168 C169 C170 C171 C172 C173 C174 C175 C176 C177 C178

2 2 2 2 2 2 2 2 2 2 2 2

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K

+2.5V
+1.25V

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K


1 1 1 1 1 1 1 1 1 1 1 1
C179 C180 C181 C182 C183 C184 C185 C186 C187 C188 C189 C190

2 2 2 2 2 2 2 2 2 2 2 2

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K

+2.5V

+1.25V

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K


1 1 1 1 1 1 1 1 1 1

C191 C192 C193 C194 C195 C196 C197 C198 C199 C200
4 4
2 2 2 2 2 2 2 2 2 2

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K

+2.5V

Title
Compal Electronics, Inc.
DDR SODIMM Decoupling
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 10 of 50
A B C D E
5 4 3 2 1

<4> H_CADOP[0..15] H_CADOP[0..15]


AGP_ADSTBF[0..1] <14>
<4> H_CADON[0..15] H_CADON[0..15]
AGP_ADSTBS[0..1] <14>
<4> H_CADIP[0..15] H_CADIP[0..15]
AGP_AD[0..31] <14>
H_CADIN[0..15]
D <4> H_CADIN[0..15] D
AGP_C/BE#[0..3] <14>

AGP_ST[0..2] <14>

U4A
U4B
H_CADIP0 AP18 AL1 H_CADOP0
H_CADIP1 HT1_TXD0 HT1_RXD0 H_CADOP1
AP17 AM1
H_CADIP2 AN16 HT1_TXD1 HT1_RXD1 AN1 H_CADOP2
H_CADIP3
H_CADIP4
AP15
AN13
HT1_TXD2
HT1_TXD3
HT1_TXD4
HT1_RXD2
HT1_RXD3
HT1_RXD4
AN2
AN4
H_CADOP3
H_CADOP4
CrushK8M/G/GM
H_CADIP5 AP12 AN5 H_CADOP5
H_CADIP6
H_CADIP7
AP11
AN10
HT1_TXD5
HT1_TXD6
HT1_TXD7
CrushK8M/G/GM HT1_RXD5
HT1_RXD6
HT1_RXD7
AN6
AM7
H_CADOP6
H_CADOP7
M33
P32 AGP_SBA0#
AGP_SBA1# AGP_AD0
AA33 AGP_AD0
H_CADIP8 AL18 AM4 H_CADOP8 P33 AA32 AGP_AD1
H_CADIP9 AJ16 HT1_TXD8 HT1_RXD8 AL5 H_CADOP9 N33 AGP_SBA2# AGP_AD1 AB32 AGP_AD2
H_CADIP10 HT1_TXD9 HT1_RXD9 H_CADOP10 AGP_SBA3# AGP_AD2 AGP_AD3
AJ15 AJ5 T33 Y33
H_CADIP11 HT1_TXD10 HT1_RXD10 H_CADOP11 AGP_SBA4# AGP_AD3 AGP_AD4
AL15 AL6 T32 AB33
H_CADIP12 AJ13 HT1_TXD11 HT1_RXD11 AJ7 H_CADOP12 U32 AGP_SBA5# AGP_AD4 Y32 AGP_AD5
H_CADIP13 HT1_TXD12 HT1_RXD12 H_CADOP13 AGP_SBA6# AGP_AD5 AGP_AD6
AL12 AJ8 U33 AC32
H_CADIP14 AJ12 HT1_TXD13 HT1_RXD13 AK10 H_CADOP14 AGP_SBA7# AGP_AD6 W33 AGP_AD7
H_CADIP15
HT1_TXD14 HT1_RXD14 H_CADOP15
AGP_AD7 AGP_AD8
AJ10 AM9 V32
HT1_TXD15 HT1_RXD15 AGP_AD8 AGP_AD9
R33 AE32
R34 AGP_SBSTBF AGP_AD9 AD33 AGP_AD10
H_CADIN0 H_CADON0 AGP_ADSTBF0 AGP_SBSTBS AGP_AD10 AGP_AD11
AN18 AL2 AD32 AF33
H_CADIN1 AN17 HT1_TXD0# HT1_RXD0# AM2 H_CADON1 AGP_ADSTBS0 AC33 AGP_ADSTBF0 AGP_AD11 AE33 AGP_AD12
H_CADIN2 HT1_TXD1# HT1_RXD1# H_CADON2 AGP_ADSTBF1 AGP_ADSTBS0 AGP_AD12 AGP_AD13
AM16 AP1 AB30 AG32
H_CADIN3 AN15
HT1_TXD2#
HT1_TXD3#
HyperTransport Interface
HT1_RXD2#
HT1_RXD3#
AP2 H_CADON3 AGP_ADSTBS1 AC30
AGP_ADSTBF1
AGP_ADSTBS1
AGP_AD13
AGP_AD14
AF32 AGP_AD14
H_CADIN4 AM13 AP4 H_CADON4 AH32 AGP_AD15
H_CADIN5 HT1_TXD4# HT1_RXD4# H_CADON5 AGP_AD15 AGP_AD16
AN12 AP5 AJ30
H_CADIN6 AN11 HT1_TXD5# HT1_RXD5# AP6 H_CADON6 AGP_C/BE#0 V33 AGP_AD16 AF31 AGP_AD17
H_CADIN7
HT1_TXD6# HT1_RXD6# H_CADON7 AGP_C/BE#1
AGP_CBE0 AGP_AD17 AGP_AD18
AM10 AN7 AG33 AF29
H_CADIN8 HT1_TXD7# HT1_RXD7# H_CADON8 AGP_C/BE#2 AGP_CBE1 AGP_AD18 AGP_AD19
AM18 AM3 AG29 AE30
C H_CADIN9 AK16 HT1_TXD8# HT1_RXD8# AL4 H_CADON9 AGP_C/BE#3 AC29 AGP_CBE2 AGP_AD19 AF30 AGP_AD20 C
H_CADIN10 HT1_TXD9# HT1_RXD9# H_CADON10 AGP_CBE3 AGP_AD20 AGP_AD21
AK15 AK5 AD30
H_CADIN11
H_CADIN12
AM15 HT1_TXD10#
HT1_TXD11#
HT1_RXD10#
HT1_RXD11#
AK6 H_CADON11
H_CADON12 AGP_ST0
AGP Interface 4x/8x AGP_AD21
AGP_AD22
AD29 AGP_AD22
AGP_AD23
AK13 AK7 L33 AC31
H_CADIN13 HT1_TXD12# HT1_RXD12# H_CADON13 AGP_ST1 AGP_ST0 AGP_AD23 AGP_AD24
AM12 AK8 M32 AA29
H_CADIN14 AK12 HT1_TXD13# HT1_RXD13# AK9 H_CADON14 AGP_ST2 L34 AGP_ST1 AGP_AD24 AA30 AGP_AD25
H_CADIN15 HT1_TXD14# HT1_RXD14# H_CADON15 AGP_RBF# AGP_ST2 AGP_AD25 AGP_AD26
AJ11 AL9 <14> AGP_RBF# N32 Y29
HT1_TXD15# HT1_RXD15# AGP_WBF# M34 AGP_RBF AGP_AD26 Y31 AGP_AD27
<14> AGP_WBF# AGP_WBF AGP_AD27
<14> AGP_FRAME# AGP_FRAME# AH29 Y30 AGP_AD28
H_CLKIP0 H_CLKOP0 AGP_IRDY# AGP_FRAME AGP_AD28 AGP_AD29
<4> H_CLKIP0 AP14 AN3 H_CLKOP0 <4> <14> AGP_IRDY# AG31 W30
H_CLKIN0 AN14 HT1_TXCLK0 HT1_RXCLK0 AP3 H_CLKON0 AGP_TRDY# AK34 AGP_IRDY AGP_AD29 V30 AGP_AD30
<4> H_CLKIN0 HT1_TXCLK0# HT1_RXCLK0# H_CLKON0 <4> <14> AGP_TRDY# AGP_TRDY AGP_AD30
<14> AGP_REQ# AGP_REQ# R29 U31 AGP_AD31
H_CLKIP1 AJ14 AM6 H_CLKOP1 AGP_GNT# T30 AGP_REQ AGP_AD31
<4> H_CLKIP1 HT1_TXCLK1 HT1_RXCLK1 H_CLKOP1 <4> <14> AGP_GNT# AGP_GNT
<4> H_CLKIN1 H_CLKIN1 AK14 AM5 H_CLKON1 H_CLKON1 <4> <14> AGP_STOP# AGP_STOP# AJ33
HT1_TXCLK1# HT1_RXCLK1# AGP_DEVESL# AGP_STOP +1.5VS
<14> AGP_DEVSEL# AJ32 E26 1 2 +3VALW
H_CTLIP0 AP9 AN8 H_CTLOP0 AGP_PAR AH33 AGP_DEVSEL AGP_PME#/GPIO32
<4> H_CTLIP0 HT1_TXCTL HT1_RXCTL H_CTLOP0 <4> <14> AGP_PAR AGP_PAR
H_CTLIN0 AN9 AP8 H_CTLON0 U30 R59 10K_0402_5%
<4> H_CTLIN0 HT1_TXCTL# HT1_RXCTL# H_CTLON0 <4> <14> AGP_PIPE# AGP_DBI1

1
U29
+3VS AGP_DBI0 AGP_CLK R61
1 2 R30 W32 1 2 AGP_CLK <14>
LDTSTOP# H_RSET +1.5VS R60 10K_0402_5% AGP_8XDE# AGP_CLK
<4> LDTSTOP# AK17 AL3
HT1_STOP# HT1_RSET R561 22_0402_5% 1K_0402_1%

1
R62 1 2 51.1_0402_1% P34

2
AN29 AK28 R63 1 2 R32 AGP_CAL_VDDQ V29 +AGP_VREF
HT2_TXD0/NC HT2_RXD0/NC R64 51.1_0402_1% AGP_CAL_GND APG_VREF
AM28 AK27
HT2_TXD1/NC ONLY FOR CrushK8GM HT2_RXD1/NC

1
AN27 AL30 51.1_0402_1%
HT2_TXD2/NC HT2_RXD2/NC 1
AN26 AK26 R65 C201
HT2_TXD3/NC ,CrushK8M/G is "NC" HT2_RXD3/NC
2

AJ20 AK24
AK20 DACA_VSYNC DACB_VSYNC AJ24 1K_0402_1% 0.1U_0402_10V6K
AP29 pin AJ28 AM23
DACA_HSYNC DACB_HSYNC
AJ23 2

2
HT2_TXD0#/NC HT2_RXD0#/NC DDC_DATA0 DDC_DATA1
AN28 AJ27 AL21 AK23
AP27 HT2_TXD1#/NC HT2_RXD1#/NC AL29 AJ21 DDC_CLK0 DDC_CLK1 AM24
HT2_TXD2#/NC HT2_RXD2#/NC DACA_RED DACB_RED
AP26 AJ26 AK22 AN24
HT2_TXD3#/NC HT2_RXD3#/NC AJ22 DACA_BLUE DACB_BLUE AP24
DACA_GREEN DACB_GREEN
AM22 AP21
DACA_RSET DACB_RSET
AM25 AL26 AM21 AN21
AN25 HT2_TXCLK0/NC HT2_RXCLK0/NC AL27 AN23 DACA_VREF DACB_VREF AL23
HT2_TXCLK0#/NC HT2_RXCLK0#/NC DACA_GND DACB_GND
+3VS AP30 AK29
B HT2_TXCTL/NC HT2_RXCTL/NC B
AN30 AJ29 +3VS AP23 AN22 +3VS
HT2_TXCTL#/NC HT2_RXCTL#/NC VDD_PLL
DACA_VDD DACB_VDD VDD_PLL
E1 C1
+3.3V_PLL +3.3V_PLL_DUAL
1

AK25
R68 HT2_STOP#/NC
AM29 AJ25
HT2_RSET/NC HT2_REQ#/NC RTC_XTALIN A11
10K_0402_5% XTALIN_RTC
RTC_XTALOUT B11
2

GATEA20 F9 A2 VR_ON XTALOUT_RTC


<30> GATEA20 A20GATE/GPIO50 CPUVDD_EN VR_ON <6,44>
H_THERMTRIP# AJ19 C2 HT1VDD_EN
<6> H_THERMTRIP# THERMTRIP#/GPIO59 HT1VDD_EN HT1VDD_EN <13>
H_RST# AL20 B1 HT1_VLD#
<6> H_RST# CPU_RST# HT1_VLD# HT1_VLD# <36> CRUSHK8G A01_PBGA708
<6> H_PWRGD H_PWRGD AK19 B4 MEM_VLD# MEM_VLD# <36>
CPU_COMP CPU_PWROK MEM_VLD# CPU_VLD#
AP20 B2 CPU_VLD# <36>
CPU_COMP CPU_VLD#
AN19 CPU_CLK_R 1 2
CPU_CLK CPU_CLK <6>
1

AM19 CPU_CLK_R# R69 1 2 0_0402_5%


R71 CPU_CLK# R70 0_0402_5% CPU_CLK# <6>

549_0402_1% CRUSHK8G A01_PBGA708


2

Y1 L3
RTC_XTALIN 4 1 RTC_XTALOUT 1 2 VDD_PLL
+3VS

3 2 BLM21P300S_0805

C211 1 1 C212 1 C207 1 C208 1 C209 1 C210


32.768KHZ_12.5P
18P_0402_50V8J 18P_0402_50V8J 0.1U_0402_10V6K 10U_1206_6.3V7K 0.1U_0402_10V6K 0.01U_0402_16V7K
2 2 2 2 2 2

A A

Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
nVIDIA CrushK8 (Host & AGP Bus)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Thursday, October 16, 2003 Sheet 11 of 50
5 4 3 2 1
5 4 3 2 1

BOOT MODE SEL BUF_SIO_CLK SEL XTAL SEL


SPKR 1 2 +3VS SPDIF 1 2 +3VS AC97_RST# 1 2 +3VALW
U45 R72 @10K_0402_5% R73 @10K_0402_5% R74 @10K_0402_5%
2 3 +1.4VBAT
+RTCVCC VIN VOUT 1 2 1 2 1 2
R75 10K_0402_5% R76 10K_0402_5% R77 10K_0402_5%
C784 1 1 C783
1 4 1 = SAFE MODE BOOT INIT TABLE 1 = 24 MHZ 1 = 27 MHZ
0.1U_0402_10V6K VSS NC 0.1U_0402_10V6K
2 S-817A14ANB-CUD-T2_SC82AB 2 0 = USER MODE BOOT INIT TABLE 0 = 14.318 MHZ 0 = 14.318 MHZ
*

PDD[0..15] U4D SDD[0..15]


D <19> PDD[0..15] SDD[0..15] <19> D

PDD0 V1 AD1 SDD0


PDD1 V5 IDE_DATA_P0 IDE_DATA_S0 AC1 SDD1
PCI_AD[0..31] U4C PDD2 IDE_DATA_P1 IDE_DATA_S1 SDD2
<20,21,22,28> PCI_AD[0..31] U6 AC3
PDD3 U1 IDE_DATA_P2 IDE_DATA_S2 AD5 SDD3
PCI_AD0 PCI_CBE#0 PDD4 IDE_DATA_P3 IDE_DATA_S3 SDD4
C33 G29 PCI_CBE#0 <20,21,22,28> U3 AC6
PCI_AD1 PCI_AD0 PCI_CBE0# PCI_CBE#1 PDD5 IDE_DATA_P4 IDE_DATA_S4 SDD5
D30 B32 PCI_CBE#1 <20,21,22,28> T3 AB5
PCI_AD2 E33 PCI_AD1 PCI_CBE1# F34 PCI_CBE#2 PDD6 T5 IDE_DATA_P5 IDE_DATA_S5 AA6 SDD6
PCI_AD2 PCI_CBE2# PCI_CBE#2 <20,21,22,28> IDE_DATA_P6 IDE_DATA_S6
PCI_AD3 C31 J32 PCI_CBE#3 PCI_CBE#3 <20,21,22,28> PDD7 R6 AB3 SDD7
PCI_AD4 D34 PCI_AD3 PCI_CBE3# J31 PCI_FRAME# PDD8 R5 IDE_DATA_P7 IDE_DATA_S7 AB2 SDD8
PCI_AD4 PCI_FRAME# PCI_FRAME# <20,21,22,28> IDE_DATA_P8 IDE_DATA_S8
PCI_AD5 F28 G30 PCI_IRDY# PCI_IRDY# <20,21,22,28> PDD9 T6 AA5 SDD9
PCI_AD6 PCI_AD5 PCI_IRDY# PCI_TRDY# PDD10 IDE_DATA_P9 IDE_DATA_S9 SDD10
B33 F29 PCI_TRDY# <20,21,22,28> T2 AB6
PCI_AD7 E32 PCI_AD6 PCI_TRDY# F31 PCI_STOP# PDD11 U2 IDE_DATA_P10 IDE_DATA_S10 AC5 SDD11
PCI_AD7 PCI_STOP# PCI_STOP# <20,21,22,28> IDE_DATA_P11 IDE_DATA_S11
PCI_AD8 B31 F30 PCI_DEVSEL# PCI_DEVSEL# <20,21,22,28> PDD12 V3 AD6 SDD12
PCI_AD8 PCI_DEVSEL# IDE_DATA_P12 IDE_DATA_S12

PCI Interface
PCI_AD9 D33 F32 PCI_PAR PDD13 U5 AC2 SDD13
PCI_AD9 PCI_PAR PCI_PAR <20,21,22,28> IDE_DATA_P13 IDE_DATA_S13
PCI_AD10 A32 A33 PCI_SERR# PCI_SERR# <20,21,22,28> PDD14 V6 AD3 SDD14
PCI_AD11 PCI_AD10 PCI_SERR# PCI_PERR# PDD15 IDE_DATA_P14 IDE_DATA_S14 SDD15
C34 C32 PCI_PERR# <20,21,22,28> V2 AD2
PCI_AD12 E31 PCI_AD11 PCI_PERR#/GPIO47 F26 PCI_PME# IDE_DATA_P15 IDE_DATA_S15
PCI_AD12 PCI_PME#/GPIO37 R78 1
PCI_AD13 B34 P29 2 33_0402_5% PCIRST_AGP#
PCIRST_AGP# <14> <19> PDA0
PDA0 Y1 AF3 SDA0
SDA0 <19>
PCI_AD14 D32 PCI_AD13 PCI_RST0# L30 R79 1 2 33_0402_5% PCIRST# PDA1 Y5 IDE_ADDR_P0 IDE_ADDR_S0 AE3 SDA1
PCI_AD14 PCI_RST1# PCIRST# <20,21,22,28> <19> PDA1 IDE_ADDR_P1 IDE_ADDR_S1 SDA1 <19>
PCI_AD15 E34 C25 PDA2 AA3 AF2 SDA2
PCI_AD15 PCI_RST2# <19> PDA2 IDE_ADDR_P2 IDE_ADDR_S2 SDA2 <19>
PCI_AD16 G32 K5 R81 1 2 33_0402_5% PCIRST_IDE# PDCS1# AA1 AF1 SDCS1#
PCI_AD16 PCI_RST3#/GPIO38 PCIRST_IDE# <19> <19> PDCS1# IDE_CS1_P# IDE_CS1_S# SDCS1# <19>
PCI_AD17 F33 H6 R82 1 2 33_0402_5% PCIRST_LPC# PCIRST_LPC# <29,30> <19> PDCS3# PDCS3# AA2 AG3 SDCS3# SDCS3# <19>
PCI_AD18 PCI_AD17 PCI_RST4#/GPIO39 PDDACK# IDE_CS3_P# IDE_CS3_S# SDDACK#
G33 <19> PDDACK# W6 AG5 SDDACK# <19>
PCI_AD19 H32 PCI_AD18 C29 PCI_REQ#0 PDIOW# W2 IDE_DACK_P# IDE_DACK_S# AE5 SDIOW#
PCI_AD19 PCI_REQ0# PCI_REQ#0 <21> <19> PDIOW# IDE_IOW_P# IDE_IOW_S# SDIOW# <19>
PCI_AD20 H34 E29 PCI_REQ#1 PCI_REQ#1 <20> <19> IRQ14 IRQ14 W5 AG6 IRQ15 IRQ15 <19>
PCI_AD21 PCI_AD20 PCI_REQ1# PCI_REQ#2 PDDREQ IDE_INTR_P IDE_INTR_S SDDREQ
H33 D27 PCI_REQ#2 <22> <19> PDDREQ W3 AE6 SDDREQ <19>
PCI_AD22 H30 PCI_AD21 PCI_REQ2# D26 PCI_REQ#3 PDIOR# Y3 IDE_DREQ_P IDE_DREQ_S AF5 SDIOR#
+3VS PCI_AD22 PCI_REQ3#/GPIO61 PCI_REQ#3 <28> <19> PDIOR# IDE_IOR_P# IDE_IOR_S# SDIOR# <19>
PCI_AD23 J30 A30 PCI_REQ#4 PDIORDY Y2 AF6 SDIORDY
PCI_AD23 PCI_REQ4#/GPIO45 PCI_REQ#4 <28> <19> PDIORDY IDE_RDY_P IDE_RDY_S SDIORDY <19>
RP59 PCI_AD24 J34 A31 PCI_REQ#5
PCI_AD24 PCI_REQ5#/GPIO63 PCI_REQ#5

I/O POWER
1 8 LAD0 PCI_AD25 K33
LAD1 PCI_AD26 PCI_AD25 PCI_GNT#0
2 7 J29 E27 PCI_GNT#0 <21> J5
3 6 LAD2 PCI_AD27 J33 PCI_AD26 PCI_GNT0# D29 PCI_GNT#1 N3 SATA_CLK/TBC/TCK A20
PCI_AD27 PCI_GNT1# PCI_GNT#1 <20> IDE_RDY_M/TxD4/TD4 USB_0/6
4 5 LAD3 PCI_AD28 K30 E28 PCI_GNT#2 PCI_GNT#2 <22> P6 B20
PCI_AD29 K29 PCI_AD28 PCI_GNT2# C26 PCI_GNT#3 N5 IDE_IOR_M#/TxD3/TD3 USB_0#/6# E21
PCI_AD29 PCI_GNT3#/GPIO62 PCI_GNT#3 <28> IDE_DREQ_M/TxD1/TD1 USB_1/NC
8.2K_1206_8P4R_5% PCI_AD30 K32 B29 PCI_GNT#4 P3 F21
PCI_AD30 PCI_GNT4#/GPIO46 PCI_GNT#4 <28> IDE_INTR_M/TxD6/TD6 USB_1#/NC
1 2 LDRQ#0 PCI_AD31 L32 B30 PCI_GNT#5 PCI_GNT#5 P5 A21
C
PCI_AD31 PCI_GNT5#/GPIO64 N2 IDE_IOW_M#/TxD2/TD2 USB_2NC B21 C
R83 8.2K_0402_5% PIRQA# IDE_DACK_M#/TxD5/TD5 USB_2#/NC
M30 PIRQA# <21,22> R2 B22
LAD0 H1 PCI_INTW# N29 PIRQB# R1 IDE_CS3_M#/CTL_T USB_3/USB_OC6 C22
<29,30> LAD0 LPC_AD0 PCI_INTX# PIRQB# <20,22> IDE_CS1_M#/CTL_R USB_3#/USB_OC7#
<29,30> LAD1 LAD1 H2 M29 PIRQC# PIRQC# <28> R3 A23
LAD2 LPC_AD1 PCI_INTY# PIRQD# IDE_ADDR_M2/TxD9/TD9 USB_4/7
<29,30> LAD2 H3 N30 PIRQD# P2 B23
R84 LAD3 G2 LPC_AD2 PCI_INTZ# P30 PIRQE# P1 IDE_ADDR_M1/TxD7/TD7 USB_4#/7# B24
<29,30> LAD3 LPC_AD3 PCI_INTE#/GPIO48 PIRQE# <14> IDE_ADDR_M0/TxD8/TD8 USB_5/NC
<29,30> LFRAME# 1 2 F2 N6 C24
LDRQ#0 J3 LPC_FRAME# A29 R85 1 2 22_0402_5% CLK_PCI_MINI M1 IDE_DATA_M15/TxD0/TD0 USB_5#/NC D20 USBP0+
<29> LDRQ#0 LPC_DRQ0# PCI_CLK0 CLK_PCI_MINI <28> IDE_DATA_M14/Rx_DATA_VALID/RD9 USB2_0 USBP0+ <27>
10_0402_5% F1 C28 R86 1 2 22_0402_5% CLK_PCI_PCM M6 C20 USBP0-
LPC_DRQ1# PCI_CLK1 CLK_PCI_PCM <22> IDE_DATA_M13/RxD8/RD7 USB2_0# USBP0- <27>
SIRQ G3 B28 R87 1 2 22_0402_5% CLK_PCI_LAN L5 E22 USBP1+
<22,29,30> SIRQ SERIRQ PCI_CLK2 CLK_PCI_LAN <20> IDE_DATA_M12/RxD6/RD5 USB2_1 USBP1+ <27>
<30> CLK_PCI_LPC CLK_PCI_LPC 1 2 E2 B27 R89 1 2 22_0402_5% CLK_PCI_1394 CLK_PCI_1394 <21> L1 F22 USBP1- USBP1- <27>
R88 22_0402_5% PCI_CLK7 PCI_CLK3 R93 22_0402_5% CLK_PCI_SIO
IDE_DATA_M11/RxD4/RD3 USB2_1# USBP2+
A27 1 2 CLK_PCI_SIO <29> L3 D21 USBP2+ <27>
B15 PCI_CLK4 B26 K3 IDE_DATA_M10/RxD2/RD1 USB2_2 C21 USBP2-
PCI_CLK8/GPIO_8 PCI_CLK5 R92 1 IDE_DATA_M9/SATACLK USB2_2# USBP2- <27>
B14 A26 2 22_0402_5% CLK_PCI_FB match to within 6000 J1 E23 USBP3+ USBP3+ <27>
PCI_CLK9/GPIO_9 PCI_CLK6 mil of each other IDE_DATA_M8/RBC0/COMINIT USB2_3 USBP3-
D2 B25 K6 F23 USBP3- <27>
PCI_CLK10/GPIO_17 PCI_CLKFB +3VS J2 IDE_DATA_M7/ASIC_CLK/RCK USB2_3# E24 USBP4+
IDE_DATA_M6/RBC1/PHYRDY USB2_4 USBP4+ <34>
B9 K2 F24 USBP4-
SMB_DATA1/GPIO44 IDE_DATA_M5/RxD1/RD0 USB2_4# USBP4- <34>
B10 D11 INTRUDER# 1 2 +1.4VBAT L2 E25 USBP5+
SMB_CLK1/GPIO43 INTRUDER# IDE_DATA_M4/RxD3/RD2 USB2_5 USBP5+ <27>

1
+3VALW R463 1 2 2.7K_0402_5% SMB_DATA0 G5 A5 EC_SMI# R94 1M_0402_5% L6 F25 USBP5-
SMB_DATA0/GPIO42 EXT_SMI#/GPIO29 EC_SMI# <30> IDE_DATA_M3/RxD5/RD4 USB2_5# USBP5- <27>
R464 1 2 2.7K_0402_5% SMB_CLK0 H5 C6 PBTN_OUT# R95 M5
SMB_CLK0/GPIO41 PWRBTN# PBTN_OUT# <30> IDE_DATA_M2/RxD7/RD6
R96 1 2 1.2K_0402_5% SMB_ALERT# C10 A3 KBRST# KBRST# <30> M3
SMB_ALERT#/GPIO40 KBRDRSTIN#/GPIO60 RSMRST# 60.4_0402_1% IDE_DATA_M1/RxD9/RD8
A8 1 2 EC_RSMRST# <30> M2
RSTBTN# D6 PWRGD_SB R97 0_0402_5% IDE_DATA_M0/RxD0/COMWAKE D18 OVCUR#0
PWRGD_SB PWRGD_SB <36> USB_OC0# OVCUR#0 <27>

2
B3 PM_PWROK PM_PWROK <36> 1 2 AG1 E18 OVCUR#1 OVCUR#1 <27>
PWRGD R98 60.4_0402_1% IDE_COMP USB_OC1#/GPIO22 OVCUR#2
AP31 E6 B18 OVCUR#2 <27>
AP32 BUF_125_25MHZ FANRPM/GPIO52 D5 USB_OC2#/GPIO23 C17
RGMII_TXD0/MII_TXD0 FANCTL0/GPIO53 USB_OC3#/GPIO24
AL32 C5 D1 A18
AL31 RGMII_TXD1/MII_TXD1 FANCTL1/GPIO54 C3 SPKR E10 SUSCLK/GPIO31 USB_OC4#/GPIO25 D17
RGMII_TXD2/MII_TXD2 CPU_SLP#/GPIO56 <25> SPKR SPKR USB_OC5#/GPIO26
AM31 F7 EC_THRM# EC_THRM# <30> 1 2 TEST B8
RGMII_TXD3/MII_TXD3 THERM#/GPIO58 EC_SWI# R100 1K_0402_5% TEST
AP33 B5 EC_SWI# <30> F11
AN32 RGMII_TXCLK/MII_TXCLK RI#/GPIO30 C11 SIO_PME# +1.4VBAT +1.2V_VBAT D24 +3VALW
RGMII_TXCTL/MII_TXEN SIO_PME#/GPIO28 SLP_S5# +3.3V_USB2_DUAL1 R103
AN34 D9 SLP_S5# <30> A4 E19 2
AM33 RGMII_RXD0/MII_RXD0 SLP_S5# C7 SLP_S3# B6 BUF_SIO_CLK +3.3V_USB2_DUAL2 A17 1 2 1 3 C213

S
RGMII_RXD1/MII_RXD1 SLP_S3# SLP_S3# <27,30> BUF_27_14MHZ/GPIO55 USB_RBIAS
AM34 C8 SLP_S1# SLP_S1# <30>
RGMII_RXD2/MII_RXD2 SLP_S1#/GPIO57 909_0402_1% 0.1U_0402_10V6K
AL33
AP34 RGMII_RXD3/MII_RXD3 Q68 1

G
RGMII_RXCLK/MII_RXCLK

2
AM32 SLP_S5# 2N7002_SOT23
AN33 RGMII_RXCTL/MII_RXDV B12 E4
B MII_RXER/GPIO21 EE_SEL/GPIO33 GPIO_20/ASF1 SPDIF B
AK31 A12 E3 B16
MII_COL EE_CLK/GPIO34 +3VALW +3VALW GPIO_19/ASF0 SPDIF/GPIO51 AC97_RST#
AK33 B13 C4 E16 AC97_RST# <25,27>
AN31 RGMII_MDIO/MII_MDIO EE_DATAO/GPIO35 C13 D3 GPIO_18 AC_RESET# C15 R104 1 2 22_0402_5%
MII_CRS EE_DATAI/GPIO36 GPIO_16 AC97_CLK CLK_CODEC_14M <25>
AL34 F8 F17 R105 1 2 0_0402_5%
RGMII_MDC/MII_MDC GPIO_15 AC_SDATA_OUT AC97_SDOUT <25,27>
1

1
AK32 B7 F16 AC97_SDIN0 <25>
R580 MII_PWRDWN R106 R107 GPIO_14 AC_SDATA_IN0
F13 E15 AC97_SDIN1 <27>
GPIO_13 AC_SDATA_IN1/GPIO27 R108 1
E13 E17 2 0_0402_5% AC97_SYNC <25,27>
1K_0402_5% CRUSHK8G A01_PBGA708 @100K_0402_5% 100K_0402_5% E11 GPIO_12 AC_SYNC C16 AC97_BITCLK
GPIO_11/STOP_AGPCLK# AC_BITCLK AC97_BITCLK <25,27>
B17
2

2
D5 RB751V_SOD323 E8 GPIO_10/HT1_REQ# B19
BATTLOW#
GPIO_7 XTALIN
<30> PM_BATLOW# 1 2 F12 C19
GPIO_6 XTALOUT Y2
D14
+3VS ICH_ACIN E14 GPIO_5 2 1
<30,38,40> ACIN GPIO_4
<30> LID_OUT# E9
+3VS
AE2 GPIO_3
RP61 <30> EC_SCI# GPIO_2 14.31818MHZ_20P_6X1430004201
1 2 DIMM_SMDATA <31> EC_FLASH# Y6
R110 10K_0402_5% GPIO_1 1 1
1 8 KBRST#
1 2 DIMM_SMCLK 2 7 SLP_S1# C216 C217
R111 10K_0402_5% 22P_0402_50V8J 22P_0402_50V8J
3 6 RSMRST#
1 2 PCI_DEVSEL# 4 5 SIRQ CRUSHK8G A01_PBGA708 2 2
R112 8.2K_0402_5%
1 2 PCI_FRAME# 10K_1206_8P4R_5%
R113 8.2K_0402_5%

+3VALW
RP62 RP63 USBP3+
1 C785 RP64
PIRQE# 1 10 1 8 PCI_PME#
+3VS
PCI_PERR# 2 9 PIRQA# 2 7 PBTN_OUT# 8 1 AC97_BITCLK
PCI_STOP# 3 8 PIRQB# 3 6 SIO_PME# USBP3- @1P_0402_50V8C 7 2
PCI_SERR# 4 7 PIRQD# 4 5 USBP2+ 2 6 3
1 C786

2
+3VS 5 6 PIRQC# 5 4 USBP4+
10K_1206_8P4R_5% 1 C787 RP68 R564
8.2K_1206_10P8R_5% USBP2- @1P_0402_50V8C 15K_1206_8P4R_5% 8 1
2 USBP4- @1P_0402_50V8C 7 2 @10_0402_5%
USBP5+ 2 6 3
1 C788

1
RP66 +3VS 5 4 1 C776
PCI_REQ#0 1 10 +3VS USBP0+ 1
A PCI_REQ#1 2 9 PCI_REQ#4 C789 RP67 USBP5- @1P_0402_50V8C 15K_1206_8P4R_5% A
PCI_REQ#2 3 8 PCI_REQ#5 8 1 2 @22P_0402_25V8K
2
2
G

PCI_REQ#3 4 7 PCI_IRDY# USBP0- @1P_0402_50V8C 7 2


5 6 PCI_TRDY# USBP1+ 2 6 3
+3VS 1 C790
DIMM_SMCLK 3 1 SMB_CLK0 5 4
<8,9> DIMM_SMCLK
2

8.2K_1206_10P8R_5%
S

USBP1- @1P_0402_50V8C 15K_1206_8P4R_5%


Q7 SMB_DATA0 1 3 DIMM_SMDATA 2
DIMM_SMDATA <8,9>
2N7002_SOT23
D

Q8
2N7002_SOT23
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
nVIDIA CrushK8 (PCI & IDE & USB & MISC)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Thursday, October 16, 2003 Sheet 12 of 50
5 4 3 2 1
5 4 3 2 1

+3VS
U4E

AA22 1 1 1 1 1 1 1 1 1
E30 GND81 AA21 C791 C218 C219 C220 C221 C222 C223 C224 C225
+5VS +5V1 GND82
AA4 AA20
+5V2 GND83 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
AA19
A14 GND84 AA18 2 2 2 2 2 2 2 2 2
+3VS +3.3V1 GND85
D12 AA17
E20 +3.3V2 GND86 AA16
D +3.3V3 GND87 D
D15 AA15
+3.3V4 GND88
C30 AA14
H29 +3.3V5 GND89 AA13
+3.3V6 GND90 +3VS
H4 AB22
L4 +3.3V7 GND91 AB21
+3.3V8 GND92
V4 AB20
+3.3V9 GND93
R4 AB19 1 1 1 1 1 1 1 1 1
AD4 +3.3V10 GND94 AB18 C792 C226 C227 C228 C229 C230 C231 C232 C233
+3.3V11 GND95
AF4 AB17
E5 +3.3V12 GND96 AB16 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
+3.3V13 GND97 2 2 2 2 2 2 2 2 2
M31 AB15
+3.3V14 GND98
V31 AB14
AD31 +3.3V15 GND99 AB13
+3.3V16 GND100
A34
GND101 A24
+3VALW GND102
D8 A15
+3.3V_DUAL1 GND103
C23 A9
F27 +3.3V_DUAL2 GND104 A6 +1.6VS
+3.3V_DUAL3 GND105
G6 A1
AK30 +3.3V_DUAL4 GND106 C18
+3.3V_DUAL5 GND108
C27 1 C234 1 C235 1 C236 1 C237 1 C238 1 C239 1 C240 1 C241 1 C242
+5VALW GND109
F15 D23
F19 +5V_DUAL1 GND110 C9
+5V_DUAL2 GND111 4.7U_0805_6.3V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
D31
+1.6VALW F4 GND112 C12 2 2 2 2 2 2 2 2 2
+1.2V_DUAL1 GND113
F5 D4
+1.2V_DUAL2 GND114
F6 E12
+1.2V_DUAL3 GND115 E7
GND116
+1.5VS R31 F18
U34 +1.5V1 GND117 F20
+1.5V2 GND118 +1.6VS +1.2V_HT
Y34 F14
+1.5V3 GND119
AA31 F10
AC34 +1.5V4 GND120 F3
+1.5V5 GND121
POWER and GROUND
AF34 H31 1 1 1 1 1 1 1 1 1
AG30 +1.5V6 GND122 J4 C243 C244 C245 C246 C247 C248 C249 C250 C251
+1.5V7 GND123
AJ34 J6
+1.5V8 GND124 4.7U_0805_6.3V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 4.7U_0805_6.3V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
L31
C
GND125 M4 2 2 2 2 2 2 2 2 2 C
GND126
+1.6VS AG2 P31
AH2 +1.2V1 GND127 P4
+1.2V2 GND128
AH3 T29
+1.2V3 GND129
AH5 U4
AH6 +1.2V4 GND130 V34
+1.2V5 GND131
AJ1 W29
AJ2 +1.2V6 GND132 Y4
+1.2V7 GND133 +1.5VS
AJ3 AA34
+1.2V8 GND134
AJ4 AE29
AK1 +1.2V9 GND135 AC4
+1.2V10 GND136
AK2 AD34 1 1 1 1 1 1 1 1
AK3 +1.2V11 GND137 AJ31 C252 C253 C254 C255 C256 C257 C258 C259
+1.2V12 GND138
AK4 AG34
+1.2V13 GND139 4.7U_0805_6.3V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
AG4
GND140 AH30 2 2 2 2 2 2 2 2
+1.2V_HT GND141
AL8 AL24
AL11 +1.2V_HT1 GND142 AK21
+1.2V_HT2 GND143
AL14 AJ18
+1.2V_HT3 GND144
AL17 AJ17
AK18 +1.2V_HT4 GND145 AK11
+1.2V_HT5 GND146 +3VALW +1.6VALW +3VS
AM27 AJ9
+1.2V_HT6 GND147 AJ6
GND148
AM30
GND149
N18 AM26 1 1 1 1 1 1 1 1 1 1
N17 GND1 GND150 AN20 C260 C261 C262 C263 C264 C265 C266 C267 C794 C795
GND2 GND151
N16 AM20
N15 GND3 GND152 AM17 4.7U_0805_6.3V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 4.7U_0805_6.3V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 1000P_0402_50V7K 1000P_0402_50V7K
GND4 GND153 2 2 2 2 2 2 2 2 2 2
N14 AM14
GND5 GND154
N13 AM11
P18 GND6 GND155 AM8
GND7 GND156
P17 C14
P16 GND8 GND157 AB29 +3V
GND9 GND158
P15 L29
GND10 GND159 +3VS
P14 Y13
P13 GND11 GND80 Y14 +5VALW +5VS
GND12 GND79
R18 Y15
R17 GND13 GND78 Y16
B GND14 GND77 1 C796 1 C797 1 C798 1 C804 B
R16 Y17 1 C268 1 C269 1 C270 1 C271
GND15 GND76
R15 Y18
R14 GND16 GND75 Y19 1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K
GND17 GND74 4.7U_0805_6.3V6K 0.1U_0402_10V6K 4.7U_0805_6.3V6K 0.1U_0402_10V6K 2 2 2 2
R13 Y20
T18 GND18 GND73 Y21 2 2 2 2
GND19 GND72
T17 Y22
GND20 GND71
T16 W13
T15 GND21 GND70 W14 +1.2VS +3VALW
GND22 GND69
T14 W15
T13 GND23 GND68 W16
GND24 GND67
U18 W17 1
GND25 GND66
U17 W18
U16 GND26 GND65 W19 C272
GND27 GND64 4.7U_0805_6.3V6K
U15 W20
U14 GND28 GND63 W21 2
GND29 GND62 +12VALW
U13 W22
GND30 GND61

1
V18 N19
V17 GND31 GND60 N20 +1.2V_HT

D
GND32 GND59

2
V16 N21 Q9
V15 GND33 GND58 N22 +12VALW R116 SI2302DS_SOT23
GND34 GND57
2

V14 P19 100K_0402_5%


GND35 GND56 R117
V13 P20

G
GND36 GND55 2

S
V22 P21
GND37 GND54

1
V21 P22 1K_0402_5% R118 +1.2V_HT

3
V20 GND38 GND53 R19 100K_0402_5%
GND39 GND52
1

2
V19 R20 1 C273 1 1
GND40 GND51 R119
U22 R21
1

GND41 GND50
1

1
D C275
U21 R22
GND42 GND49 Q10 100K_0402_5% 0.047U_0402_16V4Z C274
U20 T19 2 2
U19 GND43 GND48 T20 2N7002_SOT23 G G 2 2 2 4.7U_0805_6.3V6K
GND44 GND47

1
T22 T21 S S
3

3
GND45 GND46 Q11
2N7002_SOT23 0.1U_0402_10V6K
1

CRUSHK8G A01_PBGA708
O

A Q12 SI2302DS: N CHANNEL A


DTC124EK_SC59
VGS: 4.5V, RDS: 85 mOHM
G
I

<11> HT1VDD_EN
HT1VDD_EN VGS: 2.5V, RDS: 115mOHM
2

Id(MAX): 2.8A
VGS(MAX): +-8V

Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
nVIDIA CrushK8 (Power & Ground)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Thursday, October 16, 2003 Sheet 13 of 50
5 4 3 2 1
5 4 3 2 1

U38A
AGP_AD0 AD30 C6
AGP_AD1 AE30 PCIAD0 GPIO0 A6
DVOHSYNC VIPD3 VIPD5 VIPD4 DEVICE
AGP_AD[0..31] <11> PCIAD1 GPIO1
AGP_AD2 AD29 A7 +3VS
PCIAD2 GPIO2 ENABLT <17,30>
AGP_AD3 AE29 A8 RP93
AGP_ADSTBF[0..1] <11>
AGP_AD4 AD28 PCIAD3 GPIO3 C9
ENVDD <17>
MAP17_SUSP# 1 8 1 1 0 1 MAP17-116(16MB)
AGP_AD5 AG30 PCIAD4 GPIO4 B9 VIPD6 2 7
AGP_ADSTBS[0..1] <11>

1
AGP_AD6 PCIAD5 GPIO5 MAP17_SUSP# DVOD0
AF28 C5 3 6
PCIAD6 GPIO6 0 1 1 0 * MAP17-232(32MB)

GPIO/VIP Interface
AGP_AD7 AG29 F3 R583 R571 DVOD11 4 5
AGP_ST[0..2] <11> PCIAD7 GPIO7
AGP_AD8 AH30
AGP_AD9 AC28 PCIAD8 AH2 1K_0402_5% 1K_0402_5% 10K_0804_8P4R_5%
AGP_C/BE#[0..3] <11>
AGP_AD10 AH29
PCIAD9 ROMCS_ 1 0 0 1 MAP17-464(64MB)

2
AGP_AD11 AE28 PCIAD10 J1
AGP_AD12 PCIAD11 ROMA14
AJ30 F2
D AGP_AD13 PCIAD12 ROMA15 RP89 D
AG28
AGP_AD14 AK30 PCIAD13 K4 VIPD2 1 8
+3VS +3VS AGP_CLK AGP_AD15 PCIAD14 VIPD0 DVOCLKIN
AG27 J3 2 7 +3VS
PCIAD15 VIPD1 R498
AGP_AD16 AH23 H3 VIPD2 VIPD7 3 6 DVOHSYNC 2 1 64@10K_0402_5%

1
AGP_AD17 PCIAD16 VIPD2 VIPD3 R499 1 32@10K_0402_5%
AJ24 K5 4 5 2
R556 AGP_AD18 PCIAD17 VIPD3 VIPD4
AH22 G2
1

AGP_AD19 AK24 PCIAD18 VIPD4 G1 VIPD5 10K_1206_8P4R_5% VIPD3 R490 2 1 32@10K_0402_5%


R493 R494 @10_0402_5% PCIAD19 VIPD5 R491
AGP_AD20 AH21 F1 VIPD6 2 1 64@10K_0402_5%
AGP_AD21 AJ22 PCIAD20 VIPD6 G3 VIPD7

2
10K_0402_5% @10K_0402_5% PCIAD21 VIPD7 R496
1 AGP_AD22 AH20 VIPD5 2 1 32@10K_0402_5%
C746 AGP_AD23 PCIAD22 RP90 R497 1 64@10K_0402_5%
AK22 C8 2
2

AGP_AD24 AG21 PCIAD23 VIPHAD0 C7 DVOD1 1 8


@10P_0402_25V8K PCIAD24 VIPHAD1 R492
STOP_AGP AGP_BUSY# AGP_AD25 AJ19 B7 DVOD6 2 7 VIPD4 2 1 64@10K_0402_5%
2 PCIAD25 VIPPCLK R495
AGP_AD26 AG18 A5 DVOD10 3 6 2 1 32@10K_0402_5%
AGP_AD27 AK19 PCIAD26 VIPHCLK B6 DVOD9 4 5
AGP_AD28 PCIAD27 VIPHCTL
AG19
AGP_ADSTBS0 AGP_ADSTBS1 AGP_AD29 PCIAD28 10K_0804_8P4R_5%

PCI/AGP BUS Interface


AJ18
AGP_AD30 PCIAD29 DVOD0
AF19 AK2
AGP_AD31 PCIAD30 DVOD0 DVOD1
AK18 AK3
1

PCIAD31 DVOD1 DVOD2


AH3
R508 R509 AGP_C/BE#0 DVOD2 DVOD3
AH28 AJ1
AGP_C/BE#1 AJ27 PCICBE#0 DVOD3 AG1 DVOD4 +3VS
@220K_0402_5% @220K_0402_5% AGP_C/BE#2 AK25
PCICBE#1
PCICBE#2
DVOD4
DVOD5
AG2 DVOD5 RP91 RP92 CRYSTAL
AGP_C/BE#3 DVOD6 DVOD3 STRAP0

DVO Interface
AF21 AD3 1 8 1 8
2

PCICBE#3 DVOD6 DVOD7 DVOD4 STRAP1


AE1 2 7 2 7
AH11 DVOD7 AE3 DVOD8 DVOD5 3 6 STRAP2 3 6
<12> PCIRST_AGP#
<11> AGP_GNT# AG12 PCIRST#
PCIGNT#
DVOD8
DVOD9
AE2 DVOD9 DVOD2 4 5 STRAP3 4 5
DVOD8 DVOD7 TVMODE
AK12 AG3 DVOD10
<11> AGP_REQ# PCIREQ# DVOD10
DACRSET DACVREF AH24 AH1 DVOD11 10K_0804_8P4R_5% 10K_0804_8P4R_5%
<11> AGP_FRAME#
<11> AGP_IRDY# AJ25
PCIFRAME# DVOD11 0 0 SECAM
PCIIRDY#
<11> AGP_TRDY# AH25
1

AK27 PCITRDY#
C R512
1
C635
<11> AGP_DEVSEL#
AH26
PCIDEVSEL#
AC3
0 1 * NTSC C
<11> AGP_STOP# PCISTOP# DVOVSYNC
AH27 AB3 DVOHSYNC
<11> AGP_PAR PCIPAR DVOHSYNC
113_0402_1% 0.01U_0402_16V7K AK11 AK1
2
<12> PIRQE# PCIINTA# DVODE
AD2
1 0 PAL
2

AJ12 DVOCLKOUT AD1 DDC_CLK_CRT


<11> AGP_CLK PCICLK DVOCLKOUT# DDC_CLK_CRT <18>
AB2 DVOCLKIN DDC_DAT_CRT
AJ13
DVOCLKIN
AB1 DVOVREF DDC_CLK_LCD
DDC_DAT_CRT
DDC_CLK_LCD
<18>
<17>
1 1 VGA
<11> AGP_RBF# AGPRBF# DVOVREF
<11> AGP_WBF# AG15 DDC_DAT_LCD DDC_DAT_LCD <17>
AGPWBF#
<11> AGP_PIPE# AF18
AGP_BUSY# AF10 AGPPIPE# AK4
DAC2REST DAC2VREF STOP_AGP AGPBUSY# I2C0SCL AJ4 +3VS
AG10
+AGPVREF AGPSTOP# I2C0SDA RP94 RP95
AC30
AGPVREF I2C1SCL 8DDC_CLK_CRT DVOD8 R501 1 @10K_0402_5%
AH5 1 1 8 +5VS 2
1

I2C1SCL AH4 R502


1 AH16 I2C1SDA 2 7DDC_DAT_CRT 2 7 FBACKE 2 1 10K_0402_5%
R536 C638 AH17 AGPSBSTB I2C1SDA 3 6DDC_CLK_LCD 3 6 +3VS

I2C

2
AGPSBSTB# I2C2SCL 5DDC_DAT_LCD DVOD7 R503 1 10K_0402_5%
AK6 4 4 5 2
63.4_0402_1% 0.01U_0402_16V7K AJ15 I2C2SCL AJ6 I2C2SDA R534 R504 2 1 @10K_0402_5%
2 AGPSBA0 I2C2SDA 33_0804_8P4R_5% 2.2K_0804_8P4R_5%
AF15
2

AGPSBA1 10K_0402_5%
AK15
AG16 AGPSBA2

1
AGPSBA3 IFP0VREF
AK16 R2
AGPSBA4 IFP0VREF IFP0RSET
AF16 R1
AGPSBA5 IFP0RSET IFP1VREF
AJ16 L2
AGPSBA6 IFP1VREF IFP1RSET
AH18 L1
+1.5VS +3VS AGPSBA7 IFP1RSET
AGP_ADSTBF1 AK21 P5 LVDSA0+
AGPADSTB1 TXD0 LVDSA0+ <17>
AGP_ADSTBS1 AJ21 P4 LVDSA0-
LVDSA0- <17>
1

AGP_ADSTBF0 AK28 AGPADSTB1# TXD0# R5 LVDSA1+ IFP0RSET IFP0VREF +2.5VS +2.5VS


AGPADSTB0 TXD1 LVDSA1+ <17>
R522 L34 AGP_ADSTBS0 AJ28 R4 LVDSA1- R523 R524
LVDSA1- <17>

1
AGPADSTB0# TXD1# R3 LVDSA2+ 2 1 FBACLK1 2 1 FBACLK0
TXD2 LVDSA2+ <17> 1
1K_0402_1% 0_0603_5% AGP_ST0 AF12 P3 LVDSA2- R532 C639
LVDSA2- <17>

1
AGP_ST1 AGPST0 TXD2# @120_0402_5% @120_0402_5%
AF13 P1
2

B +AGPVREF AGP_ST2 AG13 AGPST1 TXD3 P2 1K_0402_1% 0.047U_0402_10V4M R525 R526 B


+SVDD AGPST2 TXD3# LVDSAC+ 2
LVDS/TMDS

K2 LVDSAC+ <17>
1

2
CRT_R AJ9 TXC0 K1 LVDSAC- 32@100_0402_5% 32@100_0402_5%
1 1 1 <18> CRT_R DACRED TXC0# LVDSAC- <17>
R527 C637 C772 C773 CRT_G AJ10 R528 R529
<18> CRT_G

2
CRT_B DACGREEN LVDSB0+ FBACLK1# FBACLK0#
<18> CRT_B AH8 U5 LVDSB0+ <17> 2 1 2 1
1K_0402_1% 0.1U_0402_10V6K 4.7U_0805_6.3V6K CRT_HSYNC AH10 DACBLUE TXD4 U4 LVDSB0-
<18> CRT_HSYNC CRTHSYNC TXD4# LVDSB0- <17>
2 2 2 CRT_VSYNC AH9 U3 LVDSB1+ IFP1RSET IFP1VREF @120_0402_5% @120_0402_5%
<18> CRT_VSYNC LVDSB1+ <17>
2

DACRSET AJ8 CRTVSYNC TXD5 T3 LVDSB1-


LVDSB1- <17>

1
0.1U_0402_10V6K DACVREF DACRSET TXD5# LVDSB2+
AK9 V5 LVDSB2+ <17> 1
DACVREF TXD6 LVDSB2- R535 C641
V4 LVDSB2- <17>
TV_CRMA Y2 TXD6# W5
<18,34> TV_CRMA DAC2RED TXD7
TV_LUMA 1K_0402_1% 0.047U_0402_10V4M
DAC

<18,34> TV_LUMA AA2 W4


TV_COMPS W3 DAC2GREEN TXD7# T5 LVDSBC+ 2
<18,34> TV_COMPS LVDSBC+ <17>

2
DAC2BLUE TXC1 LVDSBC- +2.5VS +3VS
AA3 T4 LVDSBC- <17>
Y3 DAC2HSYNC TXC1#
DAC2REST DAC2VSYNC
W2

1
+SVDD DAC2VREF DAC2REST
Y1 N3
DAC2VREF TXD8 M3 R530 R511
TXD8#
M5
6

U43 XTALIN AJ7 TXD9 M4 1K_0402_1% 1K_0402_1%


XTALOUT XTALIN TXD9#
AK7 N5
VDD

2
XTALOUT TXD10
CLOCK

N4 FBVREF DVOVREF
R590 TXD10# L3 Y6

1
27MOUT XTALSSIN XTALSSIN TXC2 XTALOUT
1 5 1 2 AH7 K3 4 3 1 1
X1/CLK CLKOUT 27MOUT XTALSSIN TXC2# GND OUT C640 R533 C636 R515
AH6
R557 1K_0402_5% 22_0402_5% XTALSOUTBUFF XTALIN 1 2
IN GND 0.1U_0402_10V6K 1K_0402_1% 0.1U_0402_10V6K 1K_0402_1%
+3VS 2 1 7 2
FS1 X2 R559 STRAP0 B30 N28 FBACKE 27MHz_16PF_6P27000126 2 2
1 1

2
STRAP1 MSTRAPSEL0 FBACKE FBVREF C642 C643
2 1 8 4 2 1 B29 A18
FS2 SS% MSTRAPSEL1 FBVREF
SDRAM

STRAP2 A30 A4 FBACLK0#


GND

R558 1K_0402_5% 1K_0402_5% STRAP3 MSTRAPSEL2 FBACLK1#/NC(440) FBACLK0 22P_0402_50V8J 22P_0402_50V8J


A29 B4
XTALSSIN MSTRAPSEL3 FBACLK1/NC(440) FBACLK1 2 2
C21
A P2180A_SO8 A9 FBACLK0/NC(440) C20 FBACLK1# A
3

AJ3 BUFRST# FBACLK0#/NC(440)


R562 TESTMODE
2

SA000040300(0304231100)
@10_0402_5% R537
2

10K_0402_5%
SST Ratio selection table for W180 1
C774
Compal Electronics, Inc.
1

Modulation setting
SST Ratio @10P_0402_25V8K Title
SS% 2
MAP17 AGP Interface(1/3)
0 1.25% THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.5
1 3.75% DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 14 of 50
5 4 3 2 1
5 4 3 2 1

+1.2VS +1.35VS

MAP17-116/232 MAP17-464 +1.5VS


1
C743
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
+VGA_CORE * +1.2VS +1.35VS

1
22U_1206_10V4Z
2 1 1 1 1 1 1 1 1 1 1

JOPEN1

JOPEN2
C653 C654 C655 C656 C657 C658 C659 C660 C661 C662

+2.5VS 2 2 2 2 2 2 2 2 2 2
near JOPEN1,2

2
D D
+VGA_CORE
1 1 10P_0402_50V8K 1000P_0402_50V7K 0.1U_0402_10V6K 0.1U_0402_10V6K 4.7U_0805_6.3V6K
1.5A 0.1U_0402_10V6K 0.1U_0402_10V6K 10P_0402_50V8K 0.1U_0402_10V6K C663 C664

4.7U_0805_6.3V6K 0.1U_0402_10V6K
1 1 1 1 1 1 1 1 1
C646 C647 C648 C649 C650 C651 C652 C644 C645 2 2
+2.5VS

2 2 2 2 2 2 2 2 2
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2.1A
4.7U_0805_6.3V6K 1000P_0402_50V7K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K U38B
1 1 1 1 1 1 1 1
E4 AG14 C674 C675 C676 C681 C678 C679 C680 C677
+2.5VS VDDFBIO VDDAGP +1.5VS
G4 AK14
J4 VDDFBIO VDDAGP AG17
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 1000P_0402_50V7K VDDFBIO VDDAGP 2 2 2 2 2 2 2 2
AD4 AK17
AF4 VDDFBIO VDDAGP AG20
VDDFBIO VDDAGP 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 4.7U_0805_6.3V6K
1 1 1 1 1 1 1 1 1 D5 AK20
C665 C666 C667 C668 C669 C670 C671 C672 C673 VDDFBIO VDDAGP
F5 AK23
VDDFBIO VDDAGP
D7 AK26
VDDFBIO VDDAGP
E6 AK29
2 2 2 2 2 2 2 2 2 AB27 VDDFBIO VDDAGP AF30
VDDFBIO VDDAGP
AD27
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 10P_0402_50V8K VDDFBIO 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
AF27
VDDFBIO
AE26 J25 +2.5VS
D9 VDDFBIO VDDFBC G6
VDDFBIO VDDFBC 1 1 1 1 1 1 1 1
D22 J6 C756 C689 C694 C690 C691 C688 C692 C693
VDDFBIO VDDFBC
D24 F22
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K VDDFBIO VDDFBC
AG24 F24
VDDFBIO VDDFBC 2 2 2 2 2 2 2 2
E25 F7
VDDFBIO VDDFBC
1 1 1 1 1 1 1 1 1 AF25 G25
C747 C748 C749 C750 C751 C752 C753 C754 C755 D26 VDDFBIO VDDFBC F9 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
C VDDFBIO VDDFBC C
F26 AB6
VDDFBIO NC/VDDFBC(440)
AG26 AD6
2 2 2 2 2 2 2 2 2 VDDFBIO NC/VDDFBC(440)
E27 AE7
VDDFBIO NC/VDDFBC(440) +3VS
G27 AE9
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K J27 VDDFBIO NC/VDDFBC(440) AE22
VDDFBIO NC/VDDFBC(440) 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
AG5 AE24
NC/VDDFBIO(440) NC/VDDFBC(440)
AF6 AB25
NC/VDDFBIO(440) NC/VDDFBC(440)
AG7 AD25 1 1 1 1 1 1
NC/VDDFBIO(440) NC/VDDFBC(440) C757 C714 C715 C716 C717 C718
AE5
NC/VDDFBIO(440) E1
VDD33 +3VS
L6 H1 4.7U_0805_6.3V6K
+VGA_CORE VDD VDD33
P6 AC1 2 2 2 2 2 2
VDD VDD33
U6 AF1
VDD VDD33 0.1U_0402_10V6K 0.1U_0402_10V6K
Y6 L4
D11 VDD VDD33 Y4
+VGA_CORE VDD VDD33
F11
AE11 VDD +5VS
VDD
3.3A D14 D4 +5VS
4.7U_0805_6.3V6K 1000P_0402_50V7K 0.1U_0402_10V6K VDD VD50CLAMP
F14 AG11
AE14 VDD VD50CLAMP
VDD +DACVDD
1 1 1 1 1 1 D17 AK10 1 1
C682 C683 C684 C685 C686 C687 VDD DACVDD +DAC2VDD C758 C759
F17 AA1
VDD DAC2VDD +PLL_VDD
AE17 AK5
VDD PLLVDD 0.1U_0402_10V6K
D20 AF3 +3VS
2 2 2 2 2 2 F20 VDD VDDDVO AG4 2 2
VDD VDDDVO +IFPAIOAVDD
AE20 T1 1
4.7U_0805_6.3V6K 0.1U_0402_10V6K 10P_0402_50V8K L25 VDD IFPAIOAVDD U1 C707 0.1U_0402_10V6K
P25 VDD IFPAIOBVDD M1 +IFPBIOVDD
VDD IFPBIOVDD +IFPAPLLVDD 0.1U_0402_16V4Z
U25 V1
Y25 VDD IFPAPLLVDD N1 +IFPBPLLVDD 2
VDD IFPBPLLVDD +3VS
L27
1000P_0402_50V7K 0.1U_0402_10V6K 10P_0402_50V8K VDD
P27
B U27 VDD B
VDD
1 1 1 1 1 1 Y27 1 1 1 1
C695 C696 C697 C698 C699 C700 VDD C799 C800 C805 C806

SA000040300(0304231100) 1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K


2 2 2 2 2 2 2 2 2 2

0.1U_0402_10V6K 10P_0402_50V8K 1000P_0402_50V7K

+VGA_CORE

0.1U_0402_10V6K 1000P_0402_50V7K 0.1U_0402_10V6K +DACVDD 1 2 +IFPAPLLVDD 1 2 +DAC2VDD 1 2


+3VS +2.8VS +3VS
L33 0_0603_5% L27 0_0603_5% L32 0_0603_5%
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C760 C761 C762 C763 C764 C765 C733 C731 C732 C710 C708 C709 C730 C728 C729

10P_0402_50V8K 4700P_0402_25V7K 1U_0603_10V6K 10P_0402_50V8K 4700P_0402_25V7K 1U_0603_10V6K 10P_0402_50V8K 4700P_0402_25V7K 1U_0603_10V6K


2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

0.1U_0402_10V6K 0.1U_0402_10V6K 10P_0402_50V8K

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K +IFPAIOAVDD 1 2 +3VS +PLL_VDD 1 2 +3VS


+IFPBIOVDD +IFPBPLLVDD L26 0_0603_5% L30 0_0603_5%
1 1 1 1 1 1 1 1 1 1 1 1
C766 C767 C768 C769 C770 C771 C706 C704 C705 C724 C722 C723
1

R581 R582 10P_0402_50V8K 4700P_0402_25V7K 1U_0603_10V6K 10P_0402_50V8K 4700P_0402_25V7K 1U_0603_10V6K


A 2 2 2 2 2 2 2 2 2 2 2 2 A
10K_0402_5% 10K_0402_5%
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2

Compal Electronics, Inc.


Title

MAP17 Power (2/3)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 15 of 50
5 4 3 2 1
5 4 3 2 1

U38D

K10 L17
L10 GND/NO PIN(440) GND/NO PIN(440) M17
GND/NO PIN(440) GND/NO PIN(440) U38C
M10 N17
N10 GND/NO PIN(440) GND/NO PIN(440) P17
GND/NO PIN(440) GND/NO PIN(440)
P10 R17 A1 C30
R10 GND/NO PIN(440) GND/NO PIN(440) T17 B1 NC NC V26
GND/NO PIN(440) GND/NO PIN(440) NC NC
T10 U17 C1 W26
U10 GND/NO PIN(440) GND/NO PIN(440) V17 D1 NC NC A27
GND/NO PIN(440) GND/NO PIN(440) NC NC
V10 W17 A2 B27
D GND/NO PIN(440) GND/NO PIN(440) NC NC D
W10 Y17 C2 C27
Y10 GND/NO PIN(440) GND/NO PIN(440) AA17 D2 NC NC D27
GND/NO PIN(440) GND/NO PIN(440) NC NC
AA10 K18 J2 K27
GND/NO PIN(440) GND/NO PIN(440) NC NC
K11 L18 A3 M27 +2.8VS
GND/NO PIN(440) GND/NO PIN(440) NC NC
L11 M18 B3 N27
GND/NO PIN(440) GND/NO PIN(440) NC NC U44
M11 N18 C3 R27
N11 GND/NO PIN(440) GND/NO PIN(440) P18 V3 NC NC T27 4 5
GND/NO PIN(440) GND/NO PIN(440) NC NC +3VS VIN VOUT
P11 R18 C4 V27 1 R576
R11 GND/NO PIN(440) GND/NO PIN(440) T18 AA4 NC NC Y17 C780 2 6 1 2
GND/NO PIN(440) GND/NO PIN(440) NC NC DELAY SENSE or ADJ 1
T11 U18 AB4 W27 61.9K_0603_1% C781

1
GND/NO PIN(440) GND/NO PIN(440) NC NC 1U_0603_10V6K
U11 V18 AA5 A28 7 1
V11 GND/NO PIN(440) GND/NO PIN(440) W18 AG9 NC NC B28 2 ERROR CNOISE 1U_0603_10V6K
GND/NO PIN(440) GND/NO PIN(440) NC NC 1
W11 Y18 A10 C28 8 3 C782 R577 2
GND/NO PIN(440) GND/NO PIN(440) NC NC SD GND 47K_0603_1%
Y11 AA18 C10 E28
AA11 GND/NO PIN(440) GND/NO PIN(440) K19 D10 NC NC G28 2 1 SI9182DH-AD_MSOP8
+3VS

2
GND/NO PIN(440) GND/NO PIN(440) NC NC 2
K12 L19 E10 H28
L12 GND/NO PIN(440) GND/NO PIN(440) M19 A11 NC NC L28 R578 10K_0402_5%
GND/NO PIN(440) GND/NO PIN(440) NC NC 0.01U_0402_16V7K
M12 N19 AH15 M28
GND/NO PIN(440) GND/NO PIN(440) NC NC
N12 P19 A13 P28
GND/NO PIN(440) GND/NO PIN(440) NC NC
P12 R19 C13 R28
GND/NO PIN(440) GND/NO PIN(440) NC NC
R12 T19 E13 T28
T12 GND/NO PIN(440) GND/NO PIN(440) U19 A14 NC NC U28
GND/NO PIN(440) GND/NO PIN(440) NC NC
U12 V19 C14 V28
GND/NO PIN(440) GND/NO PIN(440) NC NC
V12 W19 A15 W28
GND/NO PIN(440) GND/NO PIN(440) NC NC
W12 Y19 B15 Y28
Y12 GND/NO PIN(440) GND/NO PIN(440) AA19 C15 NC NC AA28
AA12 GND/NO PIN(440) GND/NO PIN(440) K20 D15 NC NC AB28
GND/NO PIN(440) GND/NO PIN(440) NC NC
K13 L20 E15 C29
GND/NO PIN(440) GND/NO PIN(440) NC NC
L13 M20 A16 D29
GND/NO PIN(440) GND/NO PIN(440) NC NC
M13 N20 B16 F29
GND/NO PIN(440) GND/NO PIN(440) NC NC
N13 P20 C16 G29
P13 GND/NO PIN(440) GND/NO PIN(440) R20 D16 NC NC J29
C GND/NO PIN(440) GND/NO PIN(440) NC NC C
R13 T20 E16 K29
GND/NO PIN(440) GND/NO PIN(440) NC NC
T13 U20 A17 M29
GND/NO PIN(440) GND/NO PIN(440) NC NC
U13 V20 C17 N29
GND/NO PIN(440) GND/NO PIN(440) NC NC
V13 W20 B18 T29
W13 GND/NO PIN(440) GND/NO PIN(440) Y20 C18 NC NC V29
GND/NO PIN(440) GND/NO PIN(440) NC NC
Y13 AA20 D18 F28
GND/NO PIN(440) GND/NO PIN(440) NC NC
AA13 K21 E18 K28
GND/NO PIN(440) GND/NO PIN(440) NC NC
K14 L21 B19 AA26
GND/NO PIN(440) GND/NO PIN(440) NC NC
L14 M21 C19 E12
M14 GND/NO PIN(440) GND/NO PIN(440) N21 D19 NC NC R29
GND/NO PIN(440) GND/NO PIN(440) NC NC
N14 P21 E19 W29
GND/NO PIN(440) GND/NO PIN(440) NC NC
P14 R21 A20 AA29
GND/NO PIN(440) GND/NO PIN(440) NC NC
R14 T21 A21 AB29
GND/NO PIN(440) GND/NO PIN(440) NC NC
T14 U21 B21 B13
U14 GND/NO PIN(440) GND/NO PIN(440) V21 D21 NC NC D30
GND/NO PIN(440) GND/NO PIN(440) NC NC
V14 W21 E21 E30
W14 GND/NO PIN(440) GND/NO PIN(440) Y21 A22 NC NC F30
GND/NO PIN(440) GND/NO PIN(440) NC NC
Y14 AA21 B22 H30
GND/NO PIN(440) GND/NO PIN(440) NC NC
AA14 AF17 C22 L30
K15 GND/NO PIN(440) GND AJ17 A23 NC NC N30
GND/NO PIN(440) GND NC NC
L15 B20 C23 P30
GND/NO PIN(440) GND NC NC
M15 E20 B24 R30
GND/NO PIN(440) GND NC NC
N15 G20 C24 T30
GND/NO PIN(440) GND NC NC
P15 AD20 A25 U30
R15 GND/NO PIN(440) GND AF20 B25 NC NC V30
GND/NO PIN(440) GND NC NC
T15 AJ20 C25 Y30
U15 GND/NO PIN(440) GND E22 T26 NC NC AA30
V15 GND/NO PIN(440) GND G22 C26 NC NC AB30
GND/NO PIN(440) GND NC NC
W15 AD22 K26 D13
Y15 GND/NO PIN(440) GND AF22 M26 NC NC J28
GND/NO PIN(440) GND NC NC
AA15 B23 N26 AA27
GND/NO PIN(440) GND NC NC
K16 AJ23 R26 D28
B L16 GND/NO PIN(440) GND E24 A26 NC NC C11 B
GND/NO PIN(440) GND NC NC
M16 G24 A12 B10
N16 GND/NO PIN(440) GND J24 AD17 NC NC A24
GND/NO PIN(440) GND NC NC
P16 L24 AG22 E3
GND/NO PIN(440) GND NC NC
R16 P24 AH19 D3
T16 GND/NO PIN(440) GND U24 AK13 NC NC B12
GND/NO PIN(440) GND NC NC
U16 Y24 C12
V16 GND/NO PIN(440) GND AB24 B2 NC G30
GND/NO PIN(440) GND GND NC
W16 AD24 E2 J30
GND/NO PIN(440) GND GND NC
Y16 AF24 H2 K30
AA16 GND/NO PIN(440) GND D25 AC2 GND NC AH13
GND/NO PIN(440) GND GND NC
K17 F25 AF2 A19
AB7 GND/NO PIN(440) GND AE25 AJ2 GND NC M30
GND GND GND NC
AD7 AG25 F4 W30
AF7 GND GND B26 AE4 GND NC AH14
GND GND GND NC
B8 E26 B5 D12
GND GND GND NC(440)//FBACAS#
E9 G26 E5 AC4
G9 GND GND J26 G5 GND NC/NO PIN(440)
GND GND GND
AD9 L26 J5 L7
AF9 GND GND P26 L5 GND GND U7
GND GND GND GND
B11 U26 Y5 W1
GND GND GND DAC2GND
E11 Y26 AB5 AK8
G11 GND GND AB26 AD5 GND DACGND N2
GND GND GND IFP1PLLGND
AD11 AD26 AF5 M2
GND GND GND IFP1IOGND
AF11 AF26 AJ5 V2
GND GND GND IFP0PLLGND
AJ11 AJ26 D6 T2
GND GND GND IFPIOAGND
AH12 F27 F6 U2
B14 GND GND AE27 AE6 GND IFPIOBGND E7
GND GND GND GND
E14 E29 AG6 G7
G14 GND GND H29 P7 GND GND J7
GND GND GND GND
AD14 L29
GND GND
AF14 P29
A AJ14 GND GND U29 SA000040300(0304231100) A
Y7 GND GND Y29
E17 GND GND AC29
GND GND
G17 AF29
B17 GND GND AJ29
GND GND

SA000040300(0304231100)
Compal Electronics, Inc.
Title

MAP17 NC/GND(3/3)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 16 of 50
5 4 3 2 1
A B C D E F G H

The cap.'s colsely to LCD CONN.


LCD Panel Connector +3VS
1 1

2
R141
JP6 L4
1 2 +LCDVDD_A 1000P_0402_50V7K 1 2 4.7K_0402_5%
1 2 +LCDVDD
LVDSA2+ 3 4 KC FBM-L11-201209-221LMAT_0805

1
<14> LVDSA2+ 3 4
LVDSA2- 5 6 1 1 1
<14> LVDSA2- 5 6
7 8 C302 C303 C304 1 2 DISPOFF#
LVDSA1+ 9 7 8 10 LVDSB0+ <30> BKOFF#
<14> LVDSA1+ 9 10 LVDSB0+ <14>
LVDSA1- 11 12 LVDSB0- 0.01U_0402_16V7K D7 RB751V_SOD323
<14> LVDSA1- 11 12 LVDSB0- <14> 2 2 2
13 14
LVDSB2+ 15 13 14 16 LVDSBC+
<14> LVDSB2+ 15 16 LVDSBC+ <14>
LVDSB2- 17 18 LVDSBC- 10U_0805_10V4Z 1 2
<14> LVDSB2- 17 18 LVDSBC- <14> <14,30> ENABLT
19 20
LVDSA0+ 21 19 20 22 DISPOFF# D8 RB751V_SOD323
<14> LVDSA0+ 21 22
LVDSA0- 23 24
<14> LVDSA0- 23 24 INVT_PWM <30>
25 26 DAC_BRIG <30>
LVDSAC+ 27 25 26 28
<14> LVDSAC+ 27 28
LVDSAC- 29 30 DDC_CLK_LCD
<14> LVDSAC- 29 30 DDC_CLK_LCD <14> EMI require
31 32 DDC_DAT_LCD
31 32 DDC_DAT_LCD <14>
LVDSB1+ 33 34
<14> LVDSB1+ 33 34 INVPWR_B+
LVDSB1- 35 36
<14> LVDSB1- 35 36 INVPWR_B+
37 38
39 37 38 40
+3VS 39 40 B+ INVPWR_B+
1 1 L5
C622 C623 1 2
VGA@ACES_88107-4001_40P KC FBM-L11-201209-221LMAT_0805
2 0.01U_0402_16V7K 0.01U_0402_16V7K 2
2 2

+3VS

1
C305

4.7U_0805_10V4Z
2
+12VALW

1
D
2
R146
Q13
+LCDVDD 100K_0402_5% SI2302DS_SOT23

S
1

+12VALW

3
+LCDVDD
1

3 3

2
R147 1 1 1
2

R148 C306 C307 C308


1K_0402_5% R149
150K_0402_5% 0.1U_0402_16V4Z 4.7U_0805_10V4Z
1 2

100K_0402_5% 2 0.047U_0402_16V4Z 2 2
1

D
1

D
1

Q14 2 2
2N7002_SOT23 G G
S S Q15
3

2N7002_SOT23
1

SI2302DS: N CHANNEL
O

VGS: 4.5V, RDS: 85 mOHM


Q16 VGS: 2.5V, RDS: 115mOHM
DTC124EK_SC59 Id(MAX): 2.8A
G
I

VGS(MAX): +-8V
2

ENVDD
<14> ENVDD

4 4

Compal Electronics, Inc.


Title
LVDS Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 17 of 50
A B C D E F G H
A B C D E

@DAN217_SC59
CRT Connector +3VS +5VS +RCRT_VCC +CRTVDD

1
D9 D10 D11 F1 D12
1 2 2 1 W=40mils

FUSE_1A RB411D_SOT23
1 1

1
@DAN217_SC59 @DAN217_SC59 C309

3
0.1U_0402_16V4Z
2

JP7
6
L6 11
<30> M_SEN#
<14> CRT_R 1 2 RED_L 1
FCM2012C-800_0805 7
L7 12
1 2 GREEN_L 2
<14> CRT_G
FCM2012C-800_0805 8
L8 13
75_0402_1% 75_0402_1% 22P_0402_50V8J 22P_0402_50V8J 1 2 BLUE_L 18P_0402_50V8J 3
<14> CRT_B
FCM2012C-800_0805 9
14
1

1
DDC_MD2 4
1 1 1 1 1 1
R154 R155 R156 C310 C311 C312 C313 C314 C315 10
15
22P_0402_50V8J 18P_0402_50V8J 18P_0402_50V8J 5
2 2 2 2 2 2
2

75_0402_1% SUYIN_7849S-15G2T-HC

+CRTVDD R596
DDC_DAT_CRT <14>

1K_0402_5%
2 2
5

1 DDC_CLK_CRT <14>
C318
CRT_HSYNC 2 4 1 2 L9 1 2 D_HSYNC_L
<14> CRT_HSYNC
100P_0402_50V8K 1 1
U46 R597 0_0402_5% FBM-L11-160808-800LMT_0603 2 C319 C320
74AHCT1G125GW
3

1 2 L10 1 2 D_VSYNC_L 220P_0402_50V7K 220P_0402_50V7K


2 2
R598 0_0402_5% FBM-L11-160808-800LMT_0603
1 1
C316 C317
5

22P_0402_50V8J 22P_0402_50V8J
2 2
CRT_VSYNC 2 4
<14> CRT_VSYNC
U47
74AHCT1G125GW
3

@DAN217_SC59 +3VS

1
TV-Out Connector D13 D14 D15

@DAN217_SC59 @DAN217_SC59

3
3 3

S-Video
L11 1 2 LUMA_CL
<14,34> TV_LUMA
FLM1608081R8K_0603
JP8

1
L12 1 CRMA_CL 2
<14,34> TV_CRMA 2
FLM1608081R8K_0603 3
4
5
6
75_0402_1% 75_0402_1% 270P_0402_50V7K L13 1 COMPS_CL 7
<14,34> TV_COMPS 2
FLM1608081R8K_0603 SUYIN_35138S-07T1-DF
1

1 1 1 1 1 1
R163 R164 R165 C321 C322 C323 C324 C325 C326

2 2 2 2 2 2
2

TV_GND
75_0402_1% 270P_0402_50V7K 270P_0402_50V7K 330P_0402_50V7K 330P_0402_50V7K 330P_0402_50V7K

4 4
R462
0_0603_5%

Compal Electronics, Inc.


Title
CRT & TVout Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 18 50
Date: Thursday, October 16, 2003 Sheet of
A B C D E
A B C D E F G H I J

1 1

HDD Connector
PDD[0..15]
<12> PDD[0..15]

JP9
Place closely to PCIRST_IDE# +5VS
<12> PCIRST_IDE#
PDD7 1 2 PDD8
Placea caps. near HDD CONN.
2 JP31 3 4 2
PDD6 PDD9 10U_1206_10V4Z 1U_0805_25V4Z
PDD5 5 6 PDD10
PDIOW# PDIOR# PDD4 7 8 PDD11
9 10 1 1 1 1 1
PDD3 PDD12 C328 C329 C330 C331 C332
11 12
1

PDD2 PDD13
R167 R168 PDD1 13 14 PDD14
PDD0 15 16 PDD15 2 2 2 2 2
@10_0402_5% @10_0402_5% 17 18 1000P_0402_50V7K 10U_1206_10V4Z 0.1U_0402_16V4Z
PDDREQ 19 20
<12> PDDREQ
2

PDIOW# 21 22
1 1 +3VS 1 2 <12> PDIOW#
C333 C334 R169 4.7K_0402_5% PDIOR# 23 24 R170
<12> PDIOR# 25 26
PDIORDY PCSEL 1 2
<12> PDIORDY 27 28
@15P_0402_50V8J @15P_0402_50V8J PDDACK#
<12> PDDACK# 29 30
2 2 IRQ14 470_0402_5%
<12> IRQ14 31 32
<12> PDA1 33 34
3 +5VS 1 2 <12> PDA0 PDA2 <12> 3
R171 100K_0402_5% 35 36
<12> PDCS1# 37 38 PDCS3# <12>
PHDD_LED#
39 40
+5VS 41 42 +5VS
PDD7 1 2 43 44
R172 10K_0402_5% SUYIN_200006FA044S503ZU

IRQ14 1 2
R173 10K_0402_5%

PDDREQ 1 2
R174 5.6K_0402_5%

1 2
C335 33P_0402_50V8J
4 4
Placea caps. near CDROM
CD-ROM Connector CONN.
+5VS
+5VS
W=100 mils
1 1 1 1

1
C336 C337 C338 C339
R474
1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0805_25V4Z 10U_1206_10V4Z
100K_0402_5% 2 2 2 2
D53 1N4148_SOT23

2
PHDD_LED# 1 2
ACT_LED#
5 ACT_LED# <33> 5
SHDD_LED# 1 2

D54 1N4148_SOT23

C344 @47P_0402_50V8J
2 1
<12> SDD[0..15] SDD[0..15]
R175 10K_0402_5%
2 1 CD_AGND <25>
JP10
CDROM_L CDROM_R
6 <25> CDROM_L 1 2 CDROM_R <25> 6
PCIRST_IDE# 3 4 SDD8
SDD7 5 6 SDD9
SDD6 7 8 SDD10
SDD5 9 10 SDD11
SDD4 11 12 SDD12
SDD3 13 14 SDD13
SDD2 15 16 SDD14
SDD1 17 18 SDD15
R176 SDD0 19 20
21 22 SDDREQ <12>
+3VS 2 1 SDIOR# <12>
4.7K_0402_5% 23 24
<12> SDIOW# 25 26
<12> SDIORDY 27 28 SDDACK# <12>
<12> IRQ15 29 30 PDIAG# R177
1 2@100K_0402_5% +5VS
<12> SDA1 31 32
<12> SDA0 33 34 SDA2 <12>
7 7
<12> SDCS1# 35 36 SDCS3# <12>
SHDD_LED# W=80mils
37 38 +5VS
+5VS +5VS IRQ15 1 2
R179 39 40 R178 10K_0402_5%
+5VS 41 42 +5VS
+5VS 2 1 2 1
43 44 C345 0.1U_0402_16V4Z SDDREQ 1 2
100K_0402_5% SEC_CSEL 45 46 R180 5.6K_0402_5%
47 48 1 2
49 50 +5VS
2

R181 100K_0402_5% 1 2
R182 CD-ROM CONN. C346 33P_0402_50V8J

470_0402_5%
1

8
Title
Compal Electronics, Inc. 8

IDE/FDD/CD-ROM Module
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 19 of 50
A B C D E F G H I J
5 4 3 2 1

Note : Imax for


VDD25 = 40mA +3VLAN
2.5V should be ready JP11

before +3V is ready 1


C347
1
C348
1
C349
1
C350
1
C351
2
C352
ACTIVITY# 12
Amber LED-
1 2 T=10mil 11
+3VLAN Amber LED+
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z R183 300_0402_5% 16
2 2 2 2 2 1 SHLD4
8
PR4- 15
+3VALW +3VLAN SHLD3
R459 7
PR4+
<34> RJ45_RXX- RJ45_RXX- 6
D PR2- D
1 Q22
C353 1 5
0_0805_5% C354 +2.5VLAN PR3-
1U_0603_10V6K 3 R184 4
2 E 1U_0603_10V6K PR3+
1 @0_0603_5% 2 1 1 1 RJ45_RXX+ 3
C <34> RJ45_RXX+ PR2+
C355 C356 C357
VCTRL 2 RJ45_TXX- 2
B <34> RJ45_TXX- PR1-
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 14
2 2 2 RJ45_TXX+ SHLD2
+2.5VLAN <34> RJ45_TXX+ 1
2SA1036K_SOT23 PR1+
13
LINK10_100# 10 SHLD1
1 2 Green LED-
C358 C359
1 2 T=10mil 9
+3VLAN Green LED+
10U_0805_10V4Z 0.1U_0402_16V4Z R185 300_0402_5%
2 1
AMP RJ45 with LED

2
R186 R187

75_0402_1% 75_0402_1%

1
PCI_AD[0..31] U7
<12,21,22,28> PCI_AD[0..31]
PCI_AD0 47 48 +3VLAN RJ45_GND 1 2
AD0 VDD25 +2.5VLAN <34> RJ45_GND
PCI_AD1 46 94
PCI_AD2 AD1 VDD25 C360 1000P_1206_2KV7K
45
PCI_AD3 43 AD2 58 +2.5VLAN
PCI_AD4 42 AD3 AVDD25 L14
AD4

Power
PCI_AD5 41 59 LAN_IO 1 2
PCI_AD6 AD5 AVDD KC FBM_L11-201209-601LMT 0805
40
PCI_AD7 AD6
39 70 2 2 2
PCI_AD8 AD7 AVDD C363 C364 C365
36 Close to RTL8101L
PCI_AD9 35 AD8 75
C PCI_AD10 AD9 AVDD 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C
34
PCI_AD11 AD10 1 1 1
33 2
PCI_AD12 AD11
32
PCI_AD13 AD12 U8 C366
30
PCI_AD14 29 AD13 52 EEDO 4 5 0.1U_0402_16V4Z
AD14 EEDO DO GND 1
PCI_AD15 28 53 EEDI 3 6 1 C367
PCI_AD16 AD15 EEDI EESK DI NC
15 54 2 7
PCI_AD17 AD16 EESK EECS SK NC 0.1U_0402_16V4Z
14 55 1 8 +3VLAN
PCI_AD18 AD17 EECS CS VCC 2
13
PCI_AD19 12 AD18 78 ACTIVITY# AT93C46-10SI-2.7_SO8
PCI_AD20 AD19 LED0 LINK10_100#
11 77
PCI_AD21 AD20 LED1
10 76

1
PCI_AD22 AD21 LED2
9 1 2 +3VLAN
PCI_AD23 AD22 LAN_TX+ R188 5.6K_0402_5% R189 R190
8 72
PCI_AD24 96 AD23 TXD+ 71 LAN_TX-
LAN I/F
PCI I/F

AD24 TXD- 49.9_0402_1% 49.9_0402_1%


PCI_AD25 93
PCI_AD26 92 AD25 68 LAN_RX+
1:1

2
AD26 RXIN+ U9
PCI_AD27 91 67 LAN_RX-
PCI_AD28 AD27 RXIN-
89
PCI_AD29 87 AD28 61 CLKOUT LAN_TX- 8 9 RJ45_TXX-
PCI_AD30 AD29 X1 LAN_TX+ TD- TX- RJ45_TXX+
86 7 10
PCI_AD31 AD30 TD+ TX+
85 6 11
PCI_CBE#[0..3] AD31 XTALFB C368 0.1U_0402_16V4Z CT CT
<12,21,22,28> PCI_CBE#[0..3] 60
PCI_CBE#0 X2
38 1 2
PCI_CBE#1 27 C/BE#0 64 R191 1 2 15K_0402_5% 3 14
PCI_CBE#2 C/BE#1 LWAKE LAN_RX- CT CT RJ45_RXX-
17 2 15
PCI_CBE#3 84 C/BE#2 74 ISOB R192 2 1 1K_0402_5% LAN_RX+ 1 RD- RX- 16 RJ45_RXX+
+3VS

1
C/BE#3 ISOLATE# RD+ RX+

1
PCI_AD17 1 2 98 65 2 1
IDSEL RTSET R195 R196
R193 100_0402_5% R194 5.6K_0603_1%
R197 R198 NS0019_16P 75_0402_1% 75_0402_1%
<12,21,22,28> PCI_PAR 24 63
PAR RTT3 49.9_0402_1% 49.9_0402_1%
<12,21,22,28> PCI_FRAME# 18

2
B 19 FRAME# 56 VCTRL RJ45_GND B
<12,21,22,28> PCI_IRDY#

2
IRDY# VCTRL
<12,21,22,28> PCI_TRDY# 20 1
21 TRDY# 1 C369
<12,21,22,28> PCI_DEVSEL# DEVSEL# AC_RST# 2
AC-Link

<12,21,22,28> PCI_STOP# 23 3
STOP# AC_SYNC C370 1000P_1206_2KV7K
4
25 AC_DOUT 5 0.1U_0402_16V4Z 2
<12,21,22,28> PCI_PERR# PERR# AC_DIN
26 7 1
<12,21,22,28> PCI_SERR# SERR# AC_BCK
<12> PCI_REQ#1 83
REQ#
<12> PCI_GNT#1 82 100
GNT# GPIO0 99
GPIO1
<12,22> PIRQB# 80
79 INTA#
<31> LAN_PME# 57
INTB#
PME# ROMCS/OE#
51
69 Y4
Layout Recommend :
NC CLKOUT 1 XTALFB
81 2
<12,21,22,28> PCIRST#
<12> CLK_PCI_LAN
1 2
97
50
RST#
PCICLK 2 1 25MHZ_20P_1BX25000CK1A 2
1. LAN_RD+, LAN_RD- should be equal length as possible
R572 10K_0402_5% CLKRUN# DGND1
16
6 DGND2 31 C371 C372
2. LAN_TD+, LAN_TD- should be equal length as possible
1

+3VLAN VDD DGND3 27P_0402_50V8J 27P_0402_50V8J


22 44
R200 VDD DGND4 2 1

@22_0402_5%
37
49
90
VDD
VDD
Power DGND5
AGND1
88
62
66
3. The Maximum trace length between LAN chip(U22) and
VDD AGND2
95 73
Magnetic(U24) is 12cm(4.7")
2

VDD AGND3
1
C373 RTL8101L_LQFP100

@10P_0402_50V8K
4. The distance between RJ45(Conn.) and Magnetic(U24) should
2
be as short as possible
A A

Compal Electronics, Inc.


Title
LAN RealTech8100BL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 20 of 50
5 4 3 2 1
5 4 3 2 1

+3VS +3VS

2 1 1 1 1 1 1 1 1 1
R201 10K_0402_5% C374 C375 C376 C377 C378 C379 C380 C381

RP70 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z


+3VS 1 8 2 2 2 2 2 2 2 2
2 7
3 6
4 5

D 4.7K_1206_8P4R_5% D

20
35
48
62
78

87

86
96
10
11
PCI_AD[0..31] U10 +3VS
<12,20,22,28> PCI_AD[0..31] +3VS

CYCLEOUT/CARDBUS
VDDP
VDDP
VDDP
VDDP
VDDP

CNA
TEST17
TEST16
CYCLEIN
15
PCI_AD0 84 DVDD 27
PCI_AD1 82 PCI_AD0 DVDD 39
PCI_AD2 81 PCI_AD1 DVDD 51 1 1 1 1 1
PCI_AD3 80 PCI_AD2 DVDD 59 C382 C383 C384 C385 C386
PCI_AD4 79 PCI_AD3 DVDD 72
PCI_AD5 77 PCI_AD4 DVDD 88 L15 1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K
PCI_AD6 76 PCI_AD5 DVDD 100 BLM21A601SPT_0805 2 2 2 2 2
PCI_AD7 74 PCI_AD6 DVDD 7 +PLLVDD 1 2
PCI_AD7 PLLVDD +3VS
PCI_AD8 71 1 1 1
PCI_AD9
PCI_AD10
70 PCI_AD8
PCI_AD9
TSB43AB21 AVDD
AVDD
2 C387 C388
69 107
PCI_AD11
PCI_AD12
67 PCI_AD10
PCI_AD11
/(TSB43AB22) AVDD
AVDD
108
2 2
0.01U_0402_16V7K
66 120
PCI_AD13 65 PCI_AD12 AVDD 4.7U_0805_10V4Z
PCI_AD14 63 PCI_AD13 PCI BUS INTERFACE
PCI_AD15 61 PCI_AD14 106 1 2
PCI_AD16 46 PCI_AD15 CPS R202 1K_0402_5%
PCI_AD17 45 PCI_AD16
PCI_AD18 43 PCI_AD17 125
PCI_AD19 42 PCI_AD18 NC/(TPBIAS1) 124
PCI_AD20 41 PCI_AD19 NC/(TPA1+) 123
PCI_AD21 40 PCI_AD20 NC/(TPA1-) 122
PCI_AD22 38 PCI_AD21 NC/(TPB1+) 121
PCI_AD23 37 PCI_AD22 NC/(TPB1-)
C PCI_AD24 32 PCI_AD23 118 1 2 C
BIAS CURRENT
PCI_AD25 31 PCI_AD24 R0 R203
PCI_AD26 29 PCI_AD25 6.34K_0402_1%
PCI_AD27 28 PCI_AD26 Near 1394 IC
PCI_AD28 26 PCI_AD27
PCI_AD29 25 PCI_AD28 119
PCI_AD30 24 PCI_AD29 R1 1 2
PCI_AD31 22 PCI_AD30 6 C389 22P_0402_50V8J
OSCILLATOR

1
34 PCI_AD31 X0
<12,20,22,28> PCI_CBE#3 PCI_C/BE3
47 X1
<12,20,22,28> PCI_CBE#2 PCI_C/BE2
60 24.576MHz_16P_3XG-24576-43E1
<12,20,22,28> PCI_CBE#1 PCI_C/BE1
73 5 30ppm

2
<12,20,22,28> PCI_CBE#0 PCI_C/BE0 X1
CLK_PCI_1394 16 1 2
<12> CLK_PCI_1394 PCI_CLK
18 C390 22P_0402_50V8J
<12> PCI_GNT#0 PCI_GNT
<12> PCI_REQ#0
19 FILTER 3 1 2
PCI_AD16 1 2 36 PCI_REQ FILTER0 C391
ID: AD16 R204 100_0402_5% 49 PCI_IDSEL 4 0.1U_0402_16V4Z
<12,20,22,28> PCI_FRAME# PCI_FRAME FILTER1
<12,20,22,28> PCI_IRDY#
50
52 PCI_IRDY 92 SDA_1394
<12,20,22,28> PCI_TRDY#
53 PCI_TRDY EEPROM 2 WIRE BUS SDA
<12,20,22,28> PCI_DEVSEL# PCI_DEVSEL
54 91 SCL_1394 1
<12,20,22,28> PCI_STOP#

1
56 PCI_STOP SCL
<12,20,22,28> PCI_PERR# PCI_PERR
<12,22> PIRQA#
13 POWER CLASS 99 R207 R208 C392
21 PCI_INTA/CINT PC0 98 56.2_0402_1% 56.2_0402_1% 1U_0805_25V4Z
57 PCI_PME/CSTSCHG PC1 97 2
<12,20,22,28> PCI_SERR# PCI_SERR PC2
58

2
<12,20,22,28> PCI_PAR PCI_PAR
1 2 12 116 XTPBIAS0 JP12
PCI_CLKRUN PHY PORT 1 TPBIAS0
R573 10K_0402_5% 85 115 XTPA0+ Connect To
<12,20,22,28> PCIRST# PCI_RST TPA0+ 4
114 XTPA0-
B TPA0- 113 XTPB0+ 3 Shielding B
TPB0 + 112 XTPB0- 2
TPB0 - 1 GND
AMP_440168-2
EEPROM cancel,

1
G_RST# connect to PCIRST# 94
TEST9
TEST8
95 need System R210
56.2_0402_1%
R211
56.2_0402_1%
14
RP88 G_RST 101 Support
CLK_PCI_1394 1 8 89 TEST3 102
PLLGND1

2
REG_EN

2 7 90 GPIO3 TEST2 104


REG18

REG18
DGND
DGND

DGND
DGND
DGND
DGND
DGND
DGND
DGND

DGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND

3 6 SCL_1394 GPIO2 TEST1 105


1

1
4 5 SDA_1394 TEST0
1
R214 C393 R215
220_1206_8P4R_5% TSB43AB21_PQFP128 The connector depend on
8
9
109
110
111
117
126
127
128
17
23
30
33
44
55
64
68
75
83
93
103

@10_0402_5% 220P_0402_50V7K 5.11K_0402_1%


2 defferent project
2

2
1 ** GPIO2 and GPIO3 defaults as an input
C394 and if it is not implemented, it is
@10P_0402_25V8K
recommended that it be pulled low to Close Chip
2 ground with a 220 ohm resistor.
1 1
C395 C396

0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2
Power on Entry S3 S3 Wake-up
CLOSE CHIP
VCC(+3VS)
A A

T1: >2ms
GLOBA_RESET#
T2: >=0
T1 T1
Compal Electronics, Inc.
Note: GLOAB_RESET# Title
PCI_PCIRST# Can Connect to IEEE 1394 CONTROLLER
PCI_PCIRST# THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
LA-1851 0.5
T2 T2 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 21 of 50
5 4 3 2 1
A B C D E

CARD_LED <35> +3V


1 2 JP24A2
+3V <12,20> PIRQB# SIRQ <12,29,30>
R216 10K_0402_5%
<12,21> PIRQA#
R574 1 2 10K_0402_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
<30> PCM_SUSP# 1 2 2 2 2 2 2 2 2 2 2
D16 RB751V_SOD323 CLK_48M_R 2 1 CLK_48M C398 C399 C400 C401 C402 C403 C404 C405 C406
1 2 R219 1620@0_0402_5%
+3VALW <23> SDATA
R218 10K_0402_5% SCLK +VCCP CARDBUS HOUSING for PCI1620
<23> SCLK +3V 1 1 1 1 1 1 1 1 1
<23> SLATCH +S1_VCC 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
<25> PCM_SPK# +S2_VCC
C407 1 2

2
0.1U_0402_16V4Z @JP24A1
R220

W11

W13
G19
C15

D19

C14

N19
K19

E18

E17

A16
E14

B15
A15

A12

A10

P19
F14

F15

F13

J19

W8
G1

N1

R1
E5

A7
1 @43K_0402_5% 1

L1
U37

CLOCK
DATA

VCCP

VCCA

VCCB
2.5V
VR_EN#

SUSPEND#
SPKROUT
LATCH

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
NC

NC
CARDBUS HOUSING for PCI1520
S2_D0 W10 G17 S1_D0
S2_D1 U10 B_CAD27/B_D0 A_CAD27/A_D0 F18 S1_D1
S2_D2 B_CAD29/B_D1 A_CAD29/A_D1 S1_D2
P10 F17
S2_D3 H3 B_RSVD/B_D2 A_RSVD/A_D2 P11 S1_D3
S2_D4 H1
B_CAD0/B_D3
B_CAD1/B_D4
FUNCTION POWER A_CAD0/A_D3
A_CAD1/A_D4
W12 S1_D4 EMI require
S2_D5 J2 U12 S1_D5 +VCCP 1 2 +3VS
S2_D6 J5 B_CAD3/B_D5 A_CAD3/A_D5 R12 S1_D6 R469 0_0402_5% CLK_48M_R
S2_D7 B_CAD5/B_D6 A_CAD5/A_D6 S1_D7
K2 U13
S2_D8 B_CAD7/B_D7 A_CAD7/A_D7 S1_D8
V10 G14 1 2 +3V

1
S2_D9 R10 B_CAD28/B_D8 A_CAD28/A_D8 G15 S1_D9 R470 @0_0402_5%
S2_D10 B_CAD30/B_D9 A_CAD30/A_D9 S1_D10 R468
V11 E19 2
S2_D11 H2 B_CAD31/B_D10 A_CAD31/A_D10 R11 S1_D11 C397
SCLK S2_D12 B_CAD2/B_D11 A_CAD2/A_D11 S1_D12 @10_0402_5%
J1 V12
S2_D13 B_CAD4/B_D12 A_CAD4/A_D12 S1_D13 0.1U_0402_16V4Z
J3 P12

2
S2_D14 B_CAD6/B_D13 A_CAD6/A_D13 S1_D14 1
J6 V13 1
1

S2_D15 B_RSVD/B_D14 A_RSVD/A_D14 S1_D15 C621


K3 P13
R591 B_CAD8/B_D15 A_CAD8/A_D15
@10P_0402_25V8K
47K_0402_5% S2_A0 R8 J14 S1_A0 2
S2_A1 B_CAD26/B_A0 A_CAD26/A_A0 S1_A1
W7 J17
2

S2_A2 V7 B_CAD25/B_A1 A_CAD25/A_A1 J18 S1_A2


S2_A3 P8 B_CAD24/B_A2 A_CAD24/A_A2 K15 S1_A3
S2_A4 B_CAD23/B_A3 A_CAD23/A_A3 S1_A4
V6 K18
S2_A5 B_CAD22/B_A4 A_CAD22/A_A4 S1_A5
U6 L14
S2_A6 B_CAD21/B_A5 A_CAD21/A_A5 S1_A6
V5 L17

2
S2_A7
S2_A8
S2_A9
U5
M6
M2
B_CAD20/B_A6
B_CAD18/B_A7
B_CC/BE1#/B_A8
CARDBUS CONTROLLER A_CAD20/A_A6
A_CAD18/A_A7
A_CC/BE1#/A_A8
M19
T19
U15
S1_A7
S1_A8
S1_A9 2
B_CAD14/B_A9 A_CAD14/A_A9
S2_A10 K6
PCI1520 PBGA 209 R13 S1_A10

SLOT A
S2_A11 B_CAD9/B_A10 A_CAD9/A_A10 S1_A11 +3VS
L6 SLOT B P14
S2_A12 B_CAD12/B_A11 A_CAD12/A_A11 S1_A12
T1 M17
S2_A13 N2 B_CC/BE2#/B_A12 A_CC/BE2#/A_A12 P15 S1_A13
S2_A14 B_CPAR/B_A13 A_CPAR/A_A13 S1_A14
N6 R18

1
S2_A15 B_CPERR#/B_A14 A_CPERR#/A_A14 S1_A15
P5 N18
S2_A16 B_CIRDY#/B_A15 A_CIRDY#/A_A15 S1_A16 R221
P6 M14
S2_A17 B_CCLK/B_A16 A_CCLK/A_A16 S1_A17
M3 W16
S2_A18 M5 B_CAD16/B_A17 A_CAD16/A_A17 R17 S1_A18 10K_0402_5%
S2_A19 B_RSVD/B_A18 A_RSVD/A_A18 S1_A19 X4
N3 N14

2
S2_A20 B_CBLOCK#/B_A19 A_CBLOCK#/A_A19 S1_A20 CLK_48M
P2 P17 4 3 1 2 CLK_48M <29>
S2_A21 B_CSTOP#/B_A20 A_CSTOP#/A_A20 S1_A21 VDD OUT R222 22_0402_5%
P3 N15
S2_A22 B_CDEVSL#/B_A21 A_CDEVSL#/A_A21 S1_A22
R2 N17 1 1 2

1
S2_A23 R3 B_CTRDY#/B_A22 A_CTRDY#/A_A22 M15 S1_A23 OE GND C409
S2_A24 B_CFRAME#/B_A23 A_CFRAME#/A_A23 S1_A24 C408 48MHZ_4P_FN4800002
W4 M18
S2_A25 R6 B_CAD17/B_A24 A_CAD17/A_A24 L19 S1_A25 0.1U_0402_16V4Z @15P_0402_50V

2
B_CAD19/B_A25 A_CAD19/A_A25 2

W5
<23,24> S2_RST B_CRST#/B_RESET
<23,24> S2_WE# N5
B_CGNT/B_WE#
<23> S2_IOWR# M1
B_CAD15/B_IOWR#
<23> S2_IORD# L5 L15 S1_RST <23>
U7 B_CAD13/B_IORD# A_CRST#/A_RESET P18
<23,24> S2_REG# B_CC/BE3#/B_REG# A_CGNT#/A_WE# S1_WE# <23>
<23,24> S2_OE# L3 R14 S1_IOWR# <23>
R7 B_CAD11/B_OE# A_CAD15/A_IOWR# V15
<23,24> S2_INPACK# B_CREQ#/B_INPACK# A_CAD13/A_IORD# S1_IORD# <23>
<23,24> S2_RDY# V8 K14 S1_REG# <23>
B_CINT#/B_IREQ# A_CC/BE3#/A_REG#
<23,24> S2_BVD2 V9 W15 S1_OE# <23>
W9 B_CAUDIO/B_SPKR# A_CAD11/A_OE# K17
<23,24> S2_WAIT# B_CSERR#/B_WAIT# A_CREQ#/A_INPACK# S1_INPACK# <23>
<23,24> S2_BVD1 U9 H19 S1_RDY# <23>
B_CSTSCHG/B_STSCHG# A_CINT#/A_IREQ#
<23> S2_WP R9 H17 S1_BVD2 <23>
3 B_CCLKRUN/B_IOIS16# A_CAUDIO/A_SPKR# H18 3
A_CSERR#/A_WAIT# S1_WAIT# <23>
<23,24> S2_VS1 U8 H14 S1_BVD1 <23>
P7 B_CVS1/B_VS1# A_CSTSCHG/A_STSCHG# H15
<23,24> S2_VS2 B_CVS2/B_VS2# A_CCLKRUN#/A_IOIS16# S1_WP <23>

<23,24> S2_CE1# K5 J15 S1_VS1 <23>


L2 B_CC/BE0#/B_CE1# A_CVS1/A_VS1# L18
<23> S2_CE2# B_CAD10/B_CE2# A_CVS2/A_VS2# S1_VS2 <23>
H5 U14
<23,24>
<23,24>
S2_CD1#
S2_CD2# P9
B_CCD1#/B_CD1#
B_CCD2#/B_CD2#
PCI INTERFACE A_CAD10/A_CE2# V14
A_CC/BE0#/A_CE1#
S1_CE2#
S1_CE1#
<23>
<23>
RI_OUT#/PME#

U11 S1_CD1# <23>


A_CCD1#/A_CD1# G18
A_CCD2#/A_CD2# S1_CD2# <23>
DEVSEL#

FRAME#

GROUND
C/BE3#
C/BE2#
C/BE1#
C/BE0#

GRST#

SERR#
PERR#

TRDY#
PRST#

STOP#
IRDY#
IDSEL
GNT#
REQ#
PCLK
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PAR
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9

PCI1520GHK_PBGA209
F1

F2
F3

F5

F9

F8
F6

F7
G2
G3

G5

E2

E3

B12
A4

E6
B5

B8
A8
E9

B9

B10

E11
B11
A11

E12

B14

G6

E13

B13
A13

E7
E10

B6
B7

E8
A5

A6
A9
A14
E1
K1
P1
F10

F12
F11

C12

C11
C13
C10

R19

F19
W14
H6

D1

C5

C8

C9

C6

C7

W6
CLK_PCI_PCM
<12,20,21,28> PCI_AD[0..31]

1
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

<12,20,21,28> PCI_CBE#[0..3]
R565
S1_D[0..15]
<23> S1_D[0..15]
@10_0402_5%
S1_A[0..25]
<23> S1_A[0..25] PCI_PAR <12,20,21,28>

2
PCI_FRAME# <12,20,21,28> 1
S2_D[0..15] C777
<23,24> S2_D[0..15] PCI_TRDY# <12,20,21,28>
PCI_IRDY# <12,20,21,28>
S2_A[0..25] @10P_0402_25V8K
PCI_STOP# <12,20,21,28>
<23,24> S2_A[0..25] 2
4 <31> PCM_PME# PCI_DEVSEL# <12,20,21,28> 4
1 2 PCI_AD20
R224 100_0402_5%
PCI_PERR# <12,20,21,28>
PCI_SERR# <12,20,21,28>
PCI_REQ#2 <12>
<23,30> G_RST# 1 2 PCI_GNT#2 <12>
R587 0_0402_5% CLK_PCI_PCM
CLK_PCI_PCM <12>
PCIRST# <12,20,21,28>
1 2 1 2
+3V
R225 @10K_0402_5% R226 1520@0_0402_5% Compal Electronics, Inc.
1 2 Title

C410 @0.1U_0402_16V4Z CardBus Controller PCI1620


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 22 of 50
A B C D E
PCMCIA POWER CTRL.
CARDBUS SOCKET <22> S1_D[0..15]
S1_D[0..15]
S1_A[0..25]
+12VALW

<22> S1_A[0..25] S2_D[0..15]


<22,24> S2_D[0..15] S2_A[0..25]

2
C411 <22,24> S2_A[0..25] +3V
1 2 R460
+5V
JP13 1000P_0402_50V7K @0_0603_5%
U12

1
1 35
S1_D3 2 1 35 36 S1_CD1# 3 20
2 36 S1_CD1# <22> <22> SDATA DATA 12V
S1_D4 3 37 S1_D11 4 7 1 2 C412
3 37 <22> SCLK CLOCK 12V
S1_D5 4 38 S1_D12 5 @2.2U_0805_10V4Z
4 38 <22> SLATCH LATCH
S1_D6 5 39 S1_D13 12
5 39 <22,30> G_RST# RESET#
S1_D7 6 40 S1_D14 15 14 1 2 C413
S1_CE1# 7 6 40 41 S1_D15 1 2 21 OC# 3.3V 13 4.7U_0805_10V4Z
<22> S1_CE1# 7 41 +5V SHDN# 3.3V
S1_A10 8 42 S1_CE2# R227 4.7K_0402_5% 1 2 C414
S1_OE# 8 42 S1_VS1 S1_CE2# <22> 0.1U_0402_16V4Z
<22> S1_OE#
9 43
S1_A11 10 9 43 44 S1_IORD# S1_VS1 <22> +S1_VPP 8 24
10 44 S1_IORD# <22> AVPP 5V
S1_A9 11 45 S1_IOWR# +S2_VPP 19 2
11 45 S1_IOWR# <22> BVPP 5V
S1_A8 12 46 S1_A17 1
S1_A13 13 12 46 47 S1_A18 5V
S1_A14 14 13 47 48 S1_A19 +S1_VCC 9 11 1 2 C416
S1_WE# 15 14 48 49 S1_A20 10 AVCC GND 4.7U_0805_10V4Z
<22> S1_WE# 15 49 AVCC
S1_RDY# 16 50 S1_A21 1 2 C417
<22> S1_RDY# 16 50
17 51 +S2_VCC 17 23 0.1U_0402_16V4Z
17 51 +S1_VCC BVCC NC
+S1_VCC 18 52 18 22 1 2 C418
18 52 +S1_VPP BVCC NC 0.1U_0402_16V4Z
+S1_VPP S1_A16 19 53 S1_A22 1 1 16
S1_A15 20 19 53 54 S1_A23 C419 C420 NC 6
S1_A12 21 20 54 55 S1_A24 NC
S1_A7 22 21 55 56 S1_A25 4.7U_0805_10V4Z 4.7U_0805_10V4Z
S1_A6 23 22 56 57 S1_VS2 2 2 TPS2224ADBR_HTSSOP24
23 57 S1_VS2 <22>
S1_A5 24 58 S1_RST
24 58 S1_RST <22>
S1_A4 25 59 S1_WAIT#
25 59 S1_WAIT# <22>
S1_A3 26 60 S1_INPACK#
26 60 S1_INPACK# <22>
S1_A2 27 61 S1_REG#
27 61 S1_REG# <22>
S1_A1 28 62 S1_BVD2
28 62 S1_BVD2 <22>
S1_A0 29 63 S1_BVD1
S1_D0 30 29 63 64 S1_D8 S1_BVD1 <22>
S1_D1 31 30 64 65 S1_D9
S1_D2 32 31 65 66 S1_D10
S1_WP 33 32 66 67 S1_CD2#
<22> S1_WP 33 67 S1_CD2# <22>
34 68
69 34 68 70 1
71 GND GND 72 C424
73 GND GND 74
75 GND GND 76 1000P_0402_50V7K
77 GND GND 78 2
79 GND GND 80
81 GND GND 82
83 GND GND 84 +S1_VCC +S1_VPP
GND GND

FOX_WZ21131-G2-P4 1 1 1
C427 1 1 C421 C630 C631
1 2 C422 C423
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
JP14 1520@1000P_0402_50V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2
2 2
1 35
S2_D3 2 1 35 36 S2_CD1#
2 36 S2_CD1# <22,24>
S2_D4 3 37 S2_D11
S2_D5 4 3 37 38 S2_D12 +S2_VCC +S2_VPP
S2_D6 5 4 38 39 S2_D13
S2_D7 6 5 39 40 S2_D14 1520@0.1U_0402_16V4Z
S2_CE1# 7 6 40 41 S2_D15
<22,24> S2_CE1# 1 1 1 1 1
S2_A10 8 7 41 42 S2_CE2# C425 C426 C428 C632 C633
8 42 S2_CE2# <22>
S2_OE# 9 43 S2_VS1
<22,24> S2_OE# 9 43 S2_VS1 <22,24>
S2_A11 10 44 S2_IORD# 1520@0.1U_0402_16V4Z
10 44 S2_IORD# <22> 2 2 2 2 2
S2_A9 11 45 S2_IOWR#
S2_A8 11 45 S2_A17 S2_IOWR# <22> 1520@0.1U_0402_16V4Z 1520@0.1U_0402_16V4Z 1520@0.1U_0402_16V4Z
12 46
S2_A13 13 12 46 47 S2_A18
S2_A14 14 13 47 48 S2_A19
S2_WE# 15 14 48 49 S2_A20
<22,24> S2_WE# 15 49
S2_RDY# 16 50 S2_A21
<22,24> S2_RDY# 16 50
17 51 +S2_VCC
+S2_VCC 18 17 51 52
18 52 +S2_VPP
+S2_VPP S2_A16 19 53 S2_A22
S2_A15 20 19 53 54 S2_A23
S2_A12 21 20 54 55 S2_A24
S2_A7 22 21 55 56 S2_A25
S2_A6 23 22 56 57 S2_VS2
S2_A5 23 57 S2_RST S2_VS2 <22,24>
24 58
24 58 S2_RST <22,24>
S2_A4 25 59 S2_WAIT#
S2_A3 25 59 S2_INPACK# S2_WAIT# <22,24>
26 60
S2_A2 26 60 S2_REG# S2_INPACK# <22,24>
27 61
27 61 S2_REG# <22,24>
S2_A1 28 62 S2_BVD2
S2_A0 28 62 S2_BVD1 S2_BVD2 <22,24>
29 63
S2_D0 29 63 S2_D8 S2_BVD1 <22,24>
30 64
S2_D1 31 30 64 65 S2_D9
S2_D2 32 31 65 66 S2_D10
S2_WP 33 32 66 67 S2_CD2#
<22> S2_WP 33 67 S2_CD2# <22,24>
34 68
69 34 68 70 1
71 GND GND 72 C429
73 GND GND 74
75 GND GND 76 1520@1000P_0402_50V7K
77 GND GND 78 2
79 GND GND 80
81 GND GND 82
83 GND GND 84
Compal Electronics, Inc.
GND GND B
Title

1520@FOX_WZ21131-G2-P4
CARD BUS SOCKET
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 23 of 50
10 9 8 7 6 5 4 3 2 1

+3V

MC_WP#
H +S2_VCC H

1
Close to Cardbus socket JP14 R228 R229

1
+S2_VCC Q23

2
@10K_0402_5% @10K_0402_5% 1620@MMBT3904_SOT23

C
R230

2
D17
1620@43K_0402_5%
<22,23> S2_A22 S2_A22 1 2 MC_CD# 3

1
E

B
R231 1620@0_0402_5%
1

2
2

2
R233 +S2_VCC
S2_A25 1 2 DQRYDRV 2 1 2 R235 R236
<22,23> S2_A25
R232 1620@0_0402_5% SD_WP
1620@10K_0402_5% 1620@43K_0402_5% 1620@43K_0402_5%
1620@BAT54C_SOT23~D
1 1

1
G G

2
R239 C430 C431
2 1 D18 R234 R238 R237
1620@0.1U_0402_16V4Z 1620@0.1U_0402_16V4Z
1620@10K_0402_5% 3 1620@43K_0402_5% 1620@43K_0402_5% 1620@43_0402_5% 2 2

1
1 SM_CD#
R240 1 2 1620@0_0402_5% SQRY3
<22,23> S2_WAIT# JP15
R241 1 2 1620@0_0402_5% SQRY4 2
<22,23> S2_INPACK#

1
1620@BAT54C_SOT23~D SD_CD# SSFDC_10P/SD_6P/SD_3P(GND)
2
SD_SW_CD1
3
SD_DATA1 SD_SW_WP1
4
RP71 1 8 SD_DATA0 5 SD_8P(DAT1)
<22,23> S2_BVD1 SD_7P(DAT0)
2 7 SD_CLK/MS_CLK 6
<22,23> S2_D8 SD_5P(CLK)
3 6 SD_CMD 7
F <22,23> S2_D9
4 5 SD_CD/DATA3 8
SD_2P(CMD) F
<22,23> S2_D10 SD_1P(DAT3)
1620@0_1206_8P4R_5% SD_DATA2 9
RP72 1 8 SD_CD/DATA3 10 SD_9P(DAT2)
<22,23> S2_RDY# SSFDC_12P & SD_4P(VCC)
<22,23> S2_RST 2 7 1 2 11
3 6 SM_D4 SSFDC_11P(CD)
<22,23> S2_REG# 12
R242 1620@0_0402_5% SM_D3/MS_BS SSFDC_13P(D4)
<22,23> S2_BVD2 4 5 13
1620@0_1206_8P4R_5% SM_D5 SSFDC_9P(D3)
14
SM_D2/MS_SDIO 15 SSFDC_14P(D5)
SM_D6 SSFDC_8P(D2)
16
SM_D1/MS_RFU5 SSFDC_15P(D6)
17
SM_D7 SSFDC_7P(D1)
18
SM_D0/MS_RFU7 SSFDC_16P(D7)
19
SM_LVD 20 SSFDC_6P(D0)
R243 SSFDC_17P(LVD)
<22,23> S2_A14 1 2 1620@0_0402_5% SD_DATA1 SM_WP# 21
R244 1 2 1620@0_0402_5% SD_DATA0 SM_WE# SSFDC_5P(WP_IN)
<22,23> S2_A19 22
R245 1 2 1620@0_0402_5% SD_CLK/MS_CLK SM_R/B# 23 SSFDC_4P(WE)
E <22,23> S2_A16
SM_ALE SSFDC_19P(BSY) E
24
SM_RE# 25 SSFDC_3P(ALE)
SM_CLE 26 SSFDC_20P(RE)
SM_CE# SSFDC_2P(CLE)
27
MC_WP# SSFDC_21P(CE)
28
1 2 SSFDC_WP2(SW_WP2)
29
30 SSFDC_CD2(SW_CD2)
R246 @0_0402_5% SSFDC_22P/MS_3P/MS/9P(VCC)
31
RP73 SM_D6 MS_2P(BS)
<22,23> S2_D13 1 8 32
2 7 MS_4P(SDIO)
<22,23> S2_A18 33
SM_ALE MS_5P(RESERVED1)
<22,23> S2_WE# 3 6 34
4 5 SD_CMD 35 MS_6P(INS)
<22,23> S2_A20 MS_7P(RESERVED2)
1620@0_1206_8P4R_5% 36
RP74 1 8 SM_D4 37 MS_8P(SCLK)
<22,23> S2_D11 MS_10P & MS_1P/SSFDC_1P &SSFDC_18P(GND)
<22,23> S2_D5 2 7 SM_D3/MS_BS
3 6 SM_D5
D <22,23> S2_D12
SM_D2/MS_SDIO
D
<22,23> S2_D6 4 5 1620@TAI_SOL 4 IN 1 MEMORY CONNECTOR
1620@0_1206_8P4R_5%
RP75 1 8 SM_WE#
<22,23> S2_A13
<22,23> S2_D7 2 7 SM_D1/MS_RFU5
<22,23> S2_D14 3 6 SM_D7
4 5 SM_D0/MS_RFU7
<22,23> S2_CE1#

2
1620@0_1206_8P4R_5%
RP76 1 8 SM_LVD R247 R248 R249
<22,23> S2_D15
<22,23> S2_A10 2 7 SM_WP#
3 6 SM_R/B# 1620@43K_0402_5% 1620@43K_0402_5% 1620@43K_0402_5%
<22,23> S2_OE#
4 5 SM_RE#
<22,23> S2_A8

1
2

1
2

1
2
1620@0_1206_8P4R_5%
RP77 1 8 SD_DATA2 R250 R251 R252
<22,23> S2_A21
<22,23> S2_A15 2 7 MC_WP#
3 6 SM_CLE 1620@43K_0402_5% 1620@43K_0402_5% 1620@43K_0402_5%
<22,23> S2_A12
C 4 5 SM_CE# C
<22,23> S2_A24
1
2

1
2

1
2
1620@0_1206_8P4R_5%
R253 R254 R255

1620@43K_0402_5% 1620@43K_0402_5% 1620@43K_0402_5%


1
2

1
2

1
R256 1 2 1620@0_0402_5% R257 R258
<22,23> S2_CD1#
1620@43K_0402_5% 1620@43K_0402_5%
<22,23> S2_VS1
1

R259 1 2 1620@0_0402_5%
<22,23> S2_VS2

B B
R260 1 2 1620@0_0402_5%
<22,23> S2_CD2#

A Compal Electronics, Inc. A


Title

4 IN 1 CARD READER SOCKET


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 24 of 50
10 9 8 7 6 5 4 3 2 1
A B C D E F G H

+3VALW

+3VALW
+VDDA_CODEC
1
C432 U13

1
+3VALW W=40Mil 4 5
+5VS VIN VOUT
0.1U_0402_16V4Z R262
2 +5VAMP_CODEC R263
1 1 2 6 1 2 1 1
@100K_0402_1% C433 C434 DELAY SENSE or ADJ 28.7K_0402_1% C435 C436

14

14

1
1 U23B U15A 7 1 1

1
4 C437 4.7U_0805_6.3V6K 0.1U_0402_16V4Z ERROR CNOISE 4.7U_0805_6.3V6K 0.1U_0402_16V4Z
1
P
R265

P
<30> BEEP# A R266
6 1 2 1 2 2 1 1 2 R267 2 2 8 3 C438 R264 2 2
O I O SD GND 10K_0402_1%
5 G
10K_0402_1% 560_0402_5%

G
B 1U_0603_10V6K 10K_0402_1% SI9182DH-AD_MSOP8
1

2
SN74LVC32APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 2
7

2
C439 C440 1U_0603_10V6K 2 1
+5VS
0.22U_0603_10V7K 2 1 0.1U_0402_16V4Z
2 R268 10K_0402_5%

1
R269

10K_0402_1%

2
R270 C441
+3VALW MONO_IN 1 2 MONO_INC 1 2 MONO_INR
20K_0402_5% 1U_0603_10V6K

14
U15B 1 2

1
C442 C

P
R272 R271
3 4 2 1 1 2 2 Q24
<22> PCM_SPK# I O 2.4K_0402_5%
560_0402_5% B 2SC2411K_SOT23

G
1U_0603_10V6K E

3
SN74LVC14APWLE_TSSOP14

7
+5VAMP_CODEC
+3VALW
+5VAMP_CODEC 1 2 +VDDA_CODEC
14

L16 0_0805_5%
U15C
2 C443 2
P

R273 1 1 1 1
5 6 2 1 1 2 C444 C445 C446 C447
<12> SPKR I O
560_0402_5%
G

1U_0603_10V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_1206_10V4Z


2 2 2 2
14

SN74LVC14APWLE_TSSOP14
7

1
U15E
R274 D19
P

11 10 RB751V_SOD323 2
I O @10K_0402_5% C448 L38
G

1 2 +3VS

2
SN74LVC14APWLE_TSSOP14 0.1U_0402_16V4Z
7

1 CHB1608U301_0603
1 1 1
C449 C450 C451

0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z


2 2 2
14

25

38

34

43

9
U15F U16
P

AVDD1

AVDD2

AVDD4

AVDD3

DVDD1

DVDD2
13 12
I O
G

SN74LVC14APWLE_TSSOP14 MONO_INR 14 35
7

<30,34> CONA# AUX_L LINE_OUT_L LINE_OUTL <26>


2
G

+3VS 1 2 15 36 LINE_OUTR <26>


R471 @100K_0402_5% AUX_R LINE_OUT_R C452 1U_0603_10V6K
3 1 16 37 MDMIC 1 2
<26> HPS JS1 MONO_OUT MD_MIC <27>
S

+3VS 1 2 17 39 L_HP <26> 1 2


Q59 R461 2.2K_0402_5% JS0 HP_LOUT_L
2N7002_SOT23 1 2 23 41 C626 @1000P_0402_50V7K
LINE_IN_L HP_LOUT_R R_HP <26>
R276 2 1 4.7K_0402_5% CDROM_R_L C808 0.1U_0402_16V4Z
<19> CDROM_L
R277 1 2 4.7K_0402_5% 24
3 LINE_IN_R 6 R278 2 1 33_0402_5% 3
BIT_CLK AC97_BITCLK <12,27>
R279 2 1 4.7K_0402_5% CDROM_R_R C453 1 2 1U_0603_10V6K CDROM_RC_L 18
<19> CDROM_R CD_L
R280 1 2 4.7K_0402_5% 8 R281 2 1 10_0402_5%
SDATA_IN AC97_SDIN0 <12>
C454 1 2 1U_0603_10V6K CDROM_RC_R 20
CD_R
2 2 1 CLK_CODEC_14M CLK_CODEC_14M <12>
R283 1 2 2.7K_0402_5% CD_GNA C455 1 2 1U_0603_10V6K CDGNDA 19 XTL_IN R282 0_0402_5%
<19> CD_AGND R284

1
CD_GND
2 1
R285 2 1 2.7K_0402_5% 1 2 21 @1M_0402_5% R286
<26> MIC1 C456 1U_0603_10V6K MIC1 X3
1 2 22 3 2 1 @10_0402_5%
<26> MIC2 MIC2 XTL_OUT
C616 1U_0603_10V6K
1 1

2
13 C457 @24.576MHz_16P_3XG-24576-43E1 1
PHONE @22P_0402_50V8J C458 C460
R287 2 1 @0_0402_5% MD_SPKR 1 2 MD_SPKRC 28 @22P_0402_50V8J
<27> MD_SPK VREFOUT +CODEC_REF
R288 1 2 0_0402_5% C459 0.1U_0402_16V4Z 2 2 @15P_0402_50V8J
27 2
VREF
<12,27> AC97_RST# 11
RESET# AUD_REF
R289 1 2 0_0402_5% 10 29 AFILT1
<12,27> AC97_SYNC SYNC AFILT1 1 1
30 AFILT2
AFILT2 C461
2 2 2 <12,27> AC97_SDOUT 5 31 AFILT3 1 2 270P_0402_50V7K C462 C463
C464 C617 C465 SDATA_OUT AFILT3 AFILT4 1U_0603_10V6K 0.1U_0402_16V4Z
1 2 32
R291 1 2 @1K_0402_5% 45 AFILT4 C466 1 2 270P_0402_50V7K 2 2
L18 0_1206_5% @0.1U_0402_16V4Z R292 @1K_0402_5% ID0
1 2 46
@0.1U_0402_16V4Z 1 1 1 ID1 C467 2 270P_0402_50V7K
12 1
NC
1 2 <26,27> MUTE_LED 1 2 47 42
L39 CHB1608U301_0402 EAPD NC C468 1 2 270P_0402_50V7K
L19 0_1206_5% 1 2 48 26
<34> SPDIFO SPDIFO AVSS1
@0.1U_0402_16V4Z R293 CHB1608U301_0402 40
2 1 4 AVSS2 44
2

DVSS1 AVSS3
7 33 R291 R292 FREQ. SEL
C470 @0.1U_0402_16V4Z R294 R295 DVSS2 AVSS4
4 4
2 1 @4.7K_0402_5% 4.7K_0402_5% AD1981BJST_LQFP48
X X 24.576MHZ Crystal
1

C471 @0.1U_0402_16V4Z

2 1 GNDA Stuff Stuff 14.318MHZ External


C472 @0.1U_0402_16V4Z
Compal Electronics, Inc.
Title
GND GNDA
AC97 CODEC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851
Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Thursday, October 16, 2003 Sheet 25 of 50
A B C D E F G H
A B C D E

JP16
SPKL+ L40 1 2 KC FBM-L11-201209-221LMAT_0805 1
1 +5VAMPP +5VS SPKL- L41 1 2 KC FBM-L11-201209-221LMAT_0805 1 1
2
L20 SPKR+ L42 1 2 KC FBM-L11-201209-221LMAT_0805 3 2
0.1U_0402_16V4Z SPKR- L43 KC FBM-L11-201209-221LMAT_0805 3
1 2 1 2 4
4
1 1 1 1
0_0805_5% C473 C474 C475 C476 ACES_85205-0400
1 1 1
C477 C478 C479
@47P_0402_50V8J @47P_0402_50V8J
10U_0805_10V4Z 0.1U_0402_16V4Z 2 2 2 2
2 2 2 @47P_0402_50V8J @47P_0402_50V8J

10 dB
+5VS

16
15
U17

1
R296 R297

PVDD1
PVDD2
VDD
@100K_0402_5% 100K_0402_5%

2
1 2 7 2
RIN+ GAIN0
C480 0.47U_0603_16V7K 3
GAIN1
1 2 LINE_C_OUTR 17
<25> LINE_OUTR

1
RIN- SPKR+
18
C481 0.47U_0603_16V7K ROUT+ R298 R299

14 SPKR- 100K_0402_5% @100K_0402_5%


1 2 ROUT-
9

2
LIN+
C483 0.47U_0603_16V7K 4 SPKL+
LOUT+
1 2 LINE_C_OUTL 5
2 <25> LINE_OUTL LIN- 2
8 SPKL-
C482 0.47U_0603_16V7K LOUT-

12
NC
10
1 2 19 BYPASS
<30> EC_MUTE# 1
SHUTDOWN C486
R300 0_0402_5%
Gain Settings
GND1
GND2
GND3
GND4
0.47U_0603_16V7K
2
GAIN0 GAIN1 Av(inv)
20
13
11
1

TPA6017A2_TSSOP20
0 0 6 dB

0 1 10 dB

1 0 15.6 dB

1 1 21.6 dB

3 3

AUDIO CONNECTOR

+5VS
JP17
<25> MIC1 1 2
+CODEC_REF 3 4 VOLBTN+# <27,30,34>
<25> MIC2 5 6 VOLBTN-# <27,30,34>
C484 1 2 100U_D2_10VM
<25> R_HP 7 8 WIRELESS_BTN# <30,35>
INTSPK_CR+
+

C485 9 10
<25> L_HP 1 2 100U_D2_10VM INTSPK_CL+ WIRELESS_LED <35>
11 12
<34> DOCK_LOUT_L MUTE_LED <25,27>
+

13 14
<34> DOCK_LOUT_R 15 16 +3VS
1

ACES_88028-1600_16P
R588 R589
1

1K_0402_5% 1K_0402_5% D50


RB751V_SOD323
2

4 HPS <25> 4

Compal Electronics, Inc.


Title

AMP & Audio Jack


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851
Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Thursday, October 16, 2003 Sheet 26 of 50
A B C D E
MDC Conn.
@0.1U_0402_16V4Z +5VMDC 1 2
+3VALW
+3V
+3V
1
C487
1
C488
R303 @0_0805_5%
+5V
RJ11 CONN.
1 1 +3VS
C492 C490

4.7U_0805_10V4Z 0.1U_0402_16V4Z 2 2 FOXCONN_JM34613-L002-TR


2 2 2

2
C803 C802 C493 2 2 @1000P_0402_50V7K
JP19 C491 2 1 R304 JP18
1000P_0402_50V7K 1000P_0402_50V7K 0.1U_0402_16V4Z @1000P_0402_50V7K 3 5
1 1 1 100K_0402_5% 3 5
<25> MD_MIC 1 2 4 6
3 MONO_OUT/PC_BEEP AUDIO_PWDN 4 4 6
MD_SPK <25>

1
GND MONO_PHONE

1
2
5 6
7 AUXA_RIGHT Bluetooth Enable 8 MDC_DET# <29>

1
2
AUXA_LEFT GND
9 10
CD_GND +5V
11 12
CD_RIGHT USB Data+
13 14
CD_LEFT USB Data- R305 2 10K_0402_5% JP36
Stitched capacitor 15 16 1 +3V
17 GND PRIMARY DN 18 TIP 1
+3V 3.3Vaux 5Vd 1
19 20 MRING 2
GND GND 2
21 22 AC97_SYNC <12,25>
23 3.3Vmain AC97_SYNC 24 2 1 MOLEX 53398-0290 2P
+3V <12,25> AC97_SDOUT AC97_SDATA_OUT AC97_SDATA_IN1 AC97_SDIN1 <12>
MD_AC97_RST# 25 26 R307 10_0402_5%
MD_AC97_RST# AC97_RESET# AC97_SDATA_IN0
C807 27 28
GND GND
29 30 AC97_BITCLK <12,25>
U48 AC97_MSTRCLK AC97_BITCLK

2
@0.1U_0402_16V4Z @TC7SH08FU_SSOP5
5 ACES_88021-3000 R309
SLP_S3# 1
<12,30> SLP_S3#
4 MD_AC97_RST# @10_0402_5% 0: Have primary CODEC on mother board
AC97_RST# 2
<12,25> AC97_RST#

1
1 2 AC97_RST# 1
1

C494
3

R600 R599 0_0402_5%


@22P_0402_25V8K
@10K_0402_5% 2 USB CONNECTOR 1 +USB_VCCA
2

W=40mils
1
1 1
C495 + C497 C498
+5V
+USB_VCCA 150U_D2_6.3VM 1000P_0402_50V7K
Front Board CONNECTOR C496
2 1 5
U18
1
2 2 2

IN OUT 0.1U_0402_16V4Z
Pavilion only 1

1
0.1U_0402_16V4Z 4 C499 R312 0_0402_5%
3 ON# R310 1 2
JP21 SET 0.47U_0603_16V7K
2

2
GND 10K_0402_5% 2 L35 JP20
<26,30,34> VOLBTN+# 1
1 R311 AATI4610AIGV-T1_SOT23-5 USBP2-
<30,33> BATLED_0# 2 <12> USBP2-

2
2 4 1 1
<26,30,34> VOLBTN-# 3
4 3 4.7K_0402_1% OVCUR#2 2
4 OVCUR#2 <12> 3
5 <12> USBP2+ USBP2+

1
5 3 2 4
<33> ACT_LED 6 1
6 R314 C500 @JTS0402-02_4P SUYIN_2569A-04G3T
+5VALW 7
7
+3VS 8
9 8 20K_0402_5% 1000P_0402_50V7K 1 2
<25,26> MUTE_LED 9
10 2

2
10 R313 0_0402_5%
11
12 11
<35> PAV_LEDVCC 12
<30,33> PMLED_1# 13
+5VS 14 13
14
USB CONNECTOR 2 +USB_VCCB

ACES_85201-1405 +5V W=40mils


+USB_VCCB
1
C501 U19 1 1
2 1 5 1 C502 + C504 C505
IN OUT
1

1
0.1U_0402_16V4Z 4 C503 150U_D2_6.3VM 1000P_0402_50V7K
3 ON# R315 2 2 2
SET 2 0.47U_0603_16V7K
Front Boand CONNECTOR
2

GND 10K_0402_5% 2 0.1U_0402_16V4Z


R316 AATI4610AIGV-T1_SOT23-5 R320 0_0402_5%

2
1 2
PRESARIO only 4.7K_0402_1% 1 2 OVCUR#1 <12>
R317 0_0402_5% L36 JP22
1

1
1 1 2 USBP1-
OVCUR#0 <12> <12> USBP1- 4 1 1
JP24 R319 C506 R318 0_0402_5%
2
<33> PMLED_1 1 3
20K_0402_5% 1000P_0402_50V7K USBP1+
2 <12> USBP1+ 3 2 4
2
<33> BATLED_0

2
3 @JTS0402-02_4P SUYIN_2569A-04G3T
4
<33> ACT_LED 5
1 2
6
<30,35> PRES_LEDVCC 7 R321 0_0402_5%
+5VS
8 Note: PLACE CLOSE TO EACH USB PORT
ACES_85201-0805 USB CONNECTOR 3 +USB_VCCB
BT CONNECTOR W=40mils
Q60 1
SI2301DS_SOT23 1 1
2 C507 + C508 C509
<30> BLUETOOTH_ON# G
1 +3V_BT 1 2 150U_D2_6.3VM 1000P_0402_50V7K
D 2 2 2
TP CONNECTOR +3VS
1
3
S
C624 1U_0603_10V6K
0.1U_0402_16V4Z
C625 R326 0_0402_5%
+5V
1 2

JP26
USB KEY 1U_0603_10V6K
2
JP23
L37 JP27
JP25 1 USBP0-
8 2 <12> USBP0- 4 1 1
R325 0_0402_5%
7 +5V 1 <12> USBP3+ 3 2
<30> TP_DATA <12> USBP5- 1 2 USB5- <12> USBP3-
6 2 4 3
<30> TP_CLK <12> USBP5+ 1 2 USB5+ <35> BLUETOOTH_LED <12> USBP0+ USBP0+
5 3 R486 1 2 100_0402_5% 5 3 2 4
4 4 <28> MINIPCI_AD22 6
R324 0_0402_5% R487 1 2 100_0402_5% @JTS0402-02_4P SUYIN_2569A-04G3T
3 <28> MINIPCI_PME# 7
ACES_85201-0405
2 8 1 2
1 ACES_85201-0805
ACES_87152-0807 R327 0_0402_5%

Compal Electronics, Inc.


Title

MDC , Bluetooth & USB CONN.


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 17, 2003 Sheet 27 of 50
A B C D E

1 JP28 1
LAN RESERVED LAN RESERVED
TIP 1 2 RING
1 2
KEY KEY
3 4
D55 3 4
5 6
5 6
7 8
WL_ON 1 2 9 7 8 10
<30> WL_ON 9 10
<35> MINI_LED 11 12
MINI_ON 13 11 12 14
RB751V_SOD323 13 14
15 16
R328 1 2 0_0402_5% 17 15 16 W=30mils
<12> PIRQC# 18 +5VS
0.1U_0402_16V4Z 0.1U_0402_16V4Z W=40mils 19 17 18 20 R330 1 2 0_0402_5%
+3VS 19 20 PIRQC# <12>
1 1 1 1 <12> PCI_REQ#4 21 22 PCI_GNT#4 <12>
C618 C510 C511 C512 21 22 W=40mils
23 24 +3VALW
CLK_PCI_MINI 25 23 24 26
<12> CLK_PCI_MINI 25 26 PCIRST# <12,20,21,22>
27 28 W=40mils 0.1U_0402_16V4Z 0.1U_0402_16V4Z
27 28 +3VS
2 2 2 2 29 30
<12> PCI_REQ#3 29 30 PCI_GNT#3 <12> 1 1 1 1
4.7U_0805_10V4Z 1000P_0402_50V7K 31 32 C513 C514 C515 C619
31 32 WLAN_PME#
<12,20,21,22> PCI_AD31 33 34 WLAN_PME# <31>
33 34 MINIPCI_PME#
<12,20,21,22> PCI_AD29 35 36 MINIPCI_PME# <27>
35 36 2 2 2 2
37 38 PCI_AD30 <12,20,21,22>
39 37 38 40 1000P_0402_50V7K 4.7U_0805_10V4Z
<12,20,21,22> PCI_AD27 39 40
<12,20,21,22> PCI_AD25 41 42 PCI_AD28 <12,20,21,22>
MINIPCI_AD22 41 42
<27> MINIPCI_AD22 43 44 PCI_AD26 <12,20,21,22>
43 44
<12,20,21,22> PCI_CBE#3 45 46 PCI_AD24 <12,20,21,22>
47 45 46 48 1 2 PCI_AD18
<12,20,21,22> PCI_AD23 47 48
49 50 R333 100_0402_5% IDSEL : AD18
49 50 PCI_AD22
<12,20,21,22> PCI_AD21 51 52
51 52 PCI_AD22 <12,20,21,22>
CLK_PCI_MINI 53 54
<12,20,21,22> PCI_AD19 53 54 PCI_AD20 <12,20,21,22>
55 56 PCI_PAR <12,20,21,22>
1

55 56 PCI_AD18
<12,20,21,22> PCI_AD17 57 58 PCI_AD18 <12,20,21,22>
R334 59 57 58 60
2 <12,20,21,22> PCI_CBE#2 59 60 PCI_AD16 <12,20,21,22> 2
<12,20,21,22> PCI_IRDY# 61 62
@10_0402_5% 61 62
63 64 PCI_FRAME# <12,20,21,22>
63 64
1 2 65 66 PCI_TRDY# <12,20,21,22>
2

R575 10K_0402_5% 65 66
1 <12,20,21,22> PCI_SERR# 67 68 PCI_STOP# <12,20,21,22>
C516 69 67 68 70
69 70
<12,20,21,22> PCI_PERR# 71 72 PCI_DEVSEL# <12,20,21,22>
@15P_0402_50V8J 71 72 +5VS
<12,20,21,22> PCI_CBE#1 73 74
2 73 74
<12,20,21,22> PCI_AD14 75 76 PCI_AD15 <12,20,21,22>
75 76 1000P_0402_50V7K
77 78 PCI_AD13 <12,20,21,22>
79 77 78 80
<12,20,21,22> PCI_AD12 79 80 PCI_AD11 <12,20,21,22> 1 1 1
81 82 C517 C518 C519
<12,20,21,22> PCI_AD10 81 82
83 84 PCI_AD9 <12,20,21,22>
83 84 4.7U_0805_10V4Z
<12,20,21,22> PCI_AD8 85 86 PCI_CBE#0 <12,20,21,22>
85 86 2 2 2
<12,20,21,22> PCI_AD7 87 88
89 87 88 90 0.1U_0402_16V4Z
89 90 PCI_AD6 <12,20,21,22>
<12,20,21,22> PCI_AD5
91 92 PCI_AD4 <12,20,21,22>
93 91 92 94
93 94 PCI_AD2 <12,20,21,22>
<12,20,21,22> PCI_AD3 95 96 PCI_AD0 <12,20,21,22>
W=30mils 95 96
+5VS 97 98
99 97 98 100
<12,20,21,22> PCI_AD1 99 100
101 102
101 102
103 104
103 104 R336
105 106
105 106
107 108 1 2
109 107 108 110
109 110 @10K_0402_5%
111 112
113 111 112 114 +3VALW
115 113 114 116
115 116 1000P_0402_50V7K
117 118
119 117 118 120
119 120 1 1 1
121 122 C522 C523 C524
W=30mils 121 122 W=40mils
+5VS 123 124 +3VALW
3 123 124 4.7U_0805_10V4Z 3
AMP_1318644-1 2 2 2
0.1U_0402_16V4Z

4 4

Compal Electronics, Inc.


Title
Mini PCI Slot
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 28 of 50
A B C D E
5 4 3 2 1

+3VS
R465
HWMVCC 1 2

1 1 0_0805_5%
C525 C526

10U_1206_10V4Z 0.1U_0402_16V4Z
2 2
+3VS +3VS
D D

HWMVCC

1
R337

105
4.7K_0402_5%

22
45
75
5
U20

2
28 2 INDEX#

VCC
VCC
VCC
VCC
VCCA
<12,30> PCIRST_LPC# LRESET# INDEX# INDEX# <32>
CLK_PCI_SIO 19 3
<12> CLK_PCI_SIO PCICLK MTRA# MTR0# <32>
<12,22,30> SIRQ SIRQ 21 4
+3VS LDRQ#0 20 SERIRQ DRVB# 6
C527 <12> LDRQ#0 LDRQ# DRVA# DRV0# <32>
LFRAME# 27 7
<12,30> LFRAME# LFRAME# MTRB#
1 2 8 FDDIR# <32>
LAD0 26 LPC FDD DIR# 9
<12,30> LAD0 LAD0 STEP# STEP# <32>
LAD1 25 10
<12,30> LAD1 LAD1 WDATA# WDATA# <32>
10U_0805_10V4Z LAD2 24 11
<12,30> LAD2 LAD2 WGATE# WGATE# <32>
<12,30> LAD3 LAD3 23 12 TRACK0# TRACK0# <32>
LAD3 TRK0# 13 WP#
WPT# WP# <32>
128 14 RDATA#
+3VS JAB1/GP10 RDATA# RDATA# <32>

GAME PORT
127 15 HDSEL# <32>
126 JBB11/GP11 HDSEL# 16 DSKCHG#
JACX/GP12 DSKCHG# DSKCHG# <32>
0.1U_0402_16V4Z 0.1U_0402_16V4Z 125 1
JBCX/GP13 DSEL0# 3MODE# <32>
1 1 1 1 124 120
C528 C529 C530 C531 123 JBCY/GP14 OVOLT/MSO/DSEL1
JACY/GP15
122
JBB2/GP16 LPD0
121 42 LPD0 <32>
2 2 2 2 JAB2/GP17 INDEX#PD0 LPD1
41 LPD1 <32>
0.1U_0402_16V4Z 0.1U_0402_16V4Z TRK00#/PD1 40 LPD2
WRTPRT#/PD2 LPD2 <32>
R338 39 LPD3
RDATA#/PD3 LPD3 <32>
1 2 106 38 LPD4 LPD4 <32>
@10K_0402_5% VREF DSKCHG#/PD4 37 LPD5
C PD5 LPD5 <32> C

HARDWARE MONITOR
103 36 LPD6
UIC1 PD6 LPD6 <32>
104 35 LPD7 LPD7 <32>

PARALLEL PART
107 UIC2 PD7
UIC3 LPTSLCT
108 29 LPTSLCT <32>
109 UIC4 WGATE#/SLCT 30 LPTPE
UIC5 WDATA#/PE LPTPE <32>
31 LPTBUSY LPTBUSY <32>
110 MTR1#/BUSY 32 LPTACK#
DTDN DS1#/ACK# LPTACK# <32>
111 33 LPTERR#
DTDP HDSEL#/ERR# LPTERR# <32>
34 LPTSLCTIN# LPTSLCTIN# <32>
113 STEP#/SLCTIN# 43 LPTINIT#
+3VS FANIO2/GP21 DIR#/PINIT# LPTINIT# <32>
114 44 LPTAFD#
FANIO1/DTEST DRVDEN0/AUTOFD# LPTAFD# <32>
+3VS 115 46 LPTSTB#
FANOUT2/GP20 STB# LPTSTB# <32>
RP78 116
8 1 DCD2# 1 2 117 FANOUT1 64
OVTEMP# IRRX IRRX <33>
7 2 DSR2# R339 4.7K_0402_5% 118 65
BEEP IRTX IRTXOUT <33>
6 3 CTS2# IR 100
GP24/IRRX1 IRMODE <33>
5 4 RI2#

@10K_1206_8P4R_5% 94 53 DCD1#
<27> MDC_DET# XD0/GP30 DCD1# DCD1# <34>
+3VS 1 2 FIR_DET# 93 48 DSR1#
DSR1# <34>

SERIAL POART 1
XD1/GP31 DSR1# SIN1#
92 51 SIN1# <34>
RP79 R592 10K_0402_5% XD2/GP32 SIN1 RTS1#
91 49 RTS1# <34>

1
8 1 DCD1# 89 XD3/GP33 RTS1# 52 SOUT1
XD4/GP34 SOUT1 SOUT1 <34>

1
7 2 DSR1# 88 47 CTS1# R484
XD5/GP35 CTS1# CTS1# <34>
6 3 CTS1# R593 87 50 DTR1#
XD6/GP36 DTR1# DTR1# <34>
5 4 RI1# 86 54 RI1# 10K_0402_5%
XD7/GP37 RI1# RI1# <34>
FIR@10K_0402_5% 85

2
10K_1206_8P4R_5% XA0/GP40 DCD2#
84 62
2

XA1/GP41 GP71/SMBDT/DCD2# SOUT2


83 61

SERIAL POART 2
82 XA2/GP42 GP72/SMBCK/SOUT2 59 SIN2
XA3/GP43 GP73/VID0/SIN2 DTR2#
81 58
XA4/GP44 GP74/VID1/DTR2#

1
80 57
B 79 XA5/GP45 GP75/VID2/RTS2# 56 DSR2# R485 B
XA6/GP46 GP76/VID3/DSR2# CTS2#
78 55
77 XA7/GP47 GP77/VID4/CTS2# 63 RI2# @10K_0402_5%
XA8/GP50 GP70/SCLK/ITMOFF/RI2#
76

2
74 XA9/GP51 102
73 XA10/GP52 GP22/ITMOFF//OVOLT/PLED 101
+3VS +3VS +3VS XA11/GP53 GP23/ATEST/OVFAN/COPEN
72 119
71 XA12/GP54 OVFAN/MSI/WDTO
XA13/GP55 CLK_48M
70 17 CLK_48M <22>
CLK_PCI_SIO CLK_48M XA14/GP56 CLKIN
69 98
68 XA15/GP57 SMI# 97
XA16/GP60 GP25/MEMW#
1

67 96
GNDD
GNDD
GNDD
GNDD
GNDA
XA17/GP61 GP26/MEMR#
2

R340 R341 66 95
R342 R343 R344 XA18/GP62 GP27/ROMCS#
@10_0402_5% @10_0402_5% VT1211_LQFP128
18
60
90
99
@10K_0402_5% @10K_0402_5% @10K_0402_5% 112
2

2
1

1 1
RTS1# DTR1# SOUT1 C532 C533

@10P_0402_50V8J @10P_0402_50V8J
2

2 2
R345 R346 R347

10K_0402_5% 10K_0402_5% 10K_0402_5%


1

Base address 1:2Eh/2Fh 0:Normal Opreation 0: Enable ROM I/F as GPIO


A Base address 0:4Eh/4Fh 1:Test Mode 1:Enable Flash Rom A

W
R348 +3VS
SOUT2 1 2
Super I/O strapping for VT1211
For Winbond 48M strapping
@4.7K_0402_5%

Title
Compal Electronics, Inc.
LPC SUPER I/O VIA VT1211
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 29 of 50
5 4 3 2 1
A B C D E

I/O Address
1 2 BADDR1-0 Index Data
+3VALW R594 551@10K_0402_5% 0 0 2E 2F
+3VALW 1 2 1 2 +RTCVCC 0 1 4E 4F
0.1U_0402_16V4Z R349 ENE@0_0603_5% +EC_AVCC
+3VALW
R595 591@0_0603_5%
* 1 0 (HCFGBAH, HCFGBAL) (HCFGBAH, HCFGBAL)+1
1 1 1 1 +3VS 1 2 2 1 1 Reserved
C534 C535 C536 C537 R350 591@0_0603_5%
C538
1 1

123
136
157
166

161
4.7U_0805_10V4Z 0.01U_0402_16V7K C539 C540

16

34
45

95
1U_0603_10V6K ENV0 ENV1 TRIS
2 2 2 2 U21 1
0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z IRE 0 0 0

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6

AVCC
VDD

VBAT
2 2
L22
+3VALW 1 2 +EC_AVCC BATT_TEMP <46> * OBD 0 1 0
MURATA BLM11A20PT_0603 2 1
C543 7 81 1 2 ECAGND DEV 1 0
C542 <12,22,29> SIRQ SERIRQ AD0
1 8 82 BID C541 0.01U_0402_16V7K 1
0.1U_0402_16V4Z 0
1000P_0402_50V7K 9 LDRQ# AD1 83
L23 <12,29> LFRAME# LFRAME# AD2 BATT_OVP <39> PROG 1 1 0
1 21 ECAGND 2
<12,29> LAD0 15 84 ADP_IR 1 2 ADP_I <39>
MURATA BLM11A20PT_0603 LAD0 Host interface AD3 PRES_DETECT R351 10K_0402_5%
<12,29> LAD1 14 87 1
LAD1 IOPE0AD4
<12,29> LAD2 13 88
LAD2 IOPE1/AD5 C544
<12,29> LAD3 10 89 WIRELESS_BTN# <26,35> SHBM=1: Enable shared memory with host BIOS
R352 CLK_PCI_LPC 18 LAD3 AD Input IOPE2/AD6 90 VOLBTN-# 0.22U_0603_10V7K
<12> CLK_PCI_LPC LCLK IOPE3/AD7 VOLBTN-# <26,27,34> TRIS=1: While in IRE and OBD, float all the
1 2 EC_RST# 19 93 2
+3VALW RESET1# DP/AD8 signals for clip-on ISE use
22 94
10K_0402_5% SMI# DN/AD9
2 1 23
J1 JOPEN PWUREQ#
99 DAC_BRIG <17>
DA0 100
DA1 EN_FAN1 <4> +3VALW
EC_SCI# 1 2 31 DA output 101
<12> EC_SCI# IOPD3/ECSCI# DA2 IREF <39>
R353 0_0402_5% 102
DA3 EN_FAN2 <4>

<11> GATEA20 GATEA20 5 32 INVT_PWM <17>


KBRST# 6 GA20/IOPB5 IOPA0/PWM0 33 KBA1 1 2
<12> KBRST# KBRST/IOPB6 IOPA1/PWM1
36
BEEP# <25>
1 2 EC_SCI#
(ENV1) R354 591@10K_0402_5%
KSI[0..7] PWM IOPA2/PWM2 R368 @0_0402_5%
<33,35> KSI[0..7] 37 ACOFF <39>
KSO[0..15] KSI0 or PORTA IOPA3/PWM3 KBA2
<33> KSO[0..15] 71 38 PM_BATLOW# <12> 1
(BADDR0)R355 2
KSI1 KBSIN0 IOPA4/PWM4 @10K_0402_5%
72 39 EC_ON <33>
KSI2 73 KBSIN1 IOPA5/PWM5 40
KBSIN2 IOPA6/PWM6 LID_OUT# <12>
KSI3 74 43 TP_OFF_LED# KBA3 1 2
CLK_PCI_LPC KSI4 KBSIN3 IOPA7/PWM7 TP_OFF_LED# <35> (BADDR1)R356 591@10K_0402_5%
77
KSI5 KBSIN4 KSO16
78 153 KSO16 <35>
1

KSI6 79 KBSIN5 IOPB0/URXD 154 KSO17 KBA5 1 2


R358 KSI7 80 KBSIN6 Key matrix scan IOPB1/UTXD 162 PMLED_1#
KSO17 (SHBM) R357 591@10K_0402_5%
KBSIN7 IOPB2/USCLK PMLED_1# <27,33>
163 EC_SMC_1 EEPROM/BATTERY
IOPB3/SCL1 EC_SMC_1 <31,46>
@10_0402_5% KSO0 49 PORTB 164 EC_SMD_1
KBSOUT0 IOPB4/SDA1 EC_SMD_1 <31,46>
KSO1 50 165 LRST# 1 2PCIRST_LPC# PCIRST_LPC# <12,29>
2

KBSOUT1 IOPB7/RING/PFAIL/RESET2 R359 0_0402_5% +3VALW


1 KSO2 51
C545 KSO3 52 KBSOUT2 168
2 KBSOUT3 IOPC0 PBTN_OUT# <12> 2
KSO4 53 169 EC_SMC_2
EC_SMC_2 <4>

1
@15P_0402_50V8J KSO5 KBSOUT4 IOPC1/SCL2 EC_SMD_2
56 170 EC_SMD_2 <4> THERMAL/DOCKING
2 KSO6 KBSOUT5 IOPC2/SDA2 FAN_SPEED1 R361
57 171 FAN_SPEED1 <4>
KSO7 KBSOUT6 PORTC IOPC3/TA1
58 172 PME_EC# <31> +3VS
KSO8 59 KBSOUT7 IOPC4/TB1/EXWINT22 175 @1K_0402_5%
KBSOUT8 IOPC5/TA2 EC_THRM# <12>
KSO9 60 176 FAN_SPEED2 <4>

2
KSO10 KBSOUT9 IOPC6/TB2/EXWINT23 BID
61 1 WL_ON <28>

1
RP80 KSO11 KBSOUT10 IOPC7/CLKOUT
64

1
10 1 KBD_DATA KSO12 KBSOUT11 ACIN R472
+5V 65 26 ACIN <12,38,40>
9 2 KBD_CLK KSO13 66 KBSOUT12 IOPD0/RI1/EXWINT20 29 R364
KBSOUT13 IOPD1/RI2/EXWINT21 30 JACK_DET# <34>
8 3 TP_DATA KSO14 67 PORTD-1 1K_0402_5%
KBSOUT14 IOPD2/EXWINT24/RESET2 SLP_S3# <12,27>
PS2_DATA 7 4 TP_CLK KSO15 68 1K_0402_5%

2
PS2_CLK 6 5 KBSOUT15
+5V 2 ON/OFF# <33> BLUETOOTH_ON# <27>

2
EC_TINIT# IOPE4/SWIN 44
105 SLP_S5# <12>

1
10K_1206_10P8R_5% EC_TCK 106 TINT# PORTE IOPE5/EXWINT40 24 D
TCK IOPE6/LPCPD/EXWIN45 25 M_SEN# <18>
SD307100207 EC_TDO 107 WL_ON 2
TDO IOPE7/CLKRUN/EXWINT46 CONA# <25,34>
EC_TDI 108 JTAG debug port G
EC_TMS TDI KBA0
109 124 S

3
RP81 +3VALW TMS IOPH0/A0/ENV0 KBA1 Q61
125
FSEL# 1 8 KBD_CLK 110 IOPH1/A1/ENV1 126 KBA2 2N7002_SOT23
SELIO# KBD_DATA PSCLK1/IOPF0 IOPH2/A2/BADDR0 KBA3
2 7 111 127
FRD# PS2_CLK PSDAT1/IOPF1 IOPH3/A3/BADDR1 KBA4
3 6 114 128
EC_SMI# 4 5 PS2_DATA PSCLK2/IOPF2 PORTH IOPH4/A4/TRIS KBA5 +3VS
115 131
TP_CLK PSDAT2/IOPF3 PS2 interface IOPH5/A5/SHBM KBA6
<27> TP_CLK 116 132
10K_1206_8P4R_5% TP_DATA 117 PSCLK3/IOPF4 IOPH6/A6 133 KBA7
<27> TP_DATA PSDAT3/IOPF5 IOPH7/A7
SD3021002T2 LID_SW# 118
<33> LID_SW#

2
+5VALW PWR_ACTIVE_PAV# 119 PSCLK4/IOPF6 138 ADB0
<35> PWR_ACTIVE_PAV# PSDAT4/IOPF7 IOPI0/D0
RP82 139 ADB1 ADB[0..7]
IOPI1/D1 ADB[0..7] <31>
EC_SMD_2 1 8 140 ADB2 R370 R371
EC_SMC_2 2 7 IOPI2/D2 141 ADB3 KBA[0..19] 10K_0402_5% 10K_0402_5%
IOPI3/D3 KBA[0..19] <31>
EC_SMD_1 3 6 CRY1 158 PORTI 144 ADB4

1
EC_SMC_1 32KX1/32KCLKIN IOPI4/D4 ADB5 VOLBTN+#
4 5 145
3 R365 1 2 591@20M_0603_5% CRY2 160 IOPI5/D5 146 ADB6 3
10K_1206_8P4R_5% Y5 32KX2 IOPI6/D6 ADB7 VOLBTN-#
147
2 1 2 R366 1 IOPI7/D7
120K_0402_5% 150 FRD#
1 1 IOPJ0/RD FRD# <31>
C546 C547 PORTJ-1 151 FWR#
IOPJ1/WR0 FWR# <31>
10P_0402_50V8K 10P_0402_50V8K 152 SELIO#
+3VALW SELIO# SELIO# <31>
2 2
<12> EC_SMI# EC_SMI# 62 41 VOLBTN+#
IOPJ2/BST0 IOPD4 VOLBTN+# <26,27,34>
1 2 LID_SW# 32.768KHz_12.5P_CM155 63 42
<26> EC_MUTE# IOPJ3/BST1 IOPD5 NUMLED# <35>
R367 20K_0402_5% 69 PORTD-2 54
<22,23> G_RST# IOPJ4/BST2 IOPD6 CAPSLED# <35>
70 PORTJ-2 55 LRST#
+3VS <12> EC_SWI# IOPJ5/PFS IOPD7 PWR_ACTIVE_PRES# <35>
75
<27,33> BATLED_0#
76
IOPJ6/PLI
143 KBA8 EC DEBUG port
<12> SLP_S1#

1
2 1 M_SEN# IOPJ7/BRKL_RSTO IOPK0/A8 142 KBA9
R369 10K_0402_5% IOPK1/A9 R363 JP29
<37,41,42,44> SYSON 148 135 KBA10
IOPM0/D8 PORTK IOPK2/A10 KBA11
<31,37> SUSP# 149 134 1 +5VALW
155 IOPM1/D9 IOPK3/A11 130 KBA12 ENE@10K_0402_5% 1 2 EC_TINIT#
IOPM2/D10 PORTM IOPK4/A12 KBA13 2 EC_TCK
<35> PWR_BACK# 156 129 3

2
+3VALW
3 IOPM3/D11 IOPK5/A13_BE0 121 KBA14 3 4 EC_TDO
<12> EC_RSMRST# IOPM4/D12 IOPK6/A14_BE1 4
ENE@10K_0402_5% 4 120 KBA15 5 EC_TDI
<22> PCM_SUSP# IOPM5/D13 IOPK7/A15_CBRD 5
@10K_0402_5% @10K_0402_5% 27 6 EC_TMS
<14,17> ENABLT IOPM6/D14 6
28 113 KBA16 7
<17> BKOFF# IOPM7/D15 IOPL0/A16 7
112 KBA17 8 KSO16
FSEL# PORTL IOPL1/A17 KBA18 8 KSO17
<31> FSEL# 173 104 9
R444 R446 R448 R450 R452 SEL0# IOPL2/A18 KBA19 9 PMLED_1#
174 103 10
SEL1# IOPL3/A19 10
47 48 FSTCHG <39>
@10K_0402_5% ENE@10K_0402_5% CLK IOPL4/WR1#
@96212-1011S
AGND
GND1
GND2
GND3
GND4
GND5
GND6
GND7

NC10

GPIO5
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9

R584
GPIO6 PRES_DETECT 1 2 PRES_LEDVCC <27,35>
EC_TINIT# 6.2K_0402_5%

2
4 KBA0 SUSP# PC87591L-VPCN01 A2_LQFP176 4
17
35
46
122
159
167
137

96

11
12
20
21
85
86
91
92
97
98

KBA4 R585
10K_0402_5%
1

R445 R447 R449 R451 R453 R579

1
2 1
ENE@10K_0402_5% @10K_0402_5% 10K_0402_5% C627 551@1U_0603_10V6K
ECAGND GPIO6
Compal Electronics, Inc.
2

GPIO5
ENE@10K_0402_5% ENE@10K_0402_5% Title
@10K_0402_5%
KBD EC CTRL-NS PC87591L
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 30 of 50
A B C D E
<30> ADB[0..7] ADB[0..7]
INPUT OUTPUT
KBA[0..19] +5VALW
<30> KBA[0..19]

1 2
C548 @0.1U_0402_16V4Z

20
U22
ADB0 3 2

VCC
ADB1 D0 Q0
4 5
ADB2 7 D1 Q1 6
+3VALW ADB3 D2 Q2
8 9
ADB4 D3 Q3
13 12
ADB5 D4 Q4
14 15
D5 Q5

14
ADB6 17 16
U23A ADB7 18 D6 Q6 19
KBA2 D7 Q7
1

P
A
3 11

GND
SELIO# 2 O LARST# 1 CP
<30> SELIO#

G
B MR
SN74LVC32APWLE_TSSOP14 @SN74HCT273PW_TSSOP20

10
R372 C549
+3VALW 1 2 1 2
@20K_0402_5% @1U_0603_10V6K

14
U23D
12

P
A
11
O
13

G
B
SN74LVC32APWLE_TSSOP14

7
U24
+3VALW +3VALW
KBA18 1 32
A18 VDD +3VALW
KBA16 2 31 FWE#

1
KBA15 A16 WE# KBA17
3 30 2 SUSP# <30,37>
KBA12 A15 A17 KBA14 C550 R373 R374
4 29
KBA7 A12 A14 KBA13
5 28
KBA6 6 A7 A13 27 KBA8 0.1U_0402_16V4Z +3VALW 100K_0402_5% 4.7K_0402_5%
KBA5 A6 A8 KBA9 1
7 26

2
KBA4 A5 A9 KBA11
8 25

2
KBA3 A4 A11 FRD#

14

G
9 24 <22> PCM_PME# 1 2 PME_EC# <30>
KBA2 A3 OE# KBA10 R375 0_0402_5%
10 23
KBA1 11 A2 A10 22 FSEL# 9 1 3 1 2

P
A1 CE# A EC_FLASH# <12> <20> LAN_PME#
KBA0 12 21 ADB7 FWE# 8 R377 0_0402_5%

S
ADB0 A0 DQ7 ADB6 O Q28 2N7002 1N_SOT23
13 20 10 <28> WLAN_PME# 1 2

G
ADB1 14 DQ0 DQ6 19 ADB5 U23C B R381 0_0402_5%
ADB2 DQ1 DQ5 ADB4 SN74LVC32APWLE_TSSOP14
15 18

7
DQ2 DQ4 FWR# <30>
16 17 ADB3
VSS DQ3

512K8-90_PLCC32

+3VALW +3VALW

1
+3VALW 1
U25 C551 R382

KBA0 21 31 0.1U_0402_16V4Z 100K_0402_5%


A0 VCC0 2 U26
KBA1 20 30 1

2
KBA2 19 A1 VCC1 C552 8 1
KBA3 18 A2 7 VCC A0 2
KBA4 17 A3 25 ADB0 0.1U_0402_16V4Z JP30 6 WC A1 3
A4 D0 2 <30,46> EC_SMC_1 SCL A2
KBA5 16 26 ADB1 KBA16 KBA17 5 4
<30,46> EC_SMD_1

1
KBA6 A5 D1 ADB2 KBA15 1 2 SDA GND
15 27

1
KBA7 14 A6 D2 28 ADB3 KBA14 3 4 AT24C164-10SC_SO8 R383
KBA8 8 A7 D3 32 ADB4 KBA13 5 6 KBA19 R384
KBA9 7 A8 D4 33 ADB5 KBA12 7 8 KBA10 100K_0402_5%
KBA10 A9 D5 ADB6 KBA11 9 10 ADB7 100K_0402_5%
36 34

2
KBA11 6 A10 D6 35 ADB7 KBA9 11 12 ADB6

2
KBA12 A11 D7 KBA8 13 14 ADB5
5
KBA13 4 A12 FWE# 15 16 ADB4
KBA14 3 A13 10 RESET# 1 2 RESET# 17 18
A14 RP# +3VALW 19 20 +3VALW
KBA15 2 11 R385 100K_0402_5%
KBA16 1 A15 NC 12 21 22
KBA17 A16 READY/BUSY# KBA18 23 24 ADB3
40 29
KBA18 13 A17 NC0 38 KBA7 25 26 ADB2
KBA19 37 A18 NC1 KBA6 27 28 ADB1
A19 KBA5 29 30 ADB0
FSEL# KBA4 31 32 FRD#
<30> FSEL# 22
FRD# CE# KBA3 33 34
<30> FRD# 24 23
FWE# 9 OE# GND0 39 KBA2 35 36 FSEL#
WE# GND1 KBA1 37 38 KBA0
39 40
@SST39VF080-70_TSOP40 @SUYIN-80065A-040G2T

Compal Electronics, Inc.


Title

BIOS & EC I/O Port


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 31 of 50
5 4 3 2 1

+5V_PRN
Parallel Port FDD CONN.
+5V_PRN +5VS

1 D30 EMI Requirement


C554 +5VS 2 1w=10mils JP31
D D
1
1

1
1U_0603_10V6K 1SS355_SOD323 INDEX# 2
2 <29> INDEX# 2
R386 3 CP11
DRV0# 4 3 INDEX# 1 8
<29> DRV0# 4
4.7K_0402_5% 5 DRV0# 2 7
C555 DSKCHG# 6 5 DSKCHG# 3 6

2
<29> DSKCHG# 6
LPTSTB# R387 1 2 33_0402_5% PWRPRN 1 2 7 MTR0# 4 5
<29> LPTSTB# 7
8

w=10mils
220P_0402_50V7K 9 8 180P_1206_8P4C_50V8
MTR0# 9
<29> MTR0# 10 CP12
1 10 FDDIR#
11 1 8
LPTAFD# R388 1 2 33_0402_5% AFD/3M# 14 FDDIR# 12 11 3MODE# 2 7
<29> LPTAFD# <29> FDDIR# 12
FD0 2 3MODE# 13 STEP# 3 6
<29> 3MODE# 13
LPTERR# 15 STEP# 14 WDATA# 4 5
<29> LPTERR# <29> STEP# 14
FD1 3 15
LPTINIT# R389 1 15
<29> LPTINIT#
2 33_0402_5% PRNINIT# 16 <29> WDATA#
WDATA# 16 180P_1206_8P4C_50V8
FD2 16
4 17 CP13
LPTSLCTIN# R390 1 2 33_0402_5% SLCTIN# 17 WGATE# 18 17 WGATE# 1 8
<29> LPTSLCTIN# <29> WGATE# 18
FD3 5 19 TRACK0# 2 7
18 TRACK0# 20 19 WP# 3 6
<29> TRACK0# 20
FD4 6 21 RDATA# 4 5
19 WP# 22 21
<29> WP# 22
FD5 7 23 180P_1206_8P4C_50V8
20 RDATA# 24 23 C801
C <29> RDATA# 24 C
LPD[0..7] FD6 8 25 HDSEL# 1 2
<29> LPD[0..7] 25
21 HDSEL# 26
<29> HDSEL# 26
FD7 9 180P_0402_50V8J~D
22 ACES_85201-2605
LPTACK# 10
<29> LPTACK#
23
LPTBUSY 11
<29> LPTBUSY
24
LPTPE 12 +5VS
<29> LPTPE
25 +5VS
LPTSLCT 13 RP83
<29> LPTSLCT
1 1 DSKCHG# 1 8
JP32 C629 C557 INDEX# 2 7
SUYIN_070536FR025S204AU WP# 3 6
4.7U_0805_10V4Z 0.1U_0402_16V4Z TRACK0# 4 5
2 2
1K_1206_8P4R_5%
RDATA# 1 2
+5V_PRN
RP84 CP1 R478 1K_0402_5%
FD0 1 10 SLCTIN# 1 8
FD1 2 9 FD4 PRNINIT# 2 7
FD2 3 8 FD5 LPTERR# 3 6
B FD3 4 7 FD6 AFD/3M# 4 5 RP85 B
5 6 FD7 WDATA# 6 5 +5VS
+5V_PRN 220P_1206_8P4C_50V8K WGATE# STEP#
7 4
4.7K_1206_10P8R_5% CP2 HDSEL# 8 3 MTR0#
LPTSLCT 1 8 FDDIR# 9 2 DRV0#
+5V_PRN LPTPE 2 7 10 1
+5VS
RP86 LPTBUSY 3 6
AFD/3M# 1 10 LPTACK# 4 5 @1K_1206_10P8R_5%
LPTERR# 2 9 LPTACK#
PRNINIT# 3 8 LPTBUSY 220P_1206_8P4C_50V8K
SLCTIN# 4 7 LPTPE CP3
5 6 LPTSLCT FD3 1 8
+5V_PRN FD2 2 7
4.7K_1206_10P8R_5% FD1 3 6
FD0 4 5
RP87
LPD3 1 16 FD3 220P_1206_8P4C_50V8K
LPD2 2 15 FD2 CP4
LPD1 3 14 FD1 FD7 1 8
LPD0 4 13 FD0 FD6 2 7
LPD7 5 12 FD7 FD5 3 6
LPD6 6 11 FD6 FD4 4 5
LPD5 7 10 FD5
LPD4 8 9 FD4 220P_1206_8P4C_50V8K
A A
33_1206_16P8R_5%

Title
Parallel port & FDD Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B LA-1851 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 32 of 50
5 4 3 2 1
5 4 3 2 1

Power BTN
SW1
2 1
INT_KBD CONN. R391 100K_0402_5%
1 2 +3VALW 4 3
KSI[0..7] CP5
KSI[0..7] <30,35>
KSO8 1 8 3 ON/OFF# ON/OFF# <30> TC010-PS11CET_5P

5
KSO[0..15] KSO7 2 7
KSO[0..15] <30>
KSO4 3 6 ON/OFFBTN# 1
KSO2 4 5
D JP33 2 SW2 D
EC_PWR_ON# <38>
KSI1 100P_1206_8P4C_50V8 2 ON/OFFBTN# 2 1
KSI7 24 CP6 +3VALW
KSI6 23 KSI0 D31
1 8 3 4 3
KSO9 22 KSO1 2 7 DAN202U_SC70

1
KSI4 21 KSO5 D32 @PSOT03C TC010-PS11CET_5P
3 6

5
KSI5 20 KSI3 4 5 R392
19 1
KSO0 C558 D33
KSI2 18 100P_1206_8P4C_50V8 4.7K_0402_5%
KSI3 17 RLZ20A_LL34

2
KSO5 16 CP7 EC_ON 1 2 2 22K 2
<30> EC_ON

2
KSO1 15 KSO9 1 8 R393 0_0402_5%
14 22K
KSI0 KSI6 2 7
KSO2 13 KSI7 Q29
3 6
KSO4 12 KSI1 4 5 DTC124EK_SOT23 1000P_0402_50V7K

3
KSO7 11
KSO8 10 100P_1206_8P4C_50V8
KSO6 9 CP8 WHEN R=0,Vbe=1.35V
KSO3 8 KSI2 WHEN R=33K,Vbe=0.8V
1 8
KSO12 7 KSO0 2 7
FIR Module +3VS +5VS

1
KSO13 6 KSI5
D
3 6
KSO14 5 KSI4 4 5 2
KSO11 4 Q63 G +3VS

1
KSO10 3 100P_1206_8P4C_50V8 @2N7002_SOT23 S 1 1

3
KSO15 2 C561 R394 R395 C562
1 CP9
ACES_85201-2405 KSO13 1 8 1 4.7U_0805_10V4Z 0_1206_5% @5.6_1206_5% @4.7U_0805_10V4Z

1
KSO12 2 7 C559 2 2

2
KSO3 3 6 R586
KSO6 4 5 0.1U_0402_16V4Z
2 10_1206_5%
100P_1206_8P4C_50V8 SW8 T = 40mil

2
C CP10 2 1 U27 C
LID_SW# <30>
KSO15 1 8 T = 20mil 1 +5VS_FIR
KSO10 2 IRED_A IRTXOUT
7 1 2 3 T = 12mil IRTXOUT <29>
KSO11 3 C563 IRED_C TXD IRMODE
6 4 5 T = 12mil IRMODE <29>
KSO14 4 5 6 RXD SD/MODE 7
4 3 0.1U_0402_16V4Z VCC MODE IRRX
8 T = 12mil IRRX <29>

3
100P_1206_8P4C_50V8 2 GND
ESE11MV9_4P
TFDU6102-TR3_8P

D34 @PSOT03C

Touch Pad & Status LED Conn.

+3VALW

+3VALW

<27,30> PMLED_1#
2

B B
<27,30> BATLED_0#

3
Q30
B

PDTA114EK_SC59 Q31

E
PDTA114EK_SC59
C

C
1

1
R396 R397
1 2 PMLED_1 <27> 1 2 BATLED_0 <27>
137_0402_1% 137_0402_1%

+5VS

<19> ACT_LED#
2

Q32
B

PDTA114EK_SC59
C
1

R398
A 1 2 A
ACT_LED <27>
220_0402_5%

Compal Electronics, Inc.


Title
KBD,ON/OFF,T/P,LED & FIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 33 of 50
5 4 3 2 1
A B C D E

+3VALW

1
R399

10K_0402_5%
1 1 2 JACK_DET# 1
+3VS

2
R566 @1K_0402_5%

<25,30> CONA#

1
C
B

E
JP35
Q33

3
33 34 DOCK_PRESENT MMBT3904_SOT23
1 2 DOCK_LOUT_L
+USB_VCCA DOCK_LOUT_L <26>

1
1 2 3 4 DOCK_LOUT_R
+5VS 5 6 DOCK_LOUT_R <26>
R560 1K_0402_5% DOCK_PRESENT R400
7 8 JACK_DET#
<14,18> TV_COMPS 9 10 JACK_DET# <30>
R567 200_0402_5% 470_0402_5%
<14,18> TV_LUMA 11 12 SPDIFO <25>
<14,18> TV_CRMA 1 2 VOLBTN+# <26,27,30>

2
13 14 SIN1#
15 16 SIN1# <29>
<12> USBP4- SOUT1 SOUT1 <29> 1
17 18 DCD1# C778
<12> USBP4+ 19 20 DCD1# <29>
DTR1#
<20> RJ45_GND 21 22 DTR1# <29>
RI1# 1000P_0402_50V7K
<20> RJ45_RXX- 23 24 RI1# <29> 2
<20> RJ45_RXX+ DSR1# DSR1# <29>
25 26 RTS1#
<20> RJ45_TXX- 27 28 RTS1# <29>
R568 200_0402_5%

BOSS1
BOSS2
CTS1#
<20> RJ45_TXX+ 29 30 CTS1# <29>
<26,27,30> VOLBTN-# 1 2
31 32
+DOCKVIN 35 36 +DOCKVIN
1
C779 FOX_QL11183-C6HQ

37
38
2 1000P_0402_50V7K 2
2 EMI Requirement

CP14
SIN1# 1 8
SOUT1 2 7
DCD1# 3 6
DTR1# 4 5

180P_1206_8P4C_50V8
CP15
RI1# 1 8
DSR1# 2 7
RTS1# 3 6
CTS1# 4 5

180P_1206_8P4C_50V8

+USB_VCCA
SPDIFO

1 1 1 1
C565 C564 C566 C634

0.1U_0402_16V4Z 22U_1206_10V4Z 1000P_0402_50V7K 470P_0402_50V7K


2 2 2 2

3 3

L24
VIN 1 2 +DOCKVIN
KC FBM-L18-453215-900LMA90T_1812
1 1
C567 C568

1000P_0402_50V7K 1000P_0402_50V7K
2 2

4 4

Compal Electronics, Inc.


Title
SPR Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 34 of 50
A B C D E
5 4 3 2 1

SW3
KSO16 2 1 KSI0
<30> KSO16 KSI0 <30,33>
4 3
FOR POWER BUTTON
TC010-PS11CET_5P +5V +5V
BACKLIGHT ( PAV )

2
SW4
2 1 KSI1 D35 D39
KSI1 <30,33>
D D
4 3
HSMB-C172 BLUE_0805 17-21UYOC/S530-A2/TR8_ORG
TC010-PS11CET_5P

1
SW5 PWR_ACTIVE_PAV# PWR_ACTIVE_PRES#
<30> PWR_ACTIVE_PAV# <30> PWR_ACTIVE_PRES#
2 1 KSI2
KSI2 <30,33>

3
4 3

E
5 TC010-PS11CET_5P
Q34 Q69
PDTA114EK_SC59 PDTA114EK_SC59

C
SW6
2 1 KSI3

1 1

1 1
KSI3 <30,33>
4 3
R401 R405
TC010-PS11CET_5P
5

220_0402_5% 220_0402_5%

2
SW7
2 1 WIRELESS_BTN# @0.1U_0402_16V4Z @0.1U_0402_16V4Z
WIRELESS_BTN# <26,30>
C C
4 3 2 2 2 2 2
1

C569 C570 C571 C572 C573


TC010-PS11CET_5P R466
5

10K_0402_5% 1 1 1 1 1 1 2 PAV_LEDVCC
@0.1U_0402_16V4Z @0.1U_0402_16V4Z @0.1U_0402_16V4Z
2

+3VS D36 HSMB-C172 BLUE_0805

1 2 PAV_LEDVCC
D40 17-21UYOC/S530-A2/TR8_ORG
1 2 PRES_LEDVCC D37 HSMB-C172 BLUE_0805
D42
FOR CARDREADER INDICATOR R407 2 PRES_LEDVCC
<30> PWR_BACK#
PWR_BACK# 1 2 PAV_LEDVCC
1 2 1 1 2 PAV_LEDVCC
( PAV /PRES ) <30> NUMLED#

3
3 D38 HSMB-C172 BLUE_0805

3
220_0402_5% D41 HSMB-C172 BLUE_0805

E
1

12-21UYOC/S530-A2/TR8_YEL

E
C

Q37 Q35
MMBT3904_SOT23 1 2 PAV_LEDVCC Q36 PDTA114EK_SC59
FOR 3 PROGRAMING

C
PDTA114EK_SC59

C
D43 HSMB-C172 BLUE_0805
BUTTON BACKLIGHT

1
B

R404

1
B R569 R406 (PAV) 1 2 B
2

CARD_LED 1 2 1 2
<22> CARD_LED
220_0402_5%
FOR POWER BUTTON
1

1K_0402_5% 220_0402_5%
R570
BACKLIGHT ( PRES D44 17-21UYOC/S530-A2/TR8_ORG
10K_0402_5% 1 2 PRES_LEDVCC
R410 )
2

2 1 PAV_LEDVCC 1 2 PAV_LEDVCC

220_0402_5% D45 17-21UYOC/S530-A2/TR8_ORG D46 HSMB-C172 BLUE_0805


2

1 2PRES_LEDVCC 1 2
FOR WIRLESS LED D47
PRES_LEDVCC <27,30> <30> TP_OFF_LED#

3
D58 HSMB-C172 BLUE_0805
( PAV ) HSMB-C172 BLUE_0805 1 2PAV_LEDVCC

E
<30> CAPSLED# PAV_LEDVCC <27>
D56
2

3
<27> BLUETOOTH_LED
2 1 D48 HSMB-C172 BLUE_0805
1 1

Q38
B

1N4148_SOT23 E PDTA114EK_SC59

C
D57
C

2 1 Q39

1
<28> MINI_LED
PDTA114EK_SC59 R408
C

1N4148_SOT23 Q62 1 2
MMBT3904_SOT23
1
B

A R409 220_0402_5% A
R475 1 2
2

WIRELESS_LED 1 2
<26> WIRELESS_LED
220_0402_5%
1

1K_0402_5%
R473 Title
LED & Fan Circuit
10K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
2

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B LA-1851 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 35 of 50
5 4 3 2 1
A B C D E F G H I J

+3VALW
1 1

2
R411
10K_0402_5%

1
+5VALW +3VALW
CPU_VLD# <11>

1
2

C
R412 R413
8.2K_0402_5% 15K_0402_5% Q41 DELAY 1 ms
MMBT3904_SOT23
2 2

E
PWRGD_SB <12> <44> VGATE 1 2

3
R414 1K_0402_5%
2

1
D C574
2

C
G 0.22U_0603_10V7K
Q42 S Q43 1

3
MMBT3904_SOT23 2N7002_SOT23

E
+1.6VALW 1 2

3
R415 6.8K_0402_5%
2
C575 +3VALW
3 3
0.47U_0603_16V7K

2
1
R416
10K_0402_5%

1
MEM_VLD# <11>

1
C
Q44
MMBT3904_SOT23 DELAY 1 ms
4 4

E
+2.5V 1 2

3
R417 10K_0402_5%
2
C576

0.47U_0603_16V7K
1

5 5
+3VALW

2
R418
+3VS 10K_0402_5%
C579
1 2

1
0.1U_0402_16V4Z
HT1_VLD# <11>
1

U29

1
5 6 PM_PWROK
VCC

MR# RST# PM_PWROK <12>

C
6 +5VS
1 2 3 6
2

R423 240K_0402_5% PFI Q45


4 R476 MMBT3904_SOT23
GND

DELAY 1 ms
1

PFO#
1 1

E
R425 C581 C582 100K_0402_5%
MAX6342RUT-T_SOT23-6 +1.2V_HT 1 2
2

3
100K_0402_5% 0.1U_0402_16V4Z R421 5.6K_0402_5%
2 2
2
2

C580

0.01U_0402_16V7K 0.47U_0603_16V7K
1

Delay 100 ms
7 7

8
Title
Compal Electronics, Inc. 8
Power OK/Reset Conn.& MUTE Switch
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Thursday, October 16, 2003 Sheet 36 of 50

A B C D E F G H I J
A B C D E F G H I J

+12VALW
+12VALW +12VALW
+5VALW to +5V Transfer

1
R426
1 100K_0402_5% R427 R428 1
+2.5V to +2.5VS Transfer
2 +5VALW +2.5V +2.5VS 10K_0402_5% 47K_0402_5%
0.01U_0402_16V7K +5V

2
U30 U40 SUSP SYSON#
<43> SUSP

1
8 1 0.1U_0402_16V4Z 8 1 0.1U_0402_16V4Z
1
1

1
D R429 C583 D1 S1 D1 S1 D D
7 2 7 2

1
SYSON# 2 6 D2 S2 3 6 D2 S2 3 2 2
D3 S3 1 1 D3 S3 1 1 <30,31> SUSP# <30,41,42,44> SYSON
G 1M_0402_5% 5 4 C584 C585 R430 5 4 C737 C738 R552 G Q47 G Q48
S 2 D4 G D4 G S 2N7002_SOT23 S 2N7002_SOT23
3

3
Q46 SI4800 1N_SO8 22U_1206_10V4Z 470_0402_5% SI4800 1N_SO8 22U_1206_10V4Z 470_0402_5%
2 2 1 2 2
2N7002_SOT23 SUSON C739

1 2

2
D @10U_1206_6.3V6M

1
2 D
2 SYSON# RUNON
RUNON <41>
+1.25V +2.5V
G 2 SUSP
2 +5VALW +5VALW S Q49 G 2

1
2N7002_SOT23 S Q64

3
1 2N7002_SOT23 R431 R553
1
C587 + C586 470_0402_5% 470_0402_5%

1 2

1 2
4.7U_0805_10V4Z @33U_D2_16VM
2 2 D D
2 SYSON# 2 SYSON#
Q51 G Q65 G
2N7002_SOT23 S 2N7002_SOT23 S

3
3 +3VALW to +3V Transfer 3
+3VALW
+3VALW +3V

2
U31
8 1 0.1U_0402_16V4Z D52
7 D1 S1 2 +RTCVCC @RB751V_SOD323
1

D2 S2
6 3 1 1 D49
D3 S3 C593 C594 R436
5 4
+ -

1
D4 G W=20mils 3 BATT1.1 BATT1
1
1 SI4800 1N_SO8 22U_1206_10V4Z 470_0402_5%
+ C595 C596 2 2 1 1 2
2

2
J2 C603 W=20mils
@33U_D2_10VM 10U_1206_10V4Z 2
1

2 2 D JOPEN 0.1U_0402_16V4Z
4 4

1
2 SYSON# BAS40-04_SOT23 ML1220T13RE
SUSON G
SUSON
S Q54
3

CHGRTC
2N7002_SOT23 W=15mils

For customer request


,they don't wanna
charge RTC
+5VALW to +5VS Transfer
+12VALW
+1.6VALW to +1.6VS Transfer
5 +1.6VALW +1.6VS FM1 FM2 FM3 FM4 FM5 FM6
5
1

+5VALW +5VS 1 1 1 1 1 1
R438 U32
100K_0402_5% U33 8 1 0.1U_0402_16V4Z
8 1 22U_1206_10V4Z 7 D1 S1 2

1
7 D1 S1 2 6 D2 S2 3 CF1 CF2 CF3 CF4 CF5 CF6 CF7 CF8 CF9
1 1
2

0.01U_0402_16V7K 6 D2 S2 3 5 D3 S3 4 C597 C598 R437


1

D3 S3 D4 G
5 4 1 1
1

D4 G C600 C601 R439 SI4800 1N_SO8 22U_1206_10V4Z 470_0402_5%


1 1

1
1

D R440 C602 SI4800 1N_SO8 C599 2 2

2
SUSP 2 0.1U_0402_16V4Z 470_0402_5%
G 1M_0402_5% RUNON 2 2 10U_1206_10V4Z CF10 CF11 CF12 CF13 CF14 CF15 CF16
2

1
Q56 S 2 2 D
3

2N7002_SOT23 RUNON 2 SUSP


G
1

1
D Q55
6 S 6

3
2 SUSP 2N7002_SOT23
+5VALW +5VALW G H1 H2 H3 H4 H5 H6 H7 H8 H9 H10
S Q57 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
3

1 1 2N7002_SOT23
C604
+ C605

1
4.7U_0805_10V4Z
2 @100U_D_16VM
2

H31 H11 H12 H13 H14 H16 H17 H18 H19


HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

1
7 7
+3VALW +3VS
+3VALW to +3VS Transfer
U34
8 1 0.1U_0402_16V4Z H21 H22 H23 H24 H25 H26 H27 H28 H29 H30
7 D1 S1 2 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1

D2 S2
6 3 1 1
5 D3 S3 4 C606 C607 R442
D4 G
1

1
1 SI4800 1N_SO8 22U_1206_10V4Z 82_0402_5%
+ C608 C609 2 2
2

100U_D2_10VM 10U_1206_10V4Z
1

2 2 D
RUNON 2 SUSP
G
8 S Q58 Compal Electronics, Inc. 8
3

2N7002_SOT23 Title

DC/DC Circuit
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Thursday, October 16, 2003 Sheet 37 of 50

A B C D E F G H I J
A B C D E

PD45
SBM1040-13_POWERMITE3
Detector
PL1 2
FBM-L18-453215-900LMA90T_1812 1
PCN1 PC1 3
ADPIN 100P_0402_50V8J 1 2
VIN detector
1 VIN
2 17.945 17.343 16.757

1
2 1
3 3 17.372 16.782 16.207

1
4

1000P_0402_50V7K
PD1 PD46

100P_0402_50V8J
1

1
FOX_JPD1021-W03-TR EC10QS04_SOD106 PC2 SBM1040-13_POWERMITE3

PC4
1000P_0402_50V7K PR1

PC3
2

2
1 1
1M_0402_1%

2
1 2
ADPGND
VIN VS VIN

0.01U_0402_50V7K

10K_0805_1%
1

1
PR4

1
82.5K_0603_0.1%
10K_0402_5%

PC5

PR3
PR2
1 2 ACIN <12,30,40>

2
PR5

2
PR6 22K_0402_1%
200_1206_5% 1 2 3 3.2V

P
VS + PACIN
1 2 1 PACIN <39>
O
2

G
-

0.047U_0603_16V7K
PU1A

1
19.6K_0603_0.1%
PR9

PC6

4
0.1U_0402_16V4Z
PD2 200_1206_5% LM393M_SO8 PR8

PR7

PC7
2 1 1 2 10K_0402_5%
VIN

2
PZD1

2
1N4148_SOD80 RLZ4.3B_LL34

2
2 1 RTCVREF
PR10
10K_0402_5%

PD3
2
2 1 2
VMB
1N4148_SOD80 1 PR11
2
1.5K_1206_5%

PQ1
TP0610T_SOT23
VS1 PR12
1 2
3 1.5K_1206_5%
S
CHGRTCP 2 1 1
PZD2 D PD4
RLZ4.3B_LL34 2 2 1 1 PR13
2 B+
100K_0402_5%

VIN
1

G
0.22U_1206_25V7K

1.5K_1206_5%
1

1N4148_SOD80
PC8
PR14

PC9
0.1U_0603_50V4Z
2

1 PR15
2
2

1.5K_1206_5%

<33> EC_PWR_ON# 1 2

1
PR16 PR17
22K_0402_5% PR18 PR19 432K_0402_1%
10K_0402_5% 1M_0402_1%
1 2 2 1

2
VL

5V PD5
PU1B
LM393M_SO8

8
CHGRTCP 2
1

RTCVREF <40,46> MAINPWON


3.3V 5

P
PR20 1 7 +
CHGRTC PU2 200_0805_5% O
3 6 3

1
S-81233SGUP-T1_SOT89 -
<39> ACON 3

1
PR21
PR23
2

1
PR24

0.1U_0402_16V4Z
499K_0402_1%

1000P_0402_50V7K
1
1 2 1 2 3 2 PR22 PC10

PC11
RB715F_SOT323

2
1

3 2 499K_0402_1% 1000P_0402_50V7K

PC12

2
1

200_0805_5% 200_0805_5%
1

2
1

2
PC14 PZD3
1

4.7U_0805_10V4Z RLZ16B_LL34
2

PC13 ACIN
1U_0805_25V4Z
2 1 PQ2 PR26
Precharge detector VL
2N7002_SOT23 47K_0402_5%

1
PR25 D
16.421 15.817 15.229 5V 10K_0402_5% 2 2 1 PACIN

2
14.108 13.657 13.002 S
G
PJP10 PJP11

3
3MM 3MM PR27

1
1 2 1 2 @66.5K_0603_1%

O
PJP1 PJP3 PJP9
PQ3
3MM 3MM 3MM DTC115EUA_SC70
1 2 1 2 +1.6VALWP 1 2 +1.6VALW

G
+3VALWP +3VALW +5VALWP +5VALW

I
3

2
+5VALWP
PJP4 PJP2
PJP12 3MM 3MM
3MM +1.5VSP +1.2VSP
4
1 2 +1.5VS
1 2 +1.2VS 4
1 2

PJP7 PJP6
3MM 3MM
1 2 +1.25VP 1 2
+2.5VP +2.5V +1.25V

Compal Electronics, Inc.


PJP5 PJP8 Title
2MM 3MM
+12VALW THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Detector
+12VALWP 1 2 +1.35VSP 1 2 +1.35VS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-1851 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 38 of 50
A B C D E
A B C D E

Charger

1 1
PQ4

1 8
Iadp=0~6.0A 2
S D
7
B++ S D
3 6
S D
P2 P3 B+
4 5
G D
PL2
PR28 FBM-L18-453215-900LMA90T_1812 AO4407_SO8
PQ5 PQ6

2200P_0402_50V7K
0.01_2512_1%(1W) PQ7

0.1U_0805_25V7K
10U_1210_25V6K_V1

@10U_1210_25V6K_V1
VIN 8 1 1 8 2 1 1 2 1 8
7 D S 2 2 S D 7 2 S D 7

2
D S S D S D
6 3 3 6 3 6
D S S D S D

0.01U_0402_50V7K
5 4 4 5

PC15

PC16

PC17

PC18

PC19
4 5
1

D G G D G D

1
AO4407_SO8 PR29 @AO4407_SO8
1

AO4407_SO8
200K_0402_5%
PR30
20K_0402_5% 1 2
2

VIN

3
2
1
PR31
PQ8 47K_0402_5%
2

2
SI4835DY_SO8
PR32 4 PR33
0_0402_5% 10K_0402_5%
PU3
1 24

1
-INC2 +INC2 ACOFF#
<30> ADP_I

1
2 1 2 23

5
6
7
8
PR34 OUTC2 GND PC20

O
1

PD6 47K_0402_1% 2200P_0402_50V7K


1SS355_SOD323 PR35 1.8V 3
+INE2 CS
22 CS 1 2 PQ9
2 150K_0402_5% DTC115EUA_SC70 2
ACOFF# 1 2

31.6K_0603_1%
1

G
4 21 1 2

I
2

-INE2 VCC(o)
0.1U_0402_16V7K

PR36 PC21
10K_0402_1%
1

2
PR38 0.1U_0603_50V4Z
PR39 ACOFF <30>
1 2 1 2 5 20
PC22

PR37
1

3K_0402_5% D 1K_0402_1% FB2 OUT PC24


2

1 2 2 PQ10 PC23 0.1U_0402_25V4K


<38> PACIN
2

G 2N7002_SOT23 4700P_0402_25V7K_A34 6 19 1 2 LXCHRG


S VREF VH CC=0(0.5A) ~ 3A
3

0.1U_0402_16V7K

PC27
ACON 5.0V 2 0.1U_0603_50V4Z CV=16.8V (12 CELLS)
PC25

1 2 1 2 7 18 1
<38> ACON PR40 FB1 VCC PL3 PR42
2

PC26 1K_0402_1% 15U_SPC-1204P-150_4A_20% 0.02_2512_1% BATT+


1500P_0402_50V7K 8 17 1 2 1 2 1 2 BATT+
-INE1 RT PR41
66.5K_0402_1%
1 2 9 16
+INE1 -INE3

4.7U_1210_25V6K

4.7U_1210_25V6K

4.7U_1210_25V6K
PR43

1
<30> IREF 162K_0402_1% PR44 PR45 PC28

PC29

PC30

PC31
1

PD7 PD8
2 1 10 15 1 2 1 2
90.9K_0603_1%

10K_0402_1% OUTC1 FB3 SKS30-04AT_TSMA @SKS30-04AT_TSMA

2
PC32 47K_0402_1% 1500P_0402_50V7K
PR46

IREF=1.113*Icharge 0.01U_0402_50V7K 11 14 ACON


2

2
OUTD CTL
IREF=0.373~3.3V
2

1
1 2
12 13 PR47
-INC1 +INC1 PC33 @10K_0402_5%

MB3887_SSOP24 @10P_0402_50V8K

2
3 3

2 1 4.2V 2 1
OVP voltage : LI-MH 8 CELL(4S2P) BATT+
PR48 PR49
49.9K_0603_0.1% 150K_0603_0.1%
BATT+ : 18.0V--> BATT_OVP : 2.0V
(BATT_OVP voltage = 0.1109*BATT+) 1 2 CS
1

PC34 +3VALWP
PR50 22P_0402_50V8J

1
604K_0402_1%

1
VS PR51

O
47K_0402_5%
2

PQ11
DTC115EUA_SC70
0.1U_0603_50V4Z

2
1

G
I
PR52
PC35

3
1M_0402_1%
2

1
O
2
8

PQ12
3 DTC115EUA_SC70
P

4 1 + 4

G
0
0.01U_0402_50V7K

<30> BATT_OVP 2 <30> FSTCHG

I
1

3
2.2K_0402_5%
1

1
@0.1U_0402_16V7K

PR53

PC36
4

PU4A
PC37

LM358A_SO8
2

PR54
Compal Electronics, Inc.
2

200K_0402_1%
Title

Charger
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-1851 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Thursday, October 16, 2003 Sheet 39 of 50
A B C D E
A B C D E

+3.3V/+5V/+12V
PC38
B++
4.7U_1206_25VFZ
1 2

1
PD9
EC11FS2_SOD106

1 2
1 PC39 1
2
470P_0805_100V7K

1
PL4 PR55
0_0402_5%

FBM-L18-453215-900LMA90T_1812

2
1

SNB 2 1 FLYBACK

2
PR56
22_1206_5%
PD10
PC40 DAP202U_SOT323 PC41
0.1U_0603_50V4Z 0.1U_0603_50V4Z
B+++ 1 2 BST31 BST51 1 2

3
2

3
B+++ PT1
9U_SDT-1204P-9R0-120_4.5A_20%
2200P_0402_50V7K

PR57
4.7U_1210_25V6K

@10U_1210_25V6K_V1

PQ13 0_0402_5% VL

2200P_0402_50V7K
8
7
6
5
1 8 1 2 +12VALWP
1

1
D2 G2 7

10U_1210_25V6K_V1
@10U_1210_25V6K_V1
2 VS

D
D
D
D

1
D2 D1/S2/K
3 6
PC42

PC43

PC44

G1 D1/S2/K PQ37
4 5

PC46

PC47

PC48
2

S1/A D1/S2/K

4.7U_0805_10V4Z
AO4404_SO8

2
1

G
S
S
S
AO4906_SO8 PR59

1
0_0402_5%

1
2
3
4
PD11

PC45
DL3 1SS355_SOD323

2.7K_1206_5%
1
2

PR60
+3.3V Ipeak = 6.66A ~ 10A

8
7
6
5
2 LX3 2

1
0.1U_0603_50V4Z

D
D
D
D
2

4.7U_1210_25V6K
PR58 PR61 PC50

DH3

PC49
1

PQ15 0_0402_5% 0_0402_5% PQ38 47P_0402_50V8J

PC51
2

2
PC52 2N7002_SOT23 D AO4406_SO8
PD26

G
S
S
S
47P_0402_50V8J ACIN 2
2

2
G SKS30-04AT_TSMA

1
2
3
4
S

3
1 2

1
PR62
1.27K_0402_1% PR63

22

21
1

2M_0402_5%
1M_0402_1%
2

PL5 25 4

V+

VL
10U_SPC-1204P-100_4.5A_20% PR155 BST3 12OUT
5

2
1.24K_0402_1% 27 VDD 18 BST5
PR64

DH3 BST5 DH5


16
PC53
26 PU5 DH5 17 LX5
2

0.47U_0805_16V7K LX3 MAX1902_SSOP28 LX5 DL5 PR66


+3VALWP 24 19
DL3 DL5
1 2 2 1 20 1.54K_0402_1%
PR65 PGND 14 2 1
0_0402_5% CSH5
PR153 619_0402_1% 1 13

1
CSH3 CSL5
1 2 2 12 1 2

1
CSL3 FB5 PR67
3 15 PC54 PR156
FB3 SEQ 0_0402_5%
1 1 <12,30,38> ACIN 1 2 10 9 2.5VREF
150U_D_4VM

2
@150U_D_4VM

3.57K_0402_1%

23 SKIP# REF 6 0.47U_0805_16V7K 698_0402_1%


1

2
+ + PR68 SHDN# SYNC
11
PC55

PC56

PR69

PR154

2
1
PC57 10K_0402_5% 7 RST# 1 2 PD13
TIME/ON5 PC58 SKS10-04AT_TSMA
+5VALWP
2

2 2 100P_0402_50V8K PR70 4.7U_0805_10V4Z 0_0402_5%


GND
28
2

2
@300K_0402_5% RUN/ON3
2

1
10.2K_0402_1%
1 1
1

120U_D_6.3VM

@120U_D_6.3VM
PD12
8

1
3 SKS10-04AT_TSMA PC59 1 2 1 2 PC62 + + 3

PR71

PC60

PC61
VS VL
680P_0402_50V7K
2

PR72 PR73 100P_0402_50V8K

2
@0_0402_5% 0_0402_5% 2 2

2
1
2

PR74
10K_0402_1%

47K_0402_1%
PR75

2
1

1
PR76
1

MAINPWON <38,46> 10K_0402_1%


PC63
@0.047U_0402_16V4Z
2

2
PR77
47K_0402_5% +5V Ipeak = 6.66A ~ 10A
1 2 VL
1

PC64
1U_0805_25V4Z
2

4 4

Compal Electronics, Inc.


Title

3.3V / 5V / 12V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-1851 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Thursday, October 16, 2003 Sheet 40 of 50
A B C D E
5 4 3 2 1

D D

PC66 PL6
@10U_1210_25V6K_V1
1845B+ FBM-L18-453215-900LMA90T_1812
1 2 B++

2
PC65 PC67 PR78
2200P_0402_50V7K 4.7U_1210_25V6K 0_0402_5% +5VALWP

1
4.7U_1210_25V6K PC68

2200P_0402_50V7K

10U_1210_25V6K_V1
@10U_1210_25V6K_V1
PD14 PC69 4.7U_0805_10V4Z

2
1
DAP202U_SOT323

PC72
PC70

PC71
2

5
6
7
8

2
PQ17

2
1 8 BST2.5B

D
D
D
D
D2 G2
2 7
3 D2 D1/S2/K 6 BST1.5B 1U_0805_25V4Z PQ18
4 G1 D1/S2/K 5 0.1U_0603_50V4Z PC74 AO4404_SO8

G
S1/A D1/S2/K

S
S
S
1 2 PC73 PR80
AO4906_SO8 20_0402_5% 2.5HG

4
3
2
1
PR79 BST1.5A 1845-1_VCC1 2
PC75 0_0402_5%
+1.5VSP

1
0.1U_0603_50V4Z PR81 PC76 PL8
C PL7 0_0402_5% 0.1U_0603_50V4Z 4.7U_SPC-1204P4R7_5.7A_20% +2.5VP C
2 1 LX1.5 2 1 1 2 2 1 LX2.5 1 2

2
5U_TPRH6D38-5R0M-N_2.9A_20%

22
1 PR83

SKS10-04AT_TSMA
1

5
6
7
8

1
4.7U_0805_6.3V6K
1 2 BST2.5A 0_0402_5% 1 1

220U_D2_4VM
SKS10-04AT_TSMA

220U_B2_2.5VM

@150U_D_4VM
4.7U_0805_6.3V6K

+ 25 21 1 2
PC77

V+

UVP
VCC

D
D
D
D

1
PR82 BST1 VDD PQ19 + +
PD15

PC78

PC81

PC79

PC80

PD16
0_0402_5% DH1.5 AO4406_SO8 PD32
26 19
2

2 DH1 BST2 DH2.5 SKS30-04AT_TSMA


18
2

2
S
S
S
27 DH2 17 2 2

2
DL1.5 LX1 LX2 DL2.5
24 20

4
3
2
1
DL1 PU6 DL2 PR164
16
MAX1845EEI_QSOP28 CS2 @0_0402_5%
28
CS1
1 15

2
OUT1 OUT2 14
FB2
2 12 1 2
FB1 ON2 PR165 +2.5V

1
7 0_0402_5%
1845-1_VCC

1
PGOOD PR204
5
11 TON 2 1 @0_0402_5% PC181
131.759V
ON1 @2200P_0402_25V7K_A34

2
ILIM2
SYSON <30,37,42,44>

SKIP
3

GND
OVP

REF

2
ILIM1 PR85
1.047V 0_0402_5%

1
PR86

23

10

1
13.7K_0402_1% PR206 PR205
2 1 0_0402_5% @0_0402_5% PC182
PR197 PR84 @2200P_0402_25V7K_A34

2
680K_0402_5% 0_0402_5% 2 1

2
<37> RUNON 1 2 2 1 PR158

1
1 2 PR87

100K_0402_1%
1
57.6K_0402_1%

PR89
0_0402_5%
B B
1

PC82 PR88

2
PC180 0.22U_0603_16V7K 100K_0402_1%

2
PR198 @0.1U_0402_16V4Z
2

316K_0402_1%
2

A A

COMPAL ELECTRONICS, INC


Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DDR POWER 2.5VP & +1.5VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B LA-1851
Date: Thursday, October 16, 2003 Sheet 41 of 50
5 4 3 2 1
5 4 3 2 1

+5VALWP

1
D PR168 SI3445DV_TSOP6 D
0_0603_5% PQ39 PL16
PQ41 5U_TPRH6D38-5R0M-N_2.9A_20%

D
6 SN1.4V 1 2

S
HMBT2222A_SOT23
+1.6VALWP
2

IN1.4V 4 5

1
2 PD40 1 1
1

1
4.7U_0805_10V4Z 1 SKS30-04AT_TSMA

1
PD39 PC159 + +

G
C
PC156 RB751V_SOD323 PR171
2

3
1
191K_0402_1% 470P_0402_50V7K PC162
2 PC161

2
2 @220U_B2_2.5VM
220U_B2_2.5VM

2
VL
1

NODE1

E
PR170
1 2 10K_0402_5%

2
PR169
1

1
1K_0402_5%
PC157 PC158
2200P_0402_50V7K 0.1U_0402_16V4Z
2

2
NODE2

8
3 FB1.4V

P
COMP1.4V 1 +
3

O 2 REF1.4V 1 2
C - 2.5VREF C

G
E

LM393M_SO8

1
PR173

4
PQ40 PU13A

1
107K_0402_1%
PR172
2SA1036K_SOT23 200K_0402_1%
PU13B PC160

2
8
C

4700P_0402_25V7K_A34
LM393M_SO8

2
P 5
1

+
7
O
6
-
G
4

+2.5VP

1
PR166
PU7 @0_0402_5%
<30,37,41,44> SYSON

2
7 5 1 PR167 2
STANDBY VDD
0_0402_5%
+2.5V

1
B +2.5VP 4 6 B
VD ExtRefIn

1
22U_1206_10V4Z PC83

1
PC85 PC86 8 2 0.1U_0402_16V4Z PC84

2
22U_1206_10V4Z RefOut VttSense 10U_0805_10V4Z

2
1
1 3

2
VSS VTT

1
PC87
(1.25V) 0.1U_0402_16V7K PC88

2
NE57814_HSO8 0.1U_0402_16V4Z

2
+1.25VP
1

220U_B2_2.5VM

1
PC89
+
PC90
0.1U_0402_16V7K

2
2

A A

COMPAL ELECTRONICS, INC


Title
+1.6VALWP & +1.25VP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B LA-1581 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

Date: Thursday, October 16, 2003 Sheet 42 of 50


5 4 3 2 1
5 4 3 2 1

+5VALWP

2
PR91
D 0_1206_5% D

PD17

1
1.2VIN 1SS355_SOD323

1
PC92

5
PU8 22U_1206_10V4Z

2
IN

1 1
10 BST1.2
1 BST 0.1U_0402_25V4K
HSD PC94
1

2
PC149 8 DH1.2 PQ20
10U_1206_6.3V7K DH PL9
1 8
+1.2VSP
2

2 D2 G2 7 2.2UH_PLFC1235P-2R2A_6A_30%
D2 D1/S2/K
3 6 1 2

1
LX1.2 G1 D1/S2/K
9 4 5

1
LX S1/A D1/S2/K 4.87K_0603_1%
1 1
AO4906_SO8 PR92
COMP1.2 2 + +
COMP PR90
6 DL1.2 PC95 PC96

2
1

DL 68_0805_5% 220U_D_2VM
220U_D_2VM

1 2
PR93 2 2

1
332K_0402_1% 33P_0402_50V8J
1

PC150
PC97 7 PR94
PGND 220P_0603_50V8J 9.09K_0603_1%
2

2
1

PC98

2
470P_0402_50V7K 4 3 FB1.2
2

GND FB
C C

MAX1954EUB_10UMAX

PR174
1

D
0_0402_5%
1 2 2
<37> SUSP G PQ16
1

S 2N7002_SOT23
3

PC163
0.1U_0402_10V6K
2

+5VALWP

1
PR159
@0_1206_5%

2
1.35VIN

1
PD34 PC152

5
PU12 @1SS355_SOD323 @22U_1206_10V4Z

2
IN

1 1
B 10 BST1.35 PC151 B
BST
1 @0.1U_0402_25V4K
HSD

2
PC91 8 DH1.35 PQ36
@10U_1206_6.3V7K DH 1 8 PL15

2
2
D2
D2
G2 7
D1/S2/K 6
@2.2UH_PLFC1235P-2R2A_6A_30% +1.35VSP
3 1 2
LX1.35 G1 D1/S2/K 5
9 4

1
LX S1/A D1/S2/K
@AO4906_SO8 PR161 PR162 1 1
COMP1.35 2 @2.7_0603_5% @7.32K_0402_1%
COMP 6 DL1.35 + +
1

DL PC154 PC155

1 2

2
PR175 PR160 @220U_B2_2.5VM
@220U_B2_2.5VM
1

@0_0402_5% D @220K_0402_1% PC99 2 2

1
1 2 2 7 PC153
<37> SUSP G PQ42 @10P_0402_50V8K PGND @1200P_0603_50V7K
PR163
1

1 2

2
S @2N7002_SOT23
@10.5K_0402_1%
3

PC164
PC93
@0.1U_0402_10V6K 4 3 FB1.35
2

@560P_0402_50V7K

2
GND FB
2

@MAX1954EUB_10UMAX

A A

<>

COMPAL ELECTRONICS, INC


Title
1.25V / VGA_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1851
Date: Thursday, October 16, 2003 Sheet 43 of 50
5 4 3 2 1
5 4 3 2 1

CPUB+

PD33
PR196 PR157
RLZ10C_LL34
0_0402_5% 8.06K_0402_1% PR95
<30,37,41,42> SYSON 1 2 2 1 1 2 1 2 PQ21 PQ48
1 2 B+
10K_0402_1% PL10
1 1

2200P_0402_50V7K
5

10U_1210_25V6K_V1

10U_1210_25V6K_V1

10U_1210_25V6K_V1
PR96 +5VALWP SI7392DP_SO8 @SI7392DP_SO8 FBM-L18-453215-900LMA90T_1812

@47U_25V_M

@47U_25V_M
1

1
D +3VS 10_0402_5% + + D

PC103

PC104

PC105

PC106

PC100

PC101
2 1 1 2 PR201

2
PC102 @180K_0402_1%

2
1

1
D 2.2U_0805_10V4Z 2 2

1937_VDD
1937_VCC
PR97 2 PQ14 PC107 4 4
<45> 1937_FB

2
10K_0402_5% G 2N7002_SOT23 2.2U_0805_10V4Z
S PR98

3
0_0402_5% 2
1 PL11
2

PD18
PU9 PR199 0.56UH_ETQP4LR56WFC_21A_20%
<36> VGATE

3
2
1

3
2
1
30.1K_0402_1% SKS30-04AT_TSMA
28 26 1937_DH1 2 1
1

VCC DH1

1
PC108 8 25 1937_LX1 PC109

8
7
6
5

8
7
6
5
@0.1U_0402_16V7K VDD LX1 0.22U_0603_16V7K PQ25
PR133 PR195
2

1
1937_BST1 PR99 2N7002_SOT23 D
15 27 68_0805_5%

D
D
D
D

D
D
D
D
1.05K_0603_1%

2
PWRGD BST1

IRF7832_SO8

IRF7832_SO8
0_0402_5%
1 2 2
<6> VID0 1 2 1 24 1937_CS1 1937_FB G

2
PR100 0_0402_5% VID0 CS1 1 2

PQ22

PQ23
S

G
S
S
S

S
S
S
1 2 2 23 1937_DL1
<6> VID1

1
PR101 0_0402_5% VID1 DL1 PC179
1 2

1
2
3
4

1
2
3
4
1 2 4 22 1937_5V PR102 PC146 @1000P_0603_16V7K
<6> VID2 VID2 VLG 1937_DL1 <45>
PR103 0_0402_5% 200_0402_1% 220P_0603_50V8J

2
1 2 5 21 PR105 PD19
<6> VID3

1
PR104 0_0402_5% VID3 PGND
1 0_0402_5%
2 2 1 <45> CS1+ <7,45> +CPU_CORE
1 2 6 17 1937_DH2 PC110
<6> VID4 VID4 DH2 4700P_0402_25V7K_A34
PR106 0_0402_5% EP10QY03
CPUB+

5
1 2 1937_EN 13 16 1937_BST2 PD20
<6,11> VR_ON

2200P_0402_50V7K
EN BST2

10U_1210_25V6K_V1

10U_1210_25V6K_V1

10U_1210_25V6K_V1
PR107 0_0402_5% 2 1 PQ26
120K_0402_1%

1
1 2 1937_TIME 3 18 1937_LX2 SI7392DP_SO8

PC112

PC113

PC114

PC115
PR108 TIME LX2 EP10QY03 PR109 PQ49
PC111 1 2 1937_VPOS 7 19 1937_CS2 10_0402_5% 2 @SI7392DP_SO8

2
22P_0402_50V8J VPOS CS2
1 2 4 4
1

1937_REF 12 20 1937_DL2 PR110

1
C PR111 REF DL2 0_0402_5% PC116 C
130K_0402_1% 1937_ILIM 9 14 1937_FB 0.22U_0603_16V7K PL12
ILIM FB PR200 0.56UH_ETQP4LR56WFC_21A_20%

3
2
1

3
2
1
10 11 30.1K_0402_1% 2 1
2

PC117 1 2 GND GNDS

8
7
6
5

8
7
6
5

1
0.47U_0603_16V7K MAX1937EEI_QSOP28 1 2 PQ30
1

1
PR112 2N7002_SOT23 D PR113

D
D
D
D

D
D
D
D
PR134

1
IRF7832_SO8

IRF7832_SO8
200_0402_1% 2 1.05K_0603_1%
68_0805_5%
PR114 G
200K_0402_1% PC118 1 2

PQ27

PQ28
S +CPU_CORE

1 2

2
S
S
S

S
S
S
4700P_0402_25V7K_A34
2

2
PD21 PC119

1
2
3
4

1
2
3
4

2
SKS30-04AT_TSMA @1000P_0603_16V7K
PC147
1

2
1937_VDD <45> 1937_FB 220P_0603_50V8J
1937_FB
PR115 PR202
200K_0402_1%
3.9K_0402_1%
1 2 1 2 COREFB <6>
2

PR116
100_0402_1%
1

1 2 COREFB# <6>
PR117
PR203
1

3K_0402_5% 100_0402_1%

1
PC122
1

1
<45> 1937_REF 470P_0402_50V8J PC121
2

4700P_0402_25V7K_A34 PD22
PR118 @SKS10-04AT_TSMA
PC120
2

PD23 0_0402_5%
4700P_0402_25V7K_A34

2
@1N4148_SOD80
1 2
1

B PC123 B
2

PR119 @4.7U_1206_25VFZ
2

10K_0402_1%
+5VALWP
2

1 2 1 2 PQ31 PQ50 CPUB+


PR120 PR121
5

5
PD24 8.25K_0402_1% 2.05K_0402_1% SI7392DP_SO8 @SI7392DP_SO8
PR122

2200P_0402_50V7K
10U_1210_25V6K_V1

10U_1210_25V6K_V1

10U_1210_25V6K_V1
1 2 2 1
1980_V+

1
20

1 2

PC124

PC125

PC126

PC127
0_0402_5%
EP10QY03PU10 PR123 PR124
1980_VDD 11 17 0_0402_5% 1 2
TRIG

2
1

VDD V+
2.2U_0805_10V4Z

0_0402_5% 4 4
1

18 16 1980_BST
PC128

PR125 LIMIT BST


10_0402_1% 1980_VCC 12 14 1980_DH
2

VCC DH PC129 PL13


PD25
2

3
2
1

3
2
1

7 15 1980_LX 0.22U_0603_16V7K 0.56UH_ETQP4LR56WFC_21A_20%


1

POL LX SKS30-04AT_TSMA
2 1
1

PR152 3 10 1980_DL
8
7
6
5

8
7
6
5

1
PC130 100K_0402_5% TON DL
0.22U_0603_16V7K 1980_COMP 6 9 PR135 PR126
D
D
D
D

D
D
D
D
2

COMP PGND
IRF7832_SO8

IRF7832_SO8

68_0805_5% 1.05K_0603_1%
2

1980_DD# 13 5 1980_CS+
DD# CS+
1 2
PQ32

PQ33

2
G

G
S
S
S

S
S
S

4 1980_CS-
CS- PC131
19
1
2
3
4

1
2
3
4

ILIM @1000P_0603_16V7K
1
2

CM+
PC148
8 2 1 2
2

GND CM- PR128 220P_0603_50V8J


1

MAX1980EGP_QFN20 PC132 0_0402_5%


PR127
A 0.47U_0603_16V7K A
2

200K_0402_1% 1 2
1980_ILIM PR130
1980_CM+
1 2

0_0402_5%
1

PC133 PR129 1 2
1980_CM-

100P_0402_50V8J 220K_0402_1% PR131


1

PC134 0_0402_5%
COMPAL ELECTRONICS, INC
2

0.47U_0603_16V7K Title
2

1 2 +CPU_CORE(1)
PR132 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
0_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.5
B LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 44 of 50
5 4 3 2 1
5 4 3 2 1

<44> 1937_DL1

D D

1
PR192 PD44
0_0402_5% @SKS10-04AT_TSMA

@1N4148_SOD80

2
PC168

1
470P_0402_50V8J

1 2

1
PD43
PC178
PR183 @4.7U_1206_25VFZ

2
10K_0402_1%

2
2
PU14_COMP
+5VALWP 1 2 1 2 CPUB+
EP10QY03 PR177 PR178

2200P_0402_50V7K
10U_1210_25V6K_V1

10U_1210_25V6K_V1

10U_1210_25V6K_V1
PQ46 PQ47
PD42 8.25K_0402_1% 2.05K_0402_1%

1
SI7392DP_SO8 @SI7392DP_SO8

PC174

PC175

PC176

PC177
1 2 2 1

20
PR182

PU14_BST
C 0_0402_5% PU14 C

2
11 17 PU14_V+

TRIG
VDD V+
1
PR179
1

18 16 0_0402_5%
1 2 4 4
PC167 PR181 LIMIT BST PR176
2.2U_0805_10V4Z 10_0402_1% 0_0402_5% PU14_DH
12 14 1 2
2

PU14_VCC VCC DH PC165


2

7 15 0.22U_0603_16V7K
1 2 PL17

3
2
1

3
2
1
POL LX
1
100K_0402_5%
0.56UH_ETQP4LR56WFC_21A_20%
1

3 10 PU14_DL PU14_LX 2 1 +CPU_CORE


PC166 TON DL
PR180

1
0.22U_0603_16V7K 6 9
2

COMP PGND

8
7
6
5

8
7
6
5
PR190 PR191

SKS30-04AT_TSMA
2

1
13 5 PQ44 PQ45 68_0805_5% 1.05K_0603_1%

D
D
D
D

D
D
D
D
PU14_DD# DD# CS+
IRF7832_SO8 IRF7832_SO8

PD41
4 1 2

1 1

2
PR184 PU14_ILIM 19 CS-
ILIM
2

G
S
S
S

S
S
S
200K_0402_1% PR185 1 PC173

2
CM+
1

1 2 220K_0402_1% @1000P_0603_16V7K
<44> 1937_REF

1
2
3
4

1
2
3
4
PC169 8 2 PC172

2
GND CM-
100P_0402_50V8J 220P_0603_50V8J
2

MAX1980EGP_QFN20
1

PR186
0_0402_5%
B PU14_CS+ 1 2 B
PC170

1
0.47U_0603_16V7K
PR187

2
0_0402_5%
PU14_CS- 1 2

PU14_CM+ 1 2 CS1+ <44>


PR188

1
0_0402_5%

PC171

2
PU14_CM- 0.47U_0603_16V7K
1 2 +CPU_CORE <7,44>
PR189
0_0402_5%

A A

COMPAL ELECTRONICS, INC


Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE(2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-1851
Date: Thursday, October 16, 2003 Sheet 45 of 50
5 4 3 2 1
A B C D

PH1 under CPU botten side :


VMB
CPU thermal protection at 90 +-3 degree C
PCN2 PL14
1 FBM-L18-453215-900LMA90T_1812
Recovery at 50 +-3 degree C
BATT+ 2 1 2
BATT+ BATT+

3 TS_A VL

1
TS 4 EC_SMD VS
1
SMD 5 EC_SMC PC135 PC136 1

SMC 6 1000P_0402_50V7K 0.01U_0402_50V7K

2
GND 7

1
GND PC138

1
PC137 0.1U_0603_50V4Z
SUYIN_200275MR007G135ZL_7P @0.1U_0402_10V6K

2
CPU

2
VL

PTH1
10K_1% PR136

L_10
47K_0402_1%

2
1 2

1
PR137
1

PR138 47K_0402_1%
PR139 PR140 0_0402_5%
100_0402_5% 100_0402_5% 1 2 PR142 PD27

1
+3VALWP

8
PR141 16.9K_0402_1% PU11A 1SS355_SOD323

2
25.5K_0402_1% 1 2 3

P
2

+ 1 OTP_C 2 1
2

1 2 REV 2 O

L_10T

G
PR144 VL -
1K_0402_5% PR143 LM393M_SO8

4
100K_0402_1%

1
3
1

1
PC140

1
1 PD28 0.22U_0603_16V7K
@BAS40-04_SOT23 PR145 PR146

2
2 2.74K_0402_1% 100K_0402_1%

2
2 PC139 2

2
1000P_0402_50V7K
BATT_TEMP <30> <38,40> MAINPWON

EC_SMD_1
EC_SMD_1 <30,31>
EC_SMC_1
EC_SMC_1 <30,31>
1

PD29 PD30
@BAS40-04_SOT23 @BAS40-04_SOT23
PH2 near main Battery CONN :

1
PQ35
BAT. thermal protection at 84 +-3 degree C DTC115EKA_SC59

O
Recovery at 45 +-3 degree C
3

G
VL

I
2

3
+5VALWP

1
3 PC141 3

@0.1U_0402_10V6K VL
BATTERY

2
PTH2
10K_1%
PR147

L_11
47K_0402_1%
1 2

2
PR148 PR149
0_0402_5% 47K_0402_1%

PR150

8
16.9K_0402_1%

1
1 2 5

P
L_11T

+ 7 OTP_B2 1
REV 6 O
1

G
- PD31
PR151 1SS355_SOD323

4
3.32K_0402_1% PU11B
LM393M_SO8
1

PC142
0.22U_0603_16V7K
2

4 4

COMPAL ELECTRONICS, INC


Title

BATTERY CONN / OTP/1.8V


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-1851 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 46 of 50
A B C D
5 4 3 2 1

POWER PIR LIST


PHASE
D D
DB2 page Reason for change Modify list
Change PR66 from 6.49K_0603_1% to 1.54K_0603_1%
40 Modify 3V / 5V Vout and OCP Change PR156 from 11.8K_0402_1% to 698_0402_1%
Change PR154 from 4.12K_0603_1% to 0_0603_5%
Change PC54, PC53 from 0.1U_0805_25V7K to 0.47U_0805_25V4Z
Change PR62 from 5.76K_0603_1% to 1.27K_0603_1%
Change PR155 from 27K_0603_1% to 1.24K_0603_1%
Change PR153 from 4.7K_0402_1% to 619_0402_1%

44,45 For CPU_CORE thermal issue Change PQ21, PQ26, PQ31, PQ46 From IRLR7821 to SI7392DP
Delete PD23, PD43, SC11N4148T8
42 For 1.6V voltage accuracy Change PR173 from 113K_0402_1% to 107K_0402_1%

42 For layout pad issue Change PC85, PC86 from 22U_1210_10V4Z to 22U_1206_10V4Z

41 For power sequence setting Add PR197, 680K_0603_1%


Add PR198, 316K_0603_1%
C 38 For solving cable dock shutdown issue Add PD45, SKS80-04CT C

38 For thermal issue Change PD45 from SKS80-04CT to SBM1040


SI
38 Change VIN detector sensing point Change PR2 from 174k_0603_1% to 150k_0603_0.1%
because of DOCK issue Change PR7 from 75k_0402_1% to 66.5k_0402_1%

39 Improvment noise issue


41 Modify 2.5V / 1.5V OCP Change PR87 from 24.9k_0402_1% to 57.6k_0402_1%
Change PR88 from 0_0603_1% to 13.7k_0402_1%
Add PR89, 100k_0402_1%

43 VGA with 32M VRAM Remove 1.35V regulator that is for VGA with 64M VRAM

44,45 Modify CPU_CORE current balance issue Change the connection of PC122 and PC168 from
14 pin of PU9 to ground.
Remove PD22 and PD44.

B B
38 Improve the VIN detector accuracy. Change PR1, PR2, PR5, PR7, PC6, and re-connect the reference
PV voltage that is VL connected to PR10 to RTC charger output.

39 Improve the accuracy of Constant Voltage Change PR48, PR49


mode of charger.

41 reserve devices for the adjustment Add PR204, PR205, PR206, PC181, PC182
of 2.5V

44 Improve the transient response Add PR203, PC111, and remove PR202

A A

COMPAL ELECTRONICS, INC


Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-1851
Date: Thursday, October 16, 2003 Sheet 47 of 47
5 4 3 2 1
10 9 8 7 6 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 2


Item Fixed Issue Reason for change PAGE Modify List M.B. Ver.
H H

1 Fixed USB 1.1 rising/falling time error P12 Delete C785, C786, C787, C788, C789, & C790 0.3

2 Fixed TV-out no display P14 Swap TV_CRMA and TV_COMPS 0.3

3 Prevent PCI1620 latched up P22 Reserve G_RST# to pin U37.C11 0.3

4 Design change (solve for HR60 audio issue) P26 Move two load resistors from sub-board to M/B and swap JP17.2 and 0.3
G G
JP17.3

5 Supported wake up from TP P27 Change TP connector JP26's power pin from +5VS to +5V 0.3

6 EMI required (solve for 48 MHz noise from FDD connector) P32 Add CP11, CP12, CP13, and C801 0.3

7 Design change (TFDU6102 design guide) P33 Delete C560 and C562 & add R586 0.3
Change C561 from 10uf to 4.7uf
F F

8 EMI required (solve for 48 MHz noise from serial port) P34 Add CP14, and CP15 0.3

9 ID required (for Pavillion) P35 Add D58 0.3

10 EMI required P25 Add L38, and L39 0.3

11 Add bypass cap. to solve for AC97 link cross a split plane P27 Add C802, C803, C804, C805, and C806 0.3
E E

12 Design change (reserve space for power placement and no need too P07 Delete C75, and C88 0.3
many caps.)

13 RealTech 8101L design guide P20 Change R194 to 5.6K +/- 1% 0.3

14 Solve for SPDIF no output P34 Delete C634 0.3

D D
15 CPU_CLK is current drive from CK8. So, delete damping resistors. P11 Change R69, and R70 from 15 ohm to 0 ohm 0.3

16 Solve for burst frequency error P14 Change C642, and C643 from 18 pF to 22 pF 0.3

17 Solve for chrominance and burst level P18 Change L11, L12, and L13 to 1.8uH 0.3

C C

B B

A
Title
Compal Electronics, Inc. A

P.I.R HISTORY
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 48 of 50
10 9 8 7 6 5 4 3 2 1
10 9 8 7 6 5 4 3 2 1

Version change list (P.I.R. List) Page 2 of 2


Item Fixed Issue Reason for change PAGE Modify List M.B. Ver.
H H

1 AMD change Tdiode spec up to 127 degree P4 Change U3 from MAX6649 to ADM1032 0.4

2 Support wake from Lan P20 Populate R188 0.4

3 To avoid PCI1620 unknow action P22 Reserve R591 0.4

4 To restrain audio noise P25 Change R267 pull up to +5VAMP_CODEC, and delete C626 0.4
G G

5 USB_OC# high should be between 2.5V to 5.5V P27 Change R310 and R315 to 10K / R314 and R319 to 20K 0.4

6 To detect FIR P29 Add R592 and R593 0.4

7 TP should be pull up to +5V P30 RP80 pull up to +5V 0.4

8 In order to compatible with NS97551 P30 BID routed from pin88 to pin82 0.4
F F
-- changing pin87 ~ 90 to GPIO

9 In order to compatible with NS97551 P30 Add R594 and R595 0.4
-- removing +RTCVCC

10 To prevent noise generated from FAN to +5VS cause audio noise P4 Delete D1 and D3 / add C3, C8, C612, and C614 0.4
while shut down

E E
11 Solve for PCI1620 working abnormal -- fine tune G_RST# timming P22 Populate R587, delete R225, C410 0.4

12 Double mount issue, already exist at audio board. P30 Delete D28 and D29 0.4

13 Fast power on for battery only P33 Change R392 from 100K to 4.7K 0.4

14 Presario LED color should be amber P35 Change D39, D40, D42, D44, and D45 from XX_GRN to XX_ORG 0.4

D D
15 To develop SI9182 max effect P25 Change C438 from 0.01UF to 0.1UF 0.4

16 For EMI P26 Add L40, L41, L42, and L43 / delete C473, C474, C475, and C476 0.4

17 For VGA HSYNC/VSYNC average peak to peak issue P18 Add R159 and R160 0.4

18 For 512MB non-JEDEC module ( 16 chips ) P9 Change RP42, RP46, and R481 from 68 Ohm to 47 Ohm 0.4

C C

B B

A
Title
Compal Electronics, Inc. A

P.I.R HISTORY
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 49 of 50
10 9 8 7 6 5 4 3 2 1
10 9 8 7 6 5 4 3 2 1

Version change list (P.I.R. List) Page 3 of 3


Item Fixed Issue Reason for change PAGE Modify List M.B. Ver.
H H

1 To use the same source as HR60 P4 Change U3 footprint to SOP8 0.5

2 To reset CK8 while boot up control by EC P12 Add R97 to link EC_RSMRST# and PWRGD_SB 0.5

3 For EMI P15 Change C648, C672, C685, C696, C699, C763, and C656 to 1000P 0.5
Change C651, C673, C686, C697, C700, C764, C654, C733, C710,
C730, C706, and C724 to 10P
G G
Add U46 and U47, and R596, R597, and R598 on CRT_HSYNC 0.5
4 To solve voltage level of HSYNC and VSYNC is over spec P18
and CRT_VSYNC

5 Solve for data lost while transfer data from LAN P20 Change U9 from NS0013 to NS0019 0.5

6 TI recommandation --- avoid unknow state while initiate P22 Populate R591 0.5
F F

7 Mechanical restricted area P25 R263 and R264 change footprint to R_0402 0.5

8 For EMI P25 L39 and R293 change to CHB1608U301_0402 0.5

9 For EMI P26 L40, L41, L42, and L43 change to KC FBM-L11-201209-221LMAT_0805 0.5

10 nVIDIA recommandation for WOR P27 Add U48, C807, R599, and R600 0.5
E E

11 Due to MD_SPK is no longer use, so prevent input pin floating. P25 Delete R287 and change R288 to 0_0402_5%. Also add C808. 0.5

D D

C C

B B

A
Title
Compal Electronics, Inc. A

P.I.R HISTORY
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
LA-1851
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 16, 2003 Sheet 50 of 50
10 9 8 7 6 5 4 3 2 1
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