Outline

• The ASIC Design Process

• Introduction to Synthesis
Introduction to Synthesis

Ingo Sander
ingo@imit.kth.se

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The ASIC Design Process The ASIC Design Process

Behavioral Model RTL Model System

Routing
Development Development Partitioning

Behavioral Model Floor Circuit

Logic Synthesis
Validation Planning Extraction

ASIC
RTL Model Post Synthesis Post Lay-Out Sell off
Placement
Development Logic Simulation Simulation
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The ASIC Design Process The ASIC Design Process

Behavioral model development
– Development of a model that is used to capture the
functionality of the system. This model may be
formulated in VHDL for simulation.
Behavioral model validation
– Validation shall show if the design is correct and is
mostly done by means of simulation with a test bench.
– Tools for more formal methods (Code Coverage,
Equivalence Checking, Property Checking), and are
used to support the validation process.
RTL-Model Development
– The behavioral model has to be refined, so that it
complies with the synthesizable subset of VHDL.
– The RTL-Model has to be validated!
Logic Synthesis
– A logic synthesis tool, e.g. Synopsys Design Compiler,
is used to transform the RTL specification into a
structural gate-level circuit.
– The gate-level circuit uses information from an ASIC
library.

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 The ASIC Design Process The ASIC Design Process
Post Synthesis Logic Simulation Floorplanning
– The synthesized circuit must be simulated, mainly to – Blocks are assigned
check if the timing is correct. Synthesis has introduced
library parts with delay, thus the simulation has to
for different
check for sufficient register setup and hold times or components on a
hazards, etc. chip.
System Partitioning Placement Routing
– If the gate-level circuit is very large, it may be needed
– Standard cells are – Connections are
to partition it into smaller parts. This may require the
repetition of earlier steps. placed within each made between cells
block and blocks
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The ASIC Design Process Test is important!

Circuit Extraction • Observe that a large part of the design
– Determination of the resistances and capacitances of the process is validation!
interconnect. This information is back-annotated into
the gate-level model, replacing the information from the • A wrong design costs an enormous amount
wire load model. The information can be captured by
the standard delay format (SDF). of money!
Post Layout Simulation
– The back-annotated circuit is resimulated to check
circuit-timing and to provide a final check for
functionality. Successful completition is termed ASIC
sell off. The design is now ready to be shipped to the
silicon foundry.
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Design Compiler
ASIC Design Flow
(Synthesis Tool Suite)
SystemC VHDL / Verilog Liberty (.lib)
RTL / beh. RTL behavioral

SystemC (V)HDL C. Behavioral Library

Compiler Presto Compiler Compiler

Design
DC Ultra
Design Vision

FloorPlan
Manager
Compiler ACS DesignWare
Library

DFT BSD Power Module

Compiler Compiler Compiler Compiler Milkyway
planned for U-2003.03

Verilog, VHDL, EDIF Netlist

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 Synopsys Tool Suite Synopsys Tool Suite
RTL Synthesis RTL Synthesis
Synthesis FPGA Synthesis ClockTree Syn.
Sys temC Behav ioral
(V)H DL C. Presto Librar y Co mp iler
Com pil er VHD L / Ve rilogCom pil er

Design
Design
DC Ul tra Desig n Visi o n

FPGA
Compiler
Flo orPla n

Compiler
Ma na ger
Desig n
Com pil er
ACS

Compiler II
ClockTree
Test
DF TCCo
ommpiler
piler BSD C om piler Po wer Co m piler Mo dule C om piler

Compiler
Veri log, VHDL, EDIF Netl ist

Floorplanning Place & Route

Floorplan Routing
FPGA Vendor
Compiler Tool
Astro
RTL
S. + Placement
Chip Finish
Physical
Compiler Columbia

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Synopsys Tool Suite

Design Compiler Interfaces
(RTL to GDS II)
Synthesis
Design
Compiler

Floorplanning
dc_shell
Floorplan
.db

Coding Rules Compiler Scripts

Leda RTL
Liberty.lib

S. + Placement Viewer/Editor
Milkyway

Physical Enterprise
Verilog Equivalence
Design
Compiler Design
GDS II

VCS Formality StreamOut

Compiler
Milkyway

VHDL Static Timing

ClockTree Syn.
ClockTree
Analyzer
Scirocco PrimeTime
Compiler
Crosstalk GUI
Routing
PrimeTime-SI
Astro
Chip Finish

Columbia

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ASIC Synthesis ASIC Synthesis

(Synopsys Design Compiler) (Synopsys Design Compiler)
Steps during ASIC Synthesis: • Compile:
NOTE: Before you synthesize your design should be – The network of generic components is
validated through simulation (e.g. with ModelSim)
translated into a netlist of the target library.
• Analyze:
– Compilation should be constrained in terms of
– It is analyzed, if the source code uses the
synthesizable VHDL subset. delay, power, area of the synthesized design.
• Elaborate: – A good synthesis tool offers many options and
– A design is built of generic and technology an experienced designer knows how to use
independent components (Gate, Flip-Flops, Latch, them effectively.
MUX, Adder, etc.)

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 ASIC Synthesis Half-Adder
(Synopsys Design Compiler) (Implementation independent)
LIBRARY ieee;
• Report: USE ieee.std_logic_1164.ALL;
– This command documents the properties of the
synthesized circuit. ENTITY HalvAdder IS
PORT (
– It is important to understand the information given by a : IN std_logic;
the reports of the synthesis tool. b : IN std_logic;
s : OUT std_logic_vector(1 DOWNTO 0));
• Save: END HalvAdder;
– This command allows to save the design at each step.
The *.db format is used internally by Synopsys. The ARCHITECTURE Bool OF HalvAdder IS
BEGIN -- Bool
circuit can also be saved into VHDL-format (*.vhd) s(1) <= a AND b;
in order to allow for simulation of the synthesized s(0) <= a XOR b;
circuit. END Bool;

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Half-Adder
Script for Half-Adder Synthesis
(Implementation independent)
analyze -format vhdl -lib WORK
./source/halvadder.vhd
elaborate HalvAdder -arch "Bool" -lib WORK -
update
write -format db -output ./unmapped/halvadder.db

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Script for Half-Adder Synthesis Synthesized Circuit

compile -map_effort medium
write -format db -output
./mapped/halvadder_cx4001_unconstrained.db
write -format vhdl -output
./mapped/halvadder_cx4001_unconstrained.vhd
report_timing >
./reports/halvadder_cx4001_unconstrained.rep
report_area >>
./reports/halvadder_cx4001_unconstrained.rep

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 Synthesized VHDL Description Synthesized VHDL Description
library IEEE; library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;
use work.CONV_PACK_HalvAdder.all;
package CONV_PACK_HalvAdder is
-- define attributes entity HalvAdder is
attribute ENUM_ENCODING : STRING; port( a, b : in std_logic;
end CONV_PACK_HalvAdder; s : out std_logic_vector (1 downto 0));
end HalvAdder;

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Report Files
Synthesized VHDL Description
(Timing)
architecture SYN_Bool of HalvAdder is ****************************************
component ad20 Report : timing
port( A, B : in std_logic; Z : out std_logic); -path full
end component; -delay max
-max_paths 1
Design : HalvAdder
component ex20
Version: 2002.05-SP2
port( A, B : in std_logic; Z : out std_logic);
Date : Fri Mar 14 11:11:10 2003
end component; ****************************************
begin
U7 : ad20 port map( A => b, B => a, Z => s(1)); Operating Conditions: quick_max Library:
U8 : ex20 port map( A => b, B => a, Z => s(0)); cx4001_core_max
end SYN_Bool; Wire Load Model Mode: top

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Report Files
Critical Path
(Timing)
Startpoint: a (input port)
Endpoint: s<1> (output port)
Path Group: (none)
Path Type: max

Point Incr Path

-----------------------------------------------------------
input external delay 0.00 0.00 f
a (in) 0.00 0.00 f
U7/Z (ad20) 0.31 0.31 f
s<1> (out) 0.00 0.31 f
data arrival time 0.31
-----------------------------------------------------------
(Path is unconstrained)

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 CX4001-Library Element CX4001-Library Element
AD20 EX20

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Report Files Report Files

(Area) (Area)
**************************************** Combinational area: 4.250000
Report : area Noncombinational area: 0.000000
Design : HalvAdder
Version: 2002.05-SP2
Net Interconnect area: undefined (No wire load
Date : Fri Mar 14 11:11:10 2003
specified)
****************************************
Library(s) Used: Total cell area: 4.250000
cx4001_core_max (File: Total area: undefined
/afs/it.kth.se/pkg/synopsys/extra_libraries/gate_array/Chip
Express/syn/cx4001/cx4001_core.max.db)

Number of ports: 4
Number of nets: 4
Number of cells: 2
Number of references: 2

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Script for speed-optimized Synthesized Circuit

half-adder (optimized for speed)
read -format db ./unmapped/halvadder.db
set_max_delay 0 -to all_outputs()
compile -map_effort medium
write -format db -output
./mapped/halvadder_cx4001_speed.db
report_timing >
./reports/halvadder_cx4001_speed.rep
report_area >>
./reports/halvadder_cx4001_speed.rep

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 Report Files Report Files
(Timing) (Area)
Point Incr Path Number of ports: 4
-----------------------------------------------------------
Number of nets: 5
input external delay 0.00 0.00 r
a (in) 0.00 0.00 r
Number of cells: 3
U7/Z (ex20) 0.30 0.30 r Number of references: 3
s<0> (out) 0.00 0.30 r
data arrival time 0.30 Combinational area: 6.000000
max_delay 0.00 0.00
Noncombinational area: 0.000000
output external delay 0.00 0.00 Net Interconnect area: undefined (No wire
data required time 0.00 load specified)
-----------------------------------------------------------
data required time 0.00 Total cell area: 6.000000
data arrival time -0.30
-----------------------------------------------------------
Total area: undefined
slack (VIOLATED)

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CX4001-Library Element CX4001-Library Element

AD21 IV10

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Ideal delay vs. area curve Ideal delay vs. area curve
Delay Delay
Bad Startposition for the synthesis
algorithm

Good Startposition for the

synthesis algorithm
Ideal Design

Area Area

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 To get a good starting position! Synthesis of a modulo-4 counter
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY Counter03 IS

THINK
PORT (
clk : IN std_logic;
resetn : IN std_logic;
three : OUT std_logic);
END Counter03;

HARDWARE ARCHITECTURE FSM OF Counter03 IS

SUBTYPE state_type IS integer
SIGNAL state, nextstate
ATTRIBUTE STATE_VECTOR
ATTRIBUTE STATE_VECTOR OF FSM
RANGE 0 TO 3;
: state_type := 0;
: string;
: ARCHITECTURE IS "STATE";

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Synthesis of a modulo-4 counter Synthesis of a modulo-4 counter

BEGIN -- FSM PROCESS (state)
PROCESS (clk, resetn) BEGIN -- PROCESS
BEGIN -- PROCESS three <= '0';
IF resetn = '0' THEN CASE state IS
state <= 0; WHEN 0 TO 2 => nextstate <= state + 1;
ELSIF clk'event AND clk = '1' THEN WHEN 3 => nextstate <= 0;
state <= nextstate; three <= '1';
END IF; WHEN OTHERS => nextstate <= 0;
END PROCESS; END CASE;
END PROCESS;
END FSM;

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Exercise Synthesis Script

Implement the following VHDL description with analyze -format vhdl -lib WORK ./source/counter03.vhd
a) Inverters, AND, OR-gates and D-FF elaborate Counter03 -arch "FSM" -lib WORK -update
BEGIN -- FSM
b) A PAL16R6 PLD PROCESS (clk, resetn)
c) An Actel ACT3 FPGA BEGIN -- PROCESS write -format db -output ./unmapped/counter03.db
IF resetn = '0' THEN -- asynchronous
d) A KTH-FPGA reset (active low) create_clock -period 10 -waveform {0 5} clk
state <= 0;
LIBRARY ieee; ELSIF clk'event AND clk = '1' THEN -- rising clock edge compile -map_effort medium
USE ieee.std_logic_1164.ALL; state <= nextstate;
END IF; write -format db -output
ENTITY Counter03 IS END PROCESS;
PORT ( ./mapped/counter03_cx4001_unconstrained.db
clk : IN std_logic; PROCESS (state)
resetn : IN std_logic; BEGIN -- PROCESS
write -format vhdl -output
three : OUT std_logic);
END Counter03;
three <= '0'; ./mapped/counter03_cx4001_unconstrained.vhd
CASE state IS

ARCHITECTURE FSM OF Counter03 IS

WHEN 0 TO 2 => nextstate <= state + 1; report_timing >
WHEN 3 => nextstate <= 0;
SUBTYPE state_type IS integer RANGE 0 TO 3; three <= '1'; ./reports/counter03_cx4001_unconstrained.rep
SIGNAL state, nextstate : state_type := 0; WHEN OTHERS => nextstate <= 0;
ATTRIBUTE STATE_VECTOR : string; END CASE; report_area >>
ATTRIBUTE STATE_VECTOR OF FSM : ARCHITECTURE IS END PROCESS;
"STATE";
END FSM;
./reports/counter03_cx4001_unconstrained.rep

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 Synthesis Result Timing Report
(CX4001-unconstrainded) (unconstrained)
Point Incr Path
-----------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
state_reg<1>/CP (dfnpc) 0.00 0.00 r
state_reg<1>/Q (dfnpc) 0.51 0.51 r
U45/Z (iv10s) 0.29 0.79 f
U49/Z (nd21) 0.32 1.12 f
U47/Z (ad20) 0.42 1.53 f
state_reg<0>/D (dfnpc) 0.00 1.53 f
data arrival time 1.53

clock clk (rise edge) 10.00 10.00

clock network delay (ideal) 0.00 10.00
state_reg<0>/CP (dfnpc) 0.00 10.00 r
library setup time -0.35 9.65
data required time 9.65
-----------------------------------------------------------
data required time 9.65
data arrival time -1.53
-----------------------------------------------------------
slack (MET) 8.12

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Area Report Synthesis Script

(unconstrained) (constrained)
Number of ports: 3 read -format db ./unmapped/counter03.db
Number of nets: 11 create_clock -period 10 -waveform {0 5} clk
Number of cells: 9 set_max_delay 0 -to all_outputs() +
Number of references: 5 all_registers(-data_pins)
compile -map_effort medium
Combinational area: 12.750000 write -format db -output
Noncombinational area: 4.500000 ./mapped/counter03_cx4001_speed.db
Net Interconnect area: undefined (No wire load report_constraint >
specified) ./reports/counter03_cx4001_speed.rep
report_timing >>
./reports/counter03_cx4001_speed.rep
Total cell area: 17.250000
report_area >>
Total area: undefined
./reports/counter03_cx4001_speed.rep

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Synthesis Result
Comparison
(CX4001-Speed)
Constraint
Unconstrained (Speed)
Delay 1.53 ns 0.85 ns
(Arrival Time)
Area 17.25 14.25

Constraints are needed to get a good result!

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 Synthesis Result Altera MAX 7000 Family
(Max7000) (Macrocell)

T-Flip-Flop
Macrocell can be used as
combinational or sequential output
Delay: 1.5 ns

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Timing Report
(MAX 7000)
Point Incr Path
-----------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
state_reg<0>/CLK (DFF) 0.00 0.00 r
state_reg<0>/Q (DFF) 1.00 1.00 f
U45/A_OUT (INV) 0.50 1.50 r
state_reg<0>/D (DFF) 0.00 1.50 r
data arrival time 1.50
Set-Up Time is
clock clk (rise edge) 10.00 10.00
clock network delay (ideal) 0.00 10.00 larger than
state_reg<0>/CLK (DFF) 0.00 10.00 r network delay!
library setup time -2.00 8.00
data required time 8.00
-----------------------------------------------------------
data required time 8.00
data arrival time -1.50
-----------------------------------------------------------
slack (MET) 6.50

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