Q-band Low Noise Amplifiers Using a 0.
15-µm MHEMT Process for
Broadband Communication and Radio Astronomy Applications
Shou-Hsien Weng, Chi-Hsien Lin, Hong-Yeh Chang, and Chau-Ching Chiong*
Department of Electrical Engineering, National Central University, Jhongli, Taoyuan, 320, Taiwan, R. O. C.
*
Academia Sinica, Institute of Astronomy and Astrophysics, P.O. Box 23-141, Taipei 106, Taiwan, R. O. C.
Abstract — Two Q-band low noise amplifiers using a 0.15-µm
InGaAs MHEMT process for broadband communication and
radio astronomy applications are presented in this paper.
Between 37 and 53 GHz, the LNA1 features a small signal gain
of higher than 31 dB, a noise figure of better than 3.5 dB with a
minimum noise figure of 2.8 dB at 44 GHz, and a gain-
bandwidth product (GBP) of 679 GHz. Between 32 and 50 GHz,
the LNA2 features a small signal gain of higher than 28 dB, a
noise figure of better than 3.2 dB with a minimum noise figure of
2.6 dB at 44 GHz, and a GBP of 569 GHz. The chip sizes of the
LNA1 and LNA2 are both 2¯1 mm2. The LNAs demonstrate
broad bandwidth, high gain, low noise figure, and compact chip
size, and they will be further applied to a few broadband
receivers for communications and radio astronomy applications.
Moreover, this work demonstrates the highest GBP among all the
reported Q-band LNAs.
Index Terms —Broadband, high gain, InGaAs, MHEMT, low
noise figure.
I. INTRODUCTION
A Low noise amplifier is an essential component for a
highly sensitive receiver, especially for a radio telescope, a
satellite earth station, or a mobile phone base station.
Therefore, most of them are based on GaAs or InP high
electron mobility transistors (HEMTs) processes due to their
superior noise figure and linearity. HEMT devices on InP
substrates have demonstrated excellent microwave and
millimeter-wave (MMW) characteristics, such as low noise
figure, and high gain compared to GaAs-based HEMTs [1]-
[2]. However, the main drawback of the InP substrate is the
difficulty to fabricate in mass production. So far, it is not
available in large scale, such as 6” wafer, and the cost is very
high. Over the past few years, a lot of researchers have
successfully accomplished the growth of InAlAs/InGaAs
metamorphic HEMTs (MHEMTs) on a GaAs substrate to
accommodate to the lattice mismatch between the GaAs
substrate and the active layer. The metamorphic buffer layer
gradually varies the lattice constant from the GaAs substrate
to that of the indium-rich active layer. The misfit dislocations
can be trapped by using the buffer layer, and also prevent
their propagation in the active layer grown on this buffer [3].
A MMW LNA using a GaAs HBT process has been
reported in [4] with high gain performance, but the noise
figure is too high to apply to a highly sensitive receiver. For
low noise figure amplifiers in Q-band frequency, InP-based
HEMT processes [5]-[8] and GaAs-based HEMT processes
978-1-4244-1780-3/08/$25.00 © 2008 IEEE
[8]-[11] have been adapted. However, the bandwidths of the
LNAs are relatively narrow for few broadband applications.
To achieve wide bandwidth and low noise, an architecture
based on the distributed amplifier (DA) can be used [12].
This DA using a 0.1-µm MHEMT process demonstrates broad
bandwidth with low noise, however, the dc power
consumption is high and the chip size is also large.
In this paper, we use a 0.15-µm MHEMT process to
design two LNAs for broadband communication and radio
astronomy applications. Two LNAs are both designed using a
3-stage configuration, and the LNAs demonstrate broad
bandwidth with low noise figure. Therefore, they are very
suitable for MMW broadband communication systems or
radio astronomy, such as Atacama large
millimeter/submillimeter array (ALMA) [13], or very long
baseline interferometry space observatory progreamme 2
(VSOP-2) [14]. The LNA1 features a 3-dB bandwidth of 16.2
GHz and a gain-bandwidth product (GBP) of 679 GHz; the
LNA2 features a 3-dB bandwidth of 18 GHz and a GBP of
569 GHz. To the best of the authors’ knowledge, this work
demonstrates the highest GBP among all the reported Q-band
LNAs.
II. CIRCUIT TOPOLOGY AND DESIGN METHODOLOGY
Two LNAs are fabricated using a 0.15-µm InGaAs
MHEMT process provided by WIN Semiconductors Corp. A
two-finger with a gate width of 50 µm device is selected for
the circuit designs. The device exhibits a unit current gain
frequency (fT) of 110 GHz and a maximum oscillation
frequency (fmax) of higher than 150 GHz. Metal-insulator-
metal (MIM) capacitors, spiral inductors, backside VIA holes
and thin film resistors are also available in this MMIC process.
The schematics of the LNA1 and the LNA2 are shown in
Fig.1 (a) and (b), respectively. Two LNAs are both designed
using a 3-stage configuration. In order to achieve high gain
with low noise figure, each stage of the LNAs is based on a
common-source device with two source-degeneration
inductors. The source-degeneration inductor is used to
improve the stability and the input match of the amplifiers.
The choice of the source-degeneration inductor should be a
tradeoff between the device’s maximum available gain and
minimum noise figure [15]. The micro-strip lines and MIM
capacitors are utilized for the matching networks. For the
455
bypass networks of the dc supply, an in-band bypass capacitor, III. EXPERIMENTAL RESULTS
and two low frequency bypass capacitors with and without a
The LNA1 and LNA2 chips are measured via on-wafer
small resistor are also included for the stability. The Q factor
probing. The S-parameters are measured by an Agilent
of bypass circuits can be reduced by the resistors to avoid
E8361A network analyzer. The noise figure is measured by an
unwanted resonances caused by parasitic inductance of the
Agilent N8975A noise figure analyzer and an Agilent
VIA holes and the MIM capacitors [16]. The low frequency
346Ck01 noise source with Ka- and Q-band down converters
oscillation can be further suppressed by the low frequency
to convert the MMW frequency to low frequency for the noise
bypass capacitor with the resistor, since the maximum
figure measurements. For the LNA1, the simulated and
available gain of the device is very high in the low-frequency.
measured small signal gains from 10 MHz to 70 GHz are
Furthermore, the low frequency noise and interference can be
plotted in Fig.3. The simulated and measured noise figures
further eliminated to ensure the stability of the LNAs. The
from 30 to 50 GHz are plotted in Fig.4. The measured results
differences between the LNA1 and the LNA2 are the input
agree with the simulated results. The measurement exhibits a
and output matching networks for each stage. The LNA1 is
minimum noise figure of 2.8 dB at 44 GHz. The measurement
designed for high frequency band, and the LNA2 is designed
of the LNA1 exhibits a small signal gain of better than 31 dB
for low frequency band. All of the passive components, such
from 37 to 53.2 GHz and an average noise figure of 3 dB
as the microstrip lines, and the dc-block/bypass capacitors, are
from 30 to 50 GHz. The measured average input and output
all simulated with a full wave EM simulator [17].
return losses are better than 5 dB between 30 and 55 GHz.
VD
VD
VD

Output

Input

VG
VG VG

(a)
VD
(a)
VD
VD
Output

Input

VG
VG
VG

(b)
Fig. 1 (a) Schematic of the LNA1, and (b) schematic of the LNA2
The dc bias of the LNA1 is 2 V with a total dc current
consumption of 76 mA. The first stage is designed for
minimum noise figure with an appropriate inductive feedback.
Furthermore, the optimum impedance for the minimum noise
figure and maximum gain can be obtained using the source
degeneration inductor. The second stage is also matched for
minimum noise, while the third stage is matched for gain. The
dc bias of the LNA2 is also 2 V with a total dc current
consumption of 70 mA. The chip photos of the LNA1 and
LNA2 are showed in Fig.2 (a) and (b), respectively, and the
chip sizes of the two LNAs are both 2¯1 mm2 .
(b)
Fig. 2. (a) Chip photo of the LNA1 with a chip size of 2¯1 mm2,
and (b) chip photo of the LNA2 with a chip size of 2¯1 mm2.
For the LNA2, the simulated and measured small signal
gains from 10 MHz to 70 GHz are plotted in Fig.5. The
simulated and measured noise figures from 30 to 50 GHz of
the LNA2 are plotted in Fig.6. Again, the measured results
agree with the simulated results. The LNA2 features a
minimum noise figure of 2.6 dB at 44 GHz, a small signal
gain of better than 28 dB from 32 to 50 GHz and an average
noise figure of 3.1 dB from 30 to 50 GHz. The measured
average input and output return losses of the LNA2 are better
than 5 dB between 30 and 50 GHz.

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 40 40
Measurem ent Measurem ent
35 Sim ulation 35 Sim ulation
Small Signal Gain (dB)

Small Signal Gain (dB)

30 30

25 25

20 20

15 15

10 10

5 5

0 0
0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70
Frequency (GHz) Frequency (GHz)
Fig.3. Simulated and measured small signal gain of the LNA1. Fig.5. Simulated and measured small signal gain of the LNA2

10 10
9 9
8 8
7 7

Noise Figure (dB)

Noise Figure (dB)

6 6
5 5
4 4
3 3
2 Measurement 2
Measurement
1 Simulation 1 Simulation
0 0
0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70
Frequency (GHz) Frequency (GHz)

Fig.4. Simulated and measured noise figure of the LNA1 Fig.6. Simulated and measured noise figure of the LNA2

The comparison of the previously reported LNAs and this

work are summarized in Table I. The performance of LNA
can be evaluated by a figure-of-merit (FOM) defined in [18]
and it can also be evaluated by a GBP [19]. The expressions
of the FOM and the GBP can be expressed as
S 21 mag * Bandwidth [ GHz ]
FOM =
( NF mag − 1) * Pdc [ mW ]
GBP = S 21 mag * bandwidth [ GHz ] ,
where S21mag and NFmag are the magnitudes of small signal
gain and the noise figure, respectively, and Pdc is the overall
dc power consumption (mW). Therefore, the LNA1 and the
LNA2 exhibit FOMs of 4.08 and 4.79 (GHz/mW) and GBP of
679 and 569 GHz, respectively. As can be observed, this work
demonstrates the best gain-bandwidth product among the
reported Q-band LNAs.
IV. CONCLUSION
Two LNAs using a 0.15-µm MHEMT process have been
successfully developed for broadband communication and
radio astronomy applications. Between 30 and 50 GHz, the
LNAs demonstrate high gain with low noise figure.
Furthermore, the chip sizes of the LNA1 and the LNA2 are
and (1) 2
both only 2¯1 mm , and they are very suitable for large array
applications due to their compact size, high performance, and
good median time to failure. In our future works, the LNAs
(2) will be assembled in mechanical housing with two Q-band
waveguide transitions for cryogenic measurements, and also
the LNA modules can be further applied to broadband
communication and radio astronomy receivers.
ACKNOWLEDGEMENT
This work was supported in part by the National Science
Council of Taiwan, R. O. C., under Grant NSC 96-2221-E-
008-113-MY3, Grant NSC 96-2221-E-008-019, and the
ALMA-T research project in ASIAA, Taipei, Taiwan, R. O. C.

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 TABLE I COMPARISONS OF PREVIOUSLY REPORTED LNAS AND THIS WORK.
DC Chip
Ref. Bandwidth Gain NF GBW FOM
Power Topology Process Size
(GHz) (dB) (dB) (GHz) (GHz/mW)
(mW) (mm2)
[4] 27-30 15 6 144 4-stage single ended LNA GaInP/GaAs HBT 16.87 0.04 2¯2
[5] 27-30 41 1.4 38.4 5-stage single ended LNA 0.12-µm InP HEMT 336.6 23.07 3¯1
43.3-45.7 22.2 1.9 111 3-stage single ended LNA 30.91 0.51 2¯3
[6] 0.1-µm InP HEMT
58-62 16.7 2.2 29 2-stage single ended LNA 27.35 1.43 2¯2.5
58-64 21.5 2.4 98 3-stage single ended LNA 71.31 0.99 1.5¯2.5
[7] 0.1-µm InP HEMT
58-65 15 2.3 112 4-stage single ended LNA 39.36 0.50 1.5¯3
43-46 20 1.8 18 2-stage single ended LNA 0.1-µm InP HEMT 30 3.25 -
[8]
43-46 28 2.5 108 4-stage single ended LNA 0.1-µm GaAs PHEMT 75.4 0.90 -
0.25-µm 3.5¯2
[9] 27-31 15.2 2.4 125 3-stage single ended LNA AlGaAs/InGaAs 12.84 0.25
PHEMT
[10] 35-50 22 3 - 3-stage single ended LNA 0.15-µm GaAs PHEMT 188.83 - -
[11] 55-65 18.5 5 63 3-stage single ended LNA 0.15-µm GaAs PHEMT 84.13 0.62 1.3¯0.7
This work
37-53.2 32.5 3.21 152 3-stage single ended LNA 0.15-µm MHEMT 678.93 4.08 2¯1
LNA1
This work 2¯1
32-50 29.5 2.8 140 3-stage single ended LNA 0.15-µm MHEMT 569.2 4.79
LNA2

The chip was fabricated by the WIN Semiconductors Corp..
Taiwan, R. O. C. The authors would like to acknowledge
Chip Implementation Center (CIC) of Taiwan for providing
EDA design software. Thanks also go to Prof. Heng-Kuang
Lin for the MMIC process discussions.
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