$basicsofvlsi 160504113140 PDF

VLSI
WELCOME
Lavesh Kumath
Head, R & D (VLSI Division )
Scientech Technologies Pvt. Ltd., Indore
lkumath@scientech.bz
www.ScientechWorld.com
Basics
THE ARTof
OFVLSI
VLSI
Semi conductor Power
Diodes Area Speed
DTL Transistors
BJT – TTL,RTL, ECL FET
Gates MOSFET
JFET
N MOS P MOS CMOS

ICs N Chan P Chan
SSI Gates
MSI LSI
ICs
Density
SSI MSI LSI VLSI
Functionality Features
endless Journey……
General Design Flow….
TTL Logic
Design Specification
Truth Table
Boolean Expression
Implementation
Logic minimization Cost and

Available
and multilevel performance
Inventory
logic optimization requirement
Digital Design Process
1. Design Specifications 2. Truth TableC
A A B D X
B Logic O/P = X
0 0 0 0 0
C 2 or >2 I/P = 1 then O/P 1
D 0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
AB /CD 00 01 11 10
0 1 0 0 0
3. Reduce
0 1 0 1 1
Expression
00 0 0 1 0 0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
01 0 1 1 1
1 0 0 1 1
1 0 1 0 1
11 1 1 1 1 1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
10 0 1 1 1
1 1 1 0 1
1 1 1 1 1
Boolean Eq. -> X = AB + CD + BD + BC + AD + AC OR X’ = A’B’C’ + A’B’D’ + A’C’D’ + B’C’D’
Digital Design Process
1. Design Specifications
2. Truth Table
3. Reduction using Boolean
or K Map
4. Minimize of Device or No. of Level i.e. Cost Vs Performance (Min Prop. Delay)
5. Examine Available Inventory
6. Eqn Re-written in NAND-

Few Device and Few logic i.e. Less Cost and Better Performance
NAND implementation
Boolean Eq. -> X = {(AB)’. (CD)’ . (BD)’ .(BC)’. (AD)’ .(AC)’ }’ --> 2 - 7400, 1 - 7430, 2 level of logic
1 - 7474 for
synchronization 1
2
Boolean Eq. -> X = AB + CD + BD + BC + AD + AC --> 2 - 7408, 3 - 7432, 3 level of logic

1 - 7474 for synchronization
Basics of VLSI ………..
• VLSI Introduction
• History of VLSI.
• Why VLSI …. ?
• VLSI Design Styles
• VLSI Design Flows
• VLSI Design Approaches
• Xilinx Vs Altera
VERY LARGE SCALE INTEGRATION
“ Is the art of integrating millions of transistors on a Silicon Chip ”
History of IC Design
The First Transistor
“ A device called a transistor, which has several applications

In radio where a vacuum tube ordinarily is employed, was
demonstrated for the first time at Bell Telephone
Laboratories, 463 West Street, where it was invented.”
23 December 1947
First point contact transistor (germanium), 1947

John Bardeen and Walter Brattain
Bell Laboratories
- Evolution of ICs -
High Performance
 Vacuum tubes
High Reliability
 Transistors High complexity or small Area
?
High applicability
 Gates Low Power Dissipation

Low power consumption
 ICs Integrated Circuits Low Cost

Fast Design time
Simple Design Process
IC is a collection of Electronic Circuits made by simultaneously forming individual

Transistors, Diodes and Resistors on a small chip of Semiconductor material, typically
silicon that are interconnected to one another with a metal, such as aluminum, deposited
on the chip surface.
The Progressive Trend of IC Technology
Integration Level Year Number of Transistors
SSI - Individual Gates 1950s Less than 10^2
MSI - Counter, Shift Reg. 1960s 10^2 – 10^3
LSI - Small Logic Function 1970s 10^3 – 10^5
VLSI - Large Logic Function 1980s 10^5 – 10^7
1990s 10^7 – 10^9
2000s Over 10^9
Evolution in IC Complexity
Moore’s Law
In 1965, Intel co-founder

Gordon Moore
saw the future.
His prediction, now popularly
known as Moore's Law,
states that
“The number of transistors on a
chip doubles about every two
years”
-Other Trends
Transistor Count – Number of Transistor doubles every 2-3 Yrs
Clock Frequency – Clock Frequency doubles every 2.168 Yrs
Features Size – Gate Length is divided by 2 every 5.43 Yrs

http://www.intel.com/technology/silicon/mooreslaw/
VLSI Technology - CMOS Transistors
P o lys ilico n G a te
SiO 2
I ns ula to r L D
W
S o urce D ra in
G SB G
p+ p+
channel
n substrate S sub strate connected

to VDD
p transistor
Key feature:
transistor length L 2002: L=130nm
S iO 2
P o lys ilico n G a te 2003: L=90nm
I ns ula to r L D D 2006: L=65nm
W
S o urce D ra in
G SB G
n+ n+
channel
p substrate S S
sub strate connected
n transistor to GND
2002 and beyond ?
Semiconductor Industry Association (SIA) Road Map, 1998 Update
1999 2002 2014
Technology (nm) 180 130 35
Wafer diameter (mm) 300 300 450
Memory-samples (bits) 1G 4G 1T
Transistors/cm2 (µ P) 6.2M 18M 390M
IEEE Spectrum, July
Wiring levels (maximum) 6-7 7 10 1999
Special report: “The
Clock, local (MHz) 1250 2100 10000 100-million transistor
Chip size: DRAM (mm2) 400 560 2240 IC”
Chip size: µP (mm2) 340 430 901

Power supply (V) 1.5-1.8 1.2-1.5 0.37-0.42
Maximum Power (W) 90 130 183
Number of pins (µP) 700 957 3350
These scaling trends will allow the electronics market to growth at 15% / year
Power & Clock Frequencies
 Power Consumption, Clock frequency, Supply Voltage are related as follows :-
Capacitance Supply Voltage Clock Frequency
Why VLSI Design ?
• Large Scale Integration -
Size ….. <<<
Speed …. >>>
Power …. <<<
• Integration reduce manufacturing costs

(almost) no manual assembly
• Money Vs Performance
VLSI Design Styles
Integrated Circuits
1 2 3 4
User Semi-Custom Full-Custom System-On

Programmable ASICs ASICs CHIP
PLD FPGA
PAL PLA SPLD CPLD Gates MUX LUT

(Look-Up Table)
VLSI Design Styles
1. Programmable Logic (PLD, FPGA)
2. Application-Specific Integrated Circuit (ASIC)
3. Full Custom
4. System-on-Chip
VLSI Design Styles
Integrated Circuits
1 2 3
4
Semi-Custom Full-Custom
User System-On
ASICs ASICs
Programmable CHIP
PLD FPGA
PAL PLA SPLD CPLD Gates MUX LUT

(Look-Up Table)
1. Programmable Logic (PLDs, FPGAs)
• Pre-manufactured components with programmable interconnect
• CAD tools greatly reduce design effort
• Low Design Cost
• Low NRE Cost
• High Unit Cost
• Lower Performance as compared to ASIC better than General digital design
Logic Circuits
Standard Logic Circuits Programmable Logic Circuits

• Realize single function or set of • Possibility of realizing various
functions functions
FP LD
• No possibility of changing. • Re-configurable ……
• More Debugging Time • Less Debugging Time
• More Interconnections and I/Os • Fewer total I/Os & Switching O/P-
• High Standby and Switching current • Lower Standby & Switching Currents
• No Design Security • Design Security
• Not Flexible • Flexibility …….. Greatest Advantage
• No Tools for Automation • Automation is Possible
• More NRE & Time to Market • Less NRE & Less Time to market
Single Change require – redesign only reprogramming is required
FPLD Representatives
• PLA - Programmable Logic Arrays

• PAL - Programmable Array Logic PLD
• CPLD - Complex Programmable Logic Devices
• FPGA - Field Programmable Gate Arrays
What is a CPLD ?
 Complex Programmable Logic Devices (CPLD) are another way to extend

the density of the simple PLD.
 CPLD uses less board space, improve reliability, and reduce cost.
 CPLD contains multiple logic block, which communicate with one another
using Signals routed via a programmable interconnect.
 Easily Routed.
 CPLDs are great at handling wide and complex gating at blistering

speeds
e.g. 5ns which is equivalent to 200MHz.
CPLD Architecture
CPLD Architecture
Complex Programmable Logic Devices
Why use a CPLD ?
 Ease of Design
 Lower Development Costs
 More Product Revenue
 Reduced Board Area
 Reconfigurable
 Flexible
Evolution of PLD: FPGA
contains a set of
basic functions
• Difficult extending CPLDs architectures to (gates, FFs,
higher densities
memory cells)
-
a different approach is needed
• FPGAs comprise an array of uncommited circuit elements,

called logic blocks, and interconnect resources
• FPGA configuration is performed through
programming by the end user.
Xilinx FPGA Configuration
General FPGA Architecture
• Field Programmable Gate Array
www.ScientechWorld.com 29
FPGAs -- Pros
• Reasonably Cheap at low volume

– Good for low-volume parts, more expensive than IC for high-volume parts
– Can migrate from SRAM based to fuse based when volume ramps up
• Short Design Cycle (~1sec programming time)
• Reprogrammable
– Can download bug fix into units you’ve already shipped
• Large capacity (100 million gates or so .….
• More flexible than PLDs -- can have internal state
• More compact than MSI/SSI
FPGA’s -- Cons
• Lower capacity, speed and higher power consumption than building an ASIC
– Sub-optimal mapping of logic into CLB’s – often 60% utilization
– Much lower clock frequency
– Less dense layout and placement and slower operation due to

programmability
• Overhead of configurable interconnect and logic blocks
• PLDs may be faster than FPGA for designs they can handle
• Need sophisticated tools to map design to FPGA
Key Factors For Comparing FPGAs
• Logic density
• Clock management
• On-chip memory
• DSP capabilities
• I/O compatibility
• Software support & other design services

Programmable Logic (PLDs, FPGAs)
• Pre-manufactured components with programmable interconnect
• Low Design Cost / Low NRE Cost / High Unit Cost
• Lower Performance
Medium Type Design, Combinational CLB – LUT, MUX, FF, I/Os, PI, DLL, Sequential
ADVANTAGES OF PROGRAMMABLE LOGICS
• Save Valuable Board Space

• Power Requirement is low
• Increases Performance
• Design Security
• Lower Standby and Switching Current
• Integration increases Design Reliability
• I/Os Delay Reduces
• Flexibility
• No NRC Cost
• Low Time to market
• Process Automation
• High Density ……… or Complex Design
How to Cope with Complexity ?
Electronic Design Automation (EDA)
• Computer Aided Design (CAD) …. Front - end
• Computer Aided Engineering (CAE) …. Back - end
Simulation –
H-Spice (Synopsis), Spector (Cadance), Spector RF, H-Sim (Synopsis for Digital), DA
(Design Architect Mentor), Co-Sim (Synopsis for Mixed), FineSim SPICE, Fine Wave (Megma)
Synthesis & Implementation - DC
(Synopsis), ISE (Xilinx), Quartus (Altera), Blast – Integrated RTL-to-GDSII Flow (Megma)
Timing Analysis & Verification –
Prime Time, Formality – (Synopsis), DRC & LVS (Magma), Modelsim – Mentor,
Physical Design – Astro, Layout – Vertuoso (Cadance), Magic, L-Edit
General Tool Flow for PLDs
VHDL or Verilog code

Design Entry LUT’s or Gates
Configurable
Device independent Flip-flop
Logic
Device type ,
Synthesis
Constraint
Configurable Transistor
Switch Matrix Switch Muxes
Gate Level circuit

Implementation
Device Type,
Constraints
Floor Planning
Configuration Volatile
User Constraint file Bit Stream Memory Non-volatile
www.ScientechWorld.com Software Download cable PLD Chip

VLSI Design Styles
Integrated Circuits
1 2 3
4
Semi-Custom Full-Custom
User System-On
ASICs ASICs
Programmable CHIP
FPGA PLD
Gates MUX LUT PAL PLA SPLD CPLD

(Look-Up Table)
2. Application-Specific Integrated Circuit (ASIC)
• Constrained design using pre-designed (and sometimes pre-

manufactured) components
• Also called semi-custom design
• Low Design Cost / High NRE Cost / Med. Unit Cost
• Medium Performance
Two competing implementation approaches
ASIC FPGA
Application Specific Field Programmable
Integrated Circuit Gate Array
• Designs must be sent

for expensive and time • Bought off the shelf
consuming fabrication and reconfigured by
in semiconductor foundry designers themselves
• No physical layout design;

• Designed all the way design ends with
from behavioral description a bitstream used
to physical layout to configure a device
Balance ……….
ASICs FPGAs
Off-the-shelf
High performance
Low development cost
Low power
Short time to market
Low cost in
high volumes Re-configurability
Which way to Go
FPGA = Field Programmable Gate Array

flexibility of software + speed of hardware design
ASIC = Application Specific Integrated Circuits

tailor-made on demand for specific applications
3. Full Custom Design
• Each circuit element carefully “handcrafted”

• NO use of any Library.
• Huge design effort.
• High Design & NRE Costs
• High Performance
• Typically used for high-volume applications
• Design Productivity is Very Low
4. System-on-a-chip (SOC)
• Idea: combine several large
blocks
– Predesigned custom cores
(e.g., microcontroller) -
“intellectual property” (IP)
– ASIC logic for special-purpose
hardware
– Programmable Logic (PLD,
FPGA)
– Analog
• Open issues
– Keeping design cost low
– Verifying correctness of
design
VLSI Design Flow & Tools
Front-end & Back-end
Front-end Back-end
• Logic design (RTL) • Floorplanning

• Simulation • Placement
Verification
• Synthesis • Routing
• Implementation • GDSII (final Output, Foundary)
Physical design vs. Building a City
• Microelectronic system • A City
• ASICs • Buildings
• System partitioning • City planner
• ASIC floorplanning • Architect
• Placement • Builder
• Routing • Electrician
Programmable Logic Vendors
 Xilinx - Xilinx Foundation Series.
 Altera - Max Plus – II
 Lattice - ISP Expert Compiler
 Actel - Actel’s Designer Series FPGA Development System
 Lucent - ORCA Foundry Development System
 Cypress - Warp2
 Atmel - FPGA Integrated Development System ( IDS )
 QuickLogic - QuickWorks
 Gatefield - ASIC master
XILINX Vs ALTRA
Design Flow, Tools and Files
• Key players: Xilinx, Altera, Lattice, Actel
• PLD market estimated at $57 billion and rapidly growing
• The goal is to expand the market:
– by lowering per-unit cost to attack the low-end market
– by increasing speed capabilities to attack the high-end market
www.ScientechWorld.com PLD market share

XILINX Vs ALETRA
Altera Xilinx
Cyclone Spartan
Stratix Virtex
Stratix Kintex
Max10 Artix
• Virtex and Stratix families are direct opponents, as are Spartan and Cyclone
FPGA Design Flow – Xilinx - ISE
•Schematic editor Design Entry Design Verification
•HDL (.v or .vhd)
Functional
Library
Simulation
Design
Text – (EDIF, XNF) Synthesis
XST + GUI = NGC UCF
Design
Implementation
Net list + Constraints *Translate
= NGD Static Timing
*Mapping Analysis
NCD – Native Circuit
Description *P & R Timing
VM6 -------- CPLD Simulation
*Fitting
*Bit stream
.BIT or .JED Generation
In Circuit
Download to Verification
Device
Xilinx Devices at a Glance
VertexII, 1.5V, 40000 to 10 Mil. Max System Gates
Feature Rich, High VertexE, 1.8V, 50000 to 3.2 Mil. Max System Gates
Density Vertex
Vertex, 2.5V, 50000 to 1 Mil. Max System Gates
As
FPG Spartan II E, 1.8V, 50000 to 300000 Max System Gates
Spartan II , 2.5V, 15000 to 200000 Max System Gates

Spartan
Low Cost Spartan XL, 3.3V, 5000 to 40000 Max System Gates
Spartan, 5V, 5000 to 40000 Max System Gates
XC2Cxxx, 1.8V, 32 to 512 Macrocells

Low Power, High Cool
XCR3000XL, 3.3V, 36 to 512 Macrocells
Speed, Low Cost Runner
LDs
XC9500XV, 2.5V, 36 to 288 Macrocells CP
XC9500
XC9500XL, 3.3V, 36 to 288 Macrocells
Low Cost
XC9500, 5V, 36 to 288 Macrocells
Altera Devices at a Glance
• Programmable Logic Families
– High & Medium Density FPGAs
• Stratix™ II, Stratix, APEX™ II,
APEX 20K, & FLEX® 10K
– Low-Cost FPGAs
• Cyclone™ & ACEX® 1K
– FPGAs with Clock Data Recovery

• Stratix GX & Mercury™
– CPLDs
• MAX® 7000 & MAX 3000
– Embedded Processor Solutions
• Nios™, ExcaliburT™
Compare Design Process ….
TTL Logic Programmable Logic
Truth Table
Design Description
Boolean Expression
Design Software
Implementation
Fuse Map
Logic minimization Cost and
Available
and multilevel performance
Inventory
logic optimization requirement Device
The Goal of IC Designer
 Meet the market requirement
 Satisfying the customers needs
- Beating the competition
- Increasing the functionality
- Reducing the cost
 Achieved by
- using the next generation Silicon Technologies
- new design concepts & tools
- high level integration

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VLSI

Diodes Area Speed

BJT – TTL,RTL, ECL FET

N MOS P MOS CMOS

Logic minimization Cost and

Boolean Eq. -> X = AB + CD + BD + BC + AD + AC OR X’ = A’B’C’ + A’B’D’ + A’C’D’ + B’C’D’

5. Examine Available Inventory

6. Eqn Re-written in NAND-

Boolean Eq. -> X = AB + CD + BD + BC + AD + AC --> 2 - 7408, 3 - 7432, 3 level of logic

“ Is the art of integrating millions of transistors on a Silicon Chip ”

The First Transistor

“ A device called a transistor, which has several applications

First point contact transistor (germanium), 1947

 Transistors High complexity or small Area

 Gates Low Power Dissipation

 ICs Integrated Circuits Low Cost

IC is a collection of Electronic Circuits made by simultaneously forming individual

Integration Level Year Number of Transistors

SSI - Individual Gates 1950s Less than 10^2

MSI - Counter, Shift Reg. 1960s 10^2 – 10^3

LSI - Small Logic Function 1970s 10^3 – 10^5

VLSI - Large Logic Function 1980s 10^5 – 10^7

1990s 10^7 – 10^9

2000s Over 10^9

In 1965, Intel co-founder

Clock Frequency – Clock Frequency doubles every 2.168 Yrs

Features Size – Gate Length is divided by 2 every 5.43 Yrs

n substrate S sub strate connected

Chip size: µP (mm2) 340 430 901

 Power Consumption, Clock frequency, Supply Voltage are related as follows :-

Capacitance Supply Voltage Clock Frequency

• Large Scale Integration -

Size ….. <<<

• Integration reduce manufacturing costs

User Semi-Custom Full-Custom System-On

PAL PLA SPLD CPLD Gates MUX LUT

1. Programmable Logic (PLD, FPGA)

2. Application-Specific Integrated Circuit (ASIC)

PAL PLA SPLD CPLD Gates MUX LUT

• Pre-manufactured components with programmable interconnect

• CAD tools greatly reduce design effort

• Low Design Cost

• Low NRE Cost

• High Unit Cost

• Lower Performance as compared to ASIC better than General digital design

Standard Logic Circuits Programmable Logic Circuits

• PLA - Programmable Logic Arrays

 Complex Programmable Logic Devices (CPLD) are another way to extend

 CPLDs are great at handling wide and complex gating at blistering

Complex Programmable Logic Devices

 Lower Development Costs

 More Product Revenue

 Reduced Board Area

• FPGAs comprise an array of uncommited circuit elements,

• Reasonably Cheap at low volume

– Much lower clock frequency

– Less dense layout and placement and slower operation due to

• Overhead of configurable interconnect and logic blocks

• Need sophisticated tools to map design to FPGA

• Software support & other design services

• Save Valuable Board Space

VHDL or Verilog code

Gate Level circuit