Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
Experiment # 09
______________________
Course Instructor / Lab Engineer
Objective: To Design a Small Signal Self Biased Common Emitter BJT Amplifier
Apparatus:
DC power supply, Oscilloscope, Function Generator, Multimeter, Breadboard, NPN transistor, Resistor
Circuit
Diagram: +VCC
RB RC
Cou
Cin
RL
RE
AC v
Theory:
A self biased common emitter amplifier can provide both voltage and current gain at output and is stable versus variations
in temperature compared to its fixed biased counterpart.
Voltage drop across emitter resistor is given to be between 10-15% of power supply voltage; following equation can be used
to design RE:
Stage voltage gain is calculated by taking into account unloaded voltage gain i.e. and the loading effect on both
input and output sides:
Similarly, Stage current gain is calculated by taking into account unloaded current gain i.e. and loading effect on both input
and output sides:
Procedure:
Design values of resistors using the expressions given in theory, following is the given data:
VCC=+ 15V, VCE=VCC/2, IC= 10mA, β=100, VE=0.1VCC, rs=50Ω, RL=1kΩ
Compare measured and calculated stage voltage gain and calculate percentage error
Observations:
V VL Av Ai
s s s
Calculated Measured %age Error Calculated Measured %age Error
500mV +4.18 -0.68 8.36e-9 71.5 -0.78 +0.18 0.7*10-3
1V +4.13 -0.68 4.16 11.4 -0.78 +0.20 0.8*10-4
1.5V +4.16 -0.68 2.78 106.5 -0.78 +0.36 0.3*10-3
2V +4.43 -0.68 2.219 10.7 -0.78 +0.18 1.4*10-4
2.5V +4.8 -0.68 1.78 9.0 -0.78 -0.19 1.3*10-3
3V +2.25 -0.68 1.79 10.78 -0.78 -0.32 0.4*10-2
Conclusion/ Comments:
In this experiment we learnt to draw the Small Signal Self Biased Common Emitter on proteus and to
find the VL, Vas, and Vis.