1 2 3 4 5 6

Ultra96 SBC V2
COAVNET0LOGO1
Avnet Engineering Services

www.avnet.me/ultra96-v2

Sheet Name

01 - Avnet Lead Sheet

A A
02 - Block Diagram

03 - Bank 500, Bank 501, Bank 502, Bank 503

04 - Bank 504, Bank 505

05 - SD Card, RADIO

06 - USB 3.0 MicroAB

07 - USB2.0 Downstream Device & Clock Gen

08 - Bank 0, Bank 26, Bank 65, Bank 66

09 - Switches, LEDs, JTAG

10 - Bank Power and Decoupling

11 - LPDDR4 Device

12 - USB 3.0 Dual Port Hub

13 - Jx_Jy Expansion Headers, Power On

B 14 - Display Port

15 - Rocky PMIC #1

16 - Rocky PMIC #2
Ultra96 SBC V2 B

17 - Manhattan PMIC #3

18 - Back Page
(AES-ULTRA96-V2-G)
Revision

C C

https://www.96boards.org/products/ce/

Copyright 2019, Avnet, Inc. All Rights Reserved.

This material may not be reproduced, distributed, republished, displayed, posted, transmitted or copied in any form or by any means without the prior written
permission of Avnet, Inc. AVNET and the AVNET logo are registered trademarks of Avnet, Inc. All trademarks and trade names are the properties of their
respective owners and Avnet, Inc. disclaims any proprietary interest or right in trademarks, service marks and trade names other than its own.
D Avnet is not responsible for typographical or other errors or omissions or for direct, indirect, incidental or consequential damages related to this material or D
resulting from its use. Avnet makes no warranty or representation respecting this material, which is provided on an "AS IS" basis. AVNET HEREBY
DISCLAIMS ALL WARRANTIES OR LIABILITY OF ANY KIND WITH RESPECT THERETO, INCLUDING, WITHOUT LIMITATION, REPRESENTATIONS
REGARDING ACCURACY AND COMPLETENESS, ALL IMPLIED WARRANTIES AND CONDITIONS OF MERCHANTABILITY, SUITABILITY OR FITNESS Avnet Engineering Services
FOR A PARTICULAR PURPOSE, TITLE AND/OR NON-INFRINGEMENT. This material is not designed, intended or authorized for use in medical, life Project Name: PCB Rev: BOM: Variant:
support, life sustaining or nuclear applications or applications in which the failure of the product could result in personal injury, death or property damage.
Any party using or selling products for use in any such applications do so at their sole risk and agree that Avnet is not liable, in whole or in part, for any
Ultra96 SBC V2
Doc Num: Date:
1 Time: 01 00
claim or damage arising from such use, and agree to fully indemnify, defend and hold harmless Avnet from and against any and all claims, damages, loss, SCH-US1SBC 3/1/2019 7:57:25 AM
cost, expense or liability arising out of or in connection with the use or performance of products in such applications. Sheet Title: Size: Sheet:
Note1 01 - Avnet Lead Sheet.SchDoc B 1 of 18
1 2 3 4 5 6
 1 2 3 4 5 6

A A

B B

C C

D D

Avnet Engineering Services

Project Name: PCB Rev: BOM: Variant:
Ultra96 SBC V2
Doc Num: Date:
1 Time: 01 00
SCH-US1SBC 3/1/2019 7:57:25 AM
Sheet Title: Size: Sheet:
02 - Block Diagram.SchDoc B 2 of 18
1 2 3 4 5 6
 1 2 3 4 5 6

BANK 500, BANK 501, BANK 502, BANK 503

BANK 500 BANK 501 BANK 502
COU1E
COU1F
COU1G
COU1H
U1E U1F U1G
A BANK 500 BANK 501 BANK 502 A
Y6 POMIO250VBUS0DET C13 POMIO510SD10CLK B18 POMIO770PWR0ALERT0N
PS_MIO25 PIU10Y6 MIO25_VBUS_DET 12[1D], 7[3B] PS_MIO51 PIU10C13 MIO51_SD1_CLK 5[2B] PS_MIO77 PIU10B18 MIO77_PWR_ALERT_N 15[2C], 16[1C], 17[2C]
AB6 A13 POMIO500SD10CMD F18
PS_MIO24 PIU10AB6 POMIO240SD00DETECT
MIO24_SD0_DETECT 5[3D] PS_MIO50 PIU10A13
D13
MIO50_SD1_CMD 5[2B] PS_MIO76 PIU10F18 POMIO760WLAN0IRQ
MIO76_WLAN_IRQ 5[4A]
AB5
PIU10AB5 POMIO230GPIO0PB PS_MIO49 PIU10D13 POMIO490SD10D3
MIO49_SD1_D3 5[2B] B17
PIU10B17 POMIO750USB10DATA7
PS_MIO23 COR1 MIO23_GPIO_PB 9[1A] A12 PS_MIO75 MIO75_USB1_DATA7 7[1B]
AA6
PIU10AA6 R1
PIR101 30.1
PIR102 POMIO220SD00CLK PS_MIO48 PIU10A12 POMIO480SD10D2
MIO48_SD1_D2 5[2B] D18
PIU10D18 POMIO740USB10DATA6
PS_MIO22 COR2 MIO22_SD0_CLK 5[2D] B12 PS_MIO74 MIO74_USB1_DATA6 7[1B]
W6
PIU10W6 R2
PIR201 30.1
PIR202 POMIO210SD00CMD PS_MIO47 PIU10B12 POMIO470SD10D1
MIO47_SD1_D1 5[2B] D17
PIU10D17 POMIO730USB10DATA5
PS_MIO21 MIO21_SD0_CMD 5[2D] C12 PS_MIO73 MIO73_USB1_DATA5 7[1B]
AB4
PIU10AB4 POMIO200PS0LED0 PS_MIO46 PIU10C12 POMIO460SD10D0
MIO46_SD1_D0 5[2B] C17
PIU10C17 POMIO720USB10DATA4
PS_MIO20 MIO20_PS_LED0 9[3B] A11 PS_MIO72 MIO72_USB1_DATA4 7[1B]
AA4 POMIO190PS0LED1 PS_MIO45 PIU10A11 POMIO450PS0GPIO105
MIO45_PS_GPIO1_5 13[5B] F17 POMIO710USB10DATA3
PS_MIO19 PIU10AA4 MIO19_PS_LED1 9[4B] B11 PS_MIO71 PIU10F17 MIO71_USB1_DATA3 7[1B]
Y5
PIU10Y5 POMIO180PS0LED2 PS_MIO44 PIU10B11 POMIO440PS0GPIO104
MIO44_PS_GPIO1_4 13[4B] A17
PIU10A17 POMIO700USB10STP
PS_MIO18 MIO18_PS_LED2 9[3C] E13 PS_MIO70 MIO70_USB1_STP 7[2B]
AA3
PIU10AA3 POMIO170PS0LED3 PS_MIO43 PIU10E13 POMIO430SPI00MOSI
MIO43_SPI0_MOSI 13[5A] A16
PIU10A16 POMIO690USB10DATA1
PS_MIO17 COR3 MIO17_PS_LED3 9[4C] D12 PS_MIO69 MIO69_USB1_DATA1 7[1B]
Y3
PIU10Y3 R3
PIR301 30.1
PIR302 POMIO160SD00DAT3 PS_MIO42 PIU10D12 POMIO420SPI00MISO
MIO42_SPI0_MISO 13[5A] B16
PIU10B16 POMIO680USB10DATA0
PS_MIO16 COR4 MIO16_SD0_DAT3 5[2C] B10 PS_MIO68 MIO68_USB1_DATA0 7[1B]
Y4
PIU10Y4 R4
PIR401 30.1
PIR402 POMIO150SD00DAT2 PS_MIO41 PIU10B10 POMIO410SPI00CS
MIO41_SPI0_CS 13[5A] G17
PIU10G17 POMIO670USB10NXT
PS_MIO15 MIO15_SD0_DAT2 5[2C] PS_MIO67 MIO67_USB1_NXT 7[2B]
PS_MIO14
W5
PIU10W5
COR5
R5
PIR501 30.1
PIR502 POMIO140SD00DAT1
MIO14_SD0_DAT1 5[2C] PS_MIO40
D11
PIU10D11 POMIO400PS0GPIO103
MIO40_PS_GPIO1_3 13[5B] PS_MIO66
D16
PIU10D16 POMIO660USB10DATA2
MIO66_USB1_DATA2 7[1B]
W3 COR6
R6 30.1 POMIO130SD00DAT0 C10
PIU10C10 POMIO390PS0GPIO102 B15 POMIO650USB10DIR
PS_MIO13 PIU10W3 PIR601 PIR602 MIO13_SD0_DAT0 5[2C] PS_MIO39 MIO39_PS_GPIO1_2 13[4B] PS_MIO65 PIU10B15 MIO65_USB1_DIR 7[2B]
AB2 C9
PIU10C9 POMIO380SPI00SCLK E16
PS_MIO12 PIU10AB2 POMIO120I2C0MUX0RESET0N
MIO12_I2C_MUX_RESET_N 13[4D] PS_MIO38 MIO38_SPI0_SCLK 13[5A] PS_MIO64 PIU10E16 POMIO640USB10CLK
MIO64_USB1_CLK 7[2B]
W2 POMIO110SPI10MOSI E11 POMIO370PS0GPIO101 F16 POMIO630USB00DATA7
PS_MIO11 PIU10W2 MIO11_SPI1_MOSI 13[1A] PS_MIO37 PIU10E11 MIO37_PS_GPIO1_1 13[5B] PS_MIO63 PIU10F16 MIO63_USB0_DATA7 6[1B]
AA2 POMIO100SPI10MISO D10 POMIO360PS0GPIO100 C15 POMIO620USB00DATA6
PS_MIO10 PIU10AA2 MIO10_SPI1_MISO 13[1A] PS_MIO36 PIU10D10 MIO36_PS_GPIO1_0 13[4B] PS_MIO62 PIU10C15 MIO62_USB0_DATA6 6[1B]
V5 E10 NLMIO35
MIO35 CONT11
NT11 PITP101 COTP1 G16
PS_MIO9 PIU10V5 POMIO90SPI10CS
MIO9_SPI1_CS 13[1A] PS_MIO35 PIU10E10
F13
PINT1101
PINT1102
TP1 PS_MIO61 PIU10G16 POMIO610USB00DATA5
MIO61_USB0_DATA5 6[1B]
V3 POMIO80RADIO0EN PS_MIO34 PIU10F13 POMIO340POWER0KILL0N
MIO34_POWER_KILL_N 13[4C] D15 POMIO600USB00DATA4
PS_MIO8 PIU10V3 MIO8_RADIO_EN 5[2A] E9 NLMIO33 CONT12 PS_MIO60 PIU10D15 MIO60_USB0_DATA4 6[1B]
V4
PIU10V4 POMIO70RAD0RST0N PS_MIO33 PIU10E9 MIO33 PINT1201 NT12 PITP201
PINT1202 COTP2
TP2 E15
PIU10E15 POMIO590USB00DATA3
PS_MIO7 MIO7_RAD_RST_N 8[3D] F12 NLMIO32 CONT13 PS_MIO59 MIO59_USB0_DATA3 6[1B]
Y1
PIU10Y1 POMIO60SPI10SCLK PS_MIO32 PIU10F12MIO32 PINT1301 NT13 PITP301
PINT1302 COTP3
TP3 A14
PIU10A14 POMIO580USB00STP
PS_MIO6 MIO6_SPI1_SCLK 13[1A] F11 PS_MIO58 MIO58_USB0_STP 6[3B]
AA1
PIU10AA1 POMIO50I2C10SDA PS_MIO31 PIU10F11 POMIO310MHTN0ALRT
MIO31_MHTN_ALRT 17[2C] B14
PIU10B14 POMIO570USB00DATA1
PS_MIO5 MIO5_I2C1_SDA 13[4C] G10 PS_MIO57 MIO57_USB0_DATA1 6[1B]
U6 POMIO40I2C10SCL PS_MIO30 PIU10G10 POMIO300DP0AUX0IN
MIO30_DP_AUX_IN 14[1C] E14 POMIO560USB00DATA0
PS_MIO4 PIU10U6 MIO4_I2C1_SCL 13[4C] F9 PS_MIO56 PIU10E14 MIO56_USB0_DATA0 6[1B]
U5 POMIO30UART00TX0BT0HCI0RX PS_MIO29 PIU10F9 POMIO290DP0OE
MIO29_DP_OE 14[1C] C14 POMIO550USB00NXT
PS_MIO3 PIU10U5 MIO3_UART0_TX_BT_HCI_RX 5[2A] G12 PS_MIO55 PIU10C14 MIO55_USB0_NXT 6[3B]
V2
PIU10V2 POMIO20UART00RX0BT0HCI0TX PS_MIO28 PIU10G12 POMIO280DP0HPD
MIO28_DP_HPD 14[1C] G15
PIU10G15 POMIO540USB00DATA2
B PS_MIO2 MIO2_UART0_RX_BT_HCI_TX 5[2A] G11 PS_MIO54 MIO54_USB0_DATA2 6[1B] B
W1
PIU10W1 MIO1_UART1_RX PS_MIO27 PIU10G11 POMIO270DP0AUX0OUT
MIO27_DP_AUX_OUT 14[1B] F14
PIU10F14 POMIO530USB00DIR
PS_MIO1 G9 PS_MIO53 MIO53_USB0_DIR 6[3B]
U4
PIU10U4 MIO0_UART1_TX PS_MIO26 PIU10G9 POMIO260PWR0INT
MIO26_PWR_INT 13[6C] G14
PIU10G14 POMIO520USB00CLK
PS_MIO0 PS_MIO52 MIO52_USB0_CLK 6[3B]
XCZU3EG-1SBVA484I XCZU3EG-1SBVA484I COR7
R7 4.75K XCZU3EG-1SBVA484I
PIR702 PIR701 +VCC_PSAUX

OFF BOARD UART & XNSLTR

+VCC_PSAUX +3.3V

COR8
R8
PIR801 PIR802 PIR901
4 PIN HDR BOARD ID STRAPPING OPTIONS
10.00K
PIQ10 COQ1 COR9
R9
(Refer to User's Guide for information)
1

Q1 10.00K COJ1
J1
G

NLMIO10UART10RX
MIO1_UART1_RX PIR902 1
2

PIQ102 PIQ103 PIJ101

+VCC_PSAUX +VCC_PSAUX +VCC_PSAUX
S

2
PIJ102 COJT7
JT7 COJT8
JT8 COJT9
JT9
BSS138-7-F 3
PIJ103
COR10
0
4 3
PIJT703 3
PIJT803 3
PIJT903
R10
PIR1001
DNP
PIR1002 PIJ104
BANK 503
GND MMT-104-01-T-SH-LC
COJT1
JT1 0 U1H 2
MIO35 PIJT702 2
MIO33 PIJT802 2
MIO32 PIJT902
1
PIJT101
BANK 503
+3.3V L12
PS_DONE PIU10L12 POPS0DONE
PS_DONE 9[5B] 1 1 1
K16 NLPS0ERR0OUT
PIU10K16 PS_ERR_OUT PITP401 COTP4
TP4 PIJT701 PIJT801 PIJT901
C PS_ERROR_OUT C
2 K18 NLPS0ERR0STAT
PS_ERR_STAT COTP5
+VCC_PSAUX +3.3V PIJT102 PS_ERROR_STATUS PIU10K18 PITP501 TP5 10K (1-2) 10K (1-2) 10K (1-2)
K15 POPS0INIT0N
PS_INIT_B PIU10K15 PS_INIT_N 9[5B] GND GND GND
COR11
R11 PS_JTAG_TCK
H13
PIU10H13 POJTAG0TCK
JTAG_TCK 9[2A]
PIR1101 PIR1102 PIR1201 3 PS_JTAG_TDI
H12
PIU10H12 POJTAG0TDI
JTAG_TDI 9[2B]
10.00K +VCC_PSAUX
PIQ201 COQ2 COR12
R12
PIJT103
PS_JTAG_TDO
J13
PIU10J13 POJTAG0TDO
JTAG_TDO 9[2B]
1

Q2 10.00K J12
G

Default: Pin 1-2: 0 ohm PS_JTAG_TMS PIU10J12 POJTAG0TMS

JTAG_TMS 9[2A]
NLMIO00UART10TX
MIO0_UART1_TX PIR1202 J16 CONT10
NT10
2

PIQ202 PIQ203 PS_MODE0 PIU10J16 POPS0MODE0

PS_MODE0 9[1C]
S

H15 PINT1001
PINT1002

BSS138-7-F
PS_MODE1
PS_MODE2
PIU10H15
J15
PIU10J15
POPS0MODE1
PS_MODE1
POPS0MODE2
PS_MODE2
6[1D]
9[1C]
32KHz RTC XTAL
COR14
R14
0 H18 NLPS0MODE3
PIU10H18 PS_MODE3
PIR1401 PIR1402 PS_MODE3
H17 NLPS0PAD0IN
PIU10H17 PS_PAD_IN COX1
X1
DNP PS_PADI NLPS0PAD0OUT
J17
PIU10J17 PS_PAD_OUT PS_PAD_IN 2 1 PS_PAD_OUT
PS_PADO PIX102 PIX101
PS_POR_B
K12
PIU10K12 POPOWER0GOOD
POWER_GOOD 13[5A], 15[2C], 16[1C], 17[2B], 6[1D], 9[1B] PIC102 PIC202
K14 NLPS0PROG0N
PIU10K14 PS_PROG_N COC1
C1 32.768kHz COC2
C2
PS_PROG_B
H14
PIU10H14 POPS0REF0CLK PIC101 27pF PIC201 27pF
PS_REF_CLK
K13
PS_REF_CLK 7[5B] COR13
R13
PIR1302 4.7M
PIR1301
PS_SRST_B PIU10K13 POPS0SRST0N
PS_SRST_N 9[2B]
XCZU3EG-1SBVA484I
GND GND
PS_MODE3 COR15
R15
PIR1501 4.75K
PIR1502

GND
COR16
R16 4.75K PS_PROG_N
+VCC_PSAUX PIR1601 PIR1602
D D

Avnet Engineering Services

Project Name: PCB Rev: BOM: Variant:
Ultra96 SBC V2
Doc Num: Date:
1 Time: 01 00
SCH-US1SBC 3/1/2019 7:57:25 AM
Sheet Title: Size: Sheet:
B
03 - Bank 500, Bank 501, Bank 502, Bank 503.SchDoc 3 of 18
1 2 3 4 5 6
 1 2 3 4 5 6

BANK 504, BANK 505

A A

BANK 504 - DDR BANK 504 - DDR

BANK 505 - GTR
COU1I
COU1J
COU1K
U1I U1J U1K
BANK 504 BANK 504 BANK 505
POPS0DDR0CAA0 AA22 POPS0DDR0DQ13 AA14
PIU10AA14 M22
PIU10M22
11[2B] PS_DDR_CAA0 PIU10AA22
PS_DDR_A0 11[5B] PS_DDR_DQ13 PS_DDR_DQ13 PS_MGTRRXN0_505
POPS0DDR0CAA1 AB20 POPS0DDR0DQ14 Y15 H22
11[2B] PS_DDR_CAA1 PIU10AB20 PS_DDR_A1 11[5B] PS_DDR_DQ14 PIU10Y15 PS_DDR_DQ14 PIU10H22 PS_MGTRRXN1_505
POPS0DDR0CAB0 Y21 POPS0DDR0DQ15 AB15 POGTR0LANE20RX0N D22
11[2B] PS_DDR_CAB0 PIU10Y21 PS_DDR_A10 11[5B] PS_DDR_DQ15 PIU10AB15 PS_DDR_DQ15 6[4B] GTR_LANE2_RX_N PIU10D22 PS_MGTRRXN2_505
AA21 POPS0DDR0DQ16 W8 POGTR0LANE30RX0N B22
POPS0DDR0CAB1
11[2B] PS_DDR_CAB1 PIU10AA21 PS_DDR_A11 11[5A] PS_DDR_DQ16 PIU10W8
W7
PS_DDR_DQ16 12[1B] GTR_LANE3_RX_N PIU10B22
M21
PS_MGTRRXN3_505
POPS0DDR0CAB2 AA18
PIU10AA18 POPS0DDR0DQ17
11[5B] PS_DDR_DQ17 PIU10W7 PS_DDR_DQ17 PIU10M21 PS_MGTRRXP0_505
11[2B] PS_DDR_CAB2 PS_DDR_A12 V7 H21
POPS0DDR0CAB3 AA19
PIU10AA19 POPS0DDR0DQ18
11[5B] PS_DDR_DQ18 PIU10V7 PS_DDR_DQ18 PIU10H21 PS_MGTRRXP1_505
11[2B] PS_DDR_CAB3 PS_DDR_A13 V10 D21
POPS0DDR0CAB4 AA17
PIU10AA17 POPS0DDR0DQ19
11[5B] PS_DDR_DQ19 PIU10V10 PS_DDR_DQ19 POGTR0LANE20RX0P
6[4B] GTR_LANE2_RX_P PIU10D21 PS_MGTRRXP2_505
11[2B] PS_DDR_CAB4 PS_DDR_A14 AB10 B21
POPS0DDR0CAB5 AA16 POPS0DDR0DQ2
11[5B] PS_DDR_DQ2 PIU10AB10 PS_DDR_DQ2 POGTR0LANE30RX0P
12[1B] GTR_LANE3_RX_P PIU10B21 PS_MGTRRXP3_505
11[2B] PS_DDR_CAB5 PIU10AA16 PS_DDR_A15 U7 K22
Y16 POPS0DDR0DQ20
11[5B] PS_DDR_DQ20 PIU10U7
PS_DDR_DQ20 POGTR0LANE00TX0N
14[4B] GTR_LANE0_TX_N PIU10K22
PS_MGTRTXN0_505
PIU10Y16 PS_DDR_A16 T9 F22
W16
PIU10W16 POPS0DDR0DQ21
11[5B] PS_DDR_DQ21 PIU10T9 PS_DDR_DQ21 POGTR0LANE10TX0N
14[4B] GTR_LANE1_TX_N PIU10F22 PS_MGTRTXN1_505
PS_DDR_A17 U10 C20
POPS0DDR0CAA2 AB17
PIU10AB17 POPS0DDR0DQ22
11[5B] PS_DDR_DQ22 PIU10U10 PS_DDR_DQ22 POGTR0LANE20TX0N
6[4B] GTR_LANE2_TX_N PIU10C20 PS_MGTRTXN2_505
11[2B] PS_DDR_CAA2 PS_DDR_A2 T10 A20
POPS0DDR0CAA3 AB19
PIU10AB19 POPS0DDR0DQ23
11[5C] PS_DDR_DQ23 PIU10T10 PS_DDR_DQ23 POGTR0LANE30TX0N
12[1B] GTR_LANE3_TX_N PIU10A20 PS_MGTRTXN3_505
11[2B] PS_DDR_CAA3 PS_DDR_A3 U11 K21
POPS0DDR0CAA4 AB21
PIU10AB21 POPS0DDR0DQ24
11[5C] PS_DDR_DQ24 PIU10U11 PS_DDR_DQ24 POGTR0LANE00TX0P
14[4B] GTR_LANE0_TX_P PIU10K21 PS_MGTRTXP0_505
11[2B] PS_DDR_CAA4 PS_DDR_A4 U12 F21
POPS0DDR0CAA5 AB16 POPS0DDR0DQ25
11[5C] PS_DDR_DQ25 PIU10U12
PS_DDR_DQ25 POGTR0LANE10TX0P
14[4B] GTR_LANE1_TX_P PIU10F21
PS_MGTRTXP1_505
11[2B] PS_DDR_CAA5 PIU10AB16 PS_DDR_A5 W12 C19
Y20
PIU10Y20 POPS0DDR0DQ26
11[5B] PS_DDR_DQ26 PIU10W12
PS_DDR_DQ26 POGTR0LANE20TX0P
6[4B] GTR_LANE2_TX_P PIU10C19
PS_MGTRTXP2_505
PS_DDR_A6 W11 A19
Y19
PIU10Y19 POPS0DDR0DQ27
11[5B] PS_DDR_DQ27 PIU10W11 PS_DDR_DQ27 POGTR0LANE30TX0P
12[1B] GTR_LANE3_TX_P PIU10A19 PS_MGTRTXP3_505
PS_DDR_A7 V14 COC10 L20
NLU26M0N PIU10L20
W17
PIU10W17 POPS0DDR0DQ28
11[5B] PS_DDR_DQ28 PIU10V14 PS_DDR_DQ28 POGTR0CLK00USB026M0N
7[5B] GTR_CLK0_USB_26M_N C10
PIC1002 PIC1001 U26M_N
PS_MGTREFCLK0N_505
PS_DDR_A8 U14 0.1uF NLU26M0P L19
B Y18
PIU10Y18 POPS0DDR0DQ29
11[5B] PS_DDR_DQ29 PIU10U14 PS_DDR_DQ29 POGTR0CLK00USB026M0P
7[5B] GTR_CLK0_USB_26M_P PIC1102 PIC1101 U26M_P PIU10L19
PS_MGTREFCLK0P_505 B
PS_DDR_A9 W10 COC12 COC11 0.1uF
C11 NLU27M0N PIU10J20
J20
U15 POPS0DDR0DQ3
11[5B] PS_DDR_DQ3 PIU10W10 PS_DDR_DQ3 POGTR0CLK10DP027M0N
7[5B] GTR_CLK1_DP_27M_N C12
PIC1202 PIC1201 U27M_N
PS_MGTREFCLK1N_505
PIU10U15 PS_DDR_ACT_N W15 0.1uFPIC1302 PIC1301 J19
NLU27M0P PIU10J19
T21 POPS0DDR0DQ30
11[5B] PS_DDR_DQ30 PIU10W15
PS_DDR_DQ30 POGTR0CLK10DP027M0P
7[5B] GTR_CLK1_DP_27M_P U27M_P
PS_MGTREFCLK1P_505
PIU10T21 PS_DDR_ALERT_N V15 COC13
C13 0.1uF G20
U17
PIU10U17 POPS0DDR0DQ31
11[5B] PS_DDR_DQ31 PIU10V15 PS_DDR_DQ31 PIU10G20 PS_MGTREFCLK2N_505
PS_DDR_BA0 AA8 G19
V17
PIU10V17 POPS0DDR0DQ4
11[5B] PS_DDR_DQ4 PIU10AA8 PS_DDR_DQ4 PIU10G19 PS_MGTREFCLK2P_505
PS_DDR_BA1 Y8 E20
U16
PIU10U16 POPS0DDR0DQ5
11[5B] PS_DDR_DQ5 PIU10Y8 PS_DDR_DQ5 PIU10E20 PS_MGTREFCLK3N_505
PS_DDR_BG0 AB7 E19
W18 POPS0DDR0DQ6
11[5B] PS_DDR_DQ6 PIU10AB7 PS_DDR_DQ6 LAYOUT NOTE: Pair PIU10E19 PS_MGTREFCLK3P_505
PIU10W18 PS_DDR_BG1 T22 M20
POPS0DDR0CKA0T V20 PIU10T22
PS_DDR_DQ64 differential routing to PIU10M20
PS_MGTRREF_505
11[2B] PS_DDR_CKA_T PIU10V20 PS_DDR_CK0 P22
POPS0DDR0CKB0T V18
PIU10V18 PIU10P22 PS_DDR_DQ65 appropriate name.
11[2C] PS_DDR_CKB_T PS_DDR_CK1 R21 PIR2 02 XCZU3EG-1SBVA484I
POPS0DDR0CKE0 U22
PIU10U22 PIU10R21 PS_DDR_DQ66
11[2B], 11[2C] PS_DDR_CKE0 PS_DDR_CKE0 P21 COR22
R22
POPS0DDR0CKE1 U21
PIU10U21 PIU10P21 PS_DDR_DQ67
11[5C] PS_DDR_CKE1 PS_DDR_CKE1 R18 500, 0.1%
POPS0DDR0CKA0C W20 PIU10R18 PS_DDR_DQ68 LAYOUT NOTE:
11[2B] PS_DDR_CKA_C PIU10W20 PS_DDR_CK_N0 P18 PIR2 01
POPS0DDR0CKB0C V19 PIU10P18
PS_DDR_DQ69 Place 500 ohm
11[2B] PS_DDR_CKB_C PIU10V19 PS_DDR_CK_N1 AA7
POPS0DDR0CS00N V22
PIU10V22 POPS0DDR0DQ7
11[5B] PS_DDR_DQ7 PIU10AA7 PS_DDR_DQ7 resistor close to
11[2B], 11[2C] PS_DDR_CS0_N PS_DDR_CS_N0 N18
POPS0DDR0CS10N U20
PIU10U20 PIU10N18 PS_DDR_DQ70 SoC.
11[5C] PS_DDR_CS1_N PS_DDR_CS_N1 N19
POPS0DDR0DMA0 AB9
PIU10AB9 PIU10N19 PS_DDR_DQ71
11[2B] PS_DDR_DMA0 PS_DDR_DM0 AA11 GND
POPS0DDR0DMA1 AB14 POPS0DDR0DQ8
11[5C] PS_DDR_DQ8 PIU10AA11 PS_DDR_DQ8
11[2B] PS_DDR_DMA1 PIU10AB14 PS_DDR_DM1 Y11
POPS0DDR0DMB0 U9 POPS0DDR0DQ9
11[5C] PS_DDR_DQ9 PIU10Y11
PS_DDR_DQ9
11[2C] PS_DDR_DMB0 PIU10U9 PS_DDR_DM2 AA9
POPS0DDR0DMB1 W13
PIU10W13 POPS0DDR0DQSA00C
11[5C] PS_DDR_DQSA0_C PIU10AA9 PS_DDR_DQS_N0
11[2C] PS_DDR_DMB1 PS_DDR_DM3 AA13
R19
PIU10R19 POPS0DDR0DQSA10C
11[5C] PS_DDR_DQSA1_C PIU10AA13 PS_DDR_DQS_N1
PS_DDR_DM8 V8
POPS0DDR0DQ0 AB11
PIU10AB11 POPS0DDR0DQSB00C
11[5C] PS_DDR_DQSB0_C PIU10V8 PS_DDR_DQS_N2
11[5A] PS_DDR_DQ0 PS_DDR_DQ0 V13
POPS0DDR0DQ1 Y10 POPS0DDR0DQSB10C
11[5C] PS_DDR_DQSB1_C PIU10V13 PS_DDR_DQS_N3
11[5B] PS_DDR_DQ1 PIU10Y10 PS_DDR_DQ1 R20
POPS0DDR0DQ10 AA12 PIU10R20
PS_DDR_DQS_N8
11[5B] PS_DDR_DQ10 PIU10AA12 PS_DDR_DQ10 Y9
POPS0DDR0DQ11 AB12
PIU10AB12 POPS0DDR0DQSA00T
11[5C] PS_DDR_DQSA0_T PIU10Y9 PS_DDR_DQS_P0
11[5B] PS_DDR_DQ11 PS_DDR_DQ11 Y13
POPS0DDR0DQ12 Y14
PIU10Y14 POPS0DDR0DQSA10T
11[5C] PS_DDR_DQSA1_T PIU10Y13 PS_DDR_DQS_P1
C 11[5B] PS_DDR_DQ12 PS_DDR_DQ12 V9 C
POPS0DDR0DQSB00T
11[5C] PS_DDR_DQSB0_T PIU10V9 PS_DDR_DQS_P2
XCZU3EG-1SBVA484I POPS0DDR0DQSB10T V12
11[5C] PS_DDR_DQSB1_T PIU10V12 PS_DDR_DQS_P3
P20
PIU10P20
PS_DDR_DQS_P8
W22
PIU10W22 PS_DDR_ODT0
W21
PIU10W21 PS_DDR_ODT1
U19
PIU10U19 PS_DDR_PARITY
POPS0DDR0RST0N T18
11[2D] PS_DDR_RST_N PIU10T18 PS_DDR_RAM_RST_N
T19
PIU10T19 PS_DDR_ZQ
PIR2302 XCZU3EG-1SBVA484I
COR23
R23
240
PIR2301 LAYOUT NOTE:
Place ZQ resistor
close to SoC.
GND

D D

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Project Name: PCB Rev: BOM: Variant:
Ultra96 SBC V2
Doc Num: Date:
1 Time: 01 00
SCH-US1SBC 3/1/2019 7:57:25 AM
Sheet Title: Size: Sheet:
04 - Bank 504, BANK 505.SchDoc B 4 of 18
1 2 3 4 5 6
 1 2 3 4 5 6

SD CARD, ATWILC3000 WiFi & BT RADIO

RADIO: BLUETOOTH, WiFi (SDIO Mode)
+VCC_PSAUX +3.3V
COR17
R17 1M
A GND PIR1702 PIR1701
COC3 A
COC4 C3
PIC301 PIC302
POMIO70RADIO0RST0N C4
8[3D] MIO7_RADIO_RST_N GND PIC402 PIC401 0.1uF
POMIO80RADIO0EN
3[2B] MIO8_RADIO_EN COU2
U2 1uF COC5
C5
PIC502 PIC501
12
PIU2012
10uF
VDDIO
18
PIU2018
COTP6 VBAT
TP6 COTP7
TP7 COTP8
TP8 COTP9
TP9 GND
7 33 POMIO760WLAN0IRQ
PIU207 RESETN IRQN PIU2033 MIO76_WLAN_IRQ 3[6A]
19
PIU2019 CHIP_EN
PITP601 PITP701 PITP801 PITP901 20
RADIO_CLKPIU2020
RTC_CLK
POMIO20UART00RX0BT0HCI0TX 8
PIU208
3[2B] MIO2_UART0_RX_BT_HCI_TX BT_TXD
POMIO30UART00TX0BT0HCI0RX 9
PIU209 34
PIU2034 PITP1001 COTP10
3[2B] MIO3_UART0_TX_BT_HCI_RX BT_RXD GPIO0 TP10
POBT0HCI0RTS 10 14 COTP11
8[3A] BT_HCI_RTS PIU2010 BT_RTS/I2C_SDA_S GPIO3 PIU2014 PITP1101 TP11
POBT0HCI0CTS 11 15 COTP12
8[3A] BT_HCI_CTS PIU2011 BT_CTS/I2C_SCL_S GPIO4 PIU2015 PITP1201
TP12
2
PIU202 29
PIU2029 PITP1301 COTP13
SDIO/SPI_CFG GPIO17 TP13
POMIO510SD10CLK 22
PIU2022 30
PIU2030 PITP1401 COTP14
3[4A] MIO51_SD1_CLK SD_CLK/GPIO8 GPIO18 TP14
POMIO500SD10CMD 23
PIU2023 31
PIU2031 PITP1501 COTP15
3[4A] MIO50_SD1_CMD SD_CMD/SPI_SCK GPIO19 TP15
POMIO460SD10D0 24 32 COTP16
3[4A] MIO46_SD1_D0 PIU2024 SD_DAT0/SPI_MISO GPIO20 PIU2032 PITP1601 TP16
POMIO470SD10D1 25 35 COTP17
3[4A] MIO47_SD1_D1 PIU2025 SD_DAT1/SPI_SSN GPIO21 PIU2035 PITP1701 TP17
POMIO480SD10D2 26
PIU2026 16
PIU2016 PITP1801 COTP18
3[4A] MIO48_SD1_D2 SD_DAT2/SPI_MOSI UART_TXD TP18
POMIO490SD10D3 27
PIU2027 17
PIU2017 PITP1901 COTP19
3[4A] MIO49_SD1_D3 SD_DAT3/GPIO7 UART_RXD TP19
3 PIU203
NC 1
RADIO RTC 32.768KHz CLOCK PIR1802 PIU204 4
5
NC
GND
GND
PIU201
13
PIU2013
R18 PIU205
COR18
6
NC
GND
21
PIU2021
B +VCC_PSAUX 0 PIU206 NC 28
PIU2028
B
COY1 GND
Y1
COR19
PIR1801 GND
36
PIU2036
4 1 R19 0 NLRADIO0CLK
RADIO_CLK EP
2C6
PIC60COC6
PIY104
VDD OUTPIY101 PIR1902 PIR1901
P_VSS PIU20EP

ATWILC3000-MR110CA
PIC601 0.1uF 3
PIY103 DNC
2
GNDPIY102
GND GND
32.768kHz
DSC6083CI2A-032K768 LAYOUT NOTE: PCB Cutout or no plane routes under
GND GND antenna area required! See Datasheet.

uSD CARD INTERFACE

+VCC_PSAUX
+3.3V
COC7
C7 COC8
C8
GND PIC701 PIC702 PIC801 PIC802 GND
C 0.1uF 0.1uF C

PIU305 PIU3021 PIU3017

21 POMIO240SD00DETECT
3[2A] MIO24_SD0_DETECT

17
COU3
5

U3
+3.3V COR21
R21
Vcca

Vcc_b0

Vcc_b1 COJ2
J2 PIR2102 PIR2101 GND
COC9
C9 4.75K
GND PIC901 PIC902
23 0.1uF 1
DAT2_b0 PIU3023 PIJ201DAT2
POMIO130SD00DAT0 6 22
3[2B] MIO13_SD0_DAT0 PIU306 DAT0a DAT3_b0 PIU3022
POMIO140SD00DAT1 7 20 2 9
3[2B] MIO14_SD0_DAT1 PIU307 DAT1a CMD_b0 PIU3020 PIJ202 CD/DAT3 SWA PIJ209 +VCC_PSAUX
POMIO150SD00DAT2 1
PIU301 COR192
R192
PIR19202 4.99K
PIR19201
3[2A] MIO15_SD0_DAT2 DAT2a COR20
POMIO160SD00DAT3 3
PIU303 19
PIU3019 3
PIJ203 10 R20 240
3[2A] MIO16_SD0_DAT3 DAT3a CLK_b0 CMD SWB PIJ2010 PIR2002 PIR2001

POMIO210SD00CMD 4 18 4
3[2A] MIO21_SD0_CMD PIU304 CMDa DAT0_b0 PIU3018 PIJ204 VDD
POMIO220SD00CLK 9 16
3[2A] MIO22_SD0_CLK PIU309 CLKa DAT1_b0 PIU3016
5
PIJ205 11
CLK GND PIJ2011 PIFB102 PIFB101 GND
12
GND PIJ2012 COFB1 FB1
14
PIU3014 7
PIJ207 13
DAT0_b1 DAT0 GND PIJ2013
15 14
DAT1_b1 PIU3015 GND PIJ2014
24 8 8 15
PIU3024 SEL_B0# DAT2_b1 PIU308 PIJ208 DAT1 GND PIJ2015
10 16
DAT3_b1 PIU3010 GND PIJ2016
T-PAD

12 6
GND

GND

PIU3012
CMD_b1 VSS PIJ206
13
PIU3013
CLK_b1
GND 2201778-1
PIU3025 PIU302 PIU301 TXS02612RTWR
GND SH_GND2
25

11

D D

Avnet Engineering Services

GND Project Name: PCB Rev: BOM: Variant:
Ultra96 SBC V2
Doc Num: Date:
1 Time: 01 00
SCH-US1SBC 3/1/2019 7:57:25 AM
Sheet Title: Size: Sheet:
05 - SD Card, RADIO.SchDoc B 5 of 18
1 2 3 4 5 6
 1 2 3 4 5 6

USB 3.0 MicroAB UPSTREAM INTERFACE

A A

USB 2.0 XNCVR +VCC_PSAUX

USB 3.0 Micro A/B
PWR1
PIC17302 PIC17402 PIC17502 +USB_VB COFB6
FB6 i
+5.0V COC173 COC174 COC175
C173 C174 C175 PIFB601 PIFB602

PIC17601
COC176
C176
PIC17602 GND
PIC17301 0.1uF PIC17401 0.1uF PIC17501 0.1uF
PIC17 02 220 Ohm @ 100MHz PIC17801
NLUSB0ID03V3 0.1uF COC177
C177 COC178
C178
USB_ID_3V3
PIC17 01 5.6uF COFB7
FB7 PIC17802 0.1uF
PIU1402 PIU14028 PIU1403 PIU14032 PIU1402 PIFB701 PIFB702

20

28
30

32

21
COU14
U14 USB3320C-EZK +USB_VB 220 Ohm @ 100MHz
GND
COJ7
J7
PIR15 01

VDD33

VDD18
VDD18

VDDIO

VBAT
+VCC_PSAUX GND PGND 1
COR151
R151 PIJ701USB5V0
ULPI0_D_N 2
PIJ702
COC179
C179 10.00K D-
ULPI0_D_P 3
GND PIC17901 PIC17902
0.1uF 8 22 PIR15 02 PIJ703
4
D+
PIU1408 REFSEL0 VBUS PIU14022
NLULPI00D0N PIJ704ID
11
PIU14011 19
PIU14019 ULPI0_D_N
REFSEL1 DM NLULPI00D0P
14
PIU14014 18
PIU14018 ULPI0_D_P 5
REFSEL2 DP COC180 PGND PIJ705 GND
23
PIU14023 USB_ID_3V3 PIC18001 PIC18002
C180
ID GND NLGTR0LANE20TX0N COC181
POMIO560USB00DATA0 3 2.2uF POGTR0LANE20TX0N GTR_LANE2_TX_N C181 USB3_TX2_N 6
3[6B] MIO56_USB0_DATA0 PIU1403 D0 4[5B] GTR_LANE2_TX_N PIC18101 PIC18102 PIJ706MicA_SSTX-
B POMIO570USB00DATA1 4 17 0.1uF B
3[6B] MIO57_USB0_DATA1 PIU1404 D1 CPEN PIU14017

POMIO540USB00DATA2 5 NLGTR0LANE20TX0P
GTR_LANE2_TX_P COC182 USB3_TX2_P
C182 7
3[6B] MIO54_USB0_DATA2 PIU1405
6
D2 POGTR0LANE20TX0P
4[5B] GTR_LANE2_TX_P PIC18201 PIC18202 PIJ707 MicA_SSTX+
POMIO590USB00DATA3
3[6B] MIO59_USB0_DATA3 PIU1406
D3 0.1uF
POMIO600USB00DATA4 7
PIU1407 29
PIU14029 POMIO580USB00STP 8
3[6B] MIO60_USB0_DATA4 D4 STP MIO58_USB0_STP 3[6B] GND PIJ708
GND_DRAIN
POMIO610USB00DATA5 9 2 POMIO550USB00NXT
3[6B] MIO61_USB0_DATA5 PIU1409 D5 NXT PIU1402 MIO55_USB0_NXT 3[6B]
POMIO620USB00DATA6 10 31 POMIO530USB00DIR POGTR0LANE20RX0N GTR_LANE2_RX_N 9
3[6B] MIO62_USB0_DATA6 PIU14010 D6 DIR PIU14031 MIO53_USB0_DIR 3[6B] 4[5A] GTR_LANE2_RX_N PIJ709MicA_SSRX-
POMIO630USB00DATA7 13
PIU14013 1
PIU1401 POMIO520USB00CLK
3[6B] MIO63_USB0_DATA7 D7 CLKOUT MIO52_USB0_CLK 3[6B]
POGTR0LANE20RX0P GTR_LANE2_RX_P 10
4[5B] GTR_LANE2_RX_P PIJ7010MicA_SSRX+
S1
PIJ70S1
NLUSB0RST0N NLUSB0CLKA S1
USB_RST_N 27
PIU14027 RESET REFCLK PIU14026USB_CLKA
26 POUSB0CLKA
USB_CLKA 7[5B] S2
PIJ70S2
S2
S3
25 S3 PIJ70S3

XO PIU14025 S4
15 COD16
D16 S4 PIJ70S4
PIU14015 SPK_L
16 PUSB3F96X KMMX-AB10-SMT1SB30TR
PAD

PIU14016 SPK_R
NC

24 COR152 0
RBIAS PIU14024
R152
PIR15202 PIR15201

PIR15302
PIU1403 PIU1402 COC183
C183
33

12

COR153
R153 PIC18301 PIC18302
8.06K NLUSB30TX20N 0.1uF
USB3_TX2_N 1
PID1601 2
PID1602 4
PID1604 5
PID1605
PIR15301 CH1 CH2 CH3 CH4
GND SH_GND5

GND GND Layout Notes:

C NLUSB30TX20P
USB3_TX2_P
NLGTR0LANE20RX0N
GTR_LANE2_RX_N
PID16083 GND
3,8
1) USB 2.0 ULPI_D_P/N signals differentially routed @ 90
ohms. 2) USB 3.0 SSTX/RX_P/N routed @ 85 ohms
C

NLGTR0LANE20RX0P
GTR_LANE2_RX_P differential. 3) ULPI_VBUS >30 mil thick trace for current.

GND
+VCC_PSAUX
+VCC_PSAUX PIC18402
COC184
C184
PIC18401
GND
0.1uF
COC185
C185
GND PIC18501 PIC18502 DNP COY2
Y2 +VCC_PSAUX
0.1uF COR155
R155
U15 5 VCC
COU15 PIU150 USB_CLKA
COR154
R154
PIR15402 PIR15401
4PIY204
3PIY203
VDD
OUTPUT
1
OE/STBY/FSPIY201 PIR15502
4.75K
PIR15501

1 0 2PIY202 DNP
POPOWER0GOOD
13[5A], 15[2C], 16[1C], 17[2B], 3[4D], 9[1B] POWER_GOOD PIU1501
A GND
4 USB_RST_N POUSB0RST0N DNP
Y PIU1504 USB_RST_N 12[4B], 7[1B] DSC6101MI2A-024.0000T
POPS0MODE1 2
PIU1502
3[4C] PS_MODE1 B 24MHz DNP
SN74LVC1G08DBVT GND
3 GND PIU1503
GND Layout Note: Place R154 pin 2 pad directly on clock trace
to U14.

D D

Avnet Engineering Services

Project Name: PCB Rev: BOM: Variant:
Ultra96 SBC V2
Doc Num: Date:
1 Time: 01 00
SCH-US1SBC 3/1/2019 7:57:26 AM
Sheet Title: Size: Sheet:
06 - USB 3.0 MicroAB.SchDoc B 6 of 18
1 2 3 4 5 6
 1 2 3 4 5 6

USB 2.0 DOWNSTREAM DEVICE & IDT CLOCK GENERATOR

A A
GND
USB 2.0 XNCVR IDT CLOCK GENERATOR
+VCC_PSAUX PIC1402 PIC1502 PIC1602
COC14
C14 COC15
C15 COC16
C16
+VCC_PSAUX
PIC1401 0.1uF PIC1501 0.1uF PIC1601 0.1uF

+5.0V PIC20 2 PIC2102 PIC2 02 PIC1702 PIC1802 PIC1902

COC20
C20 COC21
C21 COC22
C22 COC17
C17 COC18
C18 COC19
C19
COC23
C23
PIC2301 PIC2302
PIC20 1 0.1uF PIC2101 0.1uF PIC2 01 0.1uF PIC1701 0.1uF PIC1801 0.1uF PIC1901 0.1uF
GND
COC24
C24 0.1uF
PIC2402 PIC2401
GND
2.2uF
PIU402 PIU4028 PIU403 PIU4032 PIU4021 GND
PIU5023 PIU5021 PIU5018 PIU501 PIU501 PIU50 PIU502

23

21

18

15

10

22
20

28
30

32

21
COU4

5
U4 +5.0V COU5
U5
USB3320C-EZK GND

VDDO0

VDDO1

VDDO2

VDDO3

VDDO4

VDDA

VDDD
PIR2401
VDD33

VDD18
VDD18

VDDIO

VBAT
+VCC_PSAUX COTP20 1
PITP2001 PIU501
COR24
R24 TP20 CLKIN
COC25
C25 10.00K
GND PIC2501 PIC2502
0.1uF 8
PIU408 22
PIU4022
PIR2402 20
OUT1PIU5020 POGTR0CLK00USB026M0P
GTR_CLK0_USB_26M_P 4[5B]
REFSEL0 VBUS
11 19
PIU4011
14
REFSEL1 DM PIU4019
18
POULPI10D0N
ULPI1_D_N
POULPI10D0P
12[4C] 19
OUT1B PIU5019 POGTR0CLK00USB026M0N
GTR_CLK0_USB_26M_N 4[5B]
26 MHz LVDS
PIU4014 REFSEL2 DP PIU4018 ULPI1_D_P 12[4C]
23
PIU4023
B ID GND 2 17 B
POMIO680USB10DATA0 3
PIU403 COTP21
TP21 PITP2101 PIU502CLKINB OUT2 PIU5017 POGTR0CLK10DP027M0P
GTR_CLK1_DP_27M_P 4[5B]
3[6A] MIO68_USB1_DATA0 D0 COR25 0
4 17 R25
POMIO690USB10DATA1
3[6A] MIO69_USB1_DATA1
POMIO660USB10DATA2
PIU404
5
D1 CPEN PIU4017 PIR2502 PIR2501 POMIO250VBUS0DET
MIO25_VBUS_DET 12[1D], 3[2A]
OUT2B
16
PIU5016 POGTR0CLK10DP027M0N
GTR_CLK1_DP_27M_N 4[5B]
27 MHz LVDS (DP)
3[6B] MIO66_USB1_DATA2 PIU405
6
D2 DNP
POMIO710USB10DATA3
3[6A] MIO71_USB1_DATA3 PIU406 D3 COR26 40.2
PIU5014R26
14
POMIO720USB10DATA4
3[6A] MIO72_USB1_DATA4
7
PIU407
9
D4 STP
29
2
PIU4029 POMIO700USB10STP
MIO70_USB1_STP 3[6A] +VCC_PSAUX OUT3 PIR2601 PIR2602 POPS0REF0CLK
PS_REF_CLK 3[4D] 33.333MHz LVCMOS (SoC)
POMIO730USB10DATA5
3[6A] MIO73_USB1_DATA5 PIU409
D5 NXT PIU402 POMIO670USB10NXT
MIO67_USB1_NXT 3[6A] COJT2
JT2
10 31 COTP22 PITP2201SEL1 8 13 COTP23
POMIO740USB10DATA6
3[6A] MIO74_USB1_DATA6 PIU4010 D6 DIR PIU4031 POMIO650USB10DIR
MIO65_USB1_DIR 3[6B] TP22 PIU508SEL1/SDA OUT3B PIU5013 PITP2301
TP23
13 1 1
PIJT201
POMIO750USB10DATA7
3[6A] MIO75_USB1_DATA7 PIU4013 D7 CLKOUT PIU401 POMIO640USB10CLK
MIO64_USB1_CLK 3[6B] NLSEL0 COR27
COTP24
TP24 PITP2401SEL0 9
PIU509SEL0/SCL
11 R27
OUT4PIU5011 PIR2701
24.9
PIR2702 USB_CLKB

2 24 COR28
12 R28 24.9
24 MHz LVCMOS (USB)
PIJT202 PIU5024OUT0_SEL_I2CB OUT4B PIU5012 PIR2801 PIR2802 POUSB0CLKA
USB_CLKA 6[3B]
POUSB0RST0N 27
PIU4027 26
PIU4026 USB_CLKB
12[4B], 6[2D] USB_RST_N RESET REFCLK 7
PIU507
SD/OE
25 3
PIJT203
XO PIU4025
6
15
PIU4015 PIU506CLKSEL
SPK_L 10K (1-2) PIR2901 PIR30 1 PIR3101 EPAD
16
PAD

PIU4016
SPK_R COR29
R29 COR30
R30 COR31
R31
PIU502
NC

24
PIU4024 GND 5P49V6975A114LTGI
RBIAS 0 10.00K 10.00K 25
PIR3202 PIR2902 PIR30 2 PIR3102
PIU403 PIU4012
33

12

Layout Notes: COR32

R32
1) USB 2.0 ULPI_D_P/N signals differentially routed @ 90 8.06K
ohms. PIR3201 POUSB0HUB025MHz
12[1B] USB_HUB_25MHz GND GND GND

25 MHz LVCMOS (USB HUB)

C GND GND C

24MHz CLOCK COJT3

+VCC_PSAUX
COJT4
+VCC_PSAUX
JT3 JT4
3
PIJT303 3
PIJT403
+VCC_PSAUX
COC26
C26
PIC2602 PIC2601 GND +VCC_PSAUX
0.1uF 2 NLSEL1
SEL1 2 SEL0
PIJT302 PIJT402
DNP COY3
Y3
4PIY304 1
COR34
R34
NLUSB0CLKB COR33
R33 VDD OE/STBY/FSPIY301 PIR3402 PIR3401
1 1
USB_CLKB 0 3PIY303 4.75K PIJT301 PIJT401
PIR3302 PIR3301 OUTPUT
DNP 2PIY302 DNP
GND 10K (1-2) 10K (1-2)
DSC6101MI2A-024.0000T
24MHz DNP GND GND
GND

Layout Note: Place R33 pin 2 pad directly on clock trace to

U4.

D D

Avnet Engineering Services

Project Name: PCB Rev: BOM: Variant:
Ultra96 SBC V2
Doc Num: Date:
1 Time: 01 00
SCH-US1SBC 3/1/2019 7:57:26 AM
Sheet Title: Size: Sheet:
B
07 - USB2.0 Downstream Device & Clock Gen.SchDoc 7 of 18
1 2 3 4 5 6
 1 2 3 4 5 6

BANK0, BANK26, BANK65, BANK66

A A

BANK0 +VCCAUX BANK26 BANK65

COFB2
FB2
PIFB202 PIFB201 U1B U1C
BANK 26 BANK 65
PIC2701 PIC2802 220 Ohm @ 100MHz
IO_L12N_AD0N_26
A6
PIU10A6 POHD0GPIO06
HD_GPIO_6 13[4B] IO_T3U_N12_65
F4
PIU10F4 POFAN0PWM
FAN_PWM 9[5D]
COC27
C27 COC28
C28 B7 H3
PIU10H3
IO_L12P_AD0P_26 PIU10B7 POBT0HCI0RTS
BT_HCI_RTS 5[2B] IO_T2U_N12_65
PIC2702 0.1uF PIC2801 0.47uF
IO_L11N_AD1N_26
B5
PIU10B5 POBT0HCI0CTS
BT_HCI_CTS 5[2B] IO_T1U_N12_65
N3
PIU10N3
COR35
R35
PIR3501 240
PIR3502 GND
B6 POHD0GPIO014 P2
IO_L11P_AD1P_26 PIU10B6 HD_GPIO_14 13[5B] IO_T0U_N12_VRP_65 PIU10P2
A7 M1 POCSI00D10N
IO_L10N_AD2N_26 PIU10A7 POHD0GPIO07
HD_GPIO_7 13[4B] IO_L9N_T1L_N5_AD12N_65 PIU10M1
M2
CSI0_D1_N 13[3A]
A8
PIU10A8 IO_L9P_T1L_N4_AD12P_65 PIU10M2 POCSI00D10P
CSI0_D1_P 13[3A]
IO_L10P_AD2P_26 N4
A9
PIU10A9 PORADIO0LED0 IO_L8N_T1L_N3_AD5N_65 PIU10N4 POCSI00D00N
CSI0_D0_N 13[3A]
COU1A
COU1B
COU1C
COU1D
U1A +VCCAUX IO_L9N_AD3N_26 RADIO_LED0 9[3D] N5
GND_SYSMON B9
PIU10B9 PORADIO0LED1 IO_L8P_T1L_N2_AD5P_65 PIU10N5 POCSI00D00P
CSI0_D0_P 13[3A]
IO_L9P_AD3P_26 RADIO_LED1 9[3D] P1
BANK 0 C7 POHD0GPIO013 IO_L7N_T1L_N1_QBC_AD13N_65 PIU10P1 POCSI00C0N
CSI0_C_N 13[3A]
IO_L8N_HDGC_AD4N_26 PIU10C7 HD_GPIO_13 13[5B] N2
M10 C8 IO_L7P_T1L_N0_QBC_AD13P_65 PIU10N2 POCSI00C0P
CSI0_C_P 13[3A]
VREFP PIU10M10
L9 PIR3602 IO_L8P_HDGC_AD4P_26 PIU10C8
C5 POHD0GPIO015 R5
PIU10R5
VREFN PIU10L9
COR36
R36 IO_L7N_HDGC_AD5N_26 PIU10C5 HD_GPIO_15 13[5B] IO_L6N_T0U_N11_AD6N_65
L10 SYSMON_VR_P D5 P5
PIU10P5
VP PIU10L10
NLSYSMON0VR0N IO_L7P_HDGC_AD5P_26 PIU10D5 POHD0GPIO012
HD_GPIO_12 13[5B] IO_L6P_T0U_N10_AD6P_65
M9 SYSMON_VR_N 1.00K D8 POCSI10MCLK T1
VN PIU10M9
PIR3601 IO_L6N_HDGC_AD6N_26 PIU10D8 CSI1_MCLK 13[1A] IO_L5N_T0U_N9_AD14N_65 PIU10T1
K10 E8 POCSI00MCLK R1
VCCADC PIU10K10 IO_L6P_HDGC_AD6P_26 PIU10E8 CSI0_MCLK 13[1A] IO_L5P_T0U_N8_AD14P_65 PIU10R1
T8 NLPUDC0B
PUDC_B D6 T4
PUDC_B PIU10T8 IO_L5N_HDGC_AD7N_26 PIU10D6 POHD0GPIO011
HD_GPIO_11 13[5A] IO_L4N_T0U_N7_DBC_AD7N_65 PIU10T4
R4
T7
PIU10T7 D7
PIU10D7 POHD0GPIO00 IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65 PIU10R4
POR_OVERRIDE GND IO_L5P_HDGC_AD7P_26 HD_GPIO_0 13[4A] U1
K9
PIU10K9 F7
PIU10F7 POHD0GPIO02 IO_L3N_T0L_N5_AD15N_65 PIU10U1 POCSI10D10N
CSI1_D1_N 13[3B]
GNDADC IO_L4N_AD8N_26 HD_GPIO_2 13[4A] U2
N10
PIU10N10 F8
PIU10F8 POHD0GPIO01 IO_L3P_T0L_N4_AD15P_65 PIU10U2 POCSI10D10P
CSI1_D1_P 13[3B]
DXP PIR3701 IO_L4P_AD8P_26 HD_GPIO_1 13[4A] R3
B N9
PIU10N9 E5
PIU10E5 POHD0GPIO010 IO_L2N_T0L_N3_65 PIU10R3 POCSI10D00N
CSI1_D0_N 13[3B] B
DXN COR37
R37 IO_L3N_AD9N_26 HD_GPIO_10 13[5A] P3
COFB3
FB3 E6 POHD0GPIO09 IO_L2P_T0L_N2_65 PIU10P3 POCSI10D00P
CSI1_D0_P 13[3B]
IO_L3P_AD9P_26 PIU10E6 HD_GPIO_9 13[5A] C2
XCZU3EG-1SBVA484I 100K F6 POHD0GPIO04 IO_L24N_T3U_N11_PERSTN0_65 PIU10C2 POHSIC0DATA
HSIC_DATA 13[1B]
PIFB302 PIFB301 IO_L2N_AD10N_26 PIU10F6 HD_GPIO_4 13[4A]
220 Ohm @ 100MHz
PIR3702 DNP IO_L2P_AD10P_26
G7
PIU10G7 POHD0GPIO03
HD_GPIO_3 13[4A] IO_L24P_T3U_N10_PERSTN1_I2C_SDA_65
D2
PIU10D2
G5 POHD0GPIO05 F2
IO_L1N_AD11N_26 PIU10G5 HD_GPIO_5 13[4A] IO_L23N_T3U_N9_65 PIU10F2
G6 POHD0GPIO08 F3
IO_L1P_AD11P_26 PIU10G6 HD_GPIO_8 13[4B] IO_L23P_T3U_N8_I2C_SCLK_65 PIU10F3
C3
PIU10C3 PODSI0D30N
IO_L22N_T3U_N7_DBC_AD0N_65 DSI_D3_N 13[1B]
GND_SYSMON GND GND XCZU3EG-1SBVA484I D3
PIU10D3 PODSI0D30P
IO_L22P_T3U_N6_DBC_AD0P_65 DSI_D3_P 13[1B]
D1
PIU10D1 PODSI0D20N
IO_L21N_T3L_N5_AD8N_65 DSI_D2_N 13[1B]
E1
PIU10E1 PODSI0D20P
IO_L21P_T3L_N4_AD8P_65 DSI_D2_P 13[1B]
E3 PODSI0D10N
IO_L20N_T3L_N3_AD1N_65 PIU10E3 DSI_D1_N 13[1B]
E4 PODSI0D10P
IO_L20P_T3L_N2_AD1P_65 PIU10E4 DSI_D1_P 13[1B]
T2
PIU10T2 POCSI10C0N
IO_L1N_T0L_N1_DBC_65 CSI1_C_N 13[3B]
T3
PIU10T3 POCSI10C0P
IO_L1P_T0L_N0_DBC_65 CSI1_C_P 13[3B]
F1
PIU10F1 PODSI0D00N
IO_L19N_T3L_N1_DBC_AD9N_65 DSI_D0_N 13[1B]
G1 PODSI0D00P
IO_L19P_T3L_N0_DBC_AD9P_65 PIU10G1 DSI_D0_P 13[1B]
G4
SYSMON I2C ADDRESS SELECT IO_L18N_T2U_N11_AD2N_65
IO_L18P_T2U_N10_AD2P_65
PIU10G4
H4
PIU10H4
G2
+VCCAUX +VCCAUX BANK66 IO_L17N_T2U_N9_AD10N_65
IO_L17P_T2U_N8_AD10P_65
PIU10G2
H2
PIU10H2
H5 PODSI0CLK0N
U1D IO_L16N_T2U_N7_QBC_AD3N_65 PIU10H5 DSI_CLK_N 13[1B]
PIR3802 PIR3902 J5 PODSI0CLK0P
IO_L16P_T2U_N6_QBC_AD3P_65 PIU10J5 DSI_CLK_P 13[1B]
COR38
R38 COR39
R39 BANK 66 J1
PIU10J1
IO_L15N_T2L_N5_AD11N_65
49.9K 49.9K A2
PIU10A2 POHSIC0STR K1
PIU10K1
IO_T3U_N12_66 HSIC_STR 13[1B] IO_L15P_T2L_N4_AD11P_65
PIR3801 DNP PIR3901 DNP B2
PIU10B2 K3
PIU10K3
C IO_L11P_T1U_N8_GC_66 IO_L14N_T2L_N3_GC_65 C
NLSYSMON0VR0P B1 K4
SYSMON_VR_P SYSMON_VR_N IO_L11N_T1U_N9_GC_66 PIU10B1 IO_L14P_T2L_N2_GC_65 PIU10K4
A4 J2
IO_L12P_T1U_N10_GC_66 PIU10A4 IO_L13N_T2L_N1_GC_QBC_65 PIU10J2

PIR40 2 PIR4102 A3
PIU10A3 J3
PIU10J3
IO_L12N_T1U_N11_GC_66 IO_L13P_T2L_N0_GC_QBC_65
COR40
R40 COR41
R41 B4
PIU10B4 L3
PIU10L3
IO_T0U_N12_VRP_66 IO_L12N_T1U_N11_GC_65
20.5K 20.5K C4
PIU10C4 L4
PIU10L4
VREF_66 IO_L12P_T1U_N10_GC_65
PIR40 1 PIR4101 L1 POCSI00D30N
IO_L11N_T1U_N9_GC_65 PIU10L1 CSI0_D3_N 13[3B]
XCZU3EG-1SBVA484I L2 POCSI00D30P
IO_L11P_T1U_N8_GC_65 PIU10L2 CSI0_D3_P 13[3B]
M4
PIU10M4 POCSI00D20N
COJT5 IO_L10N_T1U_N7_QBC_AD4N_65 CSI0_D2_N 13[3B]
JT5 M5
PIU10M5 POCSI00D20P
IO_L10P_T1U_N6_QBC_AD4P_65 CSI0_D2_P 13[3A]
GND GND 3
PIJT503 K5
PIU10K5
VREF_65
XCZU3EG-1SBVA484I
2
PIJT502 POMIO70RADIO0RST0N
MIO7_RADIO_RST_N 5[2A]

1 POMIO70RAD0RST0N
PIJT501 MIO7_RAD_RST_N 3[2B]
0

D D

Avnet Engineering Services

Project Name: PCB Rev: BOM: Variant:
Ultra96 SBC V2
Doc Num: Date:
1 Time: 01 00
SCH-US1SBC 3/1/2019 7:57:26 AM
Sheet Title: Size: Sheet:
08 - Bank 0, Bank 26, Bank65, Bank66.SchDoc B 8 of 18
1 2 3 4 5 6
 1 2 3 4 5 6

USER SWITCHES, LEDs, JTAG I/F, FAN DRIVER

A SWITCHES JTAG HEADER (BOTTOM OF PCB) LED INDICATORS: A

LAYOUT NOTE: Place PS_DONE LED

MIO23_GPIO_PB header on bottom of PCB. VIN_LED VCC3v3_LED +3.3V
COD1
D1
+VCC_PSAUX COR42
+VCC_PSAUX +VIN +3.3V R42
PIR4201 261
PIR4202 2PID102 1
PID101
COJ3
J3
1
PIR4 01 PIJ301
2 COR43
R43 4.75K
PIR19302 PIR4501
COR44
R44 PIJ302 +VCC_PSAUX PIR4302 PIR4301 JTAG_TCK
COR193
R193 COR45
R45
NLJTAG0TCK
JTAG_TCK 3 COR46
R46 4.75K JTAG_TMS
4.75K - COSW1SW1 POJTAG0TCK
3[4C] JTAG_TCK PIJ303 PIR4602 PIR4601
1.00K 261 COR47
R47 4.75K
NLJTAG0TMS 4 COR48
R48 4.75K
PIR4 02 1PISW101 4 POJTAG0TMS
3[4C] JTAG_TMS
JTAG_TMS PIJ304 PIR4802 PIR4801 JTAG_TDI
PIR19301 PIR4502 +VCC_PSAUX PIR4701 PIR4702
POMIO230GPIO0PB
3[2A] MIO23_GPIO_PB
2PISW102
PISW104
3
PISW103
POJTAG0TDI
3[4C] JTAG_TDI
POPS0SRST0N
NLJTAG0TDI
JTAG_TDI
NLPS0SRST0N
PS_SRST_N
3[4D] PS_SRST_N NLJTAG0TDO
5
PIJ305
6
PIJ306
COR49
R49
PIR4902
COR50
R50
PIR5002
4.75K
PIR4901
4.75K
PIR5001
PS_SRST_N
JTAG_TDO
6PIQ406 COQ4B
COQ4A
D Q4A

2
POJTAG0TDO
3[4C] JTAG_TDO
JTAG_TDO 7
PIJ307
PID1702 PID202 POPS0DONE
3[4C] PS_DONE
2
PIQ402 FDY3000NZ
PS_POR_N 8
PIJ308
G
GND
MMT-108-01-T-SH-LC
JTAG_TCK COR51
R51
PIR5102 20 PIC2902
PIR5101
COC29
C29
PIC2901
33pF
COD17
D17 COD2
D2
1PIQ401
S

PS_POR_PB GND PID1701 PID201

1
GND GND
- SW2 COSW2 MIO/USER LEDs
1PISW201 4
MIO20_PS_LED0 MIO19_PS_LED1 GND GND
PISW204
2PISW202 PISW2033 +3.3V +3.3V COD4
B COD3
D3 D4 PS_INIT_N LED B
COR52
R52
PIR5201 261
PIR5202 2
PID302 1
PID301
COR53
R53
PIR5301 261
PIR5302 2PID402 1
PID401 +VCC_PSAUX +3.3V +3.3V

POPOWER0GOOD
13[5A], 15[2C], 16[1C], 17[2B], 3[4D], 6[1D] POWER_GOOD GND 6PIQ306 COQ3B
COQ3A
D Q3A
3 PIQ30 Q3B
COR54
R54
PIR5402 4.75K
PIR5401 PIR5 01 PIR5602
COR191
R191
0
NLPS0POR0N
PIR19101 PS_POR_N
2 FDY3000NZ 5 FDY3000NZ PIQ405 COR55
R55
COD5
COR56
R56

5
PIR19102 POMIO200PS0LED0
3[2A] MIO20_PS_LED0 PIQ302 POMIO190PS0LED1
3[2A] MIO19_PS_LED1 PIQ305
10.00K D5 261

G
G G
PIR5 02 1PID501 2 PIR5601
PIQ301 PIQ304

3
S POPS0INIT0N
3[4C] PS_INIT_N PIQ404 PIQ403 PID502
1 4
Q4B
FDY3000NZ
INIT_N = 0, LED ON
BOOT MODE: JTAG: 1,1 GND GND INIT_N = 1, LED OFF
SD: 0,1
+VCC_PSAUX

PIR5702
COR57
R57
PIR5802
COR58
R58
MIO18_PS_LED2 MIO17_PS_LED3 FAN DRIVER:
4.75K 4.75K +3.3V COD6 +3.3V COD7
COSW3
SW3 D6 D7
PIR5701 PIR5801
POPS0MODE0 1 PISW3044 COR59
R59 261 2PID602 1 COR60
R60 261 2PID702 1 +5.0V +3.3V +VIN
3[4C] PS_MODE0 PISW301 PIR5901 PIR5902 PID601 PIR6001 PIR6002 PID701
POPS0MODE2 2PISW302 PISW3033
3[4C] PS_MODE2
218-2LPSTRF
PIR6102
COR61
R61
PIR6202
COR62
R62
6 PIQ506 COQ5B
COQ5A
D Q5A
3 PIQ503 Q5B
PIR6302
COR63
R63
PIR6402
COR64
R64
PIR6502
COR65
R65
C 499 POMIO180PS0LED2 2 FDY3000NZ POMIO170PS0LED3 5 FDY3000NZ 0 0 0 C
499 3[2A] MIO18_PS_LED2 PIQ502 3[2A] MIO17_PS_LED3 PIQ505
G G
PIR6101 PIR6201 PIR6301 PIR6401 DNP PIR6501 DNP
1 PIQ501 S
4 PIQ504 PITP2501 COTP25
TP25
PID801

1
COD8
D8
GND GND
GND GND MMSD4148T1G FAN CONNECTIONS
PID802

2
+VCCO_HP PITP2601 COTP26
TP26

RADIO/USER LEDs
COR66
R66
PIR6602 1.00K
PIR6601
3PIQ903 COQ9
D Q9
1 FDN327N
PMIC I2C CONNECTIONS POFAN0PWM
8[6A] FAN_PWM PIQ901
G
+3.3V
COD9
D9
+3.3V
COD10
D10 2PIQ902
S

COR67
R67 261 COR68
R68 261 PID1002
2 1
POPMBUS0SCL
13[1D], 15[2C], 16[1C], 17[2C] PMBUS_SCL PITP2701 COTP27
TP27 PIR6701 PIR6702 PID902 PID901 PIR6801 PIR6802 PID1001
SCL
POPMBUS0SDA
13[1D], 15[2C], 16[1C], 17[2C] PMBUS_SDA PITP2801 COTP28
TP28 SDA
HSMY-C191 6 PIQ60 COQ6B
COQ6A
D Q6A
3 PIQ603 Q6B GND
COTP29 PORADIO0LED0 2 FDY3000NZ PORADIO0LED1 5 FDY3000NZ
PITP2901
TP29 GND 8[3B] RADIO_LED0 PIQ602
G
8[3B] RADIO_LED1 PIQ605
G

1 PIQ601
S
4 PIQ604
GND
D D
LAYOUT NOTE: Order these TPs as follows: SCL, SDA, GND GND
GND in a 100 mil center-to- center line. Add silkscreen
(SDA, SCL, GND) by appropriate test point. Avnet Engineering Services
Project Name: PCB Rev: BOM: Variant:
Ultra96 SBC V2
Doc Num: Date:
1 Time: 01 00
SCH-US1SBC 3/1/2019 7:57:26 AM
Sheet Title: Size: Sheet:
09 - Switches, LEDs, JTAG.SchDoc B 9 of 18
1 2 3 4 5 6
 1 2 3 4 5 6

BANK POWER & DECOUPLING U1M

+VCC_PSAUX +VCC_PSAUX VCCO +VCCAUX
+VCCINT +VCCAUX AA5
PIU10AA5 B8
PIU10B8
VCCO_PSIO0_500 VCCO_26
V6
PIU10V6 E7
PIU10E7
VCCO_PSIO0_500 VCCO_26
PIC30 2 PIC3202 PIC3102 PIC3 02 PIC3402 C11
PIU10C11 B3
PIU10B3
PIC3502 PIC3602 PIC3702 PIC3802 PIC3902 PIC40 2 PIC4102 VCCO_PSIO1_501 VCCO_65 +VCCO_HP
COC30
C30 COC32 COC31
C31 COC33
C33 COC34 F10
PIU10F10 G3
PIU10G3
COU1O
COU1L
COU1M
COU1N
U1L C32 C34 COC35 COC36 COC37 COC38 COC39 COC40 COC41 VCCO_PSIO1_501 VCCO_65
PIC30 1 0.47uF PIC3201 0.47uF PIC3101 4.7uF PIC3 01 0.47uFPIC3401 0.47uF C35 C36 C37 C38 C39 C40 C41 C16 K2
PIC3501 0.47uF PIC3601 0.47uF PIC3701 0.47uF PIC3801 0.47uF PIC3901 0.47uF PIC40 1 0.47uF PIC4101 1000pF
PIU10C16 VCCO_PSIO2_502 VCCO_65 PIU10K2

A PL CORE POWER D14

PIU10D14 P4
PIU10P4 A
VCCO_PSIO2_502 VCCO_65
M6
PIU10M6 +VCCO_PSDDR G13
PIU10G13
VCCAUX +VCCAUX VCCO_PSIO3_503
P6
PIU10P6 H16
PIU10H16 NOTE: Bank 66 HP I/Os are
VCCAUX VCCO_PSIO3_503
J6
PIU10J6 AB18
PIU10AB18 attached to VCCO 65 internally.
VCCAUX_IO GND GND VCCO_PSDDR_504
K6 P19
VCCAUX_IO PIU10K6 GND PIU10P19 VCCO_PSDDR_504
L6 T20
VCCAUX_IO PIU10L6 PIU10T20 VCCO_PSDDR_504
N7
PIU10N7 +VCC_PSINTFP +VCC_PSINTLP V16
PIU10V16
VCCBRAM +VCCINT VCCO_PSDDR_504
R6
PIU10R6 +VCCO_PSDDR V21
PIU10V21
VCCBRAM VCCO_PSDDR_504
R7
PIU10R7 Y17
PIU10Y17
VCCBRAM
T6 PIC4302 PIC4502 PIC4202 PIC4 02 PIC4602 Y22
VCCO_PSDDR_504
VCCBRAM PIU10T6
COC43
C43 COC45
C45 COC42
C42 COC44
C44 COC46
C46
PIU10Y22 VCCO_PSDDR_504
H10
VCCINT PIU10H10
H8
PIU10H8
PIC4301 0.47uF PIC4501 0.47uF PIC4201 4.7uF PIC4 01 0.47uFPIC4601 0.47uF PIC4702 PIC4802 PIC4902 PIC50 2 PIC5102 PIC5202 PIC5302 PIC5402 PIC5 02 PIC5602 XCZU3EG-1SBVA484I
VCCINT COC47 COC48 COC49 COC50 COC51 COC52 COC53 COC54 COC55 COC56
J11
PIU10J11 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56
VCCINT
VCCINT
J9
PIU10J9 PIC4701 10uF PIC4801 0.47uF PIC4901 4.7uF PIC50 1 0.047uFPIC5101 1000pF PIC5201 1000pF PIC5301 1000pF PIC5401 10000pF PIC5 01 10000pFPIC5601 10000pF Layout Note: Place direct pin connect
K8 CAPs under Zynq.
VCCINT PIU10K8
L11 GND GND
VCCINT PIU10L11
M8
PIU10M8 +MGTRAVTT +MGTRAVCC
VCCINT
N11
PIU10N11
VCCINT GND GND
P10
PIU10P10
VCCINT
P8 PIC5702 PIC5802 PIC5901 PIC60 2 PIC6102 PIC6201
VCCINT PIU10P8
COC57
C57 COC58
C58 COC59
C59 COC60
C60 COC61
C61 COC62
C62
R11
VCCINT PIU10R11
R9
PIU10R9
PIC5701 4.7uF PIC5801 0.47uFPIC5902 0.1uF PIC60 1 4.7uF PIC6101 0.47uFPIC6202 0.1uF GND_SYSMON
VCCINT
H7
PIU10H7
VCCINT_IO U1O
J7
PIU10J7
VCCINT_IO XCZU3EG-1SBVA484I
L7
VCCINT_IO PIU10L7
B M7 GND GND
PIU10Y7 PIU10Y2 PIU10Y2 PIU10W9 PIU10W4 PIU10W9 PIU10W4 PIU10V PIU10V PIU108 PIU103 PIU10 8 PIU10 6 PIU10 3 PIU10T5 PIU10T5 PIU10T PIU10R8 PIU10R2 PIU10R2 PIU10R7 PIU10R2 PIU10R PIU10P9 B

W19
W14
Y12

U18

U13
V11
VCCINT_IO

R22

R17
R12
R10
PIU10M7

T15
T11
P16
W9
W4
Y7
Y2

V1
U8
U3

R8

R2
T5

P9
XCZU3EG-1SBVA484I

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND_PSADC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A1
PIU10A1 P7
PIU10P7
GND GND
A10
PIU10A10 P14
PIU10P14
GND GND
A15 P11
PIU10A15 GND GND PIU10P11
U1N A18
PIU10A18 N8
GND GND PIU10N8
PS CORE POWER A22
PIU10A22 N6
PIU10N6
GND GND
F19 A5
PIU10A5 N22
PIU10N22
PS_MGTRAVCC PIU10F19
+MGTRAVCC GND GND
H19 AA10
PIU10AA10 N21
PIU10N21
PS_MGTRAVCC PIU10H19 GND GND
K19 AA15 N20
PS_MGTRAVCC PIU10K19 PIU10AA15 GND GND PIU10N20
A21 AA20 N16
PS_MGTRAVTT PIU10A21 +MGTRAVTT PIU10AA20 GND GND PIU10N16
B19 +VCC_PSAUX AB1
PIU10AB1 N1
PIU10N1
PS_MGTRAVTT PIU10B19 GND GND
D19 COFB4 AB13
PIU10AB13 M3
PIU10M3
PS_MGTRAVTT PIU10D19 FB4 GND GND
P15 AB22
PIU10AB22 M19
PIU10M19
VCC_PSADC PIU10P15 PIFB402 PIFB401 GND GND
VCC_PSAUX
L16
PIU10L16 +VCC_PSAUX PIC6302COC63
C63
1C64
PIC640COC64 AB3
PIU10AB3 GND
DIGITAL GND
GND
M18
PIU10M18

VCC_PSAUX
L17
PIU10L17
PIR6901 AB8
PIU10AB8 GND GND
M13
PIU10M13
M16 COR69
R69 PIC63010.47uF PIC64020.1uF COFB5
FB5 B13
PIU10B13 M11
PIU10M11
VCC_PSAUX PIU10M16 GND GND
M17 0 PIFB502 PIFB501 B20
PIU10B20 L8
PIU10L8
VCC_PSAUX PIU10M17 COTP30
TP30 COTP31 GND GND
VCC_PSBATT
N15
PIU10N15 PIR6902PITP3001 TP31
PITP3101
GND
C1
PIU10C1 GND GND
L5
PIU10L5
C M14 C18 L22 C
VCC_PSDDR_PLL PIU10M14 PIU10C18 GND GND PIU10L22
M15 GND_SYSMON GND C21 L21
VCC_PSDDR_PLL PIU10M15 PIU10C21 GND GND PIU10L21
N14 C22
PIU10C22 L18
PIU10L18
VCC_PSINTFP PIU10N14 +VCC_PSINTFP GND GND
R15 C6
PIU10C6 L15
PIU10L15
VCC_PSINTFP PIU10R15 GND GND
R16 LAYOUT NOTE: TP30/31 within 100 mils of each other. D20
PIU10D20 K7
PIU10K7
VCC_PSINTFP PIU10R16 GND GND
T12 TP30 silk: +VB, TP31 silk: GND. Add silk battery symbol if D4 K20
VCC_PSINTFP PIU10T12 PIU10D4 GND GND PIU10K20
T13 possible. D9 K17
VCC_PSINTFP PIU10T13 PIU10D9 GND GND PIU10K17
T14 E12
PIU10E12
VCC_PSINTFP PIU10T14 GND
T16
VCC_PSINTFP PIU10T16
N17
PIU10N17
VCC_PSINTFP_DDR
P17
PIU10P17
VCC_PSINTFP_DDR
T17

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC_PSINTFP_DDR PIU10T17
N12
VCC_PSINTLP PIU10N12 +VCC_PSINTLP
N13
VCC_PSINTLP PIU10N13

VCC_PSINTLP
P12
PIU10P12
PIU10E7 PIU10E8 PIU10E2 PIU10E2 PIU10E2 PIU10F5 PIU10F2 PIU10F5 PIU10G8 PIU10G21 PIU10G2 PIU10G8 PIU10H PIU10H PIU10H2 PIU10H6 PIU10H9 PIU10J PIU10J4 PIU10J8 PIU10J21 PIU10J2 PIU10J4 PIU10J8 PIU10K1

E17
E18
E2
E21
E22
F15
F20
F5
G18
G21
G22
G8
H1
H11
H20
H6
H9
J10
J14
J18
J21
J22
J4
J8
K11
P13
PIU10P13
VCC_PSINTLP
R13
PIU10R13
VCC_PSINTLP
R14
VCC_PSINTLP PIU10R14
L13
VCC_PSPLL PIU10L13 +VCC_PSPLL
L14
PIU10L14
VCC_PSPLL
M12
PIU10M12
VCC_PSPLL GND
XCZU3EG-1SBVA484I

D D

Avnet Engineering Services

Project Name: PCB Rev: BOM: Variant:
Ultra96 SBC V2
Doc Num: Date:
1 Time: 01 00
SCH-US1SBC 3/1/2019 7:57:26 AM
Sheet Title: Size: Sheet:
10 - Bank Power and Decoupling.SchDoc B 10 of 18
1 2 3 4 5 6
 1 2 3 4 5 6

LPDDR4 16Gb (2GB) RAM

POINT-TO-POINT: NO DDR TERM RESISTORS
40 OHM INTERFACE IMPEDANCE
LAYOUT NOTE: Place ZQ
resistor close to DDR IC.
A A
+VCCO_PSDDR +VCC_PSAUX +VCCO_PSDDR
COR146
R146 240
+VCCO_PSDDR PIR14602 PIR14601

PIU130A5 PIU130A PIU130A8 PIU130A5 PIU130A PIU130W2 PIU130W8 PIU130W5 PIU130W1 PIU130 PIU130 PIU130F PIU130F PIU130D2 PIU130D8 PIU130D5 PIU130D PIU130B PIU130B8 PIU130B5 PIU130B PIU130 2 PIU130U1 PIU130T9 PIU130T4 PIU130G9 PIU130G4 PIU130F2 PIU130F PIU130F8 PIU130F5 PIU130A9 PIU130A4 PIU130AB9 PIU130AB4 PIU1308 PIU130U5 PIU130R2 PIU130R8 PIU130R5 PIU130R PIU130N2 PIU130N PIU130N PIU130N PIU130K2 PIU130K PIU130K PIU130K PIU130H2 PIU130H8 PIU130H5 PIU130H1

AA10
AA8
AA5
AA3
W12

AB9
AB4
U10

D12

U12

N12
N10

K12
K10

H12
B10

R12
+VCCO_PSDDR

F10

F12
W8
W5
W1
A5

U3

D8
D5
D1

U1

G9
G4

A9
A4

U8
U5

N3
N1

K3
K1

H8
H5
H1
B8
B5
B3

R8
R5
R1
COU13

T9
T4
F3

F1

F8
F5
U13
COR147
R147
PIR14702 PIR14701 NLDDR0ODT
DDR_ODT

ZQ0

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1

VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
4.75K

B2 POPS0DDR0DQ0
DQ0_A PIU130B2 PS_DDR_DQ0 4[1C]
AA2
PIU130AA2 POPS0DDR0DQ16
DQ0_B PS_DDR_DQ16 4[3A]
POPS0DDR0CAA0 H2
PIU130H2 C2
PIU130C2 POPS0DDR0DQ1
4[1A] PS_DDR_CAA0 CA0_A DQ1_A PS_DDR_DQ1 4[1C]
POPS0DDR0CAA1 J2
PIU130J2 Y2
PIU130Y2 POPS0DDR0DQ17
4[1A] PS_DDR_CAA1 CA1_A DQ1_B PS_DDR_DQ17 4[3B]
POPS0DDR0CAA2 H9 E11 POPS0DDR0DQ10
4[1B] PS_DDR_CAA2 PIU130H9 CA2_A DQ10_A PIU130E11 PS_DDR_DQ10 4[1C]
POPS0DDR0CAA3 H10 V11 POPS0DDR0DQ26
4[1B] PS_DDR_CAA3 PIU130H10 CA3_A DQ10_B PIU130V11 PS_DDR_DQ26 4[3B]
POPS0DDR0CAA4 H11
PIU130H11 F11
PIU130F11 POPS0DDR0DQ11
4[1B] PS_DDR_CAA4 CA4_A DQ11_A PS_DDR_DQ11 4[1C]
POPS0DDR0CAA5 J11
PIU130J11 U11
PIU130U11 POPS0DDR0DQ27
4[1B] PS_DDR_CAA5 CA5_A DQ11_B PS_DDR_DQ27 4[3B]
POPS0DDR0CKA0T J8
PIU130J8 F9
PIU130F9 POPS0DDR0DQ12
4[1B] PS_DDR_CKA_T CK_t_A DQ12_A PS_DDR_DQ12 4[1C]
POPS0DDR0CKA0C J9 U9 POPS0DDR0DQ28
4[1B] PS_DDR_CKA_C PIU130J9 CK_c_A DQ12_B PIU130U9 PS_DDR_DQ28 4[3B]
POPS0DDR0CKE0 J4 E9 POPS0DDR0DQ13
11[2C], 4[1B] PS_DDR_CKE0 PIU130J4 CKE0_A DQ13_A PIU130E9 PS_DDR_DQ13 4[3A]
POPS0DDR0CS00N H4
PIU130H4 V9
PIU130V9 POPS0DDR0DQ29
11[2C], 4[1C] PS_DDR_CS0_N CS0_A DQ13_B PS_DDR_DQ29 4[3B]
DDR_ODT G2
PIU130G2 C9
PIU130C9 POPS0DDR0DQ14
ODT_CA_A DQ14_A PS_DDR_DQ14 4[3A]
POPS0DDR0DMA0 C3
PIU130C3 Y9
PIU130Y9 POPS0DDR0DQ30
4[1C] PS_DDR_DMA0 DMI0_A DQ14_B PS_DDR_DQ30 4[3B]
POPS0DDR0DMA1 C10 B9 POPS0DDR0DQ15
4[1C] PS_DDR_DMA1 PIU130C10 DMI1_A DQ15_A PIU130B9 PS_DDR_DQ15 4[3A]
B AA9 POPS0DDR0DQ31 B
DQ15_B PIU130AA9 PS_DDR_DQ31 4[3B]
E2
PIU130E2 POPS0DDR0DQ2
DQ2_A PS_DDR_DQ2 4[3B]
V2
PIU130V2 POPS0DDR0DQ18
DQ2_B PS_DDR_DQ18 4[3B]
F2
PIU130F2 POPS0DDR0DQ3
DQ3_A PS_DDR_DQ3 4[3B]
U2
POPS0DDR0CAB0 R2 MT53D512M32D2DS-053 AIT:D DQ3_B PIU130U2
F4
POPS0DDR0DQ19
PS_DDR_DQ19
POPS0DDR0DQ4
4[3B]
4[1A] PS_DDR_CAB0 PIU130R2 CA0_B DQ4_A PIU130F4 PS_DDR_DQ4 4[3B]
POPS0DDR0CAB1 P2 PIU130P2 U4
PIU130U4 POPS0DDR0DQ20
4[1A] PS_DDR_CAB1 CA1_B DQ4_B PS_DDR_DQ20 4[3B]
POPS0DDR0CAB2 R9
PIU130R9 E4
PIU130E4 POPS0DDR0DQ5
4[1B] PS_DDR_CAB2 CA2_B DQ5_A PS_DDR_DQ5 4[3B]
POPS0DDR0CAB3 R10
PIU130R10 V4
PIU130V4 POPS0DDR0DQ21
4[1B] PS_DDR_CAB3 CA3_B DQ5_B PS_DDR_DQ21 4[3B]
POPS0DDR0CAB4 R11
PIU130R11 C4
PIU130C4 POPS0DDR0DQ6
4[1B] PS_DDR_CAB4 CA4_B DQ6_A PS_DDR_DQ6 4[3B]
POPS0DDR0CAB5 P11 Y4 POPS0DDR0DQ22
4[1B] PS_DDR_CAB5 PIU130P11 CA5_B DQ6_B PIU130Y4 PS_DDR_DQ22 4[3B]
POPS0DDR0CKB0C P9 B4 POPS0DDR0DQ7
4[1C] PS_DDR_CKB_C PIU130P9 CK_c_B DQ7_A PIU130B4 PS_DDR_DQ7 4[3C]
POPS0DDR0CKB0T P8
PIU130P8 AA4
PIU130AA4 POPS0DDR0DQ23
4[1B] PS_DDR_CKB_T CK_t_B DQ7_B PS_DDR_DQ23 4[3B]
POPS0DDR0CKE0 P4
PIU130P4 B11
PIU130B11 POPS0DDR0DQ8
11[2B], 4[1B] PS_DDR_CKE0 CKE0_B DQ8_A PS_DDR_DQ8 4[3C]
POPS0DDR0CS00N R4
PIU130R4 AA11
PIU130AA11 POPS0DDR0DQ24
11[2B], 4[1C] PS_DDR_CS0_N CS0_B DQ8_B PS_DDR_DQ24 4[3B]
DDR_ODT T2 C11 POPS0DDR0DQ9
PIU130T2 ODT_CA_B DQ9_A PIU130C11 PS_DDR_DQ9 4[3C]
POPS0DDR0DMB0 Y3 Y11 POPS0DDR0DQ25
4[1C] PS_DDR_DMB0 PIU130Y3 DMI0_B DQ9_B PIU130Y11 PS_DDR_DQ25 4[3B]
POPS0DDR0DMB1 Y10
PIU130Y10 E3
PIU130E3 POPS0DDR0DQSA00C
4[1C] PS_DDR_DMB1 DMI1_B DQS0_c_A PS_DDR_DQSA0_C 4[3C]
V3
PIU130V3 POPS0DDR0DQSB00C
DQS0_c_B PS_DDR_DQSB0_C 4[3C]
D3
PIU130D3 POPS0DDR0DQSA00T
DQS0_t_A PS_DDR_DQSA0_T 4[3C]
LAYOUT NOTEs: 1) 40 Ohm Interface impedance. 2) Place W3 POPS0DDR0DQSB00T
DQS0_t_B PIU130W3 PS_DDR_DQSB0_T 4[3C]
DDR within 1 inch of Zynq device. 3) Place decoupling E10 POPS0DDR0DQSA10C
DQS1_c_A PIU130E10 PS_DDR_DQSA1_C 4[3C]
capacitors as close as possible to DDR device. V10
PIU130V10 POPS0DDR0DQSB10C
DQS1_c_B PS_DDR_DQSB1_C 4[3C]
D10
PIU130D10 POPS0DDR0DQSA10T
DQS1_t_A PS_DDR_DQSA1_T 4[3C]
W10
PIU130W10 POPS0DDR0DQSB10T
C DQS1_t_B PS_DDR_DQSB1_T 4[3C] C

R3
PIU130R3 POPS0DDR0CS10N
NC PS_DDR_CS1_N 4[1C]
A8
PIU130A8
NC
N8
NC PIU130N8
N5 COR148
NC PIU130N5 R148
PIR14802 240
PIR14801
K8
PIU130K8 +VCCO_PSDDR
NC
K5
PIU130K5
NC
G11
PIU130G11
NC
H3
NC PIU130H3
COR149
R149
P5 0 POPS0DDR0CKE1
NC PIU130P5 PIR14901 PIR14902 PS_DDR_CKE1 4[1B]
POPS0DDR0RST0N T11
PIU130T11 J5
PIU130J5
4[3C] PS_DDR_RST_N RESET_n NC
PIR150 1
COR150
R150
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
4.75K
PIR150 2
PIU130E1 PIU130E5 PIU130E8 PIU130E2 PIU130G1 PIU130G PIU130G5 PIU130G8 PIU130G PIU130G2 PIU130J1 PIU130J PIU130J PIU130J2 PIU130K2 PIU130K4 PIU130K9 PIU130K PIU130N2 PIU130N4 PIU130N9 PIU130N PIU130P PIU130P PIU130P PIU130P2 PIU130T PIU130T PIU130T5 PIU130T8 PIU130T PIU130T2 PIU130V PIU130V5 PIU130V8 PIU130V2 PIU130W2 PIU130W4 PIU130W9 PIU130W PIU130Y1 PIU130Y5 PIU130Y8 PIU130Y2 PIU130AB PIU130AB5 PIU130AB8 PIU130AB PIU130A PIU130A PIU130C1 PIU130C5 PIU130C8 PIU130C2 PIU130D2 PIU130D4 PIU130D9 PIU130D PS_DDR_CS and CKE signals
E1
E5
E8
E12
G1
G3
G5
G8
G10
G12
J1
J3
J10
J12
K2
K4
K9
K11
N2
N4
N9
N11
P1
P3
P10
P12
T1
T3
T5
T8
T10
T12
V1
V5
V8
V12
W2
W4
W9
W11
Y1
Y5
Y8
Y12
AB3
AB5
AB8
AB10
A3
A10
C1
C5
C8
C12
D2
D4
D9
D11
GND connected to maintain backwards
DDR compatibility.
+VCCO_PSDDR GND
+VCCO_PSDDR +VCC_PSAUX
D D

PIC16 02 PIC1620 PIC16302 PIC16402 PIC16502 PIC16 02 PIC16702 PIC16802 PIC16902 PIC170 2 PIC17 02 PIC1720 PIC160 1C160
COC161
C161 COC162
C162 COC163
C163 COC164
C164 COC165
C165 COC166
C166 COC167
C167 COC168
C168 COC169
C169 COC170
C170 COC171
C171 COC172
C172
COC160
Avnet Engineering Services
PIC16 01 10uF PIC16201 0.47uF PIC16301 4.7uF PIC16401 0.047uFPIC16501 1000pF PIC16 01 1000pF PIC16701 1000pF PIC16801 0.47uF PIC16901 0.047uFPIC170 1 1000pF PIC17 01 1000pF PIC17201 1000pF PIC160 2 0.1uF Project Name: PCB Rev: BOM: Variant:
Ultra96 SBC V2
Doc Num: Date:
1 Time: 01 00
SCH-US1SBC 3/1/2019 7:57:27 AM
Sheet Title: Size: Sheet:
GND GND GND 11 - LPDDR4 Device #1.SchDoc B 11 of 18
1 2 3 4 5 6
 1 2 3 4 5 6

USB 3.0 DUAL PORT HUB

GND

PIC18702 PIC18 02 PIC18902 PIC190 2 PIC18602

A COC187
C187 COC188
C188 COC189
C189 COC190
C190 COC186
C186 A
+VCCO_HP
PIC18701 0.1uF PIC18 01 0.1uF PIC18901 0.1uF PIC190 1 0.1uF PIC18601 1000pF

PIC19202 PIC19302 PIC19402 PIC19502 PIC19 02

COC192
C192 COC193
C193 COC194
C194 COC195
C195 COC191
C191 USB_PORTA_VBUS
PIC19201 0.1uF PIC19301 0.1uF PIC19401 0.1uF PIC19501 0.1uF PIC19 01 1000pF
USB 3.1 CONTROLLER HUB COC196
C196
COJ8
GND PIC19602 PIC19601 J8
150uF 1
PIJ801
VBUS
+3.3V GND USB2D1_N 2
PIJ802 D-
USB2D1_P 3
PIJ803 D+

COU16
U16
PIC19 02 PIC20 02 PIC201 2 PIC20 2 PIC19702 PIC19802 5
PIU1605 4
PIJ804
COC199
C199 COC200
C200 COC201
C201 COC202
C202 COC197
C197 COC198
C198 VDD12 GND GND
12
PIU16012
PIC19 01 0.1uF PIC20 01 0.1uF PIC201 0.1uF PIC20 1 0.1uF PIC19701 1000pF PIC19801 1000pF 15
VDD12
USB_SSTX1_N COC203
C203 8
NLUT10N PIJ808
UT1_N
PIU16015 VDD12 PIC20302 PIC20301 SSTX-
21 37 MIO25_VBUS_DET_LS 0.1uF
PIU16021 VDD12 VBUS_DET/GPIO16 PIU16037
COR156 COC204 NLUT10P PIJ809
28
PIU16028 52
PIU16052 R156
PIR15602 1.00K
PIR15601 USB_SSTX1_P PIC20402 C204
PIC20401 UT1_P 9
VDD12 ATEST GND SSTX+
33 36 ENA_FLT_A 0.1uF
GND DNP +3.3V PIU16033
43
VDD12 PRT_CTL1 PIU16036
35 ENA_FLT_B 7
PIC20502
COC205
C205
PIC20501
PIU16043 VDD12 PRT_CTL2 PIU16035 GND PIJ807 GND_DRAIN
GND 49 34
+3.3V 0.1uF PIU16049 VDD12 PRT_CTL3 PIU16034
16 32 USB_SSRX1_N 5
COY4
Y4 25MHz
PIU16016 VDD33 PRT_CTL4/GANG_PWR PIU16032
COR157
PIJ805 SSRX-
31
PIU16031 56
PIU16056 R157
PIR15702 12.0K
PIR15701
4 VDD33 RBIAS GND
PIY404 44 42 POUSB0RST0N USB_SSRX1_P 6
COR158
R158 1
VDD
3
PIU16044
55
VDD33 RESET_N PIU16042 USB_RST_N 6[2D], 7[1B] PIJ806
SSRX+
11
PIR15802 PIR15801PIY401 OE OUTPUT PIY403 PIU16055 VDD33 COR159 Shield PIJ8011
B 4.75K 2 41 R159 200K 10 B
GND PIY402
COR160 SPI_CE_N/CFG_NON_REM/GPIO7 PIU16041 PIR15901 PIR15902 Shield PIJ8010
DNP R160 0 54 38 COR161
R161 0 POUSB57440SCL
PIR16001 PIR16002 PIU16054 XTALI/CLK_IN SPI_CLK/SMCLK/GPIO4 PIU16038 PIR16101 PIR16102
COR162 USB5744_SCL 13[2D] PIC20602 PIR16302
DSC6101HI2A-025.0000T 53
PIU16053 XTALO SPI_DI/CFG_BC_EN/GPIO9
40
PIU16040 DNP R162
PIR16201 200K
PIR16202 GND
GSB311131HR
DNP DNP 39 COR164
R164 0 COC206
C206 COR163
R163
GND SPI_DO/SMDAT/GPIO5 PIU16039 PIR16401 PIR16402 POUSB57440SDA
POUSB0HUB025MHz
7[3C] USB_HUB_25MHz 1
PIU1601 DNP NLUSB2D10P
USB2D1_P
USB5744_SDA 13[2D] PIC20601 0.1uF 330
COC207 USB2DN_DP1/PRT_DIS_P1 PIR16301
POGTR0LANE30RX0N C207
PIC20702 0.1uF
PIC20701 3RX_N 48
NL3RX0NPIU16048 2 NLUSB2D10N
USB2D1_N
4[5A] GTR_LANE3_RX_N COC208 USB3UP_TXDM USB2DN_DM1/PRT_DIS_M1 PIU1602
POGTR0LANE30RX0P C208 0.1uF NL3RX0PPIU16047
3RX_P 47 8 NLUSB2D20P
USB2D2_P
4[5B] GTR_LANE3_RX_P PIC20802 PIC20801
COC209 NL3TX0N PIU16051 USB3UP_TXDP USB2DN_DP2/PRT_DIS_P2 PIU1608
NLUSB2D20N
POGTR0LANE30TX0N C209 0.1uF 3TX_N 51 9 USB2D2_N
4[5B] GTR_LANE3_TX_N COC210
PIC20902 PIC20901 USB3UP_RXDM USB2DN_DM2/PRT_DIS_M2 PIU1609

POGTR0LANE30TX0P C210 0.1uF

PIC21002 PIC21001 3TX_P 50
NL3TX0P PIU16050 17
PIU16017 POUSB2D30P GND
4[5B] GTR_LANE3_TX_P USB3UP_RXDP USB2DN_DP3/PRT_DIS_P3 USB2D3_P 13[1B]
27
PIU16027 18
PIU16018 POUSB2D30N
USB3DN_TXDM4 USB2DN_DM3/PRT_DIS_M3 USB2D3_N 13[1B]
26 24
PIU16026 USB3DN_TXDP4 USB2DN_DP4/PRT_DIS_P4 PIU16024
20 25
Layout Note: Place R160 pin 2 pad directly on clock trace
PIU16020 USB3DN_TXDM3 USB2DN_DM4/PRT_DIS_M4 PIU16025
19 45 POULPI10D0P
to U16.
PIU16019 USB3DN_TXDP3 USB2UP_DP PIU16045 ULPI1_D_P 7[2B]
NLUSB0SSTX20N
USB_SSTX2_N 11
PIU16011 46
PIU16046 POULPI10D0N
USB3DN_TXDM2 USB2UP_DM ULPI1_D_N 7[2B]
NLUSB0SSTX20P
USB_SSTX2_P 10
PIU16010 USB3DN_TXDP2 USB_PORTB_VBUS
NLUSB0SSTX10N
USB_SSTX1_N 4
PIU1604 USB3DN_TXDM1
PIR16502 PIR16 02
Layout Note: USB GTR LANE 3 differential impedance: 100 NLUSB0SSTX10P
USB_SSTX1_P 3 COR165
R165 COR166
R166
Ohms.
PIU1603 USB3DN_TXDP1 COC211
C211
30 10.00K 10.00K
PIU16030 USB3DN_RXDM4 COJ9
J9
29
PIU16029 USB3DN_RXDP4
PIR16501 PIR16 01 GND PIC21102 PIC21101
150uF 1
23
PIU16023
+3.3V PIJ901 VBUS
USB3DN_RXDM3 USB2D2_N 2
Layout Note: USB SSRX/TX_P/N signals differential 22
PIU16022
PIJ902 D-
USB3DN_RXDP3 USB2D2_P 3
impedance: 85 Ohms. NLUSB0SSRX20N
USB_SSRX2_N 14 PIJ903 D+
NLUSB0SSRX20P
PIU16014 USB3DN_RXDM2
USB_SSRX2_P 13
NLUSB0SSRX10N
PIU16013 USB3DN_RXDP2
USB_SSRX1_N 7
PIU1607 USB3DN_RXDM1 4
NLUSB0SSRX10P
USB_SSRX1_P 6
PIU1606 GND PIJ904 GND
C USB3DN_RXDP1 C
USB_SSTX2_N COC212
C212 NLUT20N PIJ908
UT2_N 8
57 PIC21202 PIC21201 SSTX-
PIU16057 VSS 0.1uF
USB_SSTX2_P COC213
C213 NLUT20P PIJ909
UT2_P 9
USB5744-I/2G PIC21302 PIC21301
SSTX+
0.1uF
GND 7
PIJ907
GND GND_DRAIN
USB_SSRX2_N 5
PIJ905 SSRX-

USB PORT POWER SWITCHES USB_SSRX2_P 6

PIJ906 SSRX+
11
PIJ9011
Shield
10
Shield PIJ9010

+5.0V USB_PORTA_VBUS +5.0V USB_PORTB_VBUS GSB311131HR PIC21402 PIR16702

COC214
C214 COR167
R167
+VCC_PSAUX +3.3V COC215
C215 COC216
C216 COC217
C217 COC218
C218
PIC21502 PIC21501 PIC21602 PIC21601
0.1uF
PIC21702 PIC21701 PIC21802 PIC21801 PIC21401 0.1uF 330
COR168
R168 0.1uF 0.1uF 0.1uF PIR16701
PIR16801 PIR16802 PIR16901
10.00K
PIQ140 COR169
R169
COU17
GND GND
1

COQ14
Q14 10.00K U17 COU18
U18
G

PIR16902 NLMIO250VBUS0DET0LS 6 1 6 1 GND

MIO25_VBUS_DET_LS
2

PIU1706 PIU1701
POMIO250VBUS0DET
3[2A], 7[3B] MIO25_VBUS_DET PIQ1402 PIQ1403 VIN VOUT PIU1806 VIN VOUT PIU1801
S

BSS138-7-F
2 3 NLENA0FLT0A
PIU1703 ENA_FLT_A 2 3 ENA_FLT_B
NLENA0FLT0B
PIR170 2 PIU1702 ILIMIT FAULT/ PIU1802 ILIMIT FAULT/ PIU1803
COR170
PIR17 02
R170 4
PIU1704 5
PIU1705
COR171
R171 4 5
D 191 ENABLE GND PIU1804 ENABLE GND PIU1805 D
7
PIU1707 191 7
PIR170 1 EP EP PIU1807
Layout Notes:
PIR17 01 1) USB 2.0 ULPI_D_P/N signals differentially routed @ 90
MIC2009YML-TR
GND
MIC2009YML-TR
GND
ohms. 2) USB 3.0 SSTX*/RX*_P/N routed @ 85 ohms
differential. 3) ULPI_VBUS >30 mil thick trace for current.
Avnet Engineering Services
GND GND Project Name: PCB Rev: BOM: Variant:
Ultra96 SBC V2
Doc Num: Date:
1 Time: 01 00
SCH-US1SBC 3/1/2019 7:57:27 AM
Sheet Title: Size: Sheet:
12 - USB 3.0 Dual Port Hub.SchDoc B 12 of 18
1 2 3 4 5 6
 1 2 3 4 5 6

I/O EXPANSION HEADERS, ON/OFF CONTROLLER

60 PIN HS EXP HDR 40 PIN LS EXP HDR
COJ4
J4 GND COJ5
J5 GND
5177983-2 55510-140LF
A A
POMIO110SPI10MOSI 1 2 POCSI00C0P 1 2
3[2B] MIO11_SPI1_MOSI PIJ401 PIJ402 CSI0_C_P 8[6B] PIJ501 PIJ502
3 4 POCSI00C0N POHD0GPIO00 3 4 PWR_PB_N
PIJ403 PIJ404 CSI0_C_N 8[6B] 8[3B] HD_GPIO_0 PIJ503 PIJ504
5
PIJ405 6
PIJ406 POHD0GPIO01 5
PIJ505 6
PIJ506 POPOWER0GOOD
8[3B] HD_GPIO_1 POWER_GOOD 15[2C], 16[1C], 17[2B], 3[4D], 6[1D], 9[1B]
POMIO90SPI10CS 7
PIJ407 8
PIJ408 POCSI00D00P POHD0GPIO02 7
PIJ507 8
PIJ508 POMIO380SPI00SCLK
3[2B] MIO9_SPI1_CS CSI0_D0_P 8[6B] 8[3B] HD_GPIO_2 MIO38_SPI0_SCLK 3[4B]
POMIO60SPI10SCLK 9
PIJ409 10
PIJ4010 POCSI00D00N POHD0GPIO03 9
PIJ509 10
PIJ5010 POMIO420SPI00MISO
3[2B] MIO6_SPI1_SCLK CSI0_D0_N 8[6B] 8[3B] HD_GPIO_3 MIO42_SPI0_MISO 3[4A]
POMIO100SPI10MISO 11
PIJ4011 12
PIJ4012 POHD0GPIO04 11
PIJ5011 12
PIJ5012 POMIO410SPI00CS
3[2B] MIO10_SPI1_MISO 8[3B] HD_GPIO_4 MIO41_SPI0_CS 3[4A]
13 14 POCSI00D10P POHD0GPIO05 13 14 POMIO430SPI00MOSI
PIJ4013 PIJ4014 CSI0_D1_P 8[6B] 8[3B] HD_GPIO_5 PIJ5013 PIJ5014 MIO43_SPI0_MOSI 3[4A]
POCSI00MCLK 15
PIJ4015 16
PIJ4016 POCSI00D10N LSEXP_I2C0_SCL 15
PIJ5015 16
PIJ5016 POHD0GPIO09
8[3B] CSI0_MCLK CSI0_D1_N 8[6A] HD_GPIO_9 8[3B]
POCSI10MCLK 17
PIJ4017 18
PIJ4018 LSEXP_I2C0_SDA 17
PIJ5017 18
PIJ5018 POHD0GPIO010
8[3B] CSI1_MCLK HD_GPIO_10 8[3B]
19
PIJ4019 20
PIJ4020 POCSI00D20P LSEXP_I2C1_SCL 19
PIJ5019 20
PIJ5020 POHD0GPIO011
CSI0_D2_P 8[6C] HD_GPIO_11 8[3B]
PODSI0CLK0P 21
PIJ4021 22
PIJ4022 POCSI00D20N LSEXP_I2C1_SDA 21
PIJ5021 22
PIJ5022 POHD0GPIO012
8[6C] DSI_CLK_P CSI0_D2_N 8[6C] HD_GPIO_12 8[3B]
PODSI0CLK0N 23 24 POMIO360PS0GPIO100 23 24 POMIO370PS0GPIO101
8[6C] DSI_CLK_N PIJ4023 PIJ4024 3[4B] MIO36_PS_GPIO1_0 PIJ5023 PIJ5024 MIO37_PS_GPIO1_1 3[4B]
25 26 POCSI00D30P POMIO390PS0GPIO102 25 26 POMIO400PS0GPIO103
PIJ4025 PIJ4026 CSI0_D3_P 8[6C] 3[4B] MIO39_PS_GPIO1_2 PIJ5025 PIJ5026 MIO40_PS_GPIO1_3 3[4B]
PODSI0D00P 27
PIJ4027 28
PIJ4028 POCSI00D30N POMIO440PS0GPIO104 27
PIJ5027 28
PIJ5028 POMIO450PS0GPIO105
8[6C] DSI_D0_P CSI0_D3_N 8[6C] 3[4A] MIO44_PS_GPIO1_4 MIO45_PS_GPIO1_5 3[4A]
PODSI0D00N 29
PIJ4029 30
PIJ4030 POHD0GPIO06 29
PIJ5029 30
PIJ5030 POHD0GPIO013
8[6C] DSI_D0_N 8[3A] HD_GPIO_6 HD_GPIO_13 8[3B]
31
PIJ4031 32
PIJ4032 HSEXP_I2C2_SCL POHD0GPIO07 31
PIJ5031 32
PIJ5032 POHD0GPIO014
8[3A] HD_GPIO_7 HD_GPIO_14 8[3A]
PODSI0D10P 33 34 HSEXP_I2C2_SDA POHD0GPIO08 33 34 POHD0GPIO015
8[6B] DSI_D1_P PIJ4033 PIJ4034 8[3B] HD_GPIO_8 PIJ5033 PIJ5034 HD_GPIO_15 8[3B]
PODSI0D10N 35 36 HSEXP_I2C3_SCL 35 36
8[6B] DSI_D1_N PIJ4035 PIJ4036 PIJ5035 PIJ5036
COD18
D18
37
PIJ4037 38
PIJ4038 HSEXP_I2C3_SDA 37
PIJ5037 38
PIJ5038 2
PID1802 1
PID1801
COC65 +5.0V COC66 COC67 +VSYS_IN
PODSI0D20P 39
PIJ4039 40
PIJ4040 C65 PIC6601 C66
PIC6602 39
PIJ5039 40
PIJ5040 C67
PIC6701 PIC6702
8[6B] DSI_D2_P +VCC_PSAUX PIC6501 PIC6502
PODSI0D20N 41
PIJ4041 42
PIJ4042 POCSI10D00P 0.1uF 0.1uF 0.1uF DB2F43100L1
8[6B] DSI_D2_N CSI1_D0_P 8[6B]
43 44 POCSI10D00N
PIJ4043 PIJ4044 CSI1_D0_N 8[6B]
PODSI0D30P 45 46
8[6B] DSI_D3_P PIJ4045 PIJ4046

PODSI0D30N 47
PIJ4047 48
PIJ4048 POCSI10D10P GND GND GND
B 8[6B] DSI_D3_N CSI1_D1_P 8[6B] B
49
PIJ4049 50
PIJ4050 POCSI10D10N
CSI1_D1_N 8[6B]
POUSB2D30P 51
PIJ4051 52
PIJ4052
12[4B] USB2D3_P
POUSB2D30N 53 54 POCSI10C0P
12[4B] USB2D3_N PIJ4053
55
PIJ4055
PIJ4054
56
PIJ4056
CSI1_C_P
POCSI10C0N
CSI1_C_N
8[6C]
8[6C]
POWER BUTTON
POHSIC0STR 57 58
8[3C] HSIC_STR
POHSIC0DATA
8[6B] HSIC_DATA
PIJ4057
59
PIJ4059
PIJ4058
60
PIJ4060
COR70
R70PIR7002 100K
PIR7001
+VCC_PSAUX
-
COSW4
SW4 ON/OFF CONTROLLER
1
PISW401 4
PISW404
COR71
R71
PIR7101
0
PIR7102
Female/Receptacle 2
PISW402 3
PISW403 PIC6902 +3V3_PRI
COC69
C69 +3V3_PRI +VCC_PSAUX
COC68
C68
GND GND
Design Note: PB_N has 100K internal PIC6901 0.1uF PIC6802 PIC6801
0.1uF
GND
pullup to VCC. KILL_N is floating and
must be pulled up to Vccio +1.8V value
(as shown). GND GND
1PIU601 PIR7202
COR72
R72
4.99K
PIR7302
COR73
R73
4.99K
VDD PIR7201 PIR7301 COR74
+3V3_PRI NLPWR0PB0N 3
PWR_PB_NPIU603 12
PIU6012 R74PIR7401 0
PIR7402 POEN0SEQ0PL
PB_N EN EN_SEQ_PL 15[2B], 16[1B], 17[2B]
COC248
C248
PIC24802 PIC24801 GND 10 11 POMIO260PWR0INT
PIU6010 KILL_N INT PIU6011 MIO26_PWR_INT 3[4B]
I2C EXPANDER (+1.8V)
0.1uF
+3V3_PRI COJT6
+VCC_PSAUX COR194 JT6
R194
COU23 PIR19402 4.99K
PIR19401 2 3
+0.4Vref U23 PIU602 NC PIJT603 USER NOTE: JT6 configures the board
5 4
+VCC_PSAUX +VCC_PSAUX
COR84
R84
PIR8402 4.99K
PIR8401 3
PIU2303
6PIU2306 COR75
0
PIU605
6
NC INIT PIU604
power up operation.
Vcc 1 R75 PIU606 NC
COR195
R195 4 Gnd
PIU2301 PIR7501 PIR7502
PIC24901 7
PIU607 2
PIJT602
Position 1-2 (default): user must press
POMIO340POWER0KILL0N NC
2PIU2302
3[4B] MIO34_POWER_KILL_N PIR19502 PIR19501 PIU2304
TS331IQT COC249 8 Power On switch. Position 2-3: board
PIR7602 PIR7 02 PIR7802 PIR7902 PIR80 2 PIR8102 PIR8202 PIR8302 499 PIC250 1 C249 PIU608
13
NC
C COR76
R76 COR77
R77 COR78
R78 COR79
R79 COR80
R80 COR81
R81 COR82
R82 COR83
R83 COC250
C250 PIC24902 0.1uF PIU6013 NC powers up when power applied. C
2.21K 2.21K 2.21K 2.21K 2.21K 2.21K 2.21K 2.21K PIC250 2 0.1uF 14
PIU6014 9
PIU609 1
PIJT601
COU7
U7 NC GND
NLLSEXP0I2C00SCL
LSEXP_I2C0_SCL
PIR7601 PIR7 01 PIR7801 PIR7901 PIR80 1 PIR8101 PIR8201 PIR8301 2 21 COC70
C70 COU6
PIU702 SC0 VCC PIU7021 PIC7002 PIC7001 GND U6 10K (1-2)
NLLSEXP0I2C00SDA
LSEXP_I2C0_SDA 1 0.1uF GND
PIU701 SD0 SLG4G42480V
GND GND GND
NLLSEXP0I2C10SCL
LSEXP_I2C1_SCL 4
PIU704 SC1
NLLSEXP0I2C10SDA
LSEXP_I2C1_SDA 3
PIU703 SD1
NLHSEXP0I2C20SCL
HSEXP_I2C2_SCL 6 19
NLHSEXP0I2C20SDA
PIU706 SC2 SCL PIU7019 POMIO40I2C10SCL
MIO4_I2C1_SCL 3[2B]
HSEXP_I2C2_SDA 5 20 POMIO50I2C10SDA +0.4Vref
PIU705
SD2 SDA PIU7020
MIO5_I2C1_SDA 3[2B]
+3.3V +VCC_PSAUX COR196
R196 COR197
R197
NLHSEXP0I2C30SCL
HSEXP_I2C3_SCL 8 COR85
R85 4.99K +3V3_PRI PIR19602 PIR19601 PIR19702 PIR19701
NLHSEXP0I2C30SDA
HSEXP_I2C3_SDA
PIU708
7
PIU707
SC3
SD3
PIR8502

COR86
R86
PIR8501

4.99K
PIR9401
COR94
PIR9302
COR93
R93
PIR9301
2.21K 2 PIU2402 COU24
U24
825
PIR19802
COR198
PIR8602 PIR8601 +VCC_PSAUX R94 R198
NLPMIC0SCL
PMIC_SCL 11 10.00K PIQ1301 2.21K 1
PIU2401 REF

1
PIU7011
SC4 COR87
R87 4.99K COQ13 392

G
NLPMIC0SDA
PMIC_SDA 10 Q13
PIU7010 SD4
PIR8702 PIR8701
PIR9402 PMIC_SDA TLVH431BIL3T PIR19801

2
POPMBUS0SDA
15[2C], 16[1C], 17[2C], 9[1D] PMBUS_SDA PIQ1303 PIQ1302

S
D
COTP32 13 24 POMIO120I2C0MUX0RESET0N
TP32 PITP3201 PIU7013 SC5 RST# PIU7024 MIO12_I2C_MUX_RESET_N 3[2B] BSS138-7-F
COTP33 12
TP33 PITP3301 PIU7012

15
PIU7015
SD5

SC6
A0
A1
22
PIU7022
23
PIU7023
COR90PIR9002
R90
COR91PIR9102
R91
4.99K
PIR9001
4.99K
PIR9101
+VCC_PSAUX
+3.3V +VCC_PSAUX
3 PIU2403 GND
14
PIU7014 18
PIU7018
COR92PIR9202
R92 4.99K
PIR9201
SD6 A2 COR88
PIR8901 R88
PIR8802 PIR8801
POUSB57440SCL 17 COR89 GND
12[4B] USB5744_SCL PIU7017 SC7 R89 2.21K
POUSB57440SDA 16 9 10.00K PIQ1201
1
PIU7016 PIU709
D 12[4B] USB5744_SDA SD7 GND D

G
25
PAD PIU7025 GND PIR8902 COQ12Q12
3
PMIC_SCL

2
POPMBUS0SCL
15[2C], 16[1C], 17[2C], 9[1D] PMBUS_SCL PIQ1203 PIQ1202

S
D

TCA9548ARGER
GND
BSS138-7-F Avnet Engineering Services
Project Name: PCB Rev: BOM: Variant:
Ultra96 SBC V2
Doc Num: Date:
1 Time: 01 00
SCH-US1SBC 3/1/2019 7:57:27 AM
Sheet Title: Size: Sheet:
13 - Jx_Jy Expansion Headers, Power On.SchDoc B 13 of 18
1 2 3 4 5 6
 1 2 3 4 5 6

DISPLAY PORT VREG Mini DISPLAY PORT

+5.0V
DNP DNP
PIC7102
COC71
C71
PIC7101
COU8
U8 COD11
D11 +3V3_DP
GND MAX8902BATA+T
0.1uF MBRS240LT3G
1
PIU801 8
PIU808 2
PID1102 1
PID1101
IN OUT PIR9601 PIC7202COC72 PIC7302COC73
DNP COR96 C72 C73
COR95
R95 1.00K 3 7 C74COC74 R96
A PIR9502 PIR9501 PIU803 EN BYP PIU807 PIC7402 PIC7401 DNP A
DNP 0.1uF 18.2K PIC720110uF PIC730110uF
+3.3V FB
6
PIU806
PIR9602 DNP DNP DNP
COD12
D12
COR97
R97 240 PID1202
2 1PIU805
5 4
PIR9701 PIR9702 PID1201 POK GS PIU804
PIR9802 GND GND
DNP EP GND COR98
R98
DNP DNP
9PIU809 2PIU802 4.02K
PIR9801

GND GND

DISPLAY PORT
DPAUX GENERATOR DISPLAY PORT CONNECTOR +3V3_DP
+3.3V
COJ6 C75 COC75
PIC7502 PIC7501
J6 GND 0.1uF
B PIC7601 PIR9 02 2129320-3 B
COR99
R99
+VCC_PSAUX +3.3V COC76
C76 2.49K
PIC7602 0.1uF
PIR9 01 POGTR0LANE10TX0P
4[5B] GTR_LANE1_TX_P
COC77
C77
PIC7702 0.1uF
PIC7701 G1_P 3PIJ603
ML_LANE0_P DP_PWR
20
PIJ6020
COC78
C78
PIC7802 PIC7801
COC79
C79
PIC7902 PIC7901 COC80
C80 PIC8001
0.1uF G1_N 5PIJ605
POGTR0LANE10TX0N
4[5B] GTR_LANE1_TX_N PIC8002 ML_LANE0_N
0.1uF 0.1uF PIR10 1 POGTR0LANE00TX0P
4[5B] GTR_LANE0_TX_P
COC81
C81 0.1uF
PIC8102 PIC8101 G0_P 9PIJ609
ML_LANE1_P GND1
1
PIJ601
COU9
U9 COR100
R100 COC82
C82 PIC8201
0.1uF G0_N 11PIJ6011 7
GND 1.50K POGTR0LANE00TX0N
4[5B] GTR_LANE0_TX_N PIC8202 ML_LANE1_N GND2 PIJ607
COU10
U10 GND FIN1019MTCX 15PIJ6015 8
PIR10 2 ML_LANE2_P GND3 PIJ608
3 2 DP_RE_NPIU901
1 14 17PIJ6017 13
PIU1003 VCCA VCCB PIU1002 DE VCCPIU9014 ML_LANE2_N GND4 PIJ6013
10PIJ6010 14
PIJ6014
COR101 ML_LANE3_P GND5
POMIO270DP0AUX0OUT 6
PIU1006 15 2 13 R101 100K 12PIJ6012 19
3[4B] MIO27_DP_AUX_OUT 1A1 1B1 PIU10015 PIU902
DIN NCPIU9013 GND PIR10102 PIR10101
ML_LANE3_N GND6 PIJ6019
GND
1
PIU1001 4 COR102
R102
PIU1004PIR10202 10.00K
PIR10201 3
PIU903 12
PIU9012 PIC8301
COC83
C83
PIC8302
NLDPAUX0C0P
DPAUX_C_P 16PIJ6016
1/OE 1DIR +3.3V NC DOUT+ AUX_CH_P
COR103
R103 0.1uF 18PIJ6018 GND
NLDP0RE0N PIR10301 PIR10302 AUX_CH_N
POMIO290DP0OE 7 14 DP_RE_N 4 11 21
3[4B] MIO29_DP_OE PIU1007
1A2 1B2 PIU10014 PIU904 ROUT DOUT- PIU9011
PIR105 2 49.9 COR104 SHLD1 PIJ6021
R104
PIR10402 1M
PIR10401 4PIJ604 22
PIJ6022
COR105
R105 COR106 CONFIG1 SHLD2
5
PIU905 10 GND R106 1M 6PIJ606 23
NC RIN+ PIU9010 49.9
PIR10602 PIR10601 CONFIG2 SHLD3 PIJ6023
24
PIJ6024
PIR105 1 COC84 NLDPAUX0C0N COR107
R107 SHLD4
POMIO300DP0AUX0IN 8 13 6 9 C84 DPAUX_C_N DP_HPD_LS PDE 2PIJ602
3[4B] MIO30_DP_AUX_IN PIU1008 2A1 2B1 PIU10013 PIU906 NC RIN- PIU909 PIC8401 PIC8402
0.1uF
PIR10701 PIR10702 HOTPLUG_DET
COR108
10 PIR109 1
16
PIU10016
2/OE
5
2DIR PIU1005 PIU907 7
GND
8
/REPIU908
DP_RE_N
+3V3_DP
R108
PIR10802 100K
PIR10801 COR109
R109 PIC25902
100K COC259
C259 COR110
0
NLDP0HPD0LS R110
POMIO280DP0HPD
3[4B] MIO28_DP_HPD
9
PIU1009 2A2
12
2B2 PIU10012
DP_HPD_LS PIR109 2 PIC25901 1000pF
PIR11002 PIR11001

GND DNP
10 11
PIU10010 GND GND PIU10011
C GND SH_GND1 C
SN74AVC4T245RSVR
GND
GND GND

Layout Note:
All Display Port data signals (GTR_LANE0,1_TX_P/N,
G0,1_P/N) differentially routed to @ 100 ohms. Trace length
ESD PROTECTION DEVICES match to within 5 mils.

Layout Note: Board edge PCB cut-out

COD13
D13 under this device! See datasheet.
IP4283CZ10-TBR,115 COD14
D14
DPAUX_C_P 1 6
I/O1
PID1401 I/O4PID1406
5
PID1405 2
+3V3_DP Vp GNDPID1402 GND
NLG10P DPAUX_C_N 3 4 NLPDE
PDE
G1_P 1 2 4 5 PID1403I/O2 I/O3PID1404
PID1301 CH1 PID1302 CH2 PID1304 CH3 PID1305 CH4
PIC8502
COC85 IP4220CZ6,125
C85
PIC8501 0.1uF

D
NLG10N
G1_N
NLG00P
G0_P
PID1308 GND
3,8
GND
D
NLG00N
G0_N

GND Avnet Engineering Services

Project Name: PCB Rev: BOM: Variant:
Ultra96 SBC V2
Doc Num: Date:
1 Time: 01 00
SCH-US1SBC 3/1/2019 7:57:27 AM
Sheet Title: Size: Sheet:
14 - Display Port.SchDoc B 14 of 18
1 2 3 4 5 6
 1 2 3 4 5 6

ROCKY PMIC #1

VIN_A VIN_B VIN_C VIN_D

+5.0V +5.0V +5.0V +5.0V
A A
2C91 PIC8602C86
PIC910COC91 02
COC86 PIC251C251
COC251 PIC9202C92 1
COC92 PIC870COC87
C87 2
PIC2520C252
COC252 PIC9302C93 02
COC93 PIC8COC88
C88 PIC25302C253
COC253 1
PIC890COC89
C89 PIC90COC90 2
2C90 PIC2540COC254
C254
PIC910122uF PIC86011uF PIC25100.1uF PIC9201 22uF PIC871uF
02 1
PIC25200.1uF PIC930122uF PIC81uF
01 PIC253010.1uF 2
PIC89047uF 1
PIC90 11uF PIC25400.1uF

GND GND GND GND

+5.0V
COC94
C94
PIC9402 PIC9401
10uF CHA: +1.8V VCCAUX, 0.5A
PIU1049 PIU1039 PIU1032 PIU102 PIU103 PIU104 PIU10 PIU102 PIU103 PIU102 +BOOT1_A PIC9501
COC95
C95
PIC9502

49

39

32

12

13

14

22
COU11
U11 0.1uF

3
GND COL1 +VCCAUX
L1
+5.0V CONT1
NT1 +1V8_FB1

VSUPPLY

VIN_A

VIN_B

VIN_C1

VIN_C2

VIN_C3

VIN_D1

VIN_D2

VIN_D3

VIN_LDO
PIL101 PIL102 PINT101
PINT102
48 +SW1_A
PIU11048 VCC 2.2µH 2.1A
SRP2512-2R2M
PIC9602C96
COC96 PIC9802C98
COC98 PIC9 02C99
COC99 PIC9702COC97
C97
COR111
R111
PIR11101 2
PIR11102 47
PIU11047 43
VDRV PWM_A PIU11043
PIC10 02 PIC10102 PIC9601100uF PIC980122uF PIC9 01 2.2uF PIC9701 0.1uF
COC100
C100 COC101
C101 PIC10201
COC102 21
C102
PIC10202 PIU11021 1V8 38
PIU11038
PIC10 01 2.2uF PIC10101 2.2uF GND BOOT_A +BOOT1_A GND
2.2uF
36
PHASE_A1 PIU11036 +SW1_A
B GND_ANA GND 42
PIU11042 37
PIU11037 C103 COC103 CHB: +1.2V VCCO, 2.0A B
+3V3_PRI EN_A PHASE_A2 +BOOT1_B PIC10301 PIC10302
0.1uF
44 46 COL2 +VCCO_HP
PIU11044 EN_B ISEN_A+ PIU11046 L2
PIR1 302 PIR1 20 PIL201 PIL202
CONT2
NT2
PINT201
PINT202 +1V2_FB
COR113 51 45 COR112
R112 +SW1_B
R113 PIU11051 EN_C ISEN_A- PIU11045 0 1.0µH 3.4A
49.9K SRP2512-1R0M PIC104 2C104
COC104 2
PIC1060C106
COC106 PIC107 2C107
COC107 PIC105 2COC105
C105
PIR1 301 DNP 53
PIU11053 EN_D RTN_A
40
PIU11040
PIR1 201 DNP GND
0
1
PIC104 1100uF PIC106022uF PIC107 12.2uF PIC105 10.1uF
POEN0SEQ0PL COR114
R114 28 41 NL01V80FB1
+1V8_FB1
13[6C], 16[1B], 17[2B] EN_SEQ_PL PIR11401 PIR11402 PIU11028 EN_L FB_A PIU11041 GND
COC108
C108
PIC10802 PIC10801 33
PIU11033
0.1uF BOOT_B +BOOT1_B
26 34 COC109
C109
CHC: +1.1V VCCO PSDDR, 1.0A
GND PIU11026 PG_A PHASE_B1 PIU11034 +SW1_B +BOOT1_C PIC10901 PIC10902
0.1uF +VCCO_PSDDR
30 35 COL3
L3
COR115 0 PIU11030 PG_B PHASE_B2 PIU11035
CONT3
NT3
POPOWER0GOOD R115
PIR11502 PIR11501 +1V1_FB
13[5A], 16[1C], 17[2B], 3[4D], 6[1D], 9[1B] POWER_GOOD NL01V20FB +SW1_C PIL301 PIL302 PINT301
PINT302
27
PIU11027 31
PIU11031 +1V2_FB 2.2µH
PG_C FB_B 2.1A
SRP2512-2R2M 2
PIC1 0C110
COC110 PIC1 20C112
COC112 PIC1 302C113
COC113 PIC1 02COC111
C111
16 11
PIU11016 PG_D BOOT_C PIU11011 +BOOT1_C
1
PIC1 0100uF 1
PIC1 2022uF PIC1 301 2.2uF PIC1 01 0.1uF
COR116
R116
PIR11601 49.9K PIU11025
PIR11602 25 8
PIU1108
+VCC_PSAUX PG_L PHASE_C1 +SW1_C GND
+3V3_PRI
9
PIU1109
COR117 PHASE_C2
R117
PIR11701 4.75K
PIR11702 CHD: 0.85V, 3.0A
20 10 C114 COC114
DNP +3V3_PRI PIU11020 VDDIO PHASE_C3 PIU11010
+BOOT1_D PIC11401 PIC11402
C COR118 0.1uF +VCCINT C
R118
PIR11801 4.75K
PIR11802 NL01V10FB
FB_C
15
PIU11015 +1V1_FB COL4
L4
DNP COR119
R119 22.1 18 CONT4
NT4 +0V85_FB1
POPMBUS0SCL
13[1D], 16[1C], 17[2C], 9[1D] PMBUS_SCL PIR11901 PIR11902 PIU11018 CLK +SW1_D PIL401 PIL402 PINT401
PINT402
4
PIU1104 1.0µH
BOOT_D +BOOT1_D
POPMBUS0SDA
13[1D], 16[1C], 17[2C], 9[1D] PMBUS_SDA
19
PIU11019 DATA SRP4020FA-1R0M 2COC115
PIC1 50C115 1
0C116
PIC1 6COC116 PIC1 702COC117
C117
5
PHASE_D1 PIU1105 +SW1_D
POMIO770PWR0ALERT0N
16[1C], 17[2C], 3[6A] MIO77_PWR_ALERT_N
COR120
R120PIR12002
0
PIR12001 17
PIU11017
ALERT#
1
PIC1 50220uF PIC1 60247uF PIC1 7010.1uF
6
PIU1106
COR121 COC118 PHASE_D2 GND
R121
PIR12101 10.00K
PIR12102
C118
PIC11801 10000pF
PIC11802
+VCC_PSAUX 7
COR122 PHASE_D3 PIU1107
R122 2.32K 55
PIR12201 PIR12202 PIU11055 ADDR_PROT NL00V850FB1
56
PIU11056 +0V85_FB1
COR123 FB_D CH_LDO: +3.3V DISPLAY PORT, 0.5A
R123
PIR12301 10.00K PIU11052
PIR12302 52
GND_ANA SYNC_CLK +3V3_D
COD15
D15 +3V3_DP
COR124
R124 10.00K 29 23 2 1 +3V3_D
+5.0V PIR12401 PIR12402 PIU11029 SLEEP# VO_LDO PIU11023
PID1502 PID1501
MSS2P3-M3/89A
COR125
R125 2.32K 54 24 NL03V30FB
+3V3_FB COR126
R126 +3V3_FB
PIR12501 PIR12502 PIU11054
GND_ANA MTP FB_L PIU11024 PIR12601 PIR12602
5.62K PIR12702
PIC11901
COC119
C119
PIC11902 2
0C121
PIC12 COC121 PIC120 2 C120
COC120 COR127
R127
10000pF AGND GND 1.00K

I2C Address Offset = +3.

50
PIU105 57
PIU1057 IRPS5401MTRPBF 1
PIC12 022uF PIC120 1 0.1uF PIR12701

Address: 0x13, 0x43. COR128

R128PIR12801 PIR12802
0
GND
D D
COC122PIC12202
C122 0.1uF
NOTE: MTP resistor set PIC12201

to allow +3 address skip. DNP Avnet Engineering Services

Project Name: PCB Rev: BOM: Variant:
GND_ANA GND
Ultra96 SBC V2
Doc Num: Date:
1 Time: 01 00
SCH-US1SBC 3/1/2019 7:57:28 AM
Sheet Title: Size: Sheet:
15 - Rocky PMIC #1.SchDoc B 15 of 18
1 2 3 4 5 6
 1 2 3 4 5 6

ROCKY PMIC #2
COC123
C123
CHA: +1.8V VCCPSAUX, 1.0A
PIC12301 PIC12302
+BOOT2_A
VIN_A VIN_B VIN_C VIN_D 0.1uF +VCC_PSAUX
COL5
L5
+5.0V +5.0V +5.0V +5.0V CONT5
NT5 +1V8_FB2
+SW2_A PIL501 PIL502 PINT501
PINT502

A 2.2µH 2.1A A
2C129 PIC130COC130
PIC1290COC129 2 2
0C255
PIC25 COC255 PIC13 02C131
2
PIC1270C127
COC127 2COC134
PIC1340C134 2
0C135
PIC135COC135 2
0C128
PIC128COC128
C130 1
COC131 PIC1240COC124
C124 PIC25602C256
COC256 PIC132COC132 02
0C132 PIC13COC133
C133 PIC25702C257
COC257 2
01C125 PIC1260COC126
PIC125COC125 PIC25802COC258
C126 C258
SRP2512-2R2M

PIC1290122uF PIC130 1uF

1 PIC25 010.1uF 02
PIC13 01 22uF PIC1241uF PIC256010.1uF 01
PIC1320122uF PIC13 1uF PIC257010.1uF
1
PIC1270100uF 1
PIC134022uF PIC135012.2uF PIC128010.1uF
1
PIC1250247uF PIC12601uF PIC258010.1uF
GND

GND GND GND GND

+5.0V
COC136
C136
PIC13602 PIC13601
10uF

PIU12049 PIU12039 PIU1203 PIU120 PIU1203 PIU1204 PIU120 PIU120 PIU1203 PIU120 COC137 CHB: +0.85V PSINT_LP, 0.3A

49

39

32

12

13

14

22
COU12
U12 C137

3
GND +BOOT2_B PIC13701 PIC13702
0.1uF +VCC_PSINTLP
+5.0V COL6
L6

VSUPPLY

VIN_A

VIN_B

VIN_C1

VIN_C2

VIN_C3

VIN_D1

VIN_D2

VIN_D3

VIN_LDO
48 CONT6
NT6 +0V85_FB2
PIU12048 VCC +SW2_B PIL601 PIL602 PINT601
PINT602

COR129 2.2µH 2.1A

R129
2 PIR12901
PIC1420COC142
2
PIR12902
PIC14302COC143
47
PIU12047 VDRV PWM_A
43
PIU12043
SRP2512-2R2M
PIC13802C138
COC138 2
PIC140C140
COC140 2
0C141
PIC14 COC141 2COC139
PIC1390C139
C142 C143
COC144
C144PIU12021 21 38 PIC13801100uF PIC14022uF
1 PIC14 012.2uF 1
PIC13900.1uF
1
PIC14202.2uF PIC143012.2uF GND PIC14401 PIC14402 1V8 BOOT_A PIU12038 +BOOT2_A
2.2uF
36
PIU12036
GND
PHASE_A1 +SW2_A
GND_ANA1 GND 42
PIU12042 37
PIU12037
+3V3_PRI EN_A PHASE_A2
B B
44 46
PIU12044 EN_B ISEN_A+ PIU12046
PIR13 02 PIR130 2
COR131
R131 51
PIU12051 45
PIU12045
COR130
R130
EN_C ISEN_A- 0
49.9K
PIR13 01 DNP 53
PIU12053 EN_D RTN_A
40
PIU12040
PIR130 1 DNP GND
COR132 0 NL01V80FB2
COC145
C145
PIC14501 PIC14502
CHC: +3.3V VCCO, 1.4A
POEN0SEQ0PL R132
PIR13201 PIR13202 28
PIU12028 41
PIU12041 +1V8_FB2 +BOOT2_C
13[6C], 15[2B], 17[2B] EN_SEQ_PL EN_L FB_A 0.1uF +3.3V
COC146
C146 COL7
L7
PIC14602 PIC14601 33
PIU12033 COR133 CONT7
NT7
0.1uF BOOT_B +BOOT2_B PIL701 PIL702 R133
PIR13301 249 PINT701PINT702
PIR13302 +3V3_VCFB
+SW2_C
GND
26
PIU12026 PG_A PHASE_B1
34
PIU12034 +SW2_B
2.2µH 2.1A
2
PIC1470C147 2
PIC150C150 PIC14802C148 PIC14902C149 PIR13402
SRP2512-2R2M COC147 COC150 COC148 COC149 COR134
R134
30 35 249
COR135 0 PIU12030
PG_B PHASE_B2 PIU12035 1
PIC1470100uF 1
PIC15022uF PIC148012.2uF PIC149010.1uF PIR13401
POPOWER0GOOD
13[5A], 15[2C], 17[2B], 3[4D], 6[1D], 9[1B] POWER_GOOD R135
PIR13502 PIR13501
27 31 NL00V850FB2
+0V85_FB2 GND
PIU12027 PG_C FB_B PIU12031

16
PIU12016 11
PIU12011
PG_D BOOT_C +BOOT2_C
COR136
R136
PIR13601 25
49.9K PIU12025
PIR13602 8
PIU1208
+VCC_PSAUX PG_L PHASE_C1 +SW2_C

PHASE_C2
9
PIU1209
PIC15101
COC151
C151
PIC15102
CHD: +0.85V PSINT_FP 3.0A
+BOOT2_D
20 10 0.1uF +VCC_PSINTFP
PIU12020 PIU12010
+3V3_PRI VDDIO PHASE_C3 COL8
L8
CONT8
NT8 +0V85_FB3
C 15
PIU12015
NL03V30VCFB
+3V3_VCFB +SW2_D PIL801 PIL802 PINT801
PINT802
C
COR137 FB_C 1.0µH
R137 22.1 18
POPMBUS0SCL
13[1D], 15[2C], 17[2C], 9[1D] PMBUS_SCL PIR13701 PIR13702 PIU12018 CLK
4 SRP4020FA-1R0M 0C152
PIC152COC152 1
PIC1540C154
COC154 PIC15302C153
COC153
BOOT_D PIU1204 +BOOT2_D
19
POPMBUS0SDA
13[1D], 15[2C], 17[2C], 9[1D] PMBUS_SDA PIU12019
DATA
5
1
PIC1520220uF PIC1540247uF PIC153010.1uF
PHASE_D1 PIU1205 +SW2_D
POMIO770PWR0ALERT0N COR138PIR13802
R138
0
PIR13801 17
PIU12017 GND
15[2C], 17[2C], 3[6A] MIO77_PWR_ALERT_N ALERT#
6
PHASE_D2 PIU1206
COC155
C155
PIC15501 10000pF
PIC15502
7
PIU1207
COR139 PHASE_D3
R139
PIR13901 55
2.87K PIU12055
PIR13902 ADDR_PROT NL00V850FB3
56 +0V85_FB3
COR140
R140 10.00K PIU12052 52
FB_D PIU12056
CH_LDO: +1.2V PSPLL, 0.5A
GND_ANA1 PIR14001 PIR14002 SYNC_CLK +VCC_PSPLL
COR141
R141
PIR14101 10.00K PIU12029
PIR14102 29 23
PIU12023
+VCC_PSPLL
+5.0V SLEEP# VO_LDO
COR142 NL01V20FB3 COR143
R143 +1V2_FB3
R142
PIR14201 PIR14202 54
2.87K PIU12054 24
PIU12024 +1V2_FB3 PIR14301 PIR14302
GND_ANA1 MTP FB_L PIR14 02
COC156
C156PIC15601 10000pF
PIC15602
2
0C157
PIC157COC157 2 1.40K
PIC1580C158
COC158 COR144
R144
AGND GND 1.00K
PIC15701
2.2uF PIC158010.1uF PIR14 01
I2C Address Offset = +4.
50
PIU1205 57
PIU12057 IRPS5401MTRPBF

Address: 0x14, 0x44. COR145

R145
PIR14501 PIR14502
0
GND

D COC159
C159 D
NOTE: MTP resistor set PIC15902 PIC159010.1uF

to allow +4 address skip. DNP

GND_ANA1 GND
Avnet Engineering Services
Project Name: PCB Rev: BOM: Variant:
Ultra96 SBC V2
Doc Num: Date:
1 Time: 01 00
SCH-US1SBC 3/1/2019 7:57:28 AM
Sheet Title: Size: Sheet:
16 - Rocky PMIC #2.SchDoc B 16 of 18
1 2 3 4 5 6
 1 2 3 4 5 6

MANHATTAN PMIC #3
MAIN POWER +8v - 16 VIN +3.3V_PRIMARY
+VIN +3V3_PRI
COU19
U19
1 6
PIU1901IN OUTPIU1906 2
0C219
PIC219COC219
A A
+VSYS_IN +VIN 2
PIC2 0COC220
C220 2
COJ10
J10 COD19
D19 COFL1 GNDPIU1902
1 PID1902
2 1 1 I/O
FL1
3 I/O PIC2 0 11uF 4
PIU1904
NC
3
GNDPIU1903
PIC219011uF
PIJ1001 PID1901 PIFL101 PIFL103 5
PIU1905 7
3 NC PADPIU1907
2PIFL102GND
PIJ1003 NFE31PT222Z1E9L
2
PIJ1002 DB2F43100L1 NCP716MT33TBG
PJ1-021-SMT-TR
GND GND

GND GND

+VSYS_IN
COJP1
JP1 COD20
D20
2 2
PIJP102 PID2002 1
PID2001
DNP 1
PIJP101
DB2F43100L1
5-146280-2 DNP
GND
CHC: +0.9V PSMGTAVCC, 0.3A
Layout Note: Place JP1 next to Power In
+3.3V +MGTRAVCC
jack. COU20
U20
2
PIU2002 1
2 PIR17202
PIC2 10C221 BIAS OUT PIU2001 2COC222 PIC2 3COC223
PIC2 0C222 2
0C223 2
0COC224
PIC2 4C224
COC221
BOARD +5.0V MAIN, 6A Max 1
PIC2 101uF COR172
R172
4
PIU2004IN
PIC2 01
4.7uF PIC2 301 0.47uF PIC2 4010.1uF
B PIR172011.00K B
3 5
POPOWER0GOOD
13[5A], 15[2C], 16[1C], 3[4D], 6[1D], 9[1B] POWER_GOOD
PIU2003EN GND PIU2005
COR173
R173 0 GND NCP134AMX090TCG
POEN0SEQ0PL
13[6C], 15[2B], 16[1B] EN_SEQ_PL PIR17301 PIR17302 GND
COC225
C225 0.1uF
PIC22502 PIC22501 PIR17402
COR174
R174
0
GND

GND
CH_LDO: +1.8V MGTRAVTT, 0.05A
For Bode plot PIR17401 PIC22602
COC226
C226
PIC22601

15

22
11
testing

4
COU21
U21 PIU2104 PIU210 5 PIU210 1 PIU2102 10uF PWR +VIN +3.3V +MGTRAVTT
COU22
U22
COR175
R175 4.02K i 4 1

Vp

En/FCCM

PGood

Vcc
PIU2204IN OUT PIU2201
PIR17501 PIR17502 21
PIU21021 2 PIR17802
PIC2 70C227 2COC228 PIC2 9COC229
PIC2 80C228 2
0C229 2
PIC230C230
COC231 COR176 COR177 Vin COC227 COC230
C231 R176 R177 10 PIU2108
8 PIC23 02C232
PIC23101 PIC23102
2200pF
PIR17601 127
PIR17602 PIR17701 PIR17702 RSo
1
2
0C233
COC232 PIC23 COC233 2
PIC2340C234
COC234 02
PIC235C235
COC235 PIC23601C236
COC236 COR178
R178
PVin PIU2101 1
PIC2 701uF 1.00K 2
GND PIU2202
PIC2 8014.7uF PIC2 9010.47uF PIC230 10.1uF
PIC23 01 33uF PIC23 0133uF PIC2340133uF PIC2350133uF PIC236020.1uF PIR17801 PIU2203
3
EN
5
PAD PIU2205
6
PIU2106
FB IR38060MTRPBF 23
PIU21023 NCP177AMX180TCG
COR179 COC237 PGnd GND GND
R179
PIR17901 3.74K
PIR17902 C237
PIC23701 PIC23702 7
PIU2107 i PWR
Comp
COC238 4700pF 12
C238 56pF
PIC23801 PIC23802 PGnd PIU21012 GND
COR180
R180
PIR18001 100K
PIR18002 3
PIU2103 25
PIU21025
Track_En PGnd
COC239
C239 20 2 R181COR181 0
GND_M1 PIC23901 PIC23902 PIU21020 P1V8 Boot PIU2102 PIR18101 PIR18102
2.2uF
C COC240
C240 PWR C
PIC24001 PIC24002 +5.0V
0.1uF COL9
L9 i
COR182
R182 22.1 19 24 CONT9
NT9
POPMBUS0SCL
13[1D], 15[2C], 16[1C], 9[1D] PMBUS_SCL PIR18201 PIR18202 PIU21019
SCL/OCSet SW PIU21024 PIL901 PIL902 PINT901
PINT902
1.2µH 15A 1
PIC2410C241
COC241 PIC24 01C242
COC242 PIC24301C243 2
0C244
COC243 PIC24 COC244
POPMBUS0SDA 18
13[1D], 15[2C], 16[1C], 9[1D] PMBUS_SDA PIU21018 SDA/IMON COR183 2
PIC241047uF PIC24 0247uF PIC24302 47uF PIC24 010.1uF
5 R183 499
COR190 0 Vsns PIU2105 PIR18302 PIR18301
POMIO770PWR0ALERT0N R190
PIR19002 PIR19001 17
PIU21017 COR184
R184 1.47K
15[2C], 16[1C], 3[6A] MIO77_PWR_ALERT_N SAlert/TMON PIR18401 PIR18402
DNP
COR185
R185
0
GND_M1 GND
POMIO310MHTN0ALRT
3[4B] MIO31_MHTN_ALRT PIR18502 PIR18501
10 COR186
R186 1.47K NL05V0FB
+5V_FB
RS+ PIU21010 PIR18601 PIR18602
Rt/Sync

COR187
R187 499
ADDR

LGnd PIC24502C245
COC245 PIR18702 PIR18701

RS-
NC
DNP
PIC24602
COC246
C246
PIC24601 PIC24501 0.1uF
0.1uF PIU21014 PIU210 6 PIU210 3 PIU21026 PIU2109 DNP
14

16

13

26

9
COR188
R188
PIR18801
0
PIR18802

2
PIC2470COC247 PIR18902COR189 LAYOUT NOTE: Place +5V_FB net at the farthest 5V output
C247 R189
capacitor. Isolate the trace by 4x the trace width from all
GND GND_M1 01
PIC24710000pF PIR18901
3.24K other signals. Place R188 & R190 within 50 mils of U22
GND pins.
DNP
GND_M1
I2C Address Offset = +5.
D Addresses: 0x15, 0x45. D

NOTE: MTP resistor set Avnet Engineering Services

to allow +5 address skip. Project Name: PCB Rev: BOM: Variant:
Ultra96 SBC V2
Doc Num: Date:
1 Time: 01 00
SCH-US1SBC 3/1/2019 7:57:28 AM
Sheet Title: Size: Sheet:
17 - Manhattan PMIC #3.SchDoc B 17 of 18
1 2 3 4 5 6
 1 2 3 4 5 6

Assembly: Mechanicals:
COPCB1 Mounting Holes:
COLabel1
Label1
COMTG1
MTG1 COMTG2
MTG2 COMTG3
MTG3 COMTG4
MTG4
Label, Product

0
PCB
PIMTG101 PIMTG201 PIMTG301 PIMTG401

1
COLabel2
Label2
A A

COPCB PN (In Copper)1

Label, Serial Number
GND GND
PCB PN (In Copper)
COESD1
ESD1

GND Test Points:

COTP34
TP34 COTP35
TP35
G G

ESD Bag
PITP3401 PITP3501
COSS1
SS1 COSS2
SS2 COSS3
SS3

COLabel0ESD1
Label_ESD1

B GND B

Label, ESD RoHS 2-Silk Screen FCC - Silk Screen

Trash Can-Silk Screen

C C

D D

Avnet Engineering Services

Project Name: PCB Rev: BOM: Variant:
Ultra96 SBC V2
Doc Num: Date:
1 Time: 01 00
SCH-US1SBC 3/1/2019 7:57:28 AM
Sheet Title: Size: Sheet:
18 - Back Page.SchDoc B 18 of 18
1 2 3 4 5 6