A High Performance DSP Controller for Three-Phase
PWM Rectifiers With Ultra Low Input Current THD
Under Unbalanced and Distorted Input Voltage
Liviu Mihalache, Member IEEE
Power Conversion Technologies Inc.
Harmony, USA
e-mail: lm@pcti.com
Abstract—Although in recent years three-phase PWM
rectifiers have become increasingly popular, in most practical
cases the line unbalance and/or the presence of distortion can
seriously affect their performances. Line unbalance and
distortion add unwanted low frequency harmonics to the input
current, leading to an increase in the total harmonic distortion
(THD). At high power level, the switching frequency is restricted
to a few kilohertz and therefore an LC filter is needed to
eliminate the switching ripple of the current. The resulting
structure is an LCL filter that causes instabilities and
oscillations. This paper details how to implement a high
performance multi-loop digital controller suitable for a boost
type PWM rectifier, leading to an extremely low THD content
even with non-ideal input voltage conditions. The multi-loop
method uses only two capacitor filter voltages and inverter
currents to estimate the line voltages and currents. Positive and
negative sequence controllers are used to regulate the
fundamental currents while resonant controllers tuned to each
harmonic from third to thirteenth remove the low frequency
components due to input voltage unbalance and/or distortion.
The proposed approach is implemented on a 16-bit fixed point
DSP (ADMC401) and tested on a three-phase 20 kW IGBT-based
PWM rectifier.
I. INTRODUCTION
Large non-sinusoidal input current with increased
harmonic content causes serious power quality problems. In
general, the source of these current harmonics is the front-end
uncontrolled rectifier using either a full-wave diode or an SCR
bridge followed by a large electrolytic capacitor. These
rectifiers do not comply with the new standards such as IEEE-
519 and IEC-61000-3-2 [22], [23]. With severe regulations
and economic restraints in recent years, three-phase PWM
rectifiers have become increasingly popular due to their ability
to provide near unity power factor, instantaneous power flow
reversal and low harmonic content. The PWM rectifiers can be
divided in two main categories: buck-type rectifiers and boost-
type rectifiers. The buck-type rectifiers can deliver a voltage
less than that of an uncontrolled diode bridge. It is however
rarely used in practice because it requires bi-directional
switches and the input current is discontinuous, thus it requires
a very large filter in order to achieve sinusoidal current. The
boost-type rectifier is by far the most popular topology used
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for PWM rectifiers due to its simple hardware structure, a
standard six switches voltage source converter (VSC). In
addition, the input current is continuous, thus the input current
filtering is much easier. The boost-type rectifier can be
controlled in a number of ways, each yielding advantages and
disadvantages related to control complexity, switching
frequencies and performances. Among them the phase and
amplitude control method [24], [25] is very popular because
its simple structure that does not involve phase current
measurement or current controllers. In this technique
controlling the phase and amplitude of the AC voltage
generated by the VSC indirectly controls the phase and
amplitude of the AC side current. The reference voltage for
the modulation is derived from the supply voltage and the
parameters of the AC power circuit. This method is essentially
an open loop type control and therefore is very sensitive to
both measurement and modeling errors. In addition, the
mathematical model of the phase and amplitude control
method is only valid if the input voltages are balanced and
free of distortion. In order to achieve high performances
under non-ideal conditions closed loop current controllers
structures must be adopted. Over the years many advanced
techniques have been proposed, involving dead-beat control,
predictive control, state-feedback control, etc [27]. In some of
the most demanding applications such as switched mode
power supplies for telecommunications, 400 Hz ground power
unit (GPU) for aircraft applications or ship board power
sources the total harmonic distortion (THD) is restricted to
less than 3% even under non-ideal conditions such as
unbalanced and distorted input voltage. Achieving such
performances is not an easy task especially at higher power
levels where the switching frequency is limited to less than
10Khz. Regardless of the switching frequency an LC filter is
needed to eliminate the switching ripple of the current. The
resulting structure is an LCL filter that affects the current
controller, causing instabilities and oscillations. Most of the
previously published papers on boost PWM rectifiers have
only dealt with individual problems encountered in practical
implementations such as: current controlled techniques with
unbalanced mains, influence of the input filter on the overall
stability, effect of the input voltage harmonics, realization of a
high performance PLL, etc. This paper details how to integrate
different solutions into a high performance multi-loop digital
controller suitable for an LCL boost type PWM rectifier,
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leading to an extremely low THD content even with non-ideal current loop is responsible for suppressing the unwanted
input voltage conditions. The multi-loop method uses only oscillations produced by the addition of the Lf-Cf filter. We
two capacitor filter voltages and inverter currents to estimate will assume for the remainder of this paper that the input
the line voltages and currents. Positive and negative sequence voltage sequence is given by (1)-(3). If the three-phase input
controllers are used to regulate the fundamental currents while voltages are balanced then VC1 = VC 2 = VC 3 = VC .
resonant controllers tuned to each harmonic from third to Assuming a balanced set of input voltages, if the capacitor
thirteenth remove the low frequency components due to input voltages are given by (1)-(3), after the transformation from
voltage unbalance and/or distortion. abc to dq coordinates the quadrature components of the
capacitor are given by (4) and (5). In a similar way, the PWM
II. PWM BOOST RECTIFIER WITH LCL FILTER current components after the abc to dq transformation are
A typical three-phase PWM rectifier with an LCL filter is given by (6) and (7).
depicted in Fig. 1, where the line voltages can be unbalanced
and/or distorted. It is well known [2], [4]-[9] that the addition Vcf _ a (t ) = VC1 ⋅ cos(ω ⋅ t ) (1)
of the switching ripple filter Lf-Cf creates instabilities and
oscillations. Several active [2], [5], [6], passive [8] or Vcf _ b (t ) = VC 2 ⋅ cos(ω ⋅ t + 120) (2)
combinations between active and passive methods have been
proposed in order to improve the stability of the system. The Vcf _ c (t ) = VC 3 ⋅ cos(ω ⋅ t + 240) (3)
active methods are preferred because they do not involve
additional components and losses but typically this involves Vcf phase A
ABC Phase voltage
Vsd
Phase rotation PLL
Sin

measuring the currents both before and after the Lf-Cf filter Vcf phase B
DQ
Estimation Vsq Identification (Fig. 4)
Cos

[2], or the measurement of the capacitor voltage instead of the Icfd

mains voltage [6] thus leading to a deterioration of the power IL phase A Phase capacitor
Estimation Icfq

factor. IL phase B ABC Isd Harmonic controllers

Phase current Isq 3rd,5th,7th,9th,11th,13th
IL phase C DQ Estimation (Fig. 3)
Q1 Q3 Q5

Harm_sd
Q1
Vdc Esd Pos_seq_sd
Lf L C PI REG p Pos D pe Kc Q2
+
LOAD

DQ

vector
Lf L PI REG DQ

modulation
Ref Q3

Harm_sq
Lf L
Q2 Q4 Q6
V1 V2 V3 pe Pos Q p Q4
Esq

Space
DQ Pos_seq_sq
PI REG DQ Kc
Cf
Q5
Cf Cf

n Neg D ne Q6
DQ DQ

Neg_seq_sq
PI REG Limitation
Dual IGBT Dual IGBT Dual IGBT
PHASE C CURRENT
PHASE B CURRENT

drive drive drive

PHASE A CURRENT

ne Neg Q n Reset
DQ PI REG DQ
Vdc
ADMC 401 DSP CONTROLLER BOARD

Vcf phase B

Vcf phase A Fig. 2 Proposed digital controller.

Fig. 1 Three-phase power factor correction boost converter with LCL filter VCfd (t ) = VC ⋅ cos(ω ⋅ t ) (4)
A systematic approach on how to design the components of VCfq (t ) = VC ⋅ sin(ω ⋅ t ) (5)
the LCL filter has been presented in [4]. In general, the
converter side inductor is larger than the mains side one I Ld (t ) = I L ⋅ cos(ω ⋅ t − φ ) (6)
because it is responsible for the reduction of most of the I Lq (t ) = I L ⋅ sin(ω ⋅ t − φ ) (7)
switching ripple. It has been shown that a stable operation can
With sinusoidal voltages across the filter capacitors, the
even be achieved without either passive or active damping
current through the Cf can be directly estimated in dq
with a proper choice of the LCL components and by moving
coordinates by using (4) and (5) and taking advantage of the
the current sensors on the mains side [9]. However the
relationships between the derivatives of sin and cos function,
experimental results presented in [9] also reveal significant
respectively.
distortion on the current waveform.
dVCfd (t )
III. PROPOSED DIGITAL CONTROL APPROACH I est Cfd (t ) = C f ⋅ =
dt
The proposed digital controller is depicted in Fig. 2 and it
uses a multi-loop approach very similar to the one presented in = −ω ⋅ C f ⋅ VC ⋅ sin(ω ⋅ t ) = −ω ⋅ C f ⋅ VCfq (t ) (8)
[2] but it only measures two capacitor filter voltages and the
PWM converter currents. Essentially this multi-loop approach dVCfq (t )
uses an outer voltage loop to provide a reference for the I est Cfq (t ) = C f ⋅ =
dt
estimated mains current while the estimated mains currents
form the second loop whose outputs are the reference for the = ω ⋅ C f ⋅ VC ⋅ cos(ω ⋅ t ) = ω ⋅ C f ⋅ VCfd (t ) (9)
most inner loop, the capacitor filters current loop. This last

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The estimated source currents in dq coordinates can now be
written as (10) and (11) taking into account that the PWM
currents are measured directly:
est est
I Sd (t ) = I Ld + I Cfd
est est
I Sq (t ) = I Lq + I Cfq
If the source currents are tightly regulated and kept
sinusoidal the line voltages can be estimated as in (12)
and (13).
est
dI Sfd (t )
V sd (t ) = VCfd + L f ⋅
dt
= VCfd − ω ⋅ L f ⋅ I S ⋅ sin(ω ⋅ t ) =
= VCfd − ω ⋅ L f ⋅ I est Sq (t )
dI Sfq (t )
V est sq (t ) = VCfq + L f ⋅
dt
= VCfq + ω ⋅ L f ⋅ I S ⋅ cos(ω ⋅ t ) =
= VCfd + ω ⋅ L f ⋅ I est Sd (t )
It is important to acknowledge that a key requirement for the
correct estimation of the input voltages is to have a balanced
set of sinusoidal input currents. This can be achieved even
under small-unbalanced input voltages by the proposed
controller since the PLL depicted in Fig. 3 extracts a clean
waveform in phase with the fundamental of the input voltage.
If the assumption of balanced input voltage is abandoned, it
can be seen that one other source of errors in (8)-(13) would
be an additional low harmonic component from the capacitor
filter current. However even the fundamental of the capacitor
current is much smaller than the mains current, therefore the
higher harmonics can be neglected in the estimations (8)-(13).
The PLL block uses a Taylor polynomial expansion
approximation [18] for the sin (x) function as in (14) in order
to generate a clean sine waveform. This waveform is
multiplied with +/- Vsd, depending on the phase rotation, and
after passing through a low-pass-filter (LPF) with a cutoff
frequency at around 10 Hz a DC signal proportional with the
phase error is obtained. This DC signal is input to a digital
integrator serving as a phase regulator, therefore the output of
the integrator is continuously added to the argument of the
sin/cosine generators. It is obvious that any input voltage
distortion will result in errors on the estimators (12) and (13),
however this is not translated in further distortion on the
current since the LPF of the PLL will remove any higher
harmonics. Furthermore, in order to ensure that a balanced set
of three-phase input current references is obtained, only one
voltage, Vsd is processed by the PLL. The references for the
input current in dq coordinates are obtained by multiplying the
output the PI regulator for the DC-link voltage with the two
sin/cos functions from the PLL block. To achieve zero steady
state error for the mains current even under unbalanced
voltage conditions the input current errors are transformed in
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synchronously rotating frame using both positive and negative
sequences.
sin( x) = 3.140625 ⋅ x + 0.02026367 ⋅ x 2 − 5.325196 ⋅ x 3 +
(10)
+ 0.5446778 ⋅ x 4 + 1.800293 ⋅ x 5 (14)
(11) Vsd
Phase Rotation
-1 1
2
1
Identification 3
O(k) SIN Ki
Sin(x) function Low Pass Filter
s
= +
+
Taylor approx.
Cos(x) function COS
Taylor approx.
(12) Fig. 3 PLL block diagram
Thus, the input current errors in appear as combinations of a
= DC signal plus a 120Hz component corresponding to the
negative and positive component, respectively as shown in
(15) and (16). Although not necessarily required, a notch filter
may additionally be used to remove the 120Hz component
(13) [19] and standard PI regulators can then be used for driving
the current errors to zero. It should be noted, that an
alternative solution with the positive and negative
synchronously rotating regulators is to use proportional +
resonant controllers [1] as in (17). This was shown to achieve
similar performances with a lower overhead, however it does
have a drawback in that it is very difficult to accomplish a
saturation mechanism in the event of an overload or during a
transient, because (17) operates on AC signals and during an
abnormal condition the result would be a clipped sine
waveform. Instead, the proposed approach can easily
implement saturation since the regulators operate on DC
quantities, which are then multiplied with sine/cosine function
from the PLL.
E pe sdq = E pe S + k n sin( 2 ⋅ ω ⋅ t + ϕ1 ) (15)
E ne sdq = E ne S + k p sin(2 ⋅ ω ⋅ t + ϕ 2 ) (16)
Ki ⋅ s
H (s) = K p + (17)
s +ω2 2
The controller detailed so far can only track the fundamental
component but several harmonics can still be present in the
input current. They are mainly due to possible distortion
and/or unbalance of the input voltage, non-ideal PWM
converter modeling as well as delays and quantization effects.
To remove these unwanted components a harmonic controller
is added to the output of the dq regulators controlling the
fundamental component. The harmonic controller is detailed
in Fig. 4 where it can be seen that each harmonic from third to
thirteenth is individually controlled to zero by the use of
resonant controllers that have an infinite gain at the selected
frequencies [1]. The resonant controllers are implemented as
IIR filters with a normal architecture to minimize the round-
off errors [15], [20]. One should mention here that the
structure of the resonant controller becomes slightly different
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[11], when a delay compensation angle is added as in (19). In 12-bit, 6 channels with a 16-bits resolution PWM unit, two
our case we have selected a leading angle of 2T. additional 8-bits PWM channels, 1-kbyte RAM for data
memory, 2-kbyte RAM for program memory, 1-kbyte ROM
program memory for boot and debug features, 12 I/O channels
Isd 2s*k3 etc. The input voltage is a standard three-phase 208Vac with a
(Isq) -
+ s2 + (3a)2 5% maximum unbalance (204/210/214Vac). Also up to 2.2%
Ref=0 of the 5th harmonic is present in the input voltage. The
2s*k5 +
+ switching frequency was 8 kHz while the sampling frequency
2
s + (5a)
2 was 16 kHz. The DC-link voltage was regulated at 350 VDC.
Both inductors of the LCL filter were 0.5mH while the
capacitor was 20µF. All harmonic and power factor
measurements were taken with a Fluke 43B power quality
analyzer. The output electrolytic capacitor used in this setup
+ Harm_sd
2s*k13 + was 3600µF. Fig. 5 depicts the total harmonic distortion
2
2
s + (13a) (Harm_sq) (THD) at half of the maximum output current and it can be
Fig. 4 Harmonic controller diagram seen that it is kept to a very low value of 0.7%. At the same
time the power factor is unity as shown from Fig. 6. It can be
2 ⋅ s ⋅ K Ik _ dq seen from Fig. 7 the input voltage is not ideal, at half load it is
H harm _ dq ( s ) = ∑ (18) slightly less than the nominal 208 volts and it has a 2.4 volts
k s 2 + ωk 2 fifth harmonic, which amounts to approximately 1.2% of the
s ⋅ cos φ k − ω k ⋅ sin φk fundamental. Fig. 8 depicts a line-line voltage and a phase
Gresonant ( s ) = 2 ⋅ Kik ⋅ (19) current at half load. When the output power is increased at 15
s2 + ωk 2 kW, the phase current is still kept sinusoidal as seen in Fig. 11
where ωk = kω, k = 3…13. where the distortion is very low, around 0.4%. Clearly the
As previously mentioned a third loop, the capacitor filter loop fifth harmonic on the input voltage displayed in Fig. 10 has no
is added in order to improve the stability of the system due to influence on the input phase current mainly due to the
the filter Lf-Cf [2]. Since the purpose of this loop is not to resonant harmonic controller tuned to the 5th harmonic.
ensure a zero steady-state error of the capacitor filter current, a
simple proportional gain is used. The overall input current
transfer function has a very complex form [2], but it can be
somewhat simplified if the series resistors of the inductors are
neglected. Neglecting the series resistance of both inductors
the transfer loop of from the current reference to the input
estimated current is given by (20), where H(s) is the total
transfer function of the rotating PI regulators (both positive
and negative sequences) and the sum of the resonant
controllers. The gain Kc should be large enough to achieve
desired dumping of the resonant peak caused by the input LCL
filter, but a computer analysis is required since the choice of
Kc also affects the current transfer function as seen in (20).
I sdq est
= Fig. 5.Phase current THD at 10.7 kW
I sdq ref

K c ⋅ H (s)
= (20)
3 2
s ⋅ L ⋅ L f ⋅ C f + s ⋅ L f ⋅ C f ⋅ K c + s ⋅ (L + L f )
Due to the complexity of (20) experimental tests were used to
adjust the gain Kc obtained by computer analysis and
simulations.
IV. EXPERIMENTAL RESULTS
The proposed digital method has been implemented on a
three-phase 20KVA PWM rectifier using a 16-bit DSP-based
controller ADMC401 (Analog Devices). This 26 MIPS single-
chip DSP controller is well suited for the easy and inexpensive
implementation of various high performance digital control
algorithms because it includes all the facilities required in a
voltage and current control loop such as: 8 A/D channels with Fig. 6 Input power factor at 10.7 kW output power

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Fig. 7 Line-line voltage distortion (THD) at 10.7 kW output power
Fig. 8 Line-line voltage and phase current at 10.7 kW output power
Fig. 9 Transient response from 4.5 kW to 15 kW
Fig. 10 Line-line voltage distortion (THD) at 15 kW output power
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Also the voltage imbalance does not affect the current
waveform, all triplen harmonics are almost negligible due to
the action of the negative sequence controller and the
harmonic controllers tuned to the third and ninth harmonics.
Fig. 12 depicts a steady state line-line voltage and a phase
current at 15 kW, while Fig. 14 displays current and voltage
on the same phase showing a nearly zero phase displacement.
This is also confirmed by the unity power factor measurement
at 15 kW, as seen in Fig. 13. Increasing the output power to
full load 20 kW does not affect the performances of the
controller as shown in Fig. 20, the total harmonic distortion
remains extremely low at 0.5% even though the phase current
has risen to nearly 55 amps RMS. A graphic of the input
current harmonic spectrum (up to the 51st harmonic) is
provided in Fig. 19. As expected the control loops are able to
maintain unity power factor when the load is increased to 20
kW as seen in Fig. 18. Steady-state line-line voltage and phase
current at full load are displayed in Fig. 17. Some transient
response experiments are presented in order to verify the
ability of the most inner loop, the capacitor loop, to suppress
unwanted oscillations. A transient response from 4.5 to 15 kW
is depicted in Fig. 9 where it can be seen there are no
oscillations on either dc link voltage or the input current. Also
note the absence of dc offset on the input current during
transient. Finally a transient response from no load to 15 kW
is depicted in Fig. 15 and Fig. 16 showing a fast response, a
very robust behavior and the absence of any transient
oscillations.
V. CONCLUSIONS
This paper details how to implement a high performance
multi-loop digital controller suitable for a boost type PWM
rectifier leading to an extremely low THD content (less than
1%) even with non-ideal input voltage conditions. The multi-
loop method uses only two capacitor filter voltages and
inverter currents to estimate the line voltages and currents.
Positive and negative sequence controllers are used to regulate
the fundamental currents while resonant controllers tuned to
each harmonic from third to thirteenth remove the low
frequency components due to input voltage unbalance and/or
distortion. The addition of a third capacitor current loop
improves the transient and eliminates the possibility of
oscillations due to the input filter. The proposed approach is
implemented on a 16-bit fixed point DSP (ADMC401) and
tested on a three-phase 20 kW IGBT-based PWM rectifier.
Fig. 11 Phase current distortion (THD) at 15 kW
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 Fig. 12 Phase voltage and current at 15kW Fig.15 DC-link and phase current during transient from no load to 15kW

Fig. 13 Input power factor at 15 kW output power Fig. 16 Phase voltage and current during transient from 0 to 15 kW

Fig. 14 Steady-state phase voltage and current at 15 kW Fig. 17 Line-line voltage and phase current at 20 kW output power

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Fig. 18 Input power factor at full load
Fig. 19 Input current spectrum at full load
Fig. 20 Input current total harmonic distortion (THD) at full load
REFERENCES
[1] D.N.Zmood, D.G.Holmes, “Stationary frame current regulation
of PWM inverters with zero steady state error”, Proc of PESC’99,
pp. 1185-1190
IAS 2005
[2] E.Twining, D.G.Holmes, “Grid current regulation of a three
phase voltage source inverter with an LCL input filter”, IEEE
Transactions in Power Electronics, May 2003, pp 888-895
[3] N.Abdel-Rahim, J.E.Quaicoe, “Modeling and analysis of a
feedback control strategy for three-phase voltage source utility
interface systems”, Proc. of 29th IAS Annual Meeting 1994, pp 895-
902
[4] M.Liserre, F.Blaajberg, S.Hansen, “Design and control of an LCL
filter based three-phase active filter”, Proc. IEEE IAS Annual
Meeting 2001, pp 297-307
[5] Y.Sato, T.Kataoka, “A current-type PWM rectifier with active
damping function”, IEEE Transactions in Industry Applications,
May/June 1996, pp 533-541.
[6] V.Blasko, V.Kaura “A novel control to actively damp resonance
in input LC filter of a three-phase voltage source converter”, IEEE
Transactions in Industry Applications, May/June 1997, pp 542-550
[7] F.Blaajberg, E.Chiarantoni, A. Dell’Aquila, M.Liserre,
S.Vergura, “Analysis of the grid side behavior of a LCL filter based
three-phase active rectifier”, pp775-780
[8] M.Liserre, A. Dell’Aquila, F.Blaajberg, “Stability improvements
of an LCL-filter based three-phase active rectifier”, pp 1195-1201
[9] R.Teodorescu, F.Blaajberg, M.Liserre, A. Dell’Aquila, “ A stable
three-phase LCL-filter based active rectifier without damping”, Proc.
of IAS 2003 CD-ROM
[10] Y.Sato, T.Ishizuka, K.Nezu, T.Kataoka,“ A new control strategy
for voltage type PWM rectifiers to realize zero steady-state control
error in input current”, IEEE Transactions in Industry Applications,
May/June 1998, pp. 480-486.
[11] P.Mattavelli, “A closed-loop selective harmonic compensation
for active filters” IEEE Transactions in Industry Applications,
May/June 2001, pp 864-872
[12] K.J.Astrom, B.Wittenmark, “Computer controlled systems - theory
and design”, Third edition, Prentice Hall Inc., 1997.
[13] N.Mohan, T.M.Undeland, W.P.Robbins, “Power electronics-
converters, applications and design”, Second edition, John Wiley &
Sons Inc., 1995
[14] T.M.Rowan and R.J.Kerkaman, “A new synchronous current
regulator and an analysis of current regulated PWM inverters”, IEEE
Transactions in Industry Applications, July/August 1986, pp. 678-690
[15] L.Mihalache, “DSP Control of 400 Hz Inverters for Aircraft
Applications”, Proc. IEEE-IAS 2002 CD-ROM
[16]S.K.Mitra and J.F.Kaiser, “ Handbook for digital signal
processing”, New York, Wiley, 1993
[17]F.Taylor, J.Mellot, “Hands-on digital signal processing”, McGraw-
Hill Inc, 1998
[18]Digital Signal Processing Applications using the ADSP-2100
Family, Volume 1, Analog Devices, 1992
[19]H.S.Song, K.Nam, “Dual current control scheme for PWM
converter under unbalanced input voltage conditions”, IEEE
Transactions in Industrial Electronics, October 1999, pp 953-959
[20] L.Mihalache, “Single loop DSP control method for low cost
inverters”, Proc.of International Signal Processing Conference,
Dallas, March 2003.
[21] M.Liserre, A.Dell’Aquila, F.Blaajberg, “ Design and control of
a three-phase active rectifier under non-ideal operating conditions”,
Proc. IEEE PESC 2002 CD-ROM
[22] Recommended Practices and Requirements of Harmonic
Control in Electrical Power Systems, IEEE Std. 519-1992, 1994
[23]Limits for Harmonic Current Emissions, IEC Std. 61000-3-2,
1995
[24]R.Wu,S.B.Dewan,G.R.Slemon, “Analysis of an AC to DC
voltage source converter using PWM with phase and amplitude
control,” IEEE Trans.Ind. Appl, vol.27, pp 355-364, Mar/April 1991
[25]J.W.Dixon, B.T.Ooi, “Indirect current control of a unity power
factor sinusoidal boost type 3 phase rectifier”, IEEE Trans. Ind.
Electron., vol 35, pp 508-515, Nov. 1988
[26] J.R.Rodriguez, J.W.Dixon, J.R.Espinoza, J.Pontt, “PWM
Regenerative rectifiers:State of the art”, IEEE Trans. Ind.Electron.,
vol 52, No.1, February 2005, pp 5-22
144 0-7803-9208-6/05/$20.00 © 2005 IEEE