L T P C

CODE ANTENNAS AND WAVE PROPAGATION

3 1 0 4
COURSE OBJECTIVES

1 To gain knowledge on antenna fundamentals

2 To give insight of the radiation phenomena
To give a thorough understanding of the radiation characteristics of different
3
types of antennas
4 To acquire knowledge about antenna measurement for special antennas.
To create awareness about the different types of propagation of radio waves at
5
different frequencies
COURSE OUTCOMES
Upon completion of the course, students shall have ability to
CO1 Provide the basic knowledge about the components of antenna
CO2 Understand the Aperture antenna, slot antenna its type’s applications and its radiation patterns.
CO3 Analyze the performance of special antenna from their radiation pattern and beamwidth
CO4 Designantennas and radiation mechanism of various antennas and antenna arrays
CO5 Design antenna with high performance with less fading level
COURSE CONTENTS
UNIT -1 ANTENNA FUNDAMENTALS (12
Hrs)
Power density, directivity, gain, radiation resistance, input impedance, radiation patterns, beam width,
bandwidth and polarization. Retarded potential- Radiation from a current element and monopole – Radiation
of half-wave and centre-fed dipole – Near and far fields, current distribution of dipole antennas. Linear array
antennas - Arrays of two point sources – Broad side and end fire arrays, binomial array - Principle of pattern
multiplication –Adaptive arrays.
UNIT –II APERTURE AND SLOT ANTENNAS (12
Hrs)
Radiation from rectangular apertures, Uniform and Tapered aperture, Aperture blockage, Feeding structures,
Horn antenna, Reflector antenna, Cassegrain reflector, Babinet’s principle, Slot antennas, Lens antenna,
Microstrip antennas.
UNIT -I1I TRAVELLING WAVE AND BROADBAND ANTENNA (12
Hrs)
Travelling wave wire, V and Rhombic antenna, folded dipole, Yagi-Uda antenna, Log-periodic antenna,
Helical antenna, Loop antenna.
UNIT -1V SPECIAL ANTENNA AND ANTENNA MEASUREMENTS (12
Hrs)
Electromagnetic compatibility antenna –Calibration- Reconfigurable antenna, Active antenna, Dielectric
antennas, Patch antenna, Smart antenna – Antenna Measurements-Test Ranges, Measurement of Gain,
Radiation pattern, Polarization, VSWR.
UNIT –V PROPAGATION (12
Hrs)
Factors involved in the propagation of radio waves - Ground wave, reflection of radio waves by the surface
of the earth - Space wave propagation, atmospheric effect in space wave propagation - Ionosphere and its
effect on radio waves, Mechanism of ionospheric propagation- Ray paths – Skip distance -Critical
frequency-Maximum usable frequency - Fading of signal - Types of fading- Diversity reception.
TEXT BOOKS
1. ‘Electromagnetic waves and radiating systems’, Edward C.Jordan and Keith
UNIT 1-5
G.Balaman, Second Edition, 2007, PHI Learning.
UNIT 1-5 2. ‘Antenna and Wave Propagation’, Sisir K Das and Annapurna Das, Third
 Edition, 2013,TataMcGraw Hill Education Private Ltd.
REFERENCE BOOKS
1. ‘Antennas and wave propagation’, A.R.Harish and M.Sachidananda, Third
UNIT 3-5
Edition, 2008, Oxford University Press.
UNIT 1-5 2. ‘Antennas’, J.D.Kraus, 2005, Thrid Edition, McGraw Hill.
UNIT 1-5 3. ‘Antenna and Wave Propagation’, K.D. Prasad’, Third Edition, 2003, SatyaPrakashan.
WEB RESOURCES
1. https://nptel.ac.in/courses/108101092/
2. https://www.classcentral.com/course/swayam-electromagnetic-waves-in-guided-and-wireless-medium-
12962
3. https://www.scientechworld.com/education-software-training-and-skill-development/sku-online-
learning/antenna-and-wave-propagation

COs/POs/PSOs Mapping

Program Specific
Program Outcomes (POs)
COs Outcomes (PSOs)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
1 3 - - - - - 2 - - - - - 2 - -
2 2 - 2 - - - - - - - - - 2 - -
3 - 2 - - - 1 1 - - - - - 1 - -
4 - - 2 - - 1 - - - - - 2 - -
5 3 1 - - - 1 1 - - - - 1 2 - -
 L T P C
CODE COMPUTER NETWORKS
3 0 0 3
COURSE OBJECTIVES
1 To study and understand the basics of data communication networks
2 To understand the division of network functionalities into layers
3 To get familiarize with the up-to-date developments in switching and network technology
4 To Learn the flow control and congestion control algorithms
5 To understand the techniques involved in application layers
COURSE OUTCOMES
Upon completion of the course, students shall have ability to

CO1 Identify the components required to build different types of networks

CO2 Understand various process of Data Link Layer such as addressing and Error correction
CO3 Trace the flow of information from one node to another node in the network with IPV4,IPV6
CO4 Be familiar with the Protocols like TCP,UDP in Transport Layer
CO5 Understand the techniques involved in application layers
COURSE CONTENTS
UNIT -1 INTRODUCTION (9
Hrs)
Data Communications – Network Criteria- Network Types- Network Models- TCP/IP Protocol Suite, OSI
Model. Digital Transmission - Digital to Digital conversion- Transmission modes- Transmission Media -
Multiplexing- Switching Techniques. Connecting devices- Hubs, Switches, Routers, Gateways
UNIT -I1 DATA LINK LAYER (9
Hrs)
Nodes and Links- Link Layer Addressing- Error Detection and Correction – Cyclic Codes, Checksum,
Forward Error Correction. Data Link Control – DLC Services, DLC Protocols, HDLC, PPP. Media Access
Control – Random Access, Controlled Access, Channelization. Wired LAN – IEEE Standards, Ethernet
Protocol, Standard Ethenet, Fast Ethernet, Gigabit Ethenet. Virtual LAN- Membership, Configuration,
Communication between switched
UNIT -1II NETWORK LAYER (9
Hrs)
Network Layer services- Packet switching- Network Layer performance – IPv4 addressing– Classful and
Classless addressing, Network Address Translation Network Layer Protocols – Dynamic Host Configuration
Protocol, Internet Protocol – IPv4, IPv6,ICMP- IPv6 Addressing - Unicast Routing algorithms and
protocols– Multicast Routing protocols–-IGMP
UNIT -1V TRANSPORT LAYER (9
Hrs)
Transport Layer services – Protocols – Simple, Stop-and-wait, Go-Back-N, Selective Repeat, Piggy
backing. User Datagram Protocol – Packet format, services, applications, Transmission Control Protocol –
Services, Features, Segment format, Windows in TCP, Flow Control, Error Control, TCP Congestion
Control, TCP Timers. Stream Controlled Transmission Protocol –Services, Features, Packet Format, Flow
andError control
UNIT -V APPLICATION LAYER (9
Hrs)
Services- Paradigms- Client Server Programming – World Wide Web- Hypertext Transfer Protocol- File
Transfer Protocol-Electronic Mail- Telnet- Domain Name system –Simple Network
Management Protocol.
TEXT BOOKS
UNIT 1-5 1. ‘‘Data Communication and Networking’, Behrouz A Forouzan , Tata McGraw-Hill,
New Delhi, 2013
UNIT 1-5 2. ‘Computer Networking: A Top-Down Approach’ ,Kurose James F and Keith W. Ross,,
Pearson Education, New Delhi, 2013
REFERENCE BOOKS
UNIT 1-5 1. ‘Computer networks’, Andrew S Tanenbaum, Prentice Hall of India, New Delhi, 2011
2. ‘’Data and Computer Communication’, William Stallings, Prentice Hall of India, New
UNIT 1-5
Delhi, 2014
UNIT 1-5 3. ‘Internetworking with TCP/IP’, Comer D E, Prentice Hall of India, New Delhi, 2013
4. ‘Computer Networks: A Systems Approach’, Larry L. Peterson, Bruce S. Davie,
UNIT 1-5
Morgan Kauffmann Publishers Inc., 2012
WEB RESOURCES
1. https://swayam.gov.in/nd2_cec20_cs01/preview
2. https://onlinecourses.nptel.ac.in/noc20_cs23/announcements?force=true

COs/POs/PSOs Mapping

Program Specific
Program Outcomes (POs)
COs Outcomes (PSOs)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
1 3 2 2 1 3 3 2 - 3 1 1 2 3 2 3
2 3 2 2 1 3 3 2 - 3 1 1 2 3 2 3
3 3 2 2 1 3 3 2 - 3 1 1 2 3 2 3
4 3 2 2 1 3 3 2 - 3 1 1 2 3 2 3
5 3 2 2 1 3 3 2 - 3 1 1 2 3 2 3
 L T P C
CODE VLSI DESIGN
3 0 0 3

COURSE OBJECTIVES
1 Introduce the basics of Integrated Circuits and fabrication process.
2 Study the fundamentals of CMOS circuits and its characteristics
3 Brief knowledge on various combinational design in Verilog module.
4 Impart knowledge on various sequential logic design in Verilog module.
5 Learn the different FPGA architectures.

COURSE OUTCOMES
Upon completion of the course, students shall have ability to

CO 1 Understand the basics of VLSI circuits and its impact in Industry.

CO 2 Analyse the MOS transistor equations for presence of parasitic components
CO 3 Construction of Combinational and Sequential logic design based on timing analysis
CO 4 use modern EDA tools to simulate and synthesize the digital designs
CO 5 Known different FPGA architectures.

COURSE CONTENTS
UNIT-1 INTRODUCTION TO VERILOG HDL (9 Hrs)
Basics of Verilog, operators, VLSI design flow, data types hierarchy procedures and assignments, timing
controls and delays, tasks and functions, control statements. Continuous assignments, Sequential and
parallel statement groups Timing control (level and edge sensitive) and delays, tasks and functions, control
statements, Blocking & non-blocking assignments, If-else and case statements, For- while-repeat and
forever loops, Rise, f all, min, max delays.
UNIT II VERILOG MODELLING (9 Hrs)
Gate-level modelling - Realization of Combinational and sequential circuits, Compilation and simulation of
Verilog code, Test bench, Dataflow modelling - Realization of Combinational and sequential circuits-
Behavioural modelling Realization of Combinational and sequential circuits -Switch-level modelling
UNIT-III VERILOG HDL FOR COMBINATIONAL DESIGN (9 Hrs)
Design of Half and Full Adders, Half and Full Subtractors, Multiplier, Binary Parallel Adder – Carry look
ahead Adder, Carry Skip adder, Carry save adder, BCD Adder, Multiplexer, Demultiplexer, Magnitude
Comparator, Decoder, Encoder, Priority Encoder, Baugh-Wooley multiplier, Wallace Tree multiplier Booth
multiplier
UNIT -IV VERILOG HDL FOR SEQUENTIAL DESIGN (9 Hrs)
Static latches and Registers, Dynamic latches and Registers, Pulse Registers, Sense Amplifier Based
Register, Pipelining, Schmitt Trigger, Monostable Sequential Circuits, Astable Sequential Circuits.
UNIT -V ULTRA FAST VLSI CIRCUITS AND PROGRAMMABLE ASIC’S (9 Hrs)
Ultra fast systems-GaAS crystal structure-GaAS fabrication-device modeling and performance
estimation(only GaAS) Antifuse and SRAM Practical issues-FPCA economics, programmable logic cells,
Actel ACT1, ACT2 and ACT3-Xilinx LCA, Ultra FLEX and Ultra MAX.

TEXT BOOKS
UNIT 1- 4 1. J. Bhasker ―A Verilog HDL Primer,‖Star Galaxy Press,1997.
UNIT 3 & 4 2. R. Jacob Baker, “CMOS Circuit Design, Layout, and Simulation”, Wiley, (3/e), 2010.
3. Morris Mano M, Michael D. Ciletti, Digital Design with an Introduction to the Verilog
HDL, 5th ed., Pearson, 2014
UNIT 5
4. M.J. Smith, “Application Specific Integrated Circuits” Addison Wesley, 1997

REFERENCE BOOKS

UNIT 1,2 1. Navabi, “VHDL analysis and modelling of digital systems”, Mc Graw Hill, 1993
2. Douglas A Pucknell and Kamran Eshranghian, ”Basic VLSI Design” Prentice Hall of
UNIT 3,4 India, New Delhi, 2011
3. R.Jacob Baker, Harry W.LI., David E.Boyee, ―CMOS Circuit Design, Layout and
4. Simulation‖, Prentice Hall of India 2005
WEB RESOURCES
1. https://www.tutorialspoint.com/vlsi_design/
2. http://www.vlsi-expert.com/p/vlsi-basic.html
3. https://www.youtube.com/watch?v=9SnR3M3CIm4
COs/POs/PSOs Mapping

Program Specific
Program Outcomes (POs)
COs Outcomes (PSOs)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
1 3 - - 3 - - - - - - - - 3 1 -
2 3 3 3 3 - - - - - - - - 3 1 -
3 3 3 3 3 3 - - - - - - - 3 1 -
4 3 3 3 3 3 - - - - - - - 3 1 -
5 3 - 3 3 3 - - - - - - - 3 1 -
 L T P C
CODE INFORMATION THEORY AND CODING
3 0 0 3
COURSE OBJECTIVES
1 To describe and analyze the information source and channel capacity
2 To attain knowledge about Continuous and discrete Communication Channel
To analyze the source coding techniques such as Shanan Fano Encoding, Huffman Coding,
3
Arithmetic Coding
To Construct the various channel coding schemes such as block codes, cyclic codes and
4
convolutional codes
5 To apply statistical techniques for signal detection
COURSE OUTCOMES
Upon completion of the course, students shall have ability to

CO1 Apply properties of information source and channel capacity

CO2 Differentiate about Continuous and discrete Communication Channel
Solve source coding techniques such as Shanan Fano Encoding, Huffman Coding, Arithmetic
CO3
Coding
Knowledge about channel coding schemes such as block codes, cyclic codes and convolutional
CO4
codes
CO5 Utilize statistical technique to find signal and channel Noise
COURSE CONTENTS
UNIT -1 INFORMATION THEORY (9
Hrs)
Introduction, Uncertainty, Information and it’s property, Entropy and its property, Joint and Conditional
Entropy, Mutual Information and its property, Information measures for Continuous random variables
UNIT -I1 CHANNEL CLASSIFICATION AND CAPACITY (9
Hrs)
Channel capacity theorem, Continuous and Discrete Communication channels – Discrete memory less
channels - channel representations - noiseless channel, lossless channels, Deterministic, Binary symmetric
channel (BSC), Binary Erasure channel (BEC) and their capacities
UNIT -1II SOURCE CODING TECHNIQUES (9
Hrs)
Coding for Discrete memory less sources: – Fixed length code words, Variable length code words, Kraft
Inequality, Prefix coding, Shannon’s first , second and third theorem, Shannon binary Encoding, Shannon-
Fano Encoding, Huffman Coding : minimum and maximum variance method, Arithmetic Coding,
Dictionary Coding- LZ , LZW Coding
UNIT -1V ERROR CONTROL CODING (9
Hrs)
Types of Errors, Types of Codes, Linear Block Codes: Error Detection and Error Correction
Capabilities of Linear Block codes, Binary Cyclic codes, Encoding using Shift register, Syndrome
Calculation, Error detection, and Error correction, Convolutional codes – Encoders and Decoders for
convolutional codes, LDPC Codes, Trellis Codes, Turbo Codes, and Viterbi Coding
UNIT -V DETECTION OF SIGNALS AND CHANNELS WITH NOISE (9
Hrs)
Hypothesis testing – Baye’s criterion – Minimum error probability criterion, Neyman Pearson
criterion,Minmax criterion-Maximum Likelihood detector-Wiener filter- Continuous and Discrete channels
with noise
TEXT BOOKS
UNIT 1-5 1. ‘Digital and Analog Communication Systems’, K. Sam Shanmugam,
2012,.John Wiley and Sons
UNIT 1-5 2. ‘Communication Systems’, Simon Haykin and Michael Moher, , 5/e, 2012.John
Wiley and Sons
REFERENCE BOOKS
UNIT 1-5 ‘Elements of Information Theory’, Thomas M. Cover, Joy.A.Thomas, John
Wiley and Sons, 2/e, 2012
‘Information Theory, Coding and Cryptography’, Ranjan Bose, Tata McGraw
UNIT 1-5
Hill, 2012
WEB RESOURCES
1. https://nptel.ac.in/courses/117101053/
2. https://www.tutorialspoint.com/principles_of_communication/principles_of_communication_informat
ion_theory.htm

COs/POs/PSOs Mapping

Program Specific
Program Outcomes (POs)
COs Outcomes (PSOs)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
1 3 3 3 2 1 1 1 - 1 1 - 2 3 2 1
2 3 3 3 2 1 1 1 - 1 1 - 2 3 2 1
3 3 3 3 2 1 1 1 - 1 1 - 2 3 2 1
4 3 3 3 2 1 1 1 - 1 1 - 2 3 2 1
5 3 3 3 2 1 1 1 - 1 1 - 2 3 2 1
 L T P C
CODE COMPUTER NETWORKS LABORATORY
0 0 3 1.5
COURSE OBJECTIVES
1 To learn to communicate between two desktop computers
2 To learn to implement the different protocols
3 To be familiar with IP Configuration
4 To be familiar with the various routing algorithms
5 To be familiar with simulation tools

COURSE OUTCOMES
Upon completion of the course, students shall have ability to

CO1 Communicate between two desktop computers

CO2 Implement the different protocols
CO3 Program using sockets
CO4 Implement and compare the various routing algorithms
CO5 Use the simulation tool

COURSE CONTENTS
1. Implementation of Error Detection / Error Correction Techniques
2. Implementation of Stop and Wait Protocol and sliding window
3. Implementation and study of Goback-N and selective repeat protocols
4. Implementation of High Level Data Link Control
5. Implementation of IP Commands such as ping, Traceroute, ns lookup.
6. Implementation of IP address configuration.
7. To create scenario and study the performance of network with CSMA / CA protocol and compare with
CSMA/CD protocols.
8. Network Topology - Star, Bus, Ring
9. Implementation of distance vector routing algorithm
10. Implementation of Link state routing algorithm
11. Study of Network simulator (NS) and simulation of Congestion Control Algorithms using NS
12. Implementation of Encryption and Decryption Algorithms using any programming language

COs/POs/PSOs Mapping

Program Specific
Program Outcomes (POs)
COs Outcomes (PSOs)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
1 3 2 3 1 3 3 2 - 2 2 3 1 3 - 3
2 3 2 3 1 3 3 2 - 2 2 3 1 3 - 3
3 3 2 3 1 3 3 2 - 2 2 3 1 3 - 3
4 3 2 3 1 3 3 2 - 2 2 3 1 3 - 3
5 3 2 3 1 3 3 2 - 2 2 3 1 3 - 3
 L T P C
CODE VLSI DESIGN LABORATORY
3 0 3 1.5
COURSE OBJECTIVES
The student should be made:
1 To learn Hardware Descriptive Language (Verilog)
2 To learn the fundamental principles of VLSI circuit design in digital
3 To provide hands on design experience with professional design (EDA) platforms
4 To familiarize fusing of logical modules on FPGAs

COURSE OUTCOMES
Upon completion of the course, students shall have ability to

CO 1 Ability to analyse and design various techniques for implementing combinational and
sequential digital circuits
CO 2 Analyzing and implementing the various combinational logic circuits and its truth table.
CO 3 Analyzing the various sequential logic circuits and its characterization.
S.No LIST OF EXPERIMENTS
1 Design an 8bit Adder using HDL. Simulate it using Xilinx/Altera Software and implement
by Xilinx/Altera FPGA
2 Design a 4bit Multiplier using HDL. Simulate it using Xilinx/Altera Software and
implement by Xilinx/Altera FPGA
3 Design an ALU using HDL. Simulate it using Xilinx/Altera Software and implement by
Xilinx/Altera FPGA
4 Design a Universal Shift Register using HDL. Simulate it using Xilinx/Altera Software and
implement by Xilinx/Altera FPGA
5 Design Finite State Machine (Moore/Mealy) using HDL. Simulate it using Xilinx/Altera
Software and implement by Xilinx/Altera FPGA
6 Design Memories using HDL. Simulate it using Xilinx/Altera Software and implement by
Xilinx/Altera FPGA
7 Design and simulate a MOD-10 counter using Xilinx/Altera Software and implement by
Xilinx/Altera FPGA
8 Design and simulate a 4-bit Asynchronous UP/DOWN counter using Xilinx/Altera Software
and implement by Xilinx/Altera FPGA
9 Design and simulate a 4-bit synchronous UP/DOWN counter using Xilinx/Altera Software
and implement by Xilinx/Altera FPGA
10 Design and simulate RTL and generate a waveform for combinational circuits

COs/POs/PSOs Mapping

Program Specific
Program Outcomes (POs)
COs Outcomes (PSOs)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
1 3 - - 3 - - - - - - - - 3 1 -
2 3 3 3 3 - - - - - - - - 3 1 -
3 3 3 3 3 3 - - - - - - - 3 1 -
4 3 3 3 3 3 - - - - - - - 3 1 -
5 3 - 3 3 3 - - - - - - - 3 1 -

CODE MINI-PROJECT L T P C
 0 0 2 1
COURSE OBJECTIVES

1 To identify problem faced in Society

2 To Understand the impact of professional engineering solutions to issue
3 To Design solutions for complex engineering problems
4 To Demonstrate knowledge and understanding of the engineering to provide solution
5 To apply the innovative solution to the identified problem

COURSE OUTCOMES
Upon completion of the course, students shall have ability to
CO1 Identify problem faced in Society
CO2 Understand the impact of professional engineering solutions to issue
CO3 Design solutions for complex engineering problems
CO4 Demonstrate knowledge and understanding of the engineering to provide solution
CO5 Apply the innovative solution to the identified problem

COURSE CONTENTS
Preparing a project – brief proposal including
 Problem Identification
 A Statement of system / process specifications proposed to be developed
(Block diagram / concept tree)
 List of possible solutions including alternatives and constraints
 Cost benefit analysis
 Time line of activities
A report highlighting the design finalization
(based on functional requirements & standards ( if any) )
A Presentation including the following
 Implementation Phase ( Hardware / Software / both )
 Testing and validation of the developed system
 Learning in the project
 Demonstration of Working Kit

Consolidated report preparation and submission

COs/POs/PSOs Mapping

Program Specific
Program Outcomes (POs)
COs Outcomes (PSOs)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
1 1 3 3 2 3 3 2 - 3 2 2 1 3 2 2
2 1 3 3 2 3 3 2 - 3 2 2 1 3 2 2
3 1 3 3 2 3 3 2 - 3 2 2 1 3 2 2
4 1 3 3 2 3 3 2 - 3 2 2 1 3 2 2
5 1 3 3 2 3 3 2 - 3 2 2 1 3 2 2