A B C D E

1 1

Compal Confidential
2 2

ZIWB2/ZIWB3/ZIWE1
DIS M/B Schematics Document
Intel Boardwell U Processor with DDR3L
AMD Topaz XT / Jet LE

2014-02-10
3 3

LA-B091P
：1.0
REV：

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

2011/06/24 2012/07/12 Title
Issued Date Deciphered Date Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B091P
Date: Wednesday, February 12, 2014 Sheet 1 of 55
A B C D E
 A B C D E

For DIS
1 1

Jet LE(15W) PCIe X4

Topaz XT(25W) (Gen2)
Memory Bus
VRAM(DDR3L) 1GB/2GB/4GB
A-ch DDR3L-SO-DIMM X1
DDR3L 1600MHz (1.35V)

Memory Bus
eDP X1
B-ch DDR3L-SO-DIMM X1
(2 Lanes) DDR3L 1600MHz (1.35V)
eDP Panel

Left USB3.0 x2 Right USB2.0 x1 Int. Camera

DDI X1
Intel Broadwell U USB3.0 x2 USB30 Port 0,1 USB20 Port 0 USB20 Port 3

CRT Translator (2 Lanes) 15W

CRT Conn. ITE USB2.0 x7 Touch Screen Right USB2.0 x1 Finger Printer
2 IT6513 For E14 2
USB20 Port 2 USB20 Port 4
1168pin BGA USB20 Port 1
DDI X1
(4 Lanes)
HDMI Conn.
SATA X1 HDD Conn.
PCIe X1 SATA Port 0
LAN (1 Lanes)
PCIe Port 0
RJ45 Conn. Realtek
RTL8106E/RTL8111G SATA X1 ODD Conn.
10/100/GIGA SATA Port 1
PCIe X1
Card Reader (1 Lanes)
PCIe Port 2
Realtek Audio Codec
RTS5229-GR AZALIA Realtek
ALC233
PCIe X1
NGFF Conn. (1 Lanes)
3
WLAN / BT 3
USB2.0 X1 Int. MIC Conn. Int. Speaker Conn. Audio Combo Jacks
(1 Lanes) HP & MIC

PCIe Port 1
LPC BUS

Sub-borad SPI ROM EC

Nuvoton
15" 8MB NPCE288N
14"
DC-in/B Docking/B
For B15
Thermal Sensor Touch Pad Int. KBD APS
For E14
Power/B Battery/B LIS34ALTR

IO/B ODD/B
4 For E14 4

USB Charge

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 12, 2014 Sheet 2 of 55
A B C D E
 1 2 3 4 5

Voltage Rails USB Port Table

3 External BOM Structure Table
USB 2.0 Port USB Port Item BOM Structure
+5VS 0 USB Port (Left Side) USB3.0 ZIWB2 (14") B14@
UHCI0
+3VS 1 USB Port (Left Side) USB3.0 ZIWB3 (15") B15@
power
plane +1.5VS 2 Touch Screen ZIWE1 (14") E14@
A UHCI1 A
+V1.05S_VCCP 3 Camera CPU_SA00006SM20 i5_4200U@
EHCI1
+5VALW +1.5V +VCC_CORE 4 CPU_SA00007AM00 QFSY@
UHCI2
+B +VGA_CORE 5 CPU_SA00006SU30 i3_4100U@
+3VALW +VCC_GFXCORE_AXG 6 CPU_SA000072Q10 i3_4005U@
UHCI3
+1.8VS 7 CPU_SA00006SX20 i3_4010U@
State +0.75VS 8 LAN 10/100 Transformer 100@
UHCI4
+1.05VS 9 USB Port (Right Side USB-BD) LAN GIGA Transformer GIGA@
10 Mini Card(WLAN) LAN Switch mode SWITCH@
EHCI2 UHCI5
11 Card Reader LAN RTL8106E-CG 8106ELDO@
12 LAN RTL8111GS-CG 8111GLDO@
UHCI6
13 LAN RTL8106EUS-CG 8106ESW@
LAN RTL8111GUS-CG 8111GSW@
S0 O O O O Audio_233 233@
Audio_233VB 233VB@
For B15 Docking@
S3
O O O X For B14, E14 NoDocking@
For Deep Sleep DS3@
S5 S4/AC O O X X For No Deep Sleep NoDS3@
B
WLAN Support ISCT ISCT@ B
S5 S4/ Battery only
O X X X WLAN No Support ISCT NoISCT@
For Intel ZERO ODD ZODD@
S5 S4/AC & Battery
X X X X For No Intel ZERO ODD NoZODD@
don't exist
For Green CLK GCLK@
For No Green CLK NoGCLK@
For No Green CLK NoGCLKDIS@ Only in DIS Schematic
Green CLK IC For DIS GCLKDIS@
Green CLK IC For UMA GCLKUMA@
EC SM Bus1 address EC SM Bus2 address
GPU support Dual Rank DR@ Only in DIS Schematic
Device Address Device Address
Smart Battery 0001 011x Thermal Sensor 0100 1100
GPU Jet LE JET@
GPU Topaz XT TOPAZ@
For DIS PX@
PCH SM Bus address AMD-GPU SM Bus address For UMA UMA@
Camera COMS@
Device Address Device Address
DDR_JDIMM1 1010 000x A0h Internal thermal sensor 0100 0001 41h
DDR_JDIMM2 1010 010x A4h
APS (G-sensor) GS@
Touch Screen TS@
C HDMI HDMI@ C

SMBUS Control Table USB 2.0 USB2@

USB 3.0 USB3@
Thermal Full HD Panel (2 Lane) FHD@
SOURCE VGA BATT KB9012 SODIMM WLAN Sensor PCH
ENE EC 9012 9012@
SMB_EC_CK1
SMB_EC_DA1
KB9012 X V
+3VALW
X X X X X HDMI Royalty
Connector
45@
ME@
+3VALW
SMB_EC_CK2
SMB_EC_DA2
KB9012 V
+3VGS
X X X X +3VS
V V
+3VALW
VRAM indentify
Un-pop component for EMI
X76@
@EMI@
No USE
+3VS
PCH_SMBCLK
X X X V V X X @ESD@
Un-pop component for ESD
PCH
PCH_SMBDATA +3VALW +3VS +3VS DA600140000 PCB_14_DIS@
PCH_SML0CLK
PCH
PCH_SML0DATA +3VALW
X X X X X X X DA600141000
DA600140100
PCB_14_UMA@
PCB_15_DIS@
SML1CLK
SML1DATA
PCH
+3VALW +3VGS
V X V
+3VS
X X V
+3VS
X DA600141100 PCB_15_UMA@

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

D Full ON HIGH HIGH HIGH HIGH ON ON ON ON D

S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF

S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF

Security Classification Compal Secret Data Compal Electronics, Inc.
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Notes List
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B091P
Wednesday, February 12, 2014 Sheet 3 of 55
1 2 3 4 5
 5 4 3 2 1

Power-Up/Down Sequence
"Mars" has the following requirements with regards to power-supply
sequencing to avoid damaging the ASIC:
Topaz XT_VRAM_STRAP ‧ All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
X76@ X76@ preferred. The maximum slew rate on all rails is 50 mV/µs.
Vendor R_pu R_pd ‧ The external pull ups on the DDC/AUX signals (if applicable) should ramp up
ID PS_3[ 3 ] PS_3[ 2 ] PS_3[ 1 ] before or after both VDDC and VDD_CT have ramped up.
D UV5, UV6, UV7, UV8 RV21 RV24 D

Hynix 4096Mbits ‧ VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC
ZZZ01 SA00006E800 should reach 90% before VDD_CT starts to ramp up (or vice versa).
2GBytes TH2G@ 256Mx16 H5TC4G63AFR-11C 0 0 0 0 NC 4.75K ‧ For power down, reversing the ramp-up sequence is recommended.
Samsung 2048Mbits
ZZZ02 SA000068U40
1GBytes TS1G@ 128Mx16 K4W2G1646Q-BC1A 1 0 0 1 8.45K 2K
VDDR3(3.3VGS)
Micron 2048Mbits
ZZZ03 SA000067500
1GBytes TM1G@ 128Mx16 MT41J128M16JT-093G:K 2 0 1 0 4.53K 2K PCIE_VDDC(0.95VGSV)
Hynix 2048Mbits
ZZZ04 SA00006H400
1GBytes TH1G@ 128Mx16 H5TC2G63FFR-11C 3 0 1 1 6.98K 4.99K VDDR1(1.5VGS)
Micron 4096Mbits
ZZZ05 SA000077K00
2GBytes TM2G@ 256Mx16 MT41J256M16HA-093G:E 4 1 0 0 4.53K 4.99K VDDC/VDDCI(1.12V)
Samsung 4096Mbits
ZZZ06 SA000076P00
2GBytes TS2G@ 256Mx16 K4W4G1646D-BC1A 5 1 0 1 3.24K 5.62K VDD_CT(1.8V)
Micron 2048Mbits
ZZZ07 SA00005XB00
1GBytes TM1G2@ 128Mx16 MT41K128M16JT-107G:K 6 1 1 0 3.4K 10K PERSTb
Micron 4096Mbits
C
ZZZ08 SA000065D00 C
2GBytes TM2G2@ 256Mx16 MT41K256M16HA-107G:E 7 1 1 1 4.75K NC REFCLK
ZZZ01 ZZZ02 ZZZ03 ZZZ04

Straps Reset

TH2G@ TS1G@ TM1G@ TH1G@ Straps Valid

2G HYNIX 1G SAMSUNG 1G MICRON 1G HYNIX
X7653638L01 X7653938L03 X7653938L02 X7653938L01

Global ASIC Reset

T4+16clock

Jet LE_VRAM_STRAP
X76@ X76@
Vendor R_pu R_pd
ID PS_3[ 3 ] PS_3[ 2 ] PS_3[ 1 ]
UV5, UV6, UV7, UV8 RV21 RV24
Hynix 2048Mbits
ZZZ09 SA00006H400
B 1GBytes JH1G@ 128Mx16 H5TC2G63FFR-11C 0 0 0 0 NC 4.75K B

Micron 2048Mbits
ZZZ10 SA000067500
1GBytes JM1G@ 128Mx16 MT41J128M16JT-093G:K 1 0 0 1 8.45K 2K
Samsung 2048Mbits
ZZZ11 SA000068U40
1GBytes JS1G@ 128Mx16 K4W2G1646Q-BC1A 2 0 1 0 4.53K 2K
Hynix 4096Mbits
ZZZ12 SA00006E800
2GBytes JH2G@ 256Mx16 H5TC4G63AFR-11C 3 0 1 1 6.98K 4.99K
Samsung 4096Mbits
ZZZ13 SA000076P00
2GBytes JS2G@ 256Mx16 K4W4G1646D-BC1A 4 1 0 0 4.53K 4.99K
Micron 4096Mbits
ZZZ14 SA000077K00
2GBytes JM2G@ 256Mx16 MT41J256M16HA-093G:E 5 1 0 1 3.24K 5.62K
Micron 4096Mbits
ZZZ08 SA000065D00
2GBytes JM2G2@ 256Mx16 MT41K256M16HA-107G:E 6 1 1 0 3.4K 10K
Micron 2048Mbits
ZZZ16 SA00005XB00
1GBytes JM1G2@ 128Mx16 MT41K128M16JT-107G:K 7 1 1 1 4.75K NC
A A

ZZZ09 ZZZ10 ZZZ11 ZZZ12

JH1G@ JM1G@ JS1G@ JH2G@

1G HYNIX 1G MICRON 1G SAMSUNG 2G HYNIX
X7653638L07 X7653638L08 X7653638L09 X7653638L04
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B091P
Date: Wednesday, February 12, 2014 Sheet 4 of 55
5 4 3 2 1
 5 4 3 2 1

DAZ
DA600140000
PCB 14I LA-B091P REV0 M/B DIS 3
PCB_14_DIS@

DAZ
DA600140100
PCB 14K LA-B091P REV0 M/B DIS 6
PCB_15_DIS@

DAZ
DA600141000
PCB 14I LA-B092P REV0 M/B UMA 3
PCB_14_UMA@

DAZ
DA600141100
D D
PCB 14K LA-B092P REV0 M/B UMA 6
PCB_15_UMA@
UC1A BDW_ULT_DDR3L(Interleaved)

C54 C45
<29> CPU_DP1_N0 C55 DDI1_TXN0 EDP_TXN0 B46 EDP_TXN0 <27>
<29> CPU_DP1_P0 DDI1_TXP0 EDP_TXP0 EDP_TXP0 <27>
CRT B58 A47
<29> CPU_DP1_N1 DDI1_TXN1 EDP_TXN1 EDP_TXN1 <27>
C58 B47
<29> CPU_DP1_P1 B55 DDI1_TXP1 EDP_TXP1 EDP_TXP1 <27>
A55 DDI1_TXN2 C47
A57 DDI1_TXP2 EDP_TXN2 C46
B57 DDI1_TXN3 EDP_TXP2 A49
DDI1_TXP3 DDI EDP EDP_TXN3 B49
eDP
CPU_DP2_N0 C51 EDP_TXP3
<37> CPU_DP2_N0 DDI2_TXN0
CPU_DP2_P0 C50 A45 EDP_AUXN <27>
<37> CPU_DP2_P0 C53 DDI2_TXP0 EDP_AUXN B45
CPU_DP2_N1 EDP_AUXP <27>
<37> CPU_DP2_N1 DDI2_TXN1 EDP_AUXP
CPU_DP2_P1 B54
<37> CPU_DP2_P1 DDI2_TXP1
CPU_DP2_N2 C49 D20 EDP_COMP R1 1 2 24.9_0402_1%
HDMI <37> CPU_DP2_N2
CPU_DP2_P2 B50 DDI2_TXN2 EDP_RCOMP A43 CPU_INV_PWM
+VCCIOA_OUT
<37> CPU_DP2_P2 DDI2_TXP2 EDP_DISP_UTIL
CPU_DP2_N3 A53 T1
<37> CPU_DP2_N3 B53 DDI2_TXN3
CPU_DP2_P3
<37> CPU_DP2_P3 DDI2_TXP3
EDP_COMP (R1):
Trace width=20 mils,Spacing=25mil,Max length=100mils
1 OF 19
BDW-ULT-DDR3L-IL_BGA1168
@

C C

UC1B BDW_ULT_DDR3L(Interleaved)

T2 D61
T3 K61 PROC_DETECT MISC
+1.05VS N62 CATERR J62 XDP_PRDY# T31
<35> H_PECI PECI PRDY K62 XDP_PREQ# T32
R2 1 2 62_0402_5% PREQ E60 XDP_TCK T4
PROC_TCK E61 XDP_TMS T5
R3 1 2 56_0402_5% H_PROCHOT#_R K63 JTAG PROC_TMS E59 XDP_TRST# T6
<35> H_PROCHOT# PROCHOT PROC_TRST
THERMAL F63 XDP_TDI T7
PROC_TDI F62 XDP_TDO T8
PROC_TDO
R4 1 2 10K_0402_5% H_CPUPWRGD C61
PROCPWRGD PWR
J60 XDP_BPM#0
BPM#0 H60 XDP_BPM#1
BPM#1 H61 XDP_BPM#2
+1.35V BPM#2 H62 XDP_BPM#3
R5 1 2 200_0402_1% SM_RCOMP0 AU60 BPM#3 K59 XDP_BPM#4
R6 1 2 470_0402_5% R7 1 2 120_0402_1% SM_RCOMP1 AV60 SM_RCOMP0 DDR3L BPM#4 H63 XDP_BPM#5
R8 1 2 100_0402_1% SM_RCOMP2 AU61 SM_RCOMP1 BPM#5 K60 XDP_BPM#6
DIMM_DRAMRST# AV15 SM_RCOMP2 BPM#6 J61 XDP_BPM#7
<16,17> DIMM_DRAMRST# SM_DRAMRST BPM#7
DDR_PG_CTRL AV61
<16> DDR_PG_CTRL SM_PG_CNTL1
1

C238 DDR3 Compensation Signals (R9, R10, R11): 2 OF 19

100P_0402_50V8J BDW-ULT-DDR3L-IL_BGA1168
20 mils to comp signals
2

25 mils to non-comp signals

500 mil for Max trace length

B ESD ESD B

H_CPUPWRGD
1

UC1
C237 SA00007G020
100P_0402_50V8J Intel 2957U 1.4G 2M D0 2cBGA CPU
2

2957U@

UC1
SA00007G220
S IC CL8064701569500 QFAN D0 1.7G BGA
3558U@

UC1
SA00006SL70
S IC CL8064701477202 QEVD C0 1.8G BGA
i7_4500U@

UC1
SA00006SM80
S IC CL8064701477702 SR170 C0 1.6G C38!
i5_4200U@

UC1
SA00007AM00
S IC CL8064701614813 QFSY C0 1.6G BGA
QFSY@

UC1
SA00006SU50
S IC CL8064701476302 SR16P C0 1.8G C38!
i3_4100U@

UC1
SA000072Q70
S IC CL8064701478404 QEAR D0 1.7G C38
A i3_4005U@ A

UC1
SA00006SX80
S IC CL8064701478202 SR16Q C0 1.7G C38!
i3_4010U@

Security Classification Compal Secret Data Compal Electronics, Inc.

2011/06/24 2012/07/12 Title
Issued Date Deciphered Date HSW MCP(1/11) DDI,MSIC,XDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B091P
Date: Wednesday, February 12, 2014 Sheet 5 of 55
5 4 3 2 1
 5 4 3 2 1

Interleaved Memory

D D

UC1C BDW_ULT_DDR3L(Interleaved) UC1D BDW_ULT_DDR3L(Interleaved)

<16> DDR_A_D[0..15]
DDR_A_D0 AH63 AU37 M_CLK_DDR#0 M_CLK_DDR#0 <16>
SA_DQ0 SA_CLK#0 <17> DDR_B_D[0..15]
DDR_A_D1 AH62 AV37 M_CLK_DDR0 DDR_B_D0 AP58 AM38 M_CLK_DDR#2
SA_DQ1 SA_CLK0 M_CLK_DDR0 <16> SB_DQ0 SB_CK#0 M_CLK_DDR#2 <17>
DDR_A_D2 AK63 AW36 M_CLK_DDR#1 DDR_B_D1 AR58 AN38 M_CLK_DDR2
SA_DQ2 SA_CLK#1 M_CLK_DDR#1 <16> SB_DQ1 SB_CK0 M_CLK_DDR2 <17>
DDR_A_D3 AK62 AY36 M_CLK_DDR1 M_CLK_DDR1 <16> DDR_B_D2 AM57 AK38 M_CLK_DDR#3 M_CLK_DDR#3 <17>
DDR_A_D4 AH61 SA_DQ3 SA_CLK1 DDR_B_D3 AK57 SB_DQ2 SB_CK#1 AL38 M_CLK_DDR3
SA_DQ4 SB_DQ3 SB_CK1 M_CLK_DDR3 <17>
DDR_A_D5 AH60 AU43 DDR_CKE0_DIMMA DDR_CKE0_DIMMA <16> DDR_B_D4 AL58
DDR_A_D6 AK61 SA_DQ5 SA_CKE0 AW43 DDR_CKE1_DIMMA DDR_B_D5 AK58 SB_DQ4 AY49 DDR_CKE2_DIMMB
SA_DQ6 SA_CKE1 DDR_CKE1_DIMMA <16> SB_DQ5 SB_CKE0 DDR_CKE2_DIMMB <17>
DDR_A_D7 AK60 AY42 DDR_B_D6 AR57 AU50 DDR_CKE3_DIMMB
SA_DQ7 SA_CKE2 T13 SB_DQ6 SB_CKE1 DDR_CKE3_DIMMB <17>
DDR_A_D8 AM63 AY43 T9 DDR_B_D7 AN57 AW49 T10
DDR_A_D9 AM62 SA_DQ8 SA_CKE3 DDR_B_D8 AP55 SB_DQ7 SB_CKE2 AV50
SA_DQ9 SB_DQ8 SB_CKE3 T11
DDR_A_D10 AP63 AP33 DDR_CS0_DIMMA# DDR_CS0_DIMMA# <16> DDR_B_D9 AR55
DDR_A_D11 AP62 SA_DQ10 SA_CS#0 AR32 DDR_CS1_DIMMA# DDR_B_D10 AM54 SB_DQ9 AM32 DDR_CS2_DIMMB#
SA_DQ11 SA_CS#1 DDR_CS1_DIMMA# <16> SB_DQ10 SB_CS#0 DDR_CS2_DIMMB# <17>
DDR_A_D12 AM61 DDR_B_D11 AK54 AK32 DDR_CS3_DIMMB#
SA_DQ12 SB_DQ11 SB_CS#1 DDR_CS3_DIMMB# <17>
DDR_A_D13 AM60 AP32 T12 DDR_B_D12 AL55
DDR_A_D14 AP61 SA_DQ13 SA_ODT0 DDR_B_D13 AK55 SB_DQ12 AL32
SA_DQ14 SB_DQ13 SB_ODT0 T14
DDR_A_D15 AP60 AY34 DDR_A_RAS# DDR_A_RAS# <16> DDR_B_D14 AR54
<16> DDR_A_D[16..31] SA_DQ15 SA_RAS SB_DQ14
DDR_A_D16 AY58 AW34 DDR_A_WE# DDR_B_D15 AN54 AM35 DDR_B_RAS#
SA_DQ16 SA_WE DDR_A_WE# <16> <17> DDR_B_D[16..31] SB_DQ15 SB_RAS DDR_B_RAS# <17>
DDR_A_D17 AW58 AU34 DDR_A_CAS# DDR_B_D16 AK40 AK35 DDR_B_WE#
SA_DQ17 SA_CAS DDR_A_CAS# <16> SB_DQ16 SB_WE DDR_B_WE# <17>
C DDR_A_D18 AY56 DDR_B_D17 AK42 AM33 DDR_B_CAS# DDR_B_CAS# <17> C
DDR_A_D19 AW56 SA_DQ18 AU35 DDR_A_BS0 DDR_B_D18 AM43 SB_DQ17 SB_CAS
SA_DQ19 SA_BA0 DDR_A_BS0 <16> SB_DQ18
DDR_A_D20 AV58 AV35 DDR_A_BS1 DDR_A_BS1 <16> DDR_B_D19 AM45 AL35 DDR_B_BS0 DDR_B_BS0 <17>
DDR_A_D21 AU58 SA_DQ20 SA_BA1 AY41 DDR_A_BS2 DDR_B_D20 AK45 SB_DQ19 SB_BA0 AM36 DDR_B_BS1
SA_DQ21 SA_BA2 DDR_A_BS2 <16> SB_DQ20 SB_BA1 DDR_B_BS1 <17>
DDR_A_D22 AV56 DDR_B_D21 AK43 AU49 DDR_B_BS2
SA_DQ22 DDR_A_MA[0..15] <16> SB_DQ21 SB_BA2 DDR_B_BS2 <17>
DDR_A_D23 AU56 AU36 DDR_A_MA0 DDR_B_D22 AM40 DDR_B_MA[0..15] <17>
DDR_A_D24 AY54 SA_DQ23 SA_MA0 AY37 DDR_A_MA1 DDR_B_D23 AM42 SB_DQ22 AP40 DDR_B_MA0
DDR_A_D25 AW54 SA_DQ24 SA_MA1 AR38 DDR_A_MA2 DDR_B_D24 AM46 SB_DQ23 SB_MA0 AR40 DDR_B_MA1
DDR_A_D26 AY52 SA_DQ25 SA_MA2 AP36 DDR_A_MA3 DDR_B_D25 AK46 SB_DQ24 SB_MA1 AP42 DDR_B_MA2
DDR_A_D27 AW52 SA_DQ26 SA_MA3 AU39 DDR_A_MA4 DDR_B_D26 AM49 SB_DQ25 SB_MA2 AR42 DDR_B_MA3
DDR_A_D28 AV54 SA_DQ27 SA_MA4 AR36 DDR_A_MA5 DDR_B_D27 AK49 SB_DQ26 SB_MA3 AR45 DDR_B_MA4
DDR_A_D29 AU54 SA_DQ28 SA_MA5 AV40 DDR_A_MA6 DDR_B_D28 AM48 SB_DQ27 SB_MA4 AP45 DDR_B_MA5
DDR_A_D30 AV52 SA_DQ29 SA_MA6 AW39 DDR_A_MA7 DDR_B_D29 AK48 SB_DQ28 SB_MA5 AW46 DDR_B_MA6
DDR_A_D31 AU52 SA_DQ30 DDR CHANNEL A SA_MA7 AY39 DDR_A_MA8 DDR_B_D30 AM51 SB_DQ29 SB_MA6 AY46 DDR_B_MA7
<16> DDR_A_D[32..47] AY31 SA_DQ31 SA_MA8 AU40 AK51 SB_DQ30 SB_MA7 AY47
DDR_A_D32 DDR_A_MA9 DDR_B_D31 DDR_B_MA8
SA_DQ32 SA_MA9 <17> DDR_B_D[32..47] SB_DQ31 DDR CHANNEL B SB_MA8
DDR_A_D33 AW31 AP35 DDR_A_MA10 DDR_B_D32 AM29 AU46 DDR_B_MA9
DDR_A_D34 AY29 SA_DQ33 SA_MA10 AW41 DDR_A_MA11 DDR_B_D33 AK29 SB_DQ32 SB_MA9 AK36 DDR_B_MA10
DDR_A_D35 AW29 SA_DQ34 SA_MA11 AU41 DDR_A_MA12 DDR_B_D34 AL28 SB_DQ33 SB_MA10 AV47 DDR_B_MA11
DDR_A_D36 AV31 SA_DQ35 SA_MA12 AR35 DDR_A_MA13 DDR_B_D35 AK28 SB_DQ34 SB_MA11 AU47 DDR_B_MA12
DDR_A_D37 AU31 SA_DQ36 SA_MA13 AV42 DDR_A_MA14 DDR_B_D36 AR29 SB_DQ35 SB_MA12 AK33 DDR_B_MA13
DDR_A_D38 AV29 SA_DQ37 SA_MA14 AU42 DDR_A_MA15 DDR_B_D37 AN29 SB_DQ36 SB_MA13 AR46 DDR_B_MA14
DDR_A_D39 AU29 SA_DQ38 SA_MA15 DDR_B_D38 AR28 SB_DQ37 SB_MA14 AP46 DDR_B_MA15
SA_DQ39 DDR_A_DQS#[0..1] <16> SB_DQ38 SB_MA15
DDR_A_D40 AY27 AJ61 DDR_A_DQS#0 DDR_B_D39 AP28 DDR_B_DQS#[0..1] <17>
DDR_A_D41 AW27 SA_DQ40 SA_DQSN0 AN62 DDR_A_DQS#1 DDR_B_D40 AN26 SB_DQ39 AM58 DDR_B_DQS#0
SA_DQ41 SA_DQSN1 DDR_A_DQS#[2..3] <16> SB_DQ40 SB_DQSN0
DDR_A_D42 AY25 AV57 DDR_A_DQS#2 DDR_B_D41 AR26 AM55 DDR_B_DQS#1
SA_DQ42 SA_DQSN2 SB_DQ41 SB_DQSN1 DDR_B_DQS#[2..3] <17>
DDR_A_D43 AW25 AV53 DDR_A_DQS#3 DDR_A_DQS#[4..5] <16> DDR_B_D42 AR25 AL43 DDR_B_DQS#2
DDR_A_D44 AV27 SA_DQ43 SA_DQSN3 AW30 DDR_A_DQS#4 DDR_B_D43 AP25 SB_DQ42 SB_DQSN2 AL48 DDR_B_DQS#3
SA_DQ44 SA_DQSN4 SB_DQ43 SB_DQSN3 DDR_B_DQS#[4..5] <17>
DDR_A_D45 AU27 AV26 DDR_A_DQS#5 DDR_A_DQS#[6..7] <16> DDR_B_D44 AK26 AN28 DDR_B_DQS#4
DDR_A_D46 AV25 SA_DQ45 SA_DQSN5 AW22 DDR_A_DQS#6 DDR_B_D45 AM26 SB_DQ44 SB_DQSN4 AN25 DDR_B_DQS#5
SA_DQ46 SA_DQSN6 SB_DQ45 SB_DQSN5 DDR_B_DQS#[6..7] <17>
DDR_A_D47 AU25 AV18 DDR_A_DQS#7 DDR_B_D46 AK25 AN21 DDR_B_DQS#6
<16> DDR_A_D[48..63] SA_DQ47 SA_DQSN7 SB_DQ46 SB_DQSN6
DDR_A_D48 AY23 DDR_A_DQS[0..1] <16> DDR_B_D47 AL25 AN18 DDR_B_DQS#7
AW23 SA_DQ48 AJ62 <17> DDR_B_D[48..63] AR21 SB_DQ47 SB_DQSN7
DDR_A_D49 DDR_A_DQS0 DDR_B_D48 DDR_B_DQS[0..1] <17>
DDR_A_D50 AY21 SA_DQ49 SA_DQSP0 AN61 DDR_A_DQS1 DDR_B_D49 AR22 SB_DQ48 AN58 DDR_B_DQS0
SA_DQ50 SA_DQSP1 DDR_A_DQS[2..3] <16> SB_DQ49 SB_DQSP0
DDR_A_D51 AW21 AW57 DDR_A_DQS2 DDR_B_D50 AL21 AN55 DDR_B_DQS1
SA_DQ51 SA_DQSP2 SB_DQ50 SB_DQSP1 DDR_B_DQS[2..3] <17>
DDR_A_D52 AV23 AW53 DDR_A_DQS3 DDR_B_D51 AM22 AL42 DDR_B_DQS2
SA_DQ52 SA_DQSP3 DDR_A_DQS[4..5] <16> SB_DQ51 SB_DQSP2
DDR_A_D53 AU23 AV30 DDR_A_DQS4 DDR_B_D52 AN22 AL49 DDR_B_DQS3 DDR_B_DQS[4..5] <17>
DDR_A_D54 AV21 SA_DQ53 SA_DQSP4 AW26 DDR_A_DQS5 DDR_B_D53 AP21 SB_DQ52 SB_DQSP3 AM28 DDR_B_DQS4
SA_DQ54 SA_DQSP5 DDR_A_DQS[6..7] <16> SB_DQ53 SB_DQSP4
DDR_A_D55 AU21 AV22 DDR_A_DQS6 DDR_B_D54 AK21 AM25 DDR_B_DQS5 DDR_B_DQS[6..7] <17>
B
DDR_A_D56 AY19 SA_DQ55 SA_DQSP6 AW18 DDR_A_DQS7 DDR_B_D55 AK22 SB_DQ54 SB_DQSP5 AM21 DDR_B_DQS6 B
DDR_A_D57 AW19 SA_DQ56 SA_DQSP7 DDR_B_D56 AN20 SB_DQ55 SB_DQSP6 AM18 DDR_B_DQS7
DDR_A_D58 AY17 SA_DQ57 AP49 +SM_VREF_CA DDR_B_D57 AR20 SB_DQ56 SB_DQSP7
SA_DQ58 SM_VREF_CA +SM_VREF_CA <16> SB_DQ57
DDR_A_D59 AW17 AR51 +SM_VREF_DQ0 DDR_B_D58 AK18
SA_DQ59 SM_VREF_DQ0 +SM_VREF_DQ0 <16> SB_DQ58
DDR_A_D60 AV19 AP51 +SM_VREF_DQ1 +SM_VREF_DQ1 <17> DDR_B_D59 AL18
DDR_A_D61 AU19 SA_DQ60 SM_VREF_DQ1 DDR_B_D60 AK20 SB_DQ59
DDR_A_D62 AV17 SA_DQ61 DDR_B_D61 AM20 SB_DQ60
SA_DQ62 Trace width >= 10mils SB_DQ61
DDR_A_D63 AU17 DDR_B_D62 AR18
SA_DQ63 DDR_B_D63 AP18 SB_DQ62
SB_DQ63

3 OF 19 4 OF 19
BDW-ULT-DDR3L-IL_BGA1168 BDW-ULT-DDR3L-IL_BGA1168

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2011/06/24 2012/07/12 Title
Issued Date Deciphered Date HSW MCP(2/11) DDRIII
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B091P
Date: Wednesday, February 12, 2014 Sheet 6 of 55
5 4 3 2 1
 5 4 3 2 1

D D

GCLK
RG3 1 GCLK@ 2 0_0402_5% PCH_RTCX1
<41> CPU_RTCX1_GCLK

PCH_RTCX1

R9 1NOGCLK@ 2 10M_0402_5% PCH_RTCX2

2

UC1E BDW_ULT_DDR3L(Interleaved)
R10
0_0402_5%
Y1 PCH_RTCX1 AW5
RTCX1
1

1 2 PCH_RTCX2 AY5
SM_INTRUDER# AU6 RTCX2 J5
INTRUDER SATA_RN0/PERN6_L3 SATA_PRX_DTX_N0 <30>
32.768KHZ 12.5PF 9H03200031 PCH_INTVRMEN AV7 H5
INTVRMEN SATA_RP0/PERP6_L3 SATA_PRX_DTX_P0 <30>
NOGCLK@ PCH_SRTCRST# AV6 RTC B15
SJ10000HW00 PCH_RTCRST# AU7 SRTCRST SATA_TN0/PETN6_L3 A15
SATA_PTX_DRX_N0 <30> HDD
1 1 RTCRST SATA_TP0/PETP6_L3 SATA_PTX_DRX_P0 <30>
C1 C2
12P_0402_50V_NPO 12P_0402_50V_NPO J8 SATA_PRX_DTX_N1 <30>
NOGCLK@ NOGCLK@ SATA_RN1/PERN6_L2 H8
2 2 SATA_RP1/PERP6_L2 SATA_PRX_DTX_P1 <30>
HDA for AUDIO A17
SATA_TN1/PETN6_L2 B17
SATA_PTX_DRX_N1 <30> ODD
SATA_TP1/PETP6_L2 SATA_PTX_DRX_P1 <30>
RP1
<39> HDA_BITCLK_AUDIO 1 8 HDA_BIT_CLK AW8 J6
2 7 HDA_SYNC AV11 HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1 H6
<39> HDA_SYNC_AUDIO HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1
3 6 HDA_RST# AU8 B14
<39> HDA_RST_AUDIO# HDA_RST/I2S_MCLK AUDIO SATA SATA_TN2/PETN6_L1
C <39> HDA_SDOUT_AUDIO 4 5HDA_SDOUT HDA_SDIN0 AY10 C15 C
AU12 HDA_SDI0/I2S0_RXD SATA_TP2/PETP6_L1
33_0804_8P4R_5% HDA_SDOUT AU11 HDA_SDI1/I2S1_RXD F5
HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0

1
@EMI@ AW10 E5
C227 AV10 HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0 C17
22P_0402_50V8J
EMI AY8 HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 D17

2
I2S1_SCLK SATA_TP3/PETP6_L0
+RTCVCC
V1 PCH_GPIO34
1 2 0_0402_5% SATA0GP/GPIO34 U1 PCH_GPIO34 <10>
<35> ME_EN R11 SATA_ODD_PRSNT SATA_ODD_PRSNT <30,9>
R12 1 2 20K_0402_5% PCH_SRTCRST# HDA_SDIN0 SATA1GP/GPIO35 V6 PCH_GPIO36 +1.05VS_ASATA3PLL
<39> HDA_SDIN0 SATA2GP/GPIO36 PCH_GPIO36 <9>
AC1 PCH_GPIO37
SATA3GP/GPIO37 PCH_GPIO37 <10>
C3 1 2 1U_0402_6.3V6K PCH_JTAG_TRST# AU62
PCH_JTAG_TCK AE62 PCH_TRST A12
CLRP1 1 2 SHORT PADS PCH_JTAG_TDI AD61 PCH_TCK SATA_IREF L11
Clear ME PCH_TDI RSVD
PCH_JTAG_TDO AE61 K10 within 500 mils
PCH_JTAG_TMS AD62 PCH_TDO JTAG
RSVD C12 SATA_RCOMP R13 1 2 3.01K_0402_1%
R14 1 2 20K_0402_5% PCH_RTCRST# AL11 PCH_TMS SATA_RCOMP U3 PCH_SATALED#
RSVD SATALED PCH_SATALED# <33>
AC4
C4 1 2 1U_0402_6.3V6K AE63 RSVD
AV2 JTAGX
CLRP2 1 2 SHORT PADS RSVD
Clear CMOS

R15 1 2 1M_0402_5% SM_INTRUDER#

5 OF 19
BDW-ULT-DDR3L-IL_BGA1168
R16 1 2 330K_0402_5% PCH_INTVRMEN
+3VS
R17 1 @ 2 330K_0402_5%

INTVRMEN: PCH_SATALED# R18 1 2 10K_0402_5%

： Integrated VRM enable
(*) H：
： Integrated VRM disable
( ) L：

B B
RTC Battery
+RTCVCC +RTCBATT

W=20mils
R19 1 2 0_0402_5%

1
C5
1U_0402_6.3V6K

Safty suggestion remove EE side ,Keep PWR side

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2011/06/24 2012/07/12 Title
Issued Date Deciphered Date HSW MCP(3/11) RTC,SATA,XDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B091P
Date: Wednesday, February 12, 2014 Sheet 7 of 55
5 4 3 2 1
 5 4 3 2 1

GCLK

RG9 1 GCLK@ 2 0_0402_5% XTAL24_IN

<41> CPU_XTAL24_IN_GCLK

UC1F BDW_ULT_DDR3L(Interleaved)

XTAL24_IN

C43 A25 XTAL24_IN R21 2NOGCLK@ 1 1M_0402_5% XTAL24_OUT

C42 CLKOUT_PCIE_N0 XTAL24_IN B25 XTAL24_OUT
PCH_GPIO18 U2 CLKOUT_PCIE_P0 XTAL24_OUT NOGCLK@
<10> PCH_GPIO18 PCIECLKRQ0/GPIO18 Y2
K21 24MHZ_12PF_7V24000020
D
B41 RSVD M21 D
<40> CLK_PCIE_CR# A41 CLKOUT_PCIE_N1 RSVD C26 1 2 3.01K_0402_1% 1 3
Card Reader XCLK_BIASREF R22 +1.05VS_AXCK_LCPLL SJ10000DI00
<40> CLK_PCIE_CR CLKOUT_PCIE_P1 DIFFCLK_BIASREF 1 3
<40> CRCLK_REQ# Y5
PCIECLKRQ1/GPIO19 C35 RP3 4 5 10K_8P4R_5% GND GND
TESTLOW_C35 1 1
C41 CLOCK C34 3 6 C6 C7
<38> CLK_PCIE_LAN# CLKOUT_PCIE_N2 TESTLOW_C34 2 4
B42 AK8 2 7 15P_0402_50V8J 15P_0402_50V8J
LAN <38> CLK_PCIE_LAN AD1 CLKOUT_PCIE_P2 SIGNALS TESTLOW_AK8 AL8 1 8 NOGCLK@ NOGCLK@
<38> LANCLK_REQ# PCIECLKRQ2/GPIO20 TESTLOW_AL8 2 2
B38 AN15 CLKOUT_LPC0 R23 2 1 22_0402_5%
<31> CLK_PCIE_WLAN# CLKOUT_PCIE_N3 CLKOUT_LPC_0 CK_LPC_KBC <35>
WLAN C37 AP15
<31> CLK_PCIE_WLAN CLKOUT_PCIE_P3 CLKOUT_LPC_1
N1
<31> WLANCLK_REQ#

<18> CLK_PCIE_GPU#
A39
B39
PCIECLKRQ3/GPIO21

CLKOUT_PCIE_N4
CLKOUT_ITPXDP
CLKOUT_ITPXDP_P
B35
A35 EMI
dGPU <18> CLK_PCIE_GPU
R25 1 2 0_0402_5% GPUCLK_REQ#_R U5 CLKOUT_PCIE_P4
<19> GPUCLK_REQ# PCIECLKRQ4/GPIO22
B37
A37 CLKOUT_PCIE_N5
PCH_GPIO23 T2 CLKOUT_PCIE_P5
<10> PCH_GPIO23 PCIECLKRQ5/GPIO23
+3VS
+3VS 6 OF 19
RP4 BDW-ULT-DDR3L-IL_BGA1168
：DIMM1, DIMM2
SMB：
1

UMA@ 1 8
R26 2 7 PCH_GPIO32
PCH_GPIO32 <9> +3VS
10K_0402_5% 3 6
4 5
2

10K_8P4R_5% @ R27 2.2K_0402_5%

2
GPUCLK_REQ#_R UC1G BDW_ULT_DDR3L(Interleaved) Q1A 1 2 +3VS
2

LPC_AD0 AU14 AN2 PCH_GPIO11 SMBDATA 6 1

<35> LPC_AD0 LAD0 SMBALERT/GPIO11 PCH_GPIO11 <10> PCH_SMB_DATA <16,17>
PX@ LPC_AD1 AW12 AP2 SMBCLK
<35> LPC_AD1 AY12 LAD1 SMBCLK AH1
R28 LPC_AD2 LPC SMBDATA DMN65D8LDW-7 2N SOT363-6
<35> LPC_AD2 LAD2 SMBUS SMBDATA
10K_0402_5% LPC_AD3 AW11 AL2 PCH_GPIO60
<35> LPC_AD3 LAD3 SML0ALERT/GPIO60 PCH_GPIO60 <10>
LPC_FRAME# AV12 AN1 SML0CLK @ R29 2.2K_0402_5%
<35> LPC_FRAME#
1

LFRAME SML0CLK

5
AK1 SML0DATA Q1B 1 2
SML0DATA +3VS
C AU4 PCH_GPIO73 C
SML1ALERT/PCHHOT/GPIO73 AU3 PCH_GPIO73 <10> 3 4
SML1CLK SMBCLK
+3V_PCH SML1CLK/GPIO75 PCH_SMB_CLK <16,17>
AH3 SML1DATA
EMI @EMI@
1
PCH_SPI_CLK
PCH_SPI_CS0#
AA3
Y7
Y4
SPI_CLK
SPI_CS0
SML1DATA/GPIO74

CL_CLK
AF2
AD2 SMBDATA R31
DMN65D8LDW-7 2N SOT363-6

1 2 0_0402_5% PCH_SMB_DATA
C225 AC2 SPI_CS1 SPI C-LINK
CL_DATA AF4
22P_0402_50V8J PCH_SPI_SI AA2 SPI_CS2 CL_RST SMBCLK R33 1 2 0_0402_5% PCH_SMB_CLK
2

PCH_SPI_SO AA4 SPI_MOSI

PCH_SPI_WP# Y6 SPI_MISO
R34 1 2 1K_0402_1% PCH_SPI_HOLD# AF1 SPI_IO2
R35 1 2 1K_0402_1% SPI_IO3

：Thermal IC, EC, dGPU

SML1：
7 OF 19
PCH_SPI_WP#_R R36 1 2 33_0402_5% PCH_SPI_WP# BDW-ULT-DDR3L-IL_BGA1168 +3VS

RP5 EMI
PCH_SPI_HOLD#_R 1 8 PCH_SPI_HOLD# @ R37 2.2K_0402_5%

2
PCH_SPI_CLK_R 2 7 PCH_SPI_CLK Q2A 1 2 +3VS
To SPI 8MByte ROM PCH_SPI_SI_R 3 6 PCH_SPI_SI From PCH
PCH_SPI_SO_R 4 5 PCH_SPI_SO SML1DATA 6 1
EC_SMB_DA2 <19,32,35>
33_0804_8P4R_5% DMN65D8LDW-7 2N SOT363-6

PCH_SPI_CS0#_R R38 1 2 0_0402_5% PCH_SPI_CS0# @ R39 2.2K_0402_5%

5
Q2B 1 2 +3VS
SML1CLK 3 4 EC_SMB_CK2 <19,32,35>
DMN65D8LDW-7 2N SOT363-6

SML1DATA R41 1 2 0_0402_5% EC_SMB_DA2

SML1CLK R42 1 2 0_0402_5% EC_SMB_CK2

B B

+3V_PCH
@
RP7
SMBCLK 1 8
EMI RP8
SMBDATA
SML1DATA
SML1CLK
2
3
4
7
6
5
1 8 PCH_SPI_CS0#_R
<35> EC_SPI_CS0#
2 7 PCH_SPI_CLK_R 2.2K_0804_8P4R_5%
<35> EC_SPI_CLK 3 6
From EC PCH_SPI_SI_R To SPI 8MByte ROM
<35> EC_SPI_MOSI
4 5 PCH_SPI_SO_R
(For share ROM) <35> EC_SPI_MISO
SML0CLK R46 1 2 499_0402_1%
1

@EMI@ 33_0804_8P4R_5% SML0DATA R47 1 2 499_0402_1%

EMI C226
22P_0402_50V8J
2

+3V_PCH

SPI ROM ( 8MByte )

U1 @
PCH_SPI_CS0#_R 1 8 +3V_ROM C8 1 2 .1U_0402_16V7K
PCH_SPI_SO_R 2 /CS VCC 7 PCH_SPI_HOLD#_R
PCH_SPI_WP#_R 3 DO(IO1) /HOLD(IO3) 6 PCH_SPI_CLK_R
4 /WP(IO2) CLK 5 PCH_SPI_SI_R
GND DI(IO0)
W25Q64FVSSIQ_SO8

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2011/06/24 2012/07/12 Title
Issued Date Deciphered Date HSW MCP(4/11) CLK,SPI,SMBUS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B091P
Date: Wednesday, February 12, 2014 Sheet 8 of 55
5 4 3 2 1
 5 4 3 2 1

ESD ESD
SYS_PWROK EC_RSMRST#
1

1
@ESD@
C239 C240
100P_0402_50V8J 100P_0402_50V8J
2

2
D D

Note: SUSACK# and SUSWARN# can be tied together if

EC does not want to involve in the handshake mechanism DSWODVREN - On Die DSW VR Enable
for the Deep Sleep state entry and exit ： Enable(DEFAULT)
(*) H：
： Disable
( ) L：
+RTCVCC
CAN be NC ,if not support Deep Sx
SUSWARN#_R R48 1 @ 2 0_0402_5% R49 1 2 330K_0402_5%
UC1H BDW_ULT_DDR3L(Interleaved) R50 1 @ 2 330K_0402_5%

SYSTEM POWER MANAGEMENT

DS3
DS3
+3VALW R51 1 DS3@ 2 0_0402_5% SUSACK#_R AK2 AW7 DSWODVREN R52 1 DS3@ 2 0_0402_5%
<35,46> SUSACK# SUSACK DSWVRMEN DPWROK_EC <35>
SYS_RESET# AC3 AV5 PCH_DPWROK R53 1NODS3@ 2 0_0402_5% EC_RSMRST#
<10> SYS_RESET# AG2 SYS_RESET DPWROK AJ5 2 1 10K_0402_5%
<35> SYS_PWROK SYS_PWROK R57
SYS_PWROK WAKE
1

<35> PCH_PWROK PCH_PWROK AY7 PCH_PCIE_WAKE# <31>

R54 R55 1 2 0_0402_5% APWROK_R AB5 PCH_PWROK
10K_0402_5% CPU_PLT_RST# AG7 APWROK V5 PCH_GPIO32
PLTRST CLKRUN/GPIO32 PCH_GPIO32 <8>
AG4
SUS_STAT/GPIO61 AE6 SUSCLK
SUSCLK <31>
2

AC_PRESENT SUSCLK/GPIO62 AP5 PM_SLP_S5#

<33,35> AC_PRESENT SLP_S5/GPIO63 PM_SLP_S5# <35>
EC_RSMRST# AW6
<35> EC_RSMRST# RSMRST
R58 1 DS3@ 2 0_0402_5% SUSWARN#_R AV4
<35> SUSWARN# SUSWARN/SUSPWRDNACK/GPIO30
<35> PBTN_OUT# PBTN_OUT# AL7 AJ6 PM_SLP_S4#
AJ8 PWRBTN SLP_S4 AT4 PM_SLP_S4# <35>
AC_PRESENT PM_SLP_S3#
ACPRESENT/GPIO31 SLP_S3 PM_SLP_S3# <35>
DS3 PCH_GPIO72 AN4 AL5
T15 @ AF3 BATLOW/GPIO72 SLP_A AP4 SLP_SUS#
AM5 SLP_S0 SLP_SUS AJ7 SLP_SUS# <35>
PCH_GPIO29
SLP_WLAN/GPIO29 SLP_LAN
DS3
+3VS

RP10
1 8 SERIRQ 8 OF 19
SERIRQ <10,35> BDW-ULT-DDR3L-IL_BGA1168
C 2 7 PCH_GPIO36 PCH_GPIO36 <7> C
3 6 TPMPD# TPMPD# <10>
4 5 SATA_ODD_PRSNT SATA_ODD_PRSNT <30,7>
10K_8P4R_5% R59 2 1 0_0402_5%

RP11
1 8 +3VS
2 7 PCH_GPIO38 PCH_GPIO38 <10>
3 6 PCH_GPIO52 @

5
4 5 U3
CPU_PLT_RST# 2

P
10K_8P4R_5% B 4
Y PLT_RST# <18,31,35,38,40>
1
A

1
G
RP12
1 8 PCH_GPIO68 PCH_GPIO68 <10,37> R60

3
2 7 DGPU_PWROK 100K_0402_5%
3 6 PCH_GPIO55 U74AHC1G08G-AL5-R_SOT353-5
4 5

2
10K_8P4R_5%

R61 1 2 2.2K_0402_5% DDI1_CTRL_CK

R62 1 2 2.2K_0402_5% DDI1_CTRL_DATA

UC1I BDW_ULT_DDR3L(Interleaved)

0_0402_5%
+3V_PCH R63 1 2 EDP_BKCTL B8 B9 DDI1_CTRL_CK
<27> INVPWM A9 EDP_BKLCTL DDPB_CTRLCLK C9 DDI1_CTRL_DATA
<27,35> ENBKL EDP_BKLEN eDP SIDEBAND DDPB_CTRLDATA
C6 D9
<27> PCH_ENVDD EDP_VDDEN DDPC_CTRLCLK HDMICLK_NB <28,37>
R64 1 2 10K_0402_5% SUSWARN#_R D11 HDMI DDC (Port C)
1 2 10K_0402_5% DDPC_CTRLDATA HDMIDAT_NB <28,37>
R65 PCH_GPIO72

U6
<51> DGPU_PWROK PIRQA/GPIO77
P4 C5 DDI1_AUX_DN
B <20,35,48,51> DGPU_PWR_EN
N4 PIRQB/GPIO78 DDPB_AUXN B6 DDI2_AUX_DN
DDI1_AUX_DN <29> DP Aux (Port B for VGA) B
<18> DGPU_HOLD_RST# N2 PIRQC/GPIO79 DISPLAY DDPC_AUXN B5 DDI1_AUX_DP
DDI2_AUX_DN <37> DP Aux (Port C for Docking)
<10,31> WLBT_OFF#
T16 @ AD4 PIRQD/GPIO80 DDPB_AUXP A6 DDI2_AUX_DP
DDI1_AUX_DP <29> DP Aux (Port B for VGA)
+3VALW PME PCIE DDPC_AUXP DDI2_AUX_DP <37> DP Aux (Port C for Docking)
PCH_GPIO55 U7
PCH_GPIO52 L1 GPIO55
PCH_GPIO54 L3 GPIO52 C8
<10> PCH_GPIO54 GPIO54 DDPB_HPD DDI1_HPD <29> From VGA Trans.
R66 1 @ 2 10K_0402_5% PCH_GPIO29 PCH_GPIO51 R5 A8 DDPC_HPD R148 1 2 0_0402_5% TMDS_B_HPD <28,37> From HDMI
1 2 1K_0402_5% <10> PCH_GPIO51 L4 GPIO51 DDPC_HPD D6
R67 PCH_PCIE_WAKE# PCH_GPIO53 EDP_HPD <27> From eDP
<10> PCH_GPIO53 GPIO53 EDP_HPD

9 OF 19
+3VGS +3VS BDW-ULT-DDR3L-IL_BGA1168

R223 1 2 10K_0402_5% DGPU_PWR_EN

R224 1 @ 2 10K_0402_5%

+3VGS +3VS

R225 1 2 10K_0402_5% DGPU_HOLD_RST#

R226 1 @ 2 10K_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2011/06/24 2012/07/12 Title
Issued Date Deciphered Date HSW MCP(5/11) PM,GPIO,DDI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B091P
Date: Wednesday, February 12, 2014 Sheet 9 of 55
5 4 3 2 1
 5 4 3 2 1

D D

+3V_PCH

1
RP13
8 Docking_PRSNT#
ESD
2 7 PCH_GPIO47 H_THERMTRIP#
3 6 PCH_GPIO24

1
4 5 PCH_GPIO28
+1.05VS C241
10K_8P4R_5% 100P_0402_50V8J

2
GPIO15 : TLS Confidentiality for iAMT

1
@ RP14 UC1J BDW_ULT_DDR3L(Interleaved)
1 8 PCH_GPIO11
： Intel ME TLS with confidenAality
( ) H： R68
PCH_GPIO11 <8> ： Intel ME TLS with no confidenAality
(*) L：
2 7 PCH_GPIO60 1K_0402_1%
PCH_GPIO60 <8>
3 6 PCH_GPIO26 (Have internal PD)
4 5 PCH_GPIO58

2
PCH_GPIO76 P1 D60 H_THERMTRIP#
10K_8P4R_5% +3V_PCH PCH_GPIO8 AU2 BMBUSY/GPIO76 THRMTRIP V4
AM7 GPIO8 RCIN/GPIO82 T4 KB_RST# <35>
SERIRQ SERIRQ <35,9>
<11> PCH_GPIO12 LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ
R69 1 @ 2 PCH_GPIO15 AD6 AW15 PCH_OPIRCOMP 1 2
R288 1 2 10K_0402_5% 1K_0402_1% Y1 GPIO15 MISC PCH_OPI_RCOMP AF20 R70
USB_OC1# <11,34> <30> ODD_EN GPIO16 RSVD
T3 AB21 49.9_0402_1%
<30> ODD_DA# GPIO17 RSVD
PCH_GPIO24 AD5
PCH_GPIO27 AN5 GPIO24
GPIO27 PCH_GPIO86： ： Boot BIOS LocaAon
PCH_GPIO28 AD7
PCH_GPIO26 AN3 GPIO28 ： LPC BUS
( ) H：
GPIO26 R6 PCH_GPIO83 ： SPI BUS
(*) L：
@ RP16 PCH_GPIO56 AG6 GSPI0_CS/GPIO83 L6 PCH_GPIO84 +3VS
1 8 PCH_GPIO59 PCH_GPIO57 AP1 GPIO56 GSPI0_CLK/GPIO84 N6 PCH_GPIO85
2 7 PCH_GPIO8 PCH_GPIO58 AL4 GPIO57 GSPI0_MISO/GPIO85 L8 PCH_GPIO86 R71 1 @ 2 1K_0402_1%
C C
3 6 PCH_GPIO43 PCH_GPIO59 AT5 GPIO58 GSPI0_MOSI/GPIO86 R7 PCH_GPIO87 R72 1 2 1K_0402_1%
PCH_GPIO43 <11> GPIO59 GPIO GSPI1_CS/GPIO87
4 5 PCH_GPIO57 PCH_GPIO44 AK4 L5 PCH_GPIO88
PCH_GPIO47 AB6 GPIO44 GSPI1_CLK/GPIO88 N7 PCH_GPIO89
10K_8P4R_5% TPMPD# U4 GPIO47 GSPI1_MISO/GPIO89 K2 PCH_GPIO90
<9> TPMPD# GPIO48 GSPI_MOSI/GPIO90
DGPU_PRSNT# Y3 J1 PCH_GPIO91
@ RP9 TS_INT# P3 GPIO49 UART0_RXD/GPIO91 K3 PCH_GPIO92
<27> TS_INT# GPIO50 UART0_TXD/GPIO92
8 1 PCH_GPIO56 PCH_GPIO71 Y2 J2 PCH_GPIO93
7 2 PCH_GPIO14 PCH_GPIO13 AT3 HSIOPC/GPIO71 SERIAL IO UART0_RTS/GPIO93 G1 PCH_GPIO94
6 3 PCH_GPIO46 PCH_GPIO14 AH4 GPIO13 UART0_CTS/GPIO94 K4 PCH_GPIO0
5 4 TS_Detect AM4 GPIO14 UART1_RXD/GPIO0 G2 PCH_GPIO1
<27> TS_Detect AG5 GPIO25 UART1_TXD/GPIO1 J3
Docking_PRSNT# PCH_GPIO2
<36,37> Docking_PRSNT# GPIO45 UART1_RST/GPIO2
10K_8P4R_5% PCH_GPIO46 AG3 J4 PCH_GPIO3
GPIO46 UART1_CTS/GPIO3 F2 PCH_GPIO4
AM3 I2C0_SDA/GPIO4 F3 PCH_GPIO5
GPIO9 I2C0_SCL/GPIO5 SDIO_D0 / GPIO66 : Top-Block Swap Override
+3VALW AM2 G4 PCH_GPIO6
<11> PCH_GPIO10
PCH_GPIO33 P2 GPIO10 I2C1_SDA/GPIO6 F1 PCH_GPIO7
： DISABLED
(*) H：
R292 1 2 10K_0402_5% PCH_GPIO27 C4 DEVSLP0/GPIO33 I2C1_SCL/GPIO7 E3 PCH_GPIO64 ： ENABLED(Have internal PD)
( ) L： +3VS
PCH_GPIO38 L2 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 F4 PCH_GPIO65
<9> PCH_GPIO38 N5 DEVSLP1/GPIO38 SDIO_CMD/GPIO65 D3 1 2 150K_0402_1%
PCH_GPIO66 R75
<35> EC_SCI# DEVSLP2/GPIO39 SDIO_D0/GPIO66
V2 E4 PCH_GPIO67
<39> HDA_SPKR SPKR/GPIO81 SDIO_D1/GPIO67 C3 PCH_GPIO68
SDIO_D2/GPIO68 PCH_GPIO68 <37,9>
E2 PCH_GPIO69
SDIO_D3/GPIO69
10 OF 19
BDW-ULT-DDR3L-IL_BGA1168

+3VS
RP17
+3VS
RP18
BIOS Strap Pin
1 8 ODD_DA# 1 8 WLBT_OFF#
WLBT_OFF# <31,9>
2 7 PCH_GPIO23 2 7 Function GPIO1 Function GPIO54 Function GPIO64
B PCH_GPIO23 <8> B
3 6 KB_RST# 3 6 PCH_GPIO33
4 5 SYS_RESET# 4 5 PCH_GPIO76
SYS_RESET# <9> Reserved 1 NoDocking SKU 1 JET LE 0
10K_8P4R_5% 10K_8P4R_5% Reserved 0 Docking SKU 0 TOPAZ XT 1
@ RP19 RP20
1 8 PCH_GPIO65 1 8 PCH_GPIO34 +3VS +3VS +3VS
PCH_GPIO34 <7>
2 7 PCH_GPIO5 2 7 ODD_EN NoDocking@
3 6 PCH_GPIO67 3 6 PCH_GPIO37 R300 1 @ 2 10K_0402_5% PCH_GPIO1 R248 1 2 10K_0402_5% PCH_GPIO54 R245 1 TOPAZ@ 2 10K_0402_5% PCH_GPIO64
PCH_GPIO37 <7> PCH_GPIO54 <9>
4 5 4 5 PCH_GPIO71 R301 1 @ 2 10K_0402_5% R247 1 2 10K_0402_5% R246 1 JET@ 2 10K_0402_5%
Docking@
10K_8P4R_5% 10K_8P4R_5%

@ RP21
1 8 PCH_GPIO93
2 7 PCH_GPIO91 DGPU_PRSNT#
3 6 PCH_GPIO92 R304 1 @ 2 10K_0402_5% PCH_GPIO2
Function GPIO94 Function GPIO44
4 5 PCH_GPIO90 R305 1 @ 2 10K_0402_5% PCH_GPIO18
Function GPIO13 (GPIO49)
PCH_GPIO18 <8> Reserved 1 Zero ODD 1
10K_8P4R_5%
SG 0 0
Reserved 0 No Zero ODD 0
@ RP24 RP2
Reserved 0 1
1 8 PCH_GPIO88 8 1 PCH_GPIO87 +3VS +3VS
2 7 PCH_GPIO53 7 2 PCH_GPIO83
DIS Only 1 0
PCH_GPIO53 <9>
3 6 PCH_GPIO84 6 3 R302 1 @ 2 10K_0402_5% PCH_GPIO94 R284 1 ZODD@ 2 10K_0402_5% PCH_GPIO44 UMA Only 1 1
4 5 PCH_GPIO3 5 4 PCH_GPIO51 R303 1 @ 2 10K_0402_5% R285 1NOZODD@ 2 10K_0402_5%
PCH_GPIO51 <9>
10K_8P4R_5% 10K_8P4R_5% +3VS

RP26 @ RP25 R282 1 UMA@ 2 10K_0402_5% PCH_GPIO13

1 8 EC_SCI# 1 8 PCH_GPIO69 R283 1 PX@ 2 10K_0402_5%
2 7 PCH_GPIO85 2 7 PCH_GPIO4
3 6 PCH_GPIO0 3 6 PCH_GPIO7 R276 1 2 0_0402_5%
Function GPIO73
4 5 4 5 I2C_1_SCL <27>
PCH_GPIO89 PCH_GPIO6 R277 1 2 0_0402_5%
Single Rank 1
I2C_1_SDA <27> +3VS
10K_8P4R_5% 2.2K_0804_8P4R_5% Dual Rank 0 R73 1 UMA@ 2 10K_0402_5% DGPU_PRSNT#
A R74 1 PX@ 2 10K_0402_5% A
+3VS
R76 1 @ 2 1K_0402_5% HDA_SPKR
R286 1 SR@ 2 10K_0402_5% PCH_GPIO73 PCH_GPIO73 <8>
R287 1 DR@ 2 10K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

2011/06/24 2012/07/12 Title
Issued Date Deciphered Date HSW MCP(6/11) GPIO,LPIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B091P
Date: Wednesday, February 12, 2014 Sheet 10 of 55
5 4 3 2 1
 5 4 3 2 1

D D

UC1K BDW_ULT_DDR3L(Interleaved)

<18> PCIE_CRX_GTX_N0 F10 AN8

PERN5_L0 USB2N0 USB20_N0 <34>
<18> PCIE_CRX_GTX_P0 E10
PERP5_L0 USB2P0
AM8
USB20_P0 <34>
Left USB2/3__I/O Port (Near End User)
C10 1 PX@ 2 .1U_0402_16V7K PCIE_PTX_DRX_N5_L0 C23 AR7
<18> PCIE_CTX_GRX_N0 PETN5_L0 USB2N1 USB20_N1 <34>
<18> PCIE_CTX_GRX_P0
C11 1 PX@ 2 .1U_0402_16V7K PCIE_PTX_DRX_P5_L0 C22
PETP5_L0 USB2P1
AT7
USB20_P1 <34>
Left USB2/3__I/O Port (Near HDMI CONN)(Debug Port)
F8 AR8
<18> PCIE_CRX_GTX_N1 PERN5_L1 USB2N2 USB20_N2 <34> Right USB2__I/O Port (Sub Board)
E8 AP8
<18> PCIE_CRX_GTX_P1 PERP5_L1 USB2P2 USB20_P2 <34> 2
R241 Docking@1 0_0402_5%
C12 USB20_N3_D <36>
1 PX@ 2 .1U_0402_16V7K PCIE_PTX_DRX_N5_L1 B23 AR10 USB20_N3 R243 2 E14@ 1 0_0402_5%
<18> PCIE_CTX_GRX_N1 C13 PETN5_L1 USB2N3 USB20_N3_U <34>
1 PX@ 2 .1U_0402_16V7K PCIE_PTX_DRX_P5_L1 A23 AT10 USB20_P3 R244 2 E14@ 1 0_0402_5%
dGPU <18> PCIE_CTX_GRX_P1 PETP5_L1 USB2P3 R242 2 Docking@1 0_0402_5%
USB20_P3_U <34>
USB20_P3_D <36>
H10 AM15
<18> PCIE_CRX_GTX_N2 G10 PERN5_L2 USB2N4 AL15 USB20_N4 <27>
<18> PCIE_CRX_GTX_P2 PERP5_L2 USB2P4 USB20_P4 <27> Touch Screen Card Reader (For G14/15)
C14 1 PX@ 2 .1U_0402_16V7K PCIE_PTX_DRX_N5_L2 B21 AM13
Right USB Port (For E14)
<18> PCIE_CTX_GRX_N2 C15 1 PX@ 2 .1U_0402_16V7K C21 PETN5_L2 USB2N5 AN13 USB20_N5 <27> Docking (For B15)
PCIE_PTX_DRX_P5_L2 Camera
<18> PCIE_CTX_GRX_P2 PETP5_L2 USB2P5 USB20_P5 <27>
C C
E6 AP11
<18> PCIE_CRX_GTX_N3 PERN5_L3 USB2N6 USB20_N6 <31>
F6 AN11 Bluetooth (NGFF)
<18> PCIE_CRX_GTX_P3 PERP5_L3 USB2P6 USB20_P6 <31>
C16 1 PX@ 2 .1U_0402_16V7K PCIE_PTX_DRX_N5_L3 B22 AR13
<18> PCIE_CTX_GRX_N3 C17 PETN5_L3 USB2N7 USB20_N7 <34>
1 PX@ 2 .1U_0402_16V7K PCIE_PTX_DRX_P5_L3 A21 AP13 Finger Print (For B14/E14/B15)
<18> PCIE_CTX_GRX_P3 PETP5_L3 USB2P7 USB20_P7 <34>

<38> PCIE_PRX_DTX_N3 G11

F11 PERN3 G20
<38> PCIE_PRX_DTX_P3 PERP3 USB3RN1 USB3_RX1_N <34>
H20
LAN C22 1 2 .1U_0402_16V7K PCIE_PTX_DRX_N3 C29 USB3RP1 USB3_RX1_P <34>
<38> PCIE_PTX_C_DRX_N3
C23 1 2 .1U_0402_16V7K PCIE_PTX_DRX_P3 B30 PETN3 PCIE USB C33
Left USB2/3__I/O Port
<38> PCIE_PTX_C_DRX_P3 PETP3 USB3TN1 USB3_TX1_N <34>
B34
USB3TP1 USB3_TX1_P <34>
F13
<31> PCIE_PRX_DTX_N4 PERN4
G13 E18
<31> PCIE_PRX_DTX_P4 PERP4 USB3RN2 USB3_RX2_N <34>
WLAN F18 USB3_RX2_P <34>
C18 1 2 .1U_0402_16V7K PCIE_PTX_DRX_N4 B29 USB3RP2
<31> PCIE_PTX_C_DRX_N4
C19 1 2 .1U_0402_16V7K PCIE_PTX_DRX_P4 A29 PETN4 B33
Left USB2/3__I/O Port
<31> PCIE_PTX_C_DRX_P4 PETP4 USB3TN2 USB3_TX2_N <34>
A33
G17 USB3TP2 USB3_TX2_P <34>
<36> USB3_RX3_N PERN1/USB3RN3
<36> USB3_RX3_P F17
PERP1/USB3RP3
USB2/3 Docking CAD note:
C30
(For B15) <36> USB3_TX3_N
C31 PETN1/USB3TN3 AJ10 USBRBIAS R77 1 2 22.6_0402_1%
Route single-end 50-ohms and max 450-mils length.
<36> USB3_TX3_P PETP1/USB3TP3 USBRBIAS AJ11 Avoid routing next to clock pins or under stitching capacitors.
F15 USBRBIAS AN10
<40> PCIE_PRX_DTX_N2 PERN2/USB3RN4 RSVD
Recommended minimum spacing to other signal traces is 15 mils
G15 AM10
<40> PCIE_PRX_DTX_P2 PERP2/USB3RP4 RSVD
Card Reader C20 1 2 .1U_0402_16V7K PCIE_PTX_DRX_N2 B31
<40> PCIE_PTX_C_DRX_N2 PETN2/USB3TN4
(For B14/E14/B15) <40> PCIE_PTX_C_DRX_P2
C21 1 2 .1U_0402_16V7K PCIE_PTX_DRX_P2 A31
PETP2/USB3TP4 AL3 USB_OC0# USB_OC0# <34>
OC0/GPIO40 AT1 USB_OC1#
+1.05VS_AUSB3PLL OC1/GPIO41 USB_OC1# <10,34>
AH2 PCH_GPIO42
E15 OC2/GPIO42 AV3 PCH_GPIO43
E13 RSVD OC3/GPIO43 PCH_GPIO43 <10>
R78 1 2 3.01K_0402_1% PCIE_RCOMP A27 RSVD
B27 PCIE_RCOMP
PCIE_IREF
B B

11 OF 19
BDW-ULT-DDR3L-IL_BGA1168

+3V_PCH
RP27
USB_OC0# 1 8
<10> PCH_GPIO10 2 7
PCH_GPIO42 3 6
4 5
<10> PCH_GPIO12
10K_8P4R_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2011/06/24 2012/07/12 Title
Issued Date Deciphered Date HSW MCP(7/11) PCIE,USB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B091P
Date: Wednesday, February 12, 2014 Sheet 11 of 55
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE
UC1L BDW_ULT_DDR3L(Interleaved)
D D
L59 C36
+1.35V J58 RSVD VCC C40
RSVD VCC C44
AH26 VCC C48
AJ31 VDDQ VCC C52
AJ33 VDDQ VCC C56
AJ37 VDDQ VCC E23
AN33 VDDQ VCC E25
AP43 VDDQ VCC E27
+1.05VS AR48 VDDQ VCC E29
AY35 VDDQ VCC E31
AY40 VDDQ VCC E33
VDDQ VCC

1
AY44 E35
+CPU_CORE AY50 VDDQ VCC E37
R79 VDDQ VCC E39
F59 VCC E41
10K_0402_5% VCC VCC
2 N58 E43
VCCST_PWRGD AC58 RSVD VCC E45
<35> VCCST_PWRGD RSVD VCC E47
VCCSENSE E63 VCC E49
AB23 VCC_SENSE VCC E51
T17 A59 RSVD VCC E53
E20 VCCIO_OUT VCC E55
+VCCIOA_OUT VCCIOA_OUT VCC
AD23 E57
AA23 RSVD VCC F24
AE59 RSVD VCC F28
RSVD VCC F32
H_CPU_SVIDALRT# L62 VCC F36
N63 VIDALERT HSW ULT POWER VCC F40
<52> VR_SVID_CLK VIDSCLK VCC
H_CPU_SVIDDATA L63 F44
VCCST_PWRGD B59 VIDSOUT VCC F48
F60 VCCST_PWRGD VCC F52
<52> VR_ON 1 2 10K_0402_5% C59 VR_EN VCC F56
R80
VR_READY VCC G23
<52> VGATE VCC
D63 G25
CPU_PWR_DEBUG H59 VSS VCC G27
P62 PWR_DEBUG VCC G29
C C
P60 VSS VCC G31
P61 RSVD_TP VCC G33
N59 RSVD_TP VCC G35
N61 RSVD_TP VCC G37
T59 RSVD_TP VCC G39
AD60 RSVD VCC G41
AD59 RSVD VCC G43
+1.05VS AA59 RSVD VCC G45
SVID ALERT Place the PU AE60 RSVD
RSVD
VCC
VCC
G47
AC59 G49
RSVD VCC
1

resistors close to CPU AG58

RSVD VCC
G51
R81 +1.05VS U59 G53
75_0402_5% V59 RSVD VCC G55
RSVD VCC G57
R82 AC22 VCC H23
2

43_0402_1% +CPU_CORE AE22 VCCST VCC J23

2 1 H_CPU_SVIDALRT# AE23 VCCST VCC K23
<52> VR_SVID_ALRT# VCCST VCC K57
AB57 VCC L22
AD57 VCC VCC M23
AG57 VCC VCC M57
C24 VCC VCC P57
C28 VCC VCC U57
C32 VCC VCC W57
+1.05VS VCC VCC
SVID DATA Place the PU BDW-ULT-DDR3L-IL_BGA1168
12 OF 19

resistors close to CPU

2

R83
130_0402_1%
1

R84
1 2 H_CPU_SVIDDATA
<52> VR_SVID_DAT
0_0402_5% +1.35V
B B
VDDQ DECOUPLING

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M
@

C24

C25

C26

C27

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1 1 1 1 1 1 1 1 1 1 @
+1.05VS

C28

C29

C30

C31

C32

C33
+CPU_CORE
2 2 2 2 2 2 2 2 2 2
2

R253: CPU_PWR_DEBUG
1

R86
R85 @
CRB mount
PU resistor should be close to CPU 150_0402_1%
Check list ,XDP use only
100_0402_1% CRB:
1

+1.35V : 470UF/2V/7343 *2 (Un-mount)

2

CPU_PWR_DEBUG
VCCSENSE 10UF/6.3V/0603 * 6
<52> VCCSENSE
2.2UF/6.3V/0402 * 4
2

R87 @
10K_0402_5%
<14,52> VSSSENSE
1
1

R88 PD resistor should be close to CPU

100_0402_1%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2011/06/24 2012/07/12 Title
Issued Date Deciphered Date HSW MCP(8/11) Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B091P
Date: Wednesday, February 12, 2014 Sheet 12 of 55
5 4 3 2 1
 5 4 3 2 1

+RTCVCC <1mA
+1.05VS +1.05VS_AUSB3PLL
41mA
@
D D
L1
2.2UH_LQM2MPN2R2NG0L_30%
1 2 1 1@
47U_0805_6.3V6M

22U_0603_6.3V6M
C37 C38

1U_0402_6.3V6K

.1U_0402_16V7K
1 1 1
1

2 2
C34

@ C35 @ C36
1U_0402_6.3V6K
R271 2 2 2
0_0402_5%
2

+1.05VS_ASATA3PLL
42mA +3V_PCH
63/62mA
1838mA
L2
2.2UH_LQM2MPN2R2NG0L_30%

1
1 2 +1.05VS
22U_0603_6.3V6M

47U_0805_6.3V6M

R89
1 1 1 0_0603_5%
C39

C40

@ C41 Close to M9 Close to K9, L10

2
1U_0402_6.3V6K
2 2 2
1 C42 1 C43 1 C44 1
@ C45

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
+1.05VS_APLLOPI
57mA 1U_0402_6.3V6K

L3 2 2 2 2 +3V_PCH
2.2UH_LQM2MPN2R2NG0L_30%
1 2 UC1M BDW_ULT_DDR3L(Interleaved)
47U_0805_6.3V6M

22U_0603_6.3V6M

1
K9 +RTCVCC C49
1 1 1 VCCHSIO
@ @ C46 L10 .1U_0402_16V7K
VCCHSIO
C47

C48

1U_0402_6.3V6K M9
+1.05VS_ASATA3PLL +1.05VS_AUSB3PLL N8 VCCHSIO HSIO RTC AH11 2
2 2 2 P9 VCC1_05 VCCSUS3_3 AG10
VCC1_05 VCCRTC 18mA 658mA
B18 AE7 +VCCRTCEXT
B11 VCCUSB3PLL DCPRTC
VCCSATA3PLL
C
+1.05VS_AXCK_DCB
200mA +1.05VS_APLLOPI
1
+1.05VS
C
@ C50
Y20 SPI Y8
L4 VCCHDA=11mA RSVD VCCSPI .1U_0402_16V7K 1741/1632mA
2.2UH_LQM2MPN2R2NG0L_30% AA21 OPI
1 2 VCCDSW3_3= 114mA W21 VCCAPLL 2@
+3V_PCH +3VALW VCCAPLL +1.05VS
22U_0603_6.3V6M

47U_0805_6.3V6M

AG14
VCCASW AG13
1 1 1 Close to AH10 Close to AH14 VCCASW
C53
1

C51

C52

@ @ @ T18 J13 USB3

1U_0402_6.3V6K 2 DCPSUS3 1 1 1
2 C54 J11 C56 C57 C58
2 2 2 C55 1U_0402_6.3V6K VCC1_05 H11 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
R272
1U_0402_6.3V6K AH14 HDA VCC1_05 H15
0_0402_5%
@ 1 VCCHDA VCC1_05 AE8 2 2 2
VCC1_05
2

1 AF22
+1.05VS_AXCK_LCPLL
31mA VRM VCC1_05
@ T19 AH13 AG19 +PCH_VCCDSW C59 1 2 1U_0402_6.3V6K
L5 DCPSUS2 CORE DCPSUSBYP AG20
2.2UH_LQM2MPN2R2NG0L_30% DCPSUSBYP AE9 +1.05VS
1 2 +3VALW VCCASW AF9
VCCASW
22U_0603_6.3V6M

47U_0805_6.3V6M

AC9 AG8
+3VS AA9 VCCSUS3_3 GPIO/LPC
VCCASW AD10 T20 @
1 1 1 VCCSUS3_3 DCPSUS1
C62 Close to V8 AH10 AD8 T21 @ 1 C64 1 C65
VCCDSW3_3 DCPSUS1 +1.5VS
C60

C61

1U_0402_6.3V6K
@ V8 3mA @

22U_0603_6.3V6M
1U_0402_6.3V6K 1 VCC3_3
41mA C63 W9
2 2 2 22U_0603_6.3V6M VCC3_3 J15
THERMAL SENSOR VCCTS1_5 K14 2 2
2 VCC3_3 K16
+1.05VS_AXCK_DCB VCC3_3

+1.05VS_AXCK_LCPLL J18
K19 VCCCLK SERIAL IO U8
A20 VCCCLK VCCSDIO T9 +3VS +3VS
+1.05VS VCCACLKPLL VCCSDIO 17mA
J17
R21 VCCCLK
T21 VCCCLK LPT LP POWER
VCCCLK 1 C68 1 C69

1U_0402_6.3V6K

.1U_0402_16V7K
K18 SUS OSCILLATOR AB8 @ T22
+3V_PCH M20 RSVD DCPSUS4
1 1 RSVD
C66 C67 V21 +1.05VS
AE20 RSVD AC20 2 2
1U_0402_6.3V6K

1U_0402_6.3V6K

B
AE21 VCCSUS3_3 RSVD AG16 B
2 2 VCCSUS3_3 USB2 VCC1_05 AG17
VCC1_05 1 C71

1U_0402_6.3V6K
1
C70
22U_0603_6.3V6M
13 OF 19 2
2 BDW-ULT-DDR3L-IL_BGA1168
Close to R21 Close to J17
Close to AC9,AA9,
AE20,AE21

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2011/06/24 2012/07/12 Title
Issued Date Deciphered Date HSW MCP(9/11) Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B091P
Date: Wednesday, February 12, 2014 Sheet 13 of 55
5 4 3 2 1
 5 4 3 2 1

D D

UC1N BDW_ULT_DDR3L(Interleaved) UC1O BDW_ULT_DDR3L(Interleaved) UC1P BDW_ULT_DDR3L(Interleaved)

H17
A11 AJ35 AP22 AV59 D33 VSS H57
A14 VSS VSS AJ39 AP23 VSS VSS AV8 D34 VSS VSS J10
A18 VSS VSS AJ41 AP26 VSS VSS AW16 D35 VSS VSS J22
A24 VSS VSS AJ43 AP29 VSS VSS AW24 D37 VSS VSS J59
A28 VSS VSS AJ45 AP3 VSS VSS AW33 D38 VSS VSS J63
A32 VSS VSS AJ47 AP31 VSS VSS AW35 D39 VSS VSS K1
A36 VSS VSS AJ50 AP38 VSS VSS AW37 D41 VSS VSS K12
A40 VSS VSS AJ52 AP39 VSS VSS AW4 D42 VSS VSS L13
A44 VSS VSS AJ54 AP48 VSS VSS AW40 D43 VSS VSS L15
A48 VSS VSS AJ56 AP52 VSS VSS AW42 D45 VSS VSS L17
A52 VSS VSS AJ58 AP54 VSS VSS AW44 D46 VSS VSS L18
A56 VSS VSS AJ60 AP57 VSS VSS AW47 D47 VSS VSS L20
AA1 VSS VSS AJ63 AR11 VSS VSS AW50 D49 VSS VSS L58
AA58 VSS VSS AK23 AR15 VSS VSS AW51 D5 VSS VSS L61
AB10 VSS VSS AK3 AR17 VSS VSS AW59 D50 VSS VSS L7
AB20 VSS VSS AK52 AR23 VSS VSS AW60 D51 VSS VSS M22
AB22 VSS VSS AL10 AR31 VSS VSS AY11 D53 VSS VSS N10
C C
AB7 VSS VSS AL13 AR33 VSS VSS AY16 D54 VSS VSS N3
AC61 VSS VSS AL17 AR39 VSS VSS AY18 D55 VSS VSS P59
AD21 VSS VSS AL20 AR43 VSS VSS AY22 D57 VSS VSS P63
AD3 VSS VSS AL22 AR49 VSS VSS AY24 D59 VSS VSS R10
AD63 VSS VSS AL23 AR5 VSS VSS AY26 D62 VSS VSS R22
AE10 VSS VSS AL26 AR52 VSS VSS AY30 D8 VSS VSS R8
AE5 VSS VSS AL29 AT13 VSS VSS AY33 E11 VSS VSS T1
AE58 VSS VSS AL31 AT35 VSS VSS AY4 E17 VSS VSS T58
AF11 VSS VSS AL33 AT37 VSS VSS AY51 F20 VSS VSS U20
AF12 VSS VSS AL36 AT40 VSS VSS AY53 F26 VSS VSS U22
AF14 VSS VSS AL39 AT42 VSS VSS AY57 F30 VSS VSS U61
AF15 VSS VSS AL40 AT43 VSS VSS AY59 F34 VSS VSS U9
AF17 VSS VSS AL45 AT46 VSS VSS AY6 F38 VSS VSS V10
AF18 VSS VSS AL46 AT49 VSS VSS B20 F42 VSS VSS V3
AG1 VSS VSS AL51 AT61 VSS VSS B24 F46 VSS VSS V7
AG11 VSS VSS AL52 AT62 VSS VSS B26 F50 VSS VSS W20
AG21 VSS VSS AL54 AT63 VSS VSS B28 F54 VSS VSS W22
AG23 VSS VSS AL57 AU1 VSS VSS B32 F58 VSS VSS Y10
AG60 VSS VSS AL60 AU16 VSS VSS B36 F61 VSS VSS Y59
AG61 VSS VSS AL61 AU18 VSS VSS B4 G18 VSS VSS Y63
AG62 VSS VSS AM1 AU20 VSS VSS B40 G22 VSS VSS
AG63 VSS VSS AM17 AU22 VSS VSS B44 G3 VSS
AH17 VSS VSS AM23 AU24 VSS VSS B48 G5 VSS V58
AH19 VSS VSS AM31 AU26 VSS VSS B52 G6 VSS VSS AH46
AH20 VSS VSS AM52 AU28 VSS VSS B56 G8 VSS VSS V23
AH22 VSS VSS AN17 AU30 VSS VSS B60 H13 VSS VSS E62 VSSSENSE
VSS VSS VSS VSS VSS VSS_SENSE VSSSENSE <12,52>
AH24 AN23 AU33 C11 AH16
AH28 VSS VSS AN31 AU51 VSS VSS C14 16 OF 19 VSS
AH30 VSS VSS AN32 AU53 VSS VSS C18 BDW-ULT-DDR3L-IL_BGA1168
AH32 VSS VSS AN35 AU55 VSS VSS C20
AH34 VSS VSS AN36 AU57 VSS VSS C25
AH36 VSS VSS AN39 AU59 VSS VSS C27
AH38 VSS VSS AN40 AV14 VSS VSS C38
AH40 VSS VSS AN42 AV16 VSS VSS C39
AH42 VSS VSS AN43 AV20 VSS VSS C57
AH44 VSS VSS AN45 AV24 VSS VSS D12
AH49 VSS VSS AN46 AV28 VSS VSS D14
B
AH51 VSS VSS AN48 AV33 VSS VSS D18 B
AH53 VSS VSS AN49 AV34 VSS VSS D2
AH55 VSS VSS AN51 AV36 VSS VSS D21
AH57 VSS VSS AN52 AV39 VSS VSS D23
AJ13 VSS VSS AN60 AV41 VSS VSS D25
AJ14 VSS VSS AN63 AV43 VSS VSS D26
AJ23 VSS VSS AN7 AV46 VSS VSS D27
AJ25 VSS VSS AP10 AV49 VSS VSS D29
AJ27 VSS VSS AP17 AV51 VSS VSS D30
AJ29 VSS VSS AP20 AV55 VSS VSS D31
VSS VSS VSS 15 OF 19 VSS
BDW-ULT-DDR3L-IL_BGA1168

14 OF 19
BDW-ULT-DDR3L-IL_BGA1168

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2011/06/24 2012/07/12 Title
Issued Date Deciphered Date HSW MCP(10/11) GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B091P
Date: Wednesday, February 12, 2014 Sheet 14 of 55
5 4 3 2 1
 1

UC1R BDW_ULT_DDR3L(Interleaved)

N23
UC1Q BDW_ULT_DDR3L(Interleaved) RSVD R23
RSVD T23
AT2 RSVD
RSVD U10
AU44 RSVD
DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3 RSVD
DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 AV44
DC_TEST_AY3_AW3 AY3 A4 @ T24 RSVD
DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4 D15
T23 @ AY60 RSVD AL1
DC_TEST_AY61_AW61 AY61 DAISY_CHAIN_NCTF_AY60 A60 @ T25 RSVD AM11
DC_TEST_AY62_AW62 AY62 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 A61 DC_TEST_A61_B61 RSVD AP7
DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 F22 RSVD
T26 @ B2 A62 @ T27 RSVD AU10
DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 H22 RSVD
DC_TEST_A3_B3 B3 AV1 @ T28 RSVD AU15
DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 J21 RSVD
DC_TEST_A61_B61 B61 AW1 @ T29 RSVD AW14
DC_TEST_B62_B63 B62 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW2 DC_TEST_AY2_AW2 RSVD AY14
B63 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 AW3 DC_TEST_AY3_AW3 RSVD
DC_TEST_C1_C2 C1 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW61 DC_TEST_AY61_AW61
C2 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 AW62 DC_TEST_AY62_AW62 18 OF 19
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW63 @ T30 BDW-ULT-DDR3L-IL_BGA1168
17 OF 19 DAISY_CHAIN_NCTF_AW63
BDW-ULT-DDR3L-IL_BGA1168

UC1S BDW_ULT_DDR3L(Interleaved)

AC60 AV63
AC62 CFG0 RSVD_TP AU63

CFG3
AC63
AA63
CFG1
CFG2
RSVD_TP
CFG Straps for Processor
CFG4 AA60 CFG3 C63
Y62 CFG4 RSVD_TP C62
Y61 CFG5 RSVD_TP B43
Y60 CFG6 RSVD CFG3
V62 CFG7 A51
CFG8 RSVD_TP

1
V61 B51
V60 CFG9 RSVD_TP R92
U60 CFG10 L60 1K_0402_1%
T63 CFG11 RSVD_TP @
T62 CFG12 RESERVED N60

2
T61 CFG13 RSVD
T60 CFG14 W23
A AA62
CFG15 RSVD
RSVD
Y22
AY15 OPI_COMP
A
U63 CFG16 PROC_OPI_RCOMP
AA61 CFG18 AV62
U62 CFG17 RSVD D58
CFG19 RSVD Physical Debug Enable (DFX Privacy)
CFG_RCOMP V63 P22
CFG_RCOMP VSS N21
A5 VSS 1: DISABLED
RSVD P20
CFG3 0: ENABLED; SET DFX ENABLED BIT
E1 RSVD R20
D1 RSVD RSVD IN DEBUG INTERFACE MSR
J20 RSVD
H18 RSVD
TD_IREF B12 RSVD CFG4
TD_IREF

1
19 OF 19
BDW-ULT-DDR3L-IL_BGA1168 R93
1K_0402_1%

2
2 1 CFG_RCOMP
R94 49.9_0402_1%
2 1 OPI_COMP
R95 49.9_0402_1%
2 1 TD_IREF
R96 8.2K_0402_5%
Display Port Presence Strap

1 : Disabled; No Physical Display Port attached

CFG4 to Embedded Display Port

0 : Enabled; An external Display Port device is

connected to the Embedded Display Port

Security Classification Compal Secret Data Compal Electronics, Inc.

2011/06/24 2012/07/12 Title
Issued Date Deciphered Date HSW MCP(11/11) RSVD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B091P
Date: Wednesday, February 12, 2014 Sheet 15 of 55
 A B C D E

+SM_VREF_DQ0 <6> DIMM1

<6> DDR_A_D[0..63]
D/DQ Signals link to CPU
+1.35V Reverse Type
<6> DDR_A_DQS#[0..7]
Near CPU

1
<6> DDR_A_DQS[0..7]
R97
1.8K_0402_1%
R98 +SM_VREF_DQ0_DIMM1
<6> DDR_A_MA[0..15]
0_0402_5% 10mils JDIMM1

2
DDR_A_BS0 1 2 1 2
<6> DDR_A_BS0 VREF_DQ VSS
DDR_A_BS1 3 4 DDR_A_D4
<6> DDR_A_BS1 VSS DQ4

2.2U_0402_6.3V6M

0.1U_0402_25V6K
DDR_A_BS2 CMD Signals from CPU C72 DDR_A_D0 5 6 DDR_A_D5
<6> DDR_A_BS2 DQ0 DQ5
DDR_A_RAS# @ 0.022U_0402_16V7K 1 1 DDR_A_D1 7 8
<6> DDR_A_RAS# DQ1 VSS

C74
DDR_A_WE# 9 10 DDR_A_DQS#0
<6> DDR_A_WE#

1 2
VSS DQS0#

C73
DDR_A_CAS# R99 11 12 DDR_A_DQS0
1 <6> DDR_A_CAS# DM0 DQS0 1
1.8K_0402_1% 13 14
R100 @2 2 DDR_A_D2 15 VSS VSS 16 DDR_A_D6
M_CLK_DDR#0 @ DDR_A_D3 17 DQ2 DQ6 18 DDR_A_D7
<6> M_CLK_DDR#0 24.9_0402_1%

2
M_CLK_DDR0 19 DQ3 DQ7 20
<6> M_CLK_DDR0 VSS VSS
M_CLK_DDR#1 Clock Signals from CPU DDR_A_D8 21 22 DDR_A_D12
<6> M_CLK_DDR#1

2
M_CLK_DDR1 DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
<6> M_CLK_DDR1 25 DQ9 DQ13 26
DDR_A_DQS#1 27 VSS VSS 28
DDR_CKE0_DIMMA DDR_A_DQS1 29 DQS1# DM1 30 DDR3_DRAMRST#
<6> DDR_CKE0_DIMMA DQS1 RESET# DIMM_DRAMRST# <17,5>
DDR_CKE1_DIMMA 31 32
<6> DDR_CKE1_DIMMA VSS VSS
DDR_CS0_DIMMA# CTL Signals from CPU DDR_A_D10 33 34 DDR_A_D14 1
<6> DDR_CS0_DIMMA# 35 DQ10 DQ14 36
DDR_CS1_DIMMA# DDR_A_D11 DDR_A_D15
<6> DDR_CS1_DIMMA# DQ11 DQ15
37 38 C75
DDR_A_D16 39 VSS VSS 40 DDR_A_D20
DQ16 DQ20 100P_0402_50V8J
PCH_SMB_DATA DDR_A_D17 41 42 DDR_A_D21 2
<17,8> PCH_SMB_DATA DQ17 DQ21 @ESD@
PCH_SMB_CLK SMBUS Signals link to CPU 43 44
<17,8> PCH_SMB_CLK 45 VSS VSS 46
DDR_A_DQS#2
DDR_A_DQS2 47 DQS2# DM2 48
49 DQS2 VSS 50 DDR_A_D22
DDR_A_D18
DDR_A_D19
51
53
55
VSS
DQ18
DQ19
DQ22
DQ23
VSS
52
54
56
DDR_A_D23

DDR_A_D28
ESD
DDR_A_D24 57 VSS DQ28 58 DDR_A_D29
DDR_A_D25 59 DQ24 DQ29 60
61 DQ25 VSS 62 DDR_A_DQS#3
Layout Note: 63 VSS DQS3# 64 DDR_A_DQS3
Place near JDIMM1 65 DM3 DQS3 66
DDR_A_D26 67 VSS VSS 68 DDR_A_D30
DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31
71 DQ27 DQ31 72
+1.35V VSS VSS +1.35V

+1.35V DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA

75 CKE0 CKE1 76
77 VDD VDD 78 DDR_A_MA15
DDR_A_BS2 79 NC A15 80 DDR_A_MA14
BA2 A14
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

81 82
DDR_A_MA12 83 VDD VDD 84 DDR_A_MA11
2 1 1 1 1 2
@ @ DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
A9 A7
C76

C77

C78

C79

87 88
DDR_A_MA8 89 VDD VDD 90 DDR_A_MA6
2 2 2 2 DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD VDD 96 DDR_A_MA2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
M_CLK_DDR0 101 VDD VDD 102 M_CLK_DDR1
M_CLK_DDR#0 103 CK0 CK1 104 M_CLK_DDR#1
105 CK0# CK1# 106
+1.35V DDR_A_MA10 107 VDD VDD 108 DDR_A_BS1 +1.35V
DDR_A_BS0 109 A10/AP BA1 110 DDR_A_RAS#
111 BA0 RAS# 112
VDD VDD

1
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

DDR_A_WE# 113 114 DDR_CS0_DIMMA#

DDR_A_CAS# 115 WE# S0# 116 SA_ODT0 R101
@ @ 117 CAS# ODT0 118 1.8K_0402_1%
1 VDD VDD
@ DDR_A_MA13 119 120 SA_ODT1 +VREF_CA
1 1 1 1 1 1 1 1 A13 ODT1
C82

C83

C84

C85

C86

C87

C88

C89

+ C250 DDR_CS1_DIMMA# 121 122 R102

2
330U_D3_2.5VY_R6M 123 S1# NC 124 0_0402_5%
VDD VDD 10mils
125 126 1 2
2 2 2 2 2 2 2 2 2 TEST VREF_CA +SM_VREF_CA <6>

2.2U_0402_6.3V6M

0.1U_0402_25V6K
127 128
DDR_A_D32 129 VSS VSS 130 DDR_A_D36 @
DQ32 DQ36

1
DDR_A_D33 131 132 DDR_A_D37 1 1 C93
DQ33 DQ37

C91

C92
133 134 0.022U_0402_16V7K
DDR_A_DQS#4 135 VSS VSS 136

1 2
DDR_A_DQS4 137 DQS4# DM4 138
DQS4 VSS

1
139 140 DDR_A_D38 2 2 @
DDR_A_D34 141 VSS DQ38 142 DDR_A_D39 @ R103 R104
DDR_A_D35 143 DQ34 DQ39 144 1.8K_0402_1%
DQ35 VSS 24.9_0402_1%
145 146 DDR_A_D44
Layout Note: Layout Note: DDR_A_D40 147 VSS DQ44 148 DDR_A_D45

2
Place near JDIMM1.203,204 Place near JDIMM1.199 DDR_A_D41 149 DQ40 DQ45 150
151 DQ41 VSS 152 DDR_A_DQS#5
153 VSS DQS5# 154 DDR_A_DQS5
155 DM5 DQS5 156
DDR_A_D42 157 VSS VSS 158 DDR_A_D46
3
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47 3

+0.675VS +3VS 161 DQ43 DQ47 162

DDR_A_D48 163 VSS VSS 164 DDR_A_D52
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53
167 DQ49 DQ53 168
VSS VSS
0.1U_0402_25V6K

0.1U_0402_25V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

DDR_A_DQS#6 169 170

@ 1 @ 1 DDR_A_DQS6 171 DQS6# DM6 172
1 1 1 1 DQS6 VSS
C94

C95

2.2U_0402_6.3V6M

0.1U_0402_25V6K

@ Address : 00 173 174 DDR_A_D54

VSS DQ54
C96

C97

DDR_A_D50 175 176 DDR_A_D55

DQ50 DQ55
C98

C99

R105 1 2 0_0402_5% DDR_A_SA0 DDR_A_D51 177 178

2 2 2 2 2 2 179 DQ51 VSS 180 DDR_A_D60
R106 1 2 0_0402_5% DDR_A_SA1 DDR_A_D56 181 VSS DQ60 182 DDR_A_D61
DDR_A_D57 183 DQ56 DQ61 184
185 DQ57 VSS 186 DDR_A_DQS#7
187 VSS DQS7# 188 DDR_A_DQS7
189 DM7 DQS7 190
DDR_A_D58 191 VSS VSS 192 DDR_A_D62
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63
+0.675VS +3VS 195 DQ59 DQ63 196 +0.675VS
DDR_A_SA0 197 VSS VSS 198
199 SA0 EVENT# 200 PCH_SMB_DATA
DDR_A_SA1 201 VDDSPD SDA 202 PCH_SMB_CLK
203 SA1 SCL 204
VTT VTT
205 206
GND1 GND2

DDR3L SODIMM ODT GENERATION ARGOS_DS2RK-20401-TP4B

ME@
SP070014D00
+1.35V

R107
1 66.5_0402_1%
C100 1 2
+5VALW +1.35V SB_ODT0 <17>
.1U_0402_16V7K
4 R109 4
2 66.5_0402_1%
1

1 2
SB_ODT1 <17>
U4 R108
1 5 220K_0402_5% Q3 R110
NC VCC LBSS138LT1G_SOT-23-3 66.5_0402_1%
1

Interleaved Memory
2 D 1 2 SA_ODT0
<5> DDR_PG_CTRL
2

A 4 2
From CPU 3 Y G R111
GND 66.5_0402_1%
S
3

74AUP1G07GW TSSOP 5P BUFFER M_A_B_DIMM_ODT 1 2 SA_ODT1

Security Classification Compal Secret Data Compal Electronics, Inc.
For ODT & VTT Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title
power control DDR_VTT_PG_CTRL <47>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR3L_DIMMA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B091P
Date: Wednesday, February 12, 2014 Sheet 16 of 55
A B C D E
 A B C D E

+SM_VREF_DQ1 <6> DIMM2

<6> DDR_B_D[0..63]
D/DQ Signals link to CPU
+1.35V Standard Type
<6> DDR_B_DQS#[0..7]
Near User

1
<6> DDR_B_DQS[0..7]
R112
1.8K_0402_1%
R113 +SM_VREF_DQ1_DIMM2
<6> DDR_B_MA[0..15]
0_0402_5% 10mils JDIMM2

2
DDR_B_BS0 1 2 1 2
<6> DDR_B_BS0 VREF_DQ VSS
DDR_B_BS1 3 4 DDR_B_D22
<6> DDR_B_BS1 VSS DQ4

2.2U_0402_6.3V6M

0.1U_0402_25V6K
DDR_B_BS2 CMD Signals from CPU C101 DDR_B_D23 5 6 DDR_B_D16
<6> DDR_B_BS2 DQ0 DQ5
DDR_B_RAS# @ 0.022U_0402_16V7K 1 1 DDR_B_D17 7 8
<6> DDR_B_RAS# DQ1 VSS

1
DDR_B_WE# 9 10 DDR_B_DQS#2
<6> DDR_B_WE#

1 2
VSS DQS0#

C102

C103
DDR_B_CAS# R114 11 12 DDR_B_DQS2
1 <6> DDR_B_CAS# DM0 DQS0 1
1.8K_0402_1% 13 14
R115 @2 2 DDR_B_D21 15 VSS VSS 16 DDR_B_D19
M_CLK_DDR#2 @ DDR_B_D18 17 DQ2 DQ6 18 DDR_B_D20
<6> M_CLK_DDR#2 24.9_0402_1%

2
M_CLK_DDR2 19 DQ3 DQ7 20
<6> M_CLK_DDR2 VSS VSS
M_CLK_DDR#3 Clock Signals from CPU DDR_B_D3 21 22 DDR_B_D4
<6> M_CLK_DDR#3

2
M_CLK_DDR3 DDR_B_D2 23 DQ8 DQ12 24 DDR_B_D5
<6> M_CLK_DDR3 25 DQ9 DQ13 26
DDR_B_DQS#0 27 VSS VSS 28
DDR_CKE2_DIMMB DDR_B_DQS0 29 DQS1# DM1 30 DDR3_DRAMRST#
<6> DDR_CKE2_DIMMB DQS1 RESET# DIMM_DRAMRST# <16,5>
DDR_CKE3_DIMMB 31 32
<6> DDR_CKE3_DIMMB VSS VSS
DDR_CS2_DIMMB# CTL Signals from CPU DDR_B_D0 33 34 DDR_B_D6 1
<6> DDR_CS2_DIMMB# 35 DQ10 DQ14 36
DDR_CS3_DIMMB# DDR_B_D1 DDR_B_D7
<6> DDR_CS3_DIMMB# DQ11 DQ15
37 38 C104
DDR_B_D12 39 VSS VSS 40 DDR_B_D13
DQ16 DQ20 100P_0402_50V8J
PCH_SMB_DATA DDR_B_D8 41 42 DDR_B_D9 2
<16,8> PCH_SMB_DATA DQ17 DQ21 @ESD@
PCH_SMB_CLK SMBUS Signals link to CPU 43 44
<16,8> PCH_SMB_CLK 45 VSS VSS 46
DDR_B_DQS#1
DDR_B_DQS1 47 DQS2# DM2 48
49 DQS2 VSS 50 DDR_B_D11
DDR_B_D14
DDR_B_D15
51
53
55
VSS
DQ18
DQ19
DQ22
DQ23
VSS
52
54
56
DDR_B_D10

DDR_B_D30
ESD
DDR_B_D31 57 VSS DQ28 58 DDR_B_D26
Layout Note: DDR_B_D25 59 DQ24 DQ29 60
Place near JDIMM2 61 DQ25 VSS 62 DDR_B_DQS#3
63 VSS DQS3# 64 DDR_B_DQS3
65 DM3 DQS3 66
DDR_B_D27 67 VSS VSS 68 DDR_B_D29
DDR_B_D24 69 DQ26 DQ30 70 DDR_B_D28
71 DQ27 DQ31 72
+1.35V +1.35V VSS VSS +1.35V

DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
CKE0 CKE1
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

75 76
@ 1 @ 1 77 VDD VDD 78 DDR_B_MA15
1 1 NC A15
DDR_B_BS2 79 80 DDR_B_MA14
BA2 A14
C105

C106

C107

C108

81 82
DDR_B_MA12 83 VDD VDD 84 DDR_B_MA11
2 2
2 2 2 2 DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA8 89 VDD VDD 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA3 95 VDD VDD 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
+1.35V M_CLK_DDR2 101 VDD VDD 102 M_CLK_DDR3
M_CLK_DDR#2 103 CK0 CK1 104 M_CLK_DDR#3
105 CK0# CK1# 106
VDD VDD
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

DDR_B_MA10 107 108 DDR_B_BS1

DDR_B_BS0 109 A10/AP BA1 110 DDR_B_RAS#
111 BA0 RAS# 112
@ 1 @ 1 DDR_B_WE# 113 VDD VDD 114 DDR_CS2_DIMMB#
1 1 1 1 1 1 WE# S0#
C111

C112

C113

C114

C115

C116

C117

C118

DDR_B_CAS# 115 116 SB_ODT0

CAS# ODT0 SB_ODT0 <16>
117 118
DDR_B_MA13 119 VDD VDD 120 SB_ODT1
2 2 2 2 2 2 2 2 121 A13 ODT1 122 SB_ODT1 <16> +VREF_CA
DDR_CS3_DIMMB#
123 S1# NC 124
VDD VDD 10mils
125 126
127 TEST VREF_CA 128
VSS VSS

2.2U_0402_6.3V6M

0.1U_0402_25V6K
DDR_B_D32 129 130 DDR_B_D33
DDR_B_D35 131 DQ32 DQ36 132 DDR_B_D34
133 DQ33 DQ37 134
VSS VSS 1 1

C121
DDR_B_DQS#4 135 136
DQS4# DM4

C120
DDR_B_DQS4 137 138
139 DQS4 VSS 140 DDR_B_D39
DDR_B_D36 141 VSS DQ38 142 DDR_B_D37 @2 2
Layout Note: Layout Note: DDR_B_D38 143 DQ34 DQ39 144
Place near JDIMM2.203,204 Place near JDIMM2.199 145 DQ35 VSS 146 DDR_B_D44
DDR_B_D40 147 VSS DQ44 148 DDR_B_D41
DDR_B_D45 149 DQ40 DQ45 150
151 DQ41 VSS 152 DDR_B_DQS#5
153 VSS DQS5# 154 DDR_B_DQS5
155 DM5 DQS5 156
+0.675VS +3VS DDR_B_D43 157 VSS VSS 158 DDR_B_D47
3
DDR_B_D42 159 DQ42 DQ46 160 DDR_B_D46 3
161 DQ43 DQ47 162
DDR_B_D52 163 VSS VSS 164 DDR_B_D51
DQ48 DQ52
0.1U_0402_25V6K

0.1U_0402_25V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_25V6K

2.2U_0402_6.3V6M

DDR_B_D49 165 166 DDR_B_D55

@ 1 @ 1 167 DQ49 DQ53 168
1 1 1 1 Address : 01 VSS VSS
C122

C123

C126

@ DDR_B_DQS#6 169 170

+3VS DQS6# DM6
C124

C125

C127

DDR_B_DQS6 171 172

173 DQS6 VSS 174 DDR_B_D48
2 2 2 2 2 2 R116 1 2 0_0402_5% DDR_B_SA1 DDR_B_D50 175 VSS DQ54 176 DDR_B_D54
DDR_B_D53 177 DQ50 DQ55 178
R117 1 2 0_0402_5% DDR_B_SA0 179 DQ51 VSS 180 DDR_B_D56
DDR_B_D63 181 VSS DQ60 182 DDR_B_D57
DDR_B_D62 183 DQ56 DQ61 184
185 DQ57 VSS 186 DDR_B_DQS#7
187 VSS DQS7# 188 DDR_B_DQS7
189 DM7 DQS7 190
DDR_B_D58 191 VSS VSS 192 DDR_B_D60
DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D61
+0.675VS +3VS 195 DQ59 DQ63 196 +0.675VS
DDR_B_SA0 197 VSS VSS 198
199 SA0 EVENT# 200 PCH_SMB_DATA
DDR_B_SA1 201 VDDSPD SDA 202 PCH_SMB_CLK
203 SA1 SCL 204
VTT VTT
205 206
207 GND1 GND2 208
BOSS1 BOSS2

ARGOS_DS2SK-20401-TP4B
ME@
SP070014E00

4 4

Interleaved Memory
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR3L_DIMMB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B091P
Date: Wednesday, February 12, 2014 Sheet 17 of 55
A B C D E
 1 2 3 4 5

UV1A
A
AC Coupling Capacitor A
PCIe Gen3: Recommended value is 220 nF
PCIe Gen1 and Gen2 only: Recommended value is 100 nF
AF30 AH30 PCIE_CRX_GTX_P0_C .1U_0402_16V7K 2 1 PX@ CV1
<11> PCIE_CTX_GRX_P0 PCIE_RX0P PCIE_TX0P PCIE_CRX_GTX_P0 <11>
AE31 AG31 PCIE_CRX_GTX_N0_C .1U_0402_16V7K 2 1 PX@ CV2
<11> PCIE_CTX_GRX_N0 PCIE_RX0N PCIE_TX0N PCIE_CRX_GTX_N0 <11>

AE29 AG29 PCIE_CRX_GTX_P1_C .1U_0402_16V7K 2 1 PX@ CV3

<11> PCIE_CTX_GRX_P1 PCIE_RX1P PCIE_TX1P PCIE_CRX_GTX_P1 <11>
AD28 AF28 PCIE_CRX_GTX_N1_C .1U_0402_16V7K 2 1 PX@ CV4
<11> PCIE_CTX_GRX_N1 PCIE_RX1N PCIE_TX1N PCIE_CRX_GTX_N1 <11>

AD30 AF27 PCIE_CRX_GTX_P2_C .1U_0402_16V7K 2 1 PX@ CV5

<11> PCIE_CTX_GRX_P2 PCIE_RX2P PCIE_TX2P PCIE_CRX_GTX_P2 <11>
AC31 AF26 PCIE_CRX_GTX_N2_C .1U_0402_16V7K 2 1 PX@ CV6
<11> PCIE_CTX_GRX_N2 PCIE_RX2N PCIE_TX2N PCIE_CRX_GTX_N2 <11>

AC29 AD27 PCIE_CRX_GTX_P3_C .1U_0402_16V7K 2 1 PX@ CV7

<11> PCIE_CTX_GRX_P3 PCIE_RX3P PCIE_TX3P PCIE_CRX_GTX_P3 <11>
AB28 AD26 PCIE_CRX_GTX_N3_C .1U_0402_16V7K 2 1 PX@ CV8
<11> PCIE_CTX_GRX_N3 PCIE_RX3N PCIE_TX3N PCIE_CRX_GTX_N3 <11>

AB30 AC25
AA31 PCIE_RX4P PCIE_TX4P AB25
PCIE_RX4N PCIE_TX4N

AA29 Y23
Y28 PCIE_RX5P PCIE_TX5P Y24
PCIE_RX5N PCIE_TX5N

Y30 AB27
W31 PCIE_RX6P PCIE_TX6P AB26
PCIE_RX6N PCIE_TX6N

W29 Y27
B
V28 PCIE_RX7P PCIE_TX7P Y26 B
PCIE_RX7N PCIE_TX7N

V30 W24
U31 NC#V30 NC#W24 W23
NC#U31 NC#W23

U29 V27
T28 NC#U29 NC#V27 U26
NC#T28 NC#U26

PCI EXPRESS INTERFACE

T30 U24
R31 NC#T30 NC#U24 U23
NC#R31 NC#U23
No Use GPU Display Port outpud
R29 T26
P28 NC#R29 NC#T26 T27
NC#P28 NC#T27 UV1F
+VGA_CORE
P30 T24
N31 NC#P30 NC#T24 T23
NC#N31 NC#T23 AB11 0_0402_5% 2 TOPAZ@
TOPAZ@1 RV255
VARY_BL AB12 0_0402_5% 2 TOPAZ@1
TOPAZ@ RV254 FOR TOPAS CORE POWER USE
N29 P27 DIGON
M28 NC#N29 NC#P27 P26
NC#M28 NC#P26

M30 P24 AL15

L31 NC#M30 NC#P24 P23 TXCAP_DPA3P AK14
NC#L31 NC#P23 TXCAM_DPA3N
AH16
L29 M27 TX0P_DPA2P AJ15
K30 NC#L29 NC#M27 N26 TX0M_DPA2N
NC#K30 NC#N26 AL17
TX1P_DPA1P AK16
C C
TX1M_DPA1N
CLOCK AH18
CLK_PCIE_GPU AK30 TX2P_DPA0P AJ17
<8> CLK_PCIE_GPU PCIE_REFCLKP TX2M_DPA0N
CLK_PCIE_GPU# AK32
<8> CLK_PCIE_GPU# PCIE_REFCLKN +0.95VGS AL19
+3VGS NC_TXOUT_L3P AK18
CALIBRATION NC_TXOUT_L3N
Y22 RV1 1 PX@ 2 1.69K_0402_1%
PCIE_CALR_TX TMDP
RV2 1 PX@ 2 1K_0402_5% N10 AA22 RV3 1 PX@ 2 1K_0402_1%
TEST_PG PCIE_CALR_RX
5

UV2 PX@ AH20

PLT_RST# 2 TXCBP_DPB3P AJ19
P

35,38,40,9> PLT_RST# B TXCBM_DPB3N

4 GPU_RST# AL27
DGPU_HOLD_RST# 1 Y PERSTB AL21
<9> DGPU_HOLD_RST# A TX3P_DPB2P
G

AK20
TX3M_DPB2N
1

216-0856050 A0 JET LE S3
3

PX@ JET@ AH22

MC74VHC1G08DFT2G_SC70-5 RV4 TX4P_DPB1P AJ21
100K_0402_5% UV1 TX4M_DPB1N
SA000079N00 AL23
2

S IC 216-0858020 A0 TOPAZ XT S3 BGA C38 TX5P_DPB0P AK22

TOPAZ@ TX5M_DPB0N
AK24
NC_TXOUT_U3P AJ23
NC_TXOUT_U3N

216-0856050 A0 JET LE S3
JET@

D D

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2013/01/11 Deciphered Date 2013/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SUN_PCIE/DP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B091P
Wednesday, February 12, 2014 Sheet 18 of 55
1 2 3 4 5
 1 2 3 4 5

+3VGS

+1.8VGS
PS_0[3:1]=001 Strap Name :

1
UV1B U?
RV202 RV203 PS_0[5:4]=11

1
45.3K_0402_5% 45.3K_0402_5% PS_0[1] ROM_CONFIG[0]

2
@ @ PX@
AF2 RV12 PS_0[2] ROM_CONFIG[1]

2
6 1 VGA_SMB_DA3 NC#AF2 AF4 8.45K_0402_1%
<32,35,8> EC_SMB_DA2 NC#AF4
PS_0[3] ROM_CONFIG[2]

2
QV9A N9 AG3 PS_0
DBG_DATA16 NC#AG3

5
DMN65D8LDW-7 2N SOT363-6 L9 AG5 Resistor Divider Lookup Lable PS_0[4] N/A
DBG_DATA15 NC#AG5

1
@ AE9 1

0.68U_0402_10V
DPA
3 4 VGA_SMB_CK3 Y11 DBG_DATA14 AH3 PX@
<32,35,8> EC_SMB_CK2 AE8 DBG_DATA13 NC#AH3 AH1 CV30 RV7
PS_0[5] AUD_PORT_CONN_PINSTRAP[0]
QV9B AD9 DBG_DATA12 NC#AH1 R_pu (ohm) R_pd (ohm) Bitd [3:1] 2K_0402_1%
A DMN65D8LDW-7 2N SOT363-6 AC10 DBG_DATA11 AK3 @ 2 A

2
@ AD7 DBG_DATA10 NC#AK3 AK1
AC8 DBG_DATA9 NC#AK1 NC 4.75k 000
DVO
AC7 DBG_DATA8 AK5
AB9 DBG_DATA7 NC#AK5 AM3
8.45k 2k 001
AB8 DBG_DATA6 NC#AM3
+3VGS +3VGS +3VGS +1.8VGS AB7 DBG_DATA5 AK6
4.53k 2k 010
AB4 DBG_DATA4 NC#AK6 AM5
AB2 DBG_DATA3 NC#AM5 6.98k 4.99k 011 +1.8VGS
DBG_DATA2 DPB PS_1[3:1]=000 Strap Name :
2

2 2 JET@ Y8 AJ7 4.53k 4.99k 100

CV209 RV91 RV256 Y7 DBG_DATA1 NC#AJ7 AH6
DBG_DATA0 NC#AH6 PS_1[5:4]=11

1
10K_0402_5% 10K_0402_5% CV208 3.24k 5.62k 101 PS_1[1] STRAP_BIF_GEN3_EN_A
.1U_0402_16V7K @ JET@ .1U_0402_16V7K AK8 @
JET@ 1 1 NC#AK8 AL7 RV9
3.4k 10k 110 PS_1[2] TRAP_BIF_CLK_PM_EN
1

JET@ FOR TOPAZ,JET/SUN DOESN'T HAVE NC#AL7 8.45K_0402_1%

UV13 JET@ 4.75k NC 111 PS_1[3] N/A

2
JET@ 33_0402_5% 1 8 33_0402_5% +1.8VGS W6 PS_1
GPU_VID3 RV247 1 2GPU_VID3_GPIO_15 2 VCCA VCCB 7 RV131 1 2 GPU_SVD V6 NC#W6
A1 B1 NC#V6 0402 1% resistors are equired PS_1[4] STRAP_TX_CFG_DRV_FULL_SWING

1
GPU_VID1 RV92 1 2GPU_VID1_GPIO_20 3 6 RV130 1 2 GPU_SVC V4 1

0.68U_0402_10V
JET@ 33_0402_5%DIR 5 A2 B2 4 AC6 NC#V4 U5 PX@
DIR GND 33_0402_5%JET@ AC5 NC#AC5 NC#U5 CV31 RV14
PS_1[5] STRAP_TX_DEEMPH_EN
NC#AC6
2

W3 4.75K_0402_1%
NC#W3

2
SN74LVC2T45DCTR_SM8 AA5 V2 @ 2
Capacitor Divider Lookup Lable

2
RV16 RV11 AA6 NC#AA5 NC#V2
DPC
RV135 RV134 4.7K_0402_5% 4.7K_0402_5% NC#AA6 Y4
10K_0402_5% 10K_0402_5% TOPAZ@ TOPAZ@ NC#Y4 W5 Cap (nF) Bitd [5:4]
1

JET@ @ NC#W5

1
GPU_VID3 RV245 1 @ 2 0_0402_5% GPU_SVD U1 AA3 PLL_ANALOG_OUT 1 PX@ 2
GPU_VID1 RV246 1 @ 2 0_0402_5% GPU_SVC 1 FB_VDDCI W1 NC#U1 NC#AA3 Y2 RV17
JET@
TV23
U3 NC#W1 NC#Y2 16.2K_0402_1%
680nF 00
+3VGS 10K_0402_5% CV210 10U_0603_6.3V6M Y6 NC#U3 J8 +1.8VGS
RV250 2 1 DIR 2 1 1 PLL_ANALOG_IN AA1 NC#Y6 NC#J8 82nF 01 PS_2[3:1]=000 Strap Name :
TV18 NC#AA1
3.3V TO 1.8V LEVEL SHIF 10nF 10 PS_2[5:4]=00

1
JET@ CV211 PS_2[1] N/A
2 1 .1U_0402_16V7K NC 11 @
For JET/SUN to support SVI2 reaulator RV57 PS_2[2] N/A
JET@ I2C 8.45K_0402_1%
DNI for TOPAZ PS_2[3] STRAP_BIOS_ROM_EN

2
B R1 PS_2 B
R3 SCL
SDA PS_2[4] STRAP_BIF_VGA_DIS

1
+3VGS
1

0.68U_0402_10V
+3VGS AM26 PX@ PX@
REAK CURRENT CONTROL ( Topaz only ) +VGA_CORE R AK26 CV32 RV19
PS_2[5] N/A
GENERAL PURPOSE I/O AVSSN#AK26

2
U6 +3VGS 4.75K_0402_1%
GPIO_0
2

RV257 1 TOPAZ@2 0_0402_5% U10 AL25 2

2
RV10 FOR TOPAS CORE POWER USE RV258 1 TOPAZ@2 0_0402_5% T10 GPIO_1 G AJ25 @ RV373
GPIO_2 AVSSN#AJ25

2
10K_0402_5% VGA_SMB_DA3 U8 4.7K_0402_5%
@ VGA_SMB_CK3 U7 SMBDATA AH24 RV371
TOPAZ@

2 1
RV15 DV1 1 2 GPU_GPIO5 T9 SMBCLK B AG25
<33,35,45> VCIN1_AC_IN 4.7K_0402_5%
1

GPIO_5_AC_BATT AVSSN#AG25

G
1K_0402_5% GPU_GPIO6 T8 @
GPU_GPIO6 1 2 GPU_PROCHOT# DB2J31400L SOD323-2 T7 GPIO_6 DAC1 AH26
GPU_PROCHOT# <51>

1
TOPAZ@ P10 GPIO_7_BLON HSYNC AJ27 3 1 GPU_WAKEB
1 GPIO_8_ROMSO VSYNC
P4 +1.8VGS

D
GPIO_9_ROMSI PS_3[3:1]=000 Strap Name :

2
CV17 P2 @
+VGA_CORE N6 GPIO_10_ROMSCK AD22 RV372 2N7002K_SOT23-3
.1U_0402_16V7K GPIO_11 RSET PS_3[5:4]=11

1
2 N5
TOPAZ@
N3 GPIO_12 AG24
4.7K_0402_5%
PX@
QV20
X76@
PS_3[1] BOARD_CONFIG[0] (Memory ID)
RV236 1 TOPAZ@2 0_0402_5% Y9 GPIO_13 AVDD AE22
OBFF OPTION: RV21 PS_3[2] BOARD_CONFIG[1] (Memory ID)

1
GPU_VID3 N1 GPIO_14_HPD2 AVSSQ Pull down for none OBFF design reserve by AMD request 8.45K_0402_1%
M4 GPIO_15_PWRCNTL_0 AE23 PS_3[3] BOARD_CONFIG[2] (Memory ID)

2
FOR TOPAS CORE POWER USE THM_ALERT# RV251 1 PX@ 2 0_0402_5% THM_ALERT#_R R6 GPIO_16 VDD1DI AD23 PS_3
<32> THM_ALERT# GPIO_17_THERMAL_INT VSS1DI
RV252 1 TOPAZ@2 0_0402_5% W10 PS_3[4] AUD_PORT_CONN_PINSTRAP[1]
GPIO_18

1
GPIO19_CTF M2 1

0.68U_0402_10V
GPIO_19_CTF FutureASIC/SEYMOUR/PARK
GPU_VID1 P8 AM12

CV33
X76@ PS_3[5] AUD_PORT_CONN_PINSTRAP[2]
+1.8VGS P7 GPIO_20_PWRCNTL_1 CEC_1 @ RV24
N8 GPIO_21 2K_0402_1%
1 RV13 2 GPIO19_CTF AK10 GPIO_22_ROMCSB AK12 SVI2_SVD RV242 1 TOPAZ@2 0_0402_5% GPU_SVD 2
GPU_SVD <51>

2
10K_0402_5% AM10 GPIO_29 RSVD#AK12 AL11 SVI2_SVT RV243 1 TOPAZ@2 0_0402_5% GPU_SVT
GPIO_30 RSVD#AL11 GPU_SVT <51>
@ 1 @ 2 GPUCLK_REQ#_GPU N7 AJ11 SVI2_SVC RV244 1 TOPAZ@2 0_0402_5% GPU_SVC GPU_SVC <51>
<8> GPUCLK_REQ# CLKREQB RSVD#AJ11
2

RV25 0_0402_5%
RV22 JTAG_TRSTB L6 FOR TOPAZ
JTAG_TDI L5 JTAG_TRSTB JET/SUN DOESN'T HAVE NATIVE SVI2
10K_0402_5%
JTAG_TCK L3 JTAG_TDI
1 @ 2 JTAG_TMS L1 JTAG_TCK AL13
+3VGS
1

RV26 5.11K_0402_5% 1 JTAG_TDO K4 JTAG_TMS GENLK_CLK AJ13

TV24 JTAG_TDO GENLK_VSYNC
+3VGS 1 PX@ 2 TESTEN K7
C RV27 1K_0402_5% AF24 TESTEN C
RV18 2 PX@ 1 4.7K_0402_5% THM_ALERT# +VGA_CORE NC#AF24 AG13
SWAPLOCKA AH12
RV237 1 TOPAZ@2 0_0402_5% AB13 SWAPLOCKB
W8 GENERICA
RV238 1 TOPAZ@2 0_0402_5% W9 GENERICB
W7 GENERICC AC19 PS_0
FOR TOPAS CORE POWER USE AD10 GENERICD PS_0
AJ9 GENERICE AD19 PS_1
+3VGS 1 AL9 NC#AJ9 PS_1
TV22 NC#AL9 AE17 PS_2
RV261 1 TOPAZ@2 0_0402_5% AC14 PS_2
1 PX_EN AB16 HPD1 AE20 PS_3
TV25 PX_EN PS_3
RV58 1 @ 2 GPU_GPIO5
10K_0402_5%
RV20 1 @ 2 JTAG_TDO AE19
10K_0402_5% AC16 TS_A
DBG_VREFG
VGA_AC_BATT
pull up DDC/AUX
+3VGS AE6
PLL/CLOCK DDC1CLK AE5
DDC1DATA OPTIAN FOR 3.3V tolerance VR,
RPV1 @ AD2 Check with VR vendor
1 8 JTAG_TRSTB AUX1P AD4 +VGA_CORE +1.8VGS +3VGS
2 7 JTAG_TDI AUX1N RV206 RV207
3 6 JTAG_TMS AC11 RV259 1 TOPAZ@2 0_0402_5% 1 TOPAZ@2 1 @ 2
4 5 JTAG_TCK DDC2CLK AC13 RV260 1 TOPAZ@2 0_0402_5% FOR TOPAZ CORE POWER USE 0_0402_5% 0_0402_5%
DDC2DATA

2
10K_8P4R_5% XTALIN AM28 AD13 RV209 RV208
XTALOUT AK28 XTALIN AUX2P AD11 10K_0402_5% 10K_0402_5%
XTALOUT AUX2N TOPAZ@ @
RV28 RV29 1 PX@ 2 10K_0402_5% AC22 AD20 FB_GND RV37 1 TOPAZ@2 0_0402_5%

1
XTALIN 1M_0402_5% XTALOUT RV31 1 PX@ 2 10K_0402_5% AB22 XO_IN NC#AD20 AC20 FB_VDDC RV51 1 TOPAZ@2 0_0402_5% GPU_VDD_RUN_FB_L <51> SVI2_SVD
NOGCLKDIS@ XO_IN2 NC#AC20 ONLY AVAILABLE ON TOPAZ, NC BALLS ON JET/SUN GPU_VDD_SEN <51> SVI2_SVC
AE16
NC#AE16

2
AD16
D YV1 NOGCLKDIS@ NC#AD16 D
4 3 SEYMOUR/FutureASIC AC1 @ TOPAZ@
NC OSC RV248 1 2 0_0402_5% THERM_D+ T4 DDCVGACLK AC3 RV204 RV205
<32> REMOTE1+ DPLUS THERMAL DDCVGADATA
1 2 TO EXTERNAL THERMAL SENSOR RV249 1 2 0_0402_5% THERM_D- T2 10K_0402_5% 10K_0402_5%
<32> REMOTE1-

1
OSC NC DMINUS GPU_VDD_RUN_FB_L RV30 1 2 10_0402_5%
27MHZ 10PF 5YEA27000102IF50Q3 +1.8VGS Enable MLPS GPU_VDD_SEN RV32 1 2 10_0402_5%
2 2 +VGA_CORE
CV19 SJ10000GI00 CV20 RV33 1 JET@ 2 10K_0402_5% GPIO28 R5
8.2P_0402_50V_NPO 8.2P_0402_50V_NPO 13mA AD17 GPIO28_FDO
NOGCLKDIS@ NOGCLKDIS@ LV4 1 2 0_0402_5% +TSVDD AC17 TSVDD
1 1 TSVSS
1
CV21
1U_0402_6.3V6K
PX@ 216-0856050 A0 JET LE S3
Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
2 JET@
Issued Date 2013/01/11 Deciphered Date 2013/12/31 SUN_MSIC
GPU_XTALIN_GCLK RV253 1GCLKDIS@2 0_0402_5% XTALIN
<41> GPU_XTALIN_GCLK THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B091P
Wednesday, February 12, 2014
Sheet 19 of 55
1 2 3 4 5
 1 2 3 4 5

+1.35VS to +1.35VGS (6.234A) UV1E JET@ U?

+1.35V +1.35VGS
UV14 PX@ AA27 A3
DMN3030LSS-13_SOP8L-8 No Use GPU Display Port outpud AB24 GND GND A30
8 1 +1.8VGS AB32 GND GND AA13
7 2 AC24 GND GND AA16
GND GND

2
.1U_0402_16V7K
6 3 UV1G JET@ U? AC26 AB10
GND GND

10U_0603_6.3V6M

1U_0402_6.3V6K
1 5 1 1 AC27 AB15
GND GND

CV25

CV26

CV22
RV34 AD25 AB6

CV23

CV24
DP POWER NC/DP POWER
10_0603_5% AD32 GND GND AC9
1 1

4
@ AG15 AE11 AE27 GND GND AD6
A A

3 1
2 PX@ 2 PX@ 2 PX@ AG16 DP_VDDR#AG15 NC#AE11 AF11 AF32 GND GND AD8
AF16 DP_VDDR#AG16 NC#AF11 AE13 AG27 GND GND AE7

1U_0402_6.3V6K

10U_0603_6.3V6M
2 2 AG17 DP_VDDR#AF16 NC#AE13 AF13 AH32 GND GND AG12
DP_VDDR#AG17 NC#AF13 GND GND

PX@

PX@
AG18 AG8 K28 AH10
RV60 5 GPU_PWR_EN# AG19 DP_VDDR#AG18 NC#AG8 AG10 K32 GND GND AH28
1 2 1.35VSG_GATE_R PX@ 1.35VSG_GATE AF14 DP_VDDR#AG19 NC#AG10 L27 GND GND B10
B+ DP_VDDR#AF14 GND GND
RV35 1M_0402_5% QV10B M32 B12

4
PX@ 220K_0402_5% DMN65D8LDW-7 2N SOT363-6 N25 GND GND B14
GND GND
6

1 PX@ N27 B16

CV27 P25 GND GND B18
0.022U_0402_16V7K AG20 AF6 P32 GND GND B20
GPU_PWR_EN# 2 PX@ AG21 DP_VDDC#AG20 NC#AF6 AF7 R27 GND GND B22
2 +0.95VGS AF22 DP_VDDC#AG21 NC#AF7 AF8 T25 GND GND B24
AG22 DP_VDDC#AF22 NC#AF8 AF9 T32 GND GND B26
1

QV10A AD14 DP_VDDC#AG22 NC#AF9 U25 GND GND B6

DMN65D8LDW-7 2N SOT363-6 DP_VDDC#AD14 U27 GND GND B8
PX@ V32 GND GND C1

CV28

CV29
W25 GND GND C32
1 1 GND GND
AG14 AE1 W26 E28
AH14 DP_VSSR NC#AE1 AE3 W27 GND GND F10
AM14 DP_VSSR NC#AE3 AG1 Y25 GND GND F12

1U_0402_6.3V6K

.1U_0402_16V7K
2 2 AM16 DP_VSSR NC#AG1 AG6 Y32 GND GND F14
DP_VSSR NC#AG6 GND GND

PX@

PX@
AM18 AH5 F16
AF23 DP_VSSR NC#AH5 AF10 GND F18
AG23 DP_VSSR NC#AF10 AG9 GND F2
AM20 DP_VSSR NC#AG9 AH8 GND F20
AM22 DP_VSSR NC#AH8 AM6 M6 GND F22
AM24 DP_VSSR NC#AM6 AM8 N13 GND GND F24
AF19 DP_VSSR NC#AM8 AG7 N16 GND GND F26
AF20 DP_VSSR NC#AG7 AG11 N18 GND GND F6
+1.05VS to +0.95VGS AE14 DP_VSSR
DP_VSSR
NC#AG11 N21
P6
GND
GND
GND
GND
GND
F8
G10
P9 GND GND G27
R12 GND GND G31
B +1.05VS +0.95VGS AF17 AE10 R15 GND GND G8 B
UV15 @ DPAB_CALR NC#AE10 R17 GND GND H14
AO4354_SO8 R20 GND GND H17
8 1 T13 GND GND H2
7 2 T16 GND GND H20
GND GND

2
B+

.1U_0402_16V7K
6 3 216-0856050 A0 JET LE S3? T18 H6
GND GND

1U_0402_6.3V6K
1 5 1 T21 J27
GND GND

CV44

CV34
RV239 T6 J31
GND GND
1

10_0603_5% U15 K11

4
RV59 @ U17 GND GND K2

3 1
2@ 2@ U20 GND GND K22
200K_0402_5% GND GND
@ U9 K6
+5VALW V13 GND GND
2

V16 GND
RV61 5 DGPU_PWR_EN_1.05VS V18 GND
GND
2

DGPU_PWR_EN#_GATE_R @ DGPU_PWR_EN#_GATE Y10

@ QV22B Y15 GND

4
RV241 10K_0402_5% DMN65D8LDW-7 2N SOT363-6 Y17 GND
GND
6

100K_0402_5% 1 @ Y20
CV35 R11 GND A32
1

0.01U_0402_25V7K T11 GND VSS_MECH AM1

DGPU_PWR_EN_1.05VS 2 @ AA11 GND VSS_MECH AM32
2 M12 GND VSS_MECH
N11 GND
1

GND
1

@ D @ QV22A V11
DGPU_PWR_EN 1 RV262 2 DGPU_PWR_EN_MOS 2 QV19 DMN65D8LDW-7 2N SOT363-6 GND
0_0402_5% G 2N7002H_SOT23-3 @
S
3

@ 216-0856050 A0 JET LE? S3

1 RV263 2
<35,48> GPU_1.8VGS_PWR_EN
0_0402_5%

Reserve for GPU Sequence

C C

+3VS to +3VS_VGA (25mA)

+3VS +3VGS +5VALW
+VGA_CORE +1.8VGS +0.95VGS

2
3 1 4.7U_0603_6.3V6K 1U_0402_6.3V6K PX@

2
RV38
1

QV16 1 1 100K_0402_5% RV39 RV53 RV56

LP2301ALT1G_SOT23-3 CV36 CV37 @ 470_0603_5% 470_0603_5% 470_0603_5%
PX@ RV40 @ @ @
2

1
PX@ @ 470_0603_5% GPU_PWR_EN#

DMN65D8LDW-7 2N SOT363-6

DMN65D8LDW-7 2N SOT363-6

DMN65D8LDW-7 2N SOT363-6
6 1

6 1

3 1
2 2

DMN65D8LDW-7 2N SOT363-6
2

3
+5VALW
1

D @
2 1 RV267 2 5 2 DGPU_PWR_EN# 2 DGPU_PWR_EN# 5 DGPU_PWR_EN#
<35,51> GPU_PWR_EN
G 0_0402_5%

1
RV42 PX@ DGPU_PWR_EN# RV43 PX@ S @ QV11B QV11A QV21A QV21B
3

4
QV17 RV41 PX@ PX@ @ @
20K_0402_5% 10K_0402_5% 2N7002H_SOT23-3 100K_0402_5%
@
1 PX@

2
1

PX@ D PX@ DGPU_PWR_EN#

D
1 RV264 2 DGPU_PWR_EN_3V3_MOS 2 QV18 CV38 D
<35,48,51,9> DGPU_PWR_EN .1U_0402_16V7K
0_0402_5% G 2N7002H_SOT23-3
2
S
3

@ PX@
1 RV265 2 DGPU_PWR_EN 1 RV266 2
<35> GPU_3VGS_PWR_EN
0_0402_5% 0_0402_5%

Reserve for GPU Sequence

Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date 2013/01/11 Deciphered Date 2013/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SUN_Power/GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B091P
Wednesday, February 12, 2014 Sheet 20 of 55
1 2 3 4 5
 1 2 3 4 5

A
+VGA_CORE 10uF 2.2uF 1uF 0.1uF A

+PCIE_PVDD:
VDDC TBD +1.35VGS 50mA (PCIE2.0) +1.8VGS
UV1D JET@
7 16 4 3 U?
100mA (PCIE3.0)
AM30
VDDCI 3.5A MEM I/O PCIE_PVDD

PCIE

CV47

CV48
1A +1.35VGS H13 AB23 1 1
H16 VDDR1 NC#AB23 AC23
H19 VDDR1 NC#AC23 AD24

CV75

CV88

CV74

CV80

CV83

CV87

CV76

CV77

CV78

CV79

CV81

CV82

CV89

CV86

CV85

CV84
1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
220U_B2_2.5VM_R35
J10 VDDR1 NC#AD24 AE24
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

10U_0603_6.3V6M

1U_0402_6.3V6K
+ J23 VDDR1 NC#AE24 AE25 2 2
+0.95VGS 10uF 1uF 0.1uF VDDR1 NC#AE25

PX@

PX@
@ J24 AE26
J9 VDDR1 NC#AE26 AF25
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 VDDR1 NC#AF25

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@
@

@
K10 AG26
K23 VDDR1 NC#AG26
PCIE_VDDC 1A 1 5(1@) 0 K24 VDDR1
K9 VDDR1 L23
L11 VDDR1 PCIE_VDDC L24
L12 VDDR1 PCIE_VDDC L25
BIF_VDDC 0.8A 0 1(1@) 0 L13 VDDR1 PCIE_VDDC L26
L20 VDDR1 PCIE_VDDC M22 +0.95VGS
L21 VDDR1 PCIE_VDDC N22 +PCIE_VDDC: 1A
L22 VDDR1 PCIE_VDDC N23
SPLL_VDDC 100mA 0 1 1 VDDR1 PCIE_VDDC N24
PCIE_VDDC R22
PCIE_VDDC T22

CV49

CV50

CV51

CV52

CV54
+1.8VGS 13mA LEVEL PCIE_VDDC U22 1 1 1 1 1
TRANSLATION PCIE_VDDC V22
AA20 PCIE_VDDC
+1.35VGS 10uF 1uF 0.1uF 0.01uF AA21 VDD_CT

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
AB20 VDD_CT AA15 2 2 2 2 2

CV55
B VDD_CT CORE VDDC B

PX@

PX@

PX@

PX@

PX@
1 AB21 N15
VDD_CT VDDC N17
VDDR1 1.5A 5(3@) 5 5 0 +3VGS VDDC R13
25mA I/O VDDC R16

1U_0402_6.3V6K
2 AA17 VDDC R18
VDDR3 VDDC

PX@
AA18 Y21
AB17 VDDR3 VDDC T12

CV56
AB18 VDDR3 VDDC T15 +VGA_CORE
+1.8VGS 10uF 1uF 0.1uF 1 VDDR3 VDDC T17
V12 VDDC T20
Y12 VDDR4 VDDC U13

1U_0402_6.3V6K
2 U12 VDDR4 VDDC U16
PCIE_PVDD 100mA 1 1 0 VDDR4 VDDC

PX@
U18
VDDC V21 VGA_CORE Cap in power side sheet
VDDC V15
VDDC V17
MPLL_PVDD 130mA 2 1 0 VDDC V20
VDDC

POWER
Y13
VDDC Y16
VDDC Y18
SPLL_PVDD 75mA 0 1 0 VDDC AA12
VDDC M11
VDDC N12 21A (VDDC + VDDCI (Merged) - PRO S3 (DDR3))
VDDC U11
VDDR4 (300mA) 0 0 0 VDDC
+1.8VGS
90mA PLL
LV1 1 2 0_0603_5% +MPLL_PVDD +0.95VGS
VDD_CT 13mA 0 1 0
R21 0.8A
CV39

CV40

CV41
1U_0402_6.3V6K
10U_0603_6.3V6M

10U_0603_6.3V6M

BIF_VDDC U21
+TSVDD 13mA 0 1 0 1 1 1 BIF_VDDC
L8

CV62
+1.8VGS MPLL_PVDD
C
2 2 2 75mA +VGA_CORE
1 C
PX@

PX@

PX@

+DP_VDDR 1 1 0 LV2 1 2 0_0402_5% +SPLL_PVDD

ISOLATED
CORE I/O
M13 +VDDCI RV234 1 2 0_0402_5%

1U_0402_6.3V6K
H7 VDDCI M15 2

CV42

CV43
10U_0603_6.3V6M

1U_0402_6.3V6K
SPLL_PVDD VDDCI

@
M16 RV235 1 2 0_0402_5%
+DP_VDDC 0 1 1 1 1 VDDCI M17
+0.95VGS VDDCI M18
100mA VDDCI M20
2 2 VDDCI
PX@

PX@ LV3 1 2 0_0402_5% +SPLL_VDDC H8 M21

SPLL_VDDC VDDCI N20
J7 VDDCI
+3VGS 10uF 1uF 0.1uF SPLL_PVSS

CV46

CV90
1U_0402_6.3V6K

.1U_0402_16V7K
1 1

VDDR3 25mA 0 1 0 216-0856050 A0 JET LE S3 ? VGA_CORE Cap in power side sheet

2 2

PX@

PX@
D D

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2013/01/11 Deciphered Date 2013/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SUN_Power
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B091P
Wednesday, February 12, 2014 Sheet 21 of 55
1 2 3 4 5
 1 2 3 4 5

JET@
A UV1C U? A
M_DA[63..0]
<23,24> M_DA[63..0] GDDR5/DDR3 GDDR5/DDR3
M_MA[15..0] M_DA0 K27 K17 M_MA0
<23,24> M_MA[15..0] DQA0_0 MAA0_0/MAA_0
M_DA1 J29 J20 M_MA1
M_DQM[7..0] M_DA2 H30 DQA0_1 MAA0_1/MAA_1 H23 M_MA2
<23,24> M_DQM[7..0] DQA0_2 MAA0_2/MAA_2
M_DA3 H32 G23 M_MA3
M_DQS[7..0] M_DA4 G29 DQA0_3 MAA0_3/MAA_3 G24 M_MA4
<23,24> M_DQS[7..0] DQA0_4 MAA0_4/MAA_4
M_DA5 F28 H24 M_MA5
M_DQS#[7..0] M_DA6 F32 DQA0_5 MAA0_5/MAA_5 J19 M_MA6
<23,24> M_DQS#[7..0] DQA0_6 MAA0_6/MAA_6
M_DA7 F30 K19 M_MA7
M_DA8 C30 DQA0_7 MAA0_7/MAA_7 G20 M_MA13
M_DA9 F27 DQA0_8 MAA0_8/MAA_13 L17 M_MA15
M_DA10 A28 DQA0_9 MAA0_9/MAA_15
M_DA11 C28 DQA0_10 J14 M_MA8
M_DA12 E27 DQA0_11 MAA1_0/MAA_8 K14 M_MA9
M_DA13 G26 DQA0_12 MAA1_1/MAA_9 J11 M_MA10
M_DA14 D26 DQA0_13 MAA1_2/MAA_10 J13 M_MA11
M_DA15 F25 DQA0_14 MAA1_3/MAA_11 H11 M_MA12
M_DA16 A25 DQA0_15 MAA1_4/MAA_12 G11 M_BA2
DQA0_16 MAA1_5/MAA_BA2 M_BA2 <23,24>
M_DA17 C25 J16 M_BA0
DQA0_17 MAA1_6/MAA_BA0 M_BA0 <23,24>
M_DA18 E25 L15 M_BA1 +1.35VGS
DQA0_18 MAA1_7/MAA_BA1 M_BA1 <23,24>
M_DA19 D24 G14 M_MA14
M_DA20 E23 DQA0_19 MAA1_8/MAA_14 L16

MEMORY INTERFACE
M_DA21 F23 DQA0_20 MAA1_9/RSVD RV136 1 PX@ 2 100_0402_1% M_MA0 100_0402_1% 1 PX@ 2 RV137
M_DA22 D22 DQA0_21 E32 M_DQM0 RV138 1 PX@ 2 100_0402_1% M_MA1 100_0402_1% 1 PX@ 2 RV139
+1.35VGS M_DA23 F21 DQA0_22 WCKA0_0/DQMA0_0 E30 M_DQM1 RV140 1 PX@ 2 100_0402_1% M_MA2 100_0402_1% 1 PX@ 2 RV141
M_DA24 E21 DQA0_23 WCKA0B_0/DQMA0_1 A21 M_DQM2 RV142 1 PX@ 2 100_0402_1% M_MA3 100_0402_1% 1 PX@ 2 RV143
M_DA25 D20 DQA0_24 WCKA0_1/DQMA0_2 C21 M_DQM3 RV144 1 PX@ 2 100_0402_1% M_MA4 100_0402_1% 1 PX@ 2 RV145
M_DA26 F19 DQA0_25 WCKA0B_1/DQMA0_3 E13 M_DQM4 RV146 1 PX@ 2 100_0402_1% M_MA5 100_0402_1% 1 PX@ 2 RV147
DQA0_26 WCKA1_0/DQMA1_0
1

M_DA27 A19 D12 M_DQM5 RV148 1 PX@ 2 100_0402_1% M_MA6 100_0402_1% 1 PX@ 2 RV149
PX@ M_DA28 D18 DQA0_27 WCKA1B_0/DQMA1_1 E3 M_DQM6 RV150 1 PX@ 2 100_0402_1% M_MA7 100_0402_1% 1 PX@ 2 RV151
RV44 M_DA29 F17 DQA0_28 WCKA1_1/DQMA1_2 F4 M_DQM7 RV152 1 PX@ 2 100_0402_1% M_MA8 100_0402_1% 1 PX@ 2 RV153
40.2_0402_1% M_DA30 A17 DQA0_29 WCKA1B_1/DQMA1_3 RV154 1 PX@ 2 100_0402_1% M_MA9 100_0402_1% 1 PX@ 2 RV155
M_DA31 C17 DQA0_30 H28 M_DQS0 RV156 1 PX@ 2 100_0402_1% M_MA10 100_0402_1% 1 PX@ 2 RV157
2

B
M_DA32 E17 DQA0_31 EDCA0_0/QSA0_0 C27 M_DQS1 RV158 1 PX@ 2 100_0402_1% M_MA11 100_0402_1% 1 PX@ 2 RV159 B
M_DA33 D16 DQA1_0 EDCA0_1/QSA0_1 A23 M_DQS2 RV160 1 PX@ 2 100_0402_1% M_MA12 100_0402_1% 1 PX@ 2 RV161
M_DA34 F15 DQA1_1 EDCA0_2/QSA0_2 E19 M_DQS3 RV162 1 PX@ 2 100_0402_1% M_MA13 100_0402_1% 1 PX@ 2 RV163
M_DA35 A15 DQA1_2 EDCA0_3/QSA0_3 E15 M_DQS4 RV164 1 PX@ 2 100_0402_1% M_MA14 100_0402_1% 1 PX@ 2 RV165
DQA1_3 EDCA1_0/QSA1_0
1

1 M_DA36 D14 D10 M_DQS5 RV166 1 PX@ 2 100_0402_1% M_MA15 100_0402_1% 1 PX@ 2 RV167
PX@ PX@ M_DA37 F13 DQA1_4 EDCA1_1/QSA1_1 D6 M_DQS6
RV46 CV65 M_DA38 A13 DQA1_5 EDCA1_2/QSA1_2 G5 M_DQS7
100_0402_1% 1U_0402_6.3V6K M_DA39 C13 DQA1_6 EDCA1_3/QSA1_3 RV168 1 PX@ 2 100_0402_1% M_BA0 100_0402_1% 1 PX@ 2 RV169
2 M_DA40 E11 DQA1_7 H27 M_DQS#0 RV170 1 PX@ 2 100_0402_1% M_BA1 100_0402_1% 1 PX@ 2 RV171
2

M_DA41 A11 DQA1_8 DDBIA0_0/QSA0_0B A27 M_DQS#1 RV172 1 PX@ 2 100_0402_1% M_BA2 100_0402_1% 1 PX@ 2 RV173
M_DA42 C11 DQA1_9 DDBIA0_1/QSA0_1B C23 M_DQS#2
M_DA43 F11 DQA1_10 DDBIA0_2/QSA0_2B C19 M_DQS#3
M_DA44 A9 DQA1_11 DDBIA0_3/QSA0_3B C15 M_DQS#4 RV174 1 PX@ 2 100_0201_1% VRAM_ODT0100_0201_1% 1 PX@ 2 RV175
M_DA45 C9 DQA1_12 DDBIA1_0/QSA1_0B E9 M_DQS#5 RV176 1 PX@ 2 100_0201_1% VRAM_ODT1100_0201_1% 1 PX@ 2 RV177
M_DA46 F9 DQA1_13 DDBIA1_1/QSA1_1B C5 M_DQS#6
M_DA47 D8 DQA1_14 DDBIA1_2/QSA1_2B H4 M_DQS#7
+1.35VGS M_DA48 E7 DQA1_15 DDBIA1_3/QSA1_3B RV178 1 PX@ 2 100_0201_1% M_RAS#0 100_0201_1% 1 PX@ 2 RV179
M_DA49 A7 DQA1_16 L18 VRAM_ODT0 RV180 1 PX@ 2 100_0201_1% M_RAS#1 100_0201_1% 1 PX@ 2 RV181
DQA1_17 ADBIA0/ODTA0 VRAM_ODT0 <23,24>
M_DA50 C7 K16 VRAM_ODT1
DQA1_18 ADBIA1/ODTA1 VRAM_ODT1 <23,24>
M_DA51 F7
DQA1_19
1

M_DA52 A5 H26 M_CLK0 RV182 1 PX@ 2 100_0201_1% M_CAS#0 100_0201_1% 1 PX@ 2 RV183
DQA1_20 CLKA0 M_CLK0 <23,24>
PX@ M_DA53 E5 H25 M_CLK#0 RV184 1 PX@ 2 100_0201_1% M_CAS#1 100_0201_1% 1 PX@ 2 RV185
DQA1_21 CLKA0B M_CLK#0 <23,24>
RV45 M_DA54 C3
40.2_0402_1% M_DA55 E1 DQA1_22 G9 M_CLK1
DQA1_23 CLKA1 M_CLK1 <23,24>
M_DA56 G7 H9 M_CLK#1 RV186 1 PX@ 2 100_0201_1% M_CS0B#0 100_0201_1% 1 PX@ 2 RV187
M_CLK#1 <23,24>
2

M_DA57 G6 DQA1_24 CLKA1B RV190 1 PX@ 2 100_0201_1% M_CS1B#0 100_0201_1% 1 PX@ 2 RV191
M_DA58 G1 DQA1_25 G22 M_RAS#0
DQA1_26 RASA0B M_RAS#0 <23,24>
M_DA59 G3 G17 M_RAS#1
DQA1_27 RASA1B M_RAS#1 <23,24>
M_DA60 J6 RV188 1 PX@ 2 100_0201_1% M_CS0B#1 100_0201_1% 1 PX@ 2 RV189
DQA1_28
1

1 M_DA61 J1 G19 M_CAS#0 RV192 1 PX@ 2 100_0201_1% M_CS1B#1 100_0201_1% 1 PX@ 2 RV193
DQA1_29 CASA0B M_CAS#0 <23,24>
PX@ PX@ M_DA62 J3 G16 M_CAS#1
DQA1_30 CASA1B M_CAS#1 <23,24>
RV47 CV66 M_DA63 J5
100_0402_1% 1U_0402_6.3V6K DQA1_31 H22 M_CS0B#0 RV194 1 PX@ 2 100_0201_1% M_CKE0 100_0201_1% 1 PX@ 2 RV195
2 CSA0B_0 M_CS0B#0 <23>
+MVREFDA K26 J22 M_CS0B#1 RV196 1 PX@ 2 100_0201_1% M_CKE1 100_0201_1% 1 PX@ 2 RV197
M_CS0B#1 <24>
2

+MVREFSA J26 MVREFDA CSA0B_1

C C
MVREFSA G13 M_CS1B#0
CSA1B_0 M_CS1B#0 <23>
J25 K13 M_CS1B#1 RV198 1 PX@ 2 100_0201_1% M_WE#0 100_0201_1% 1 PX@ 2 RV199
NC#J25 CSA1B_1 M_CS1B#1 <24>
RV52 1 PX@ 2 120_0402_1% K25 RV200 1 PX@ 2 100_0201_1% M_WE#1 100_0201_1% 1 PX@ 2 RV201
MEM_CALRP0 K20 M_CKE0
CKEA0 M_CKE0 <23,24>
PX@ PX@ J17 M_CKE1
CKEA1 M_CKE1 <23,24>
RV48 RV49
49.9_0402_1% 10_0402_1% G25 M_WE#0
WEA0B M_WE#0 <23,24>
1 2 2 1 DRST L10 H10 M_WE#1
<23,24> DRAM_RST DRAM_RST WEA1B M_WE#1 <23,24>
1 RV54 @ 1 2 51.1_0402_1% CV69 @1
@ 2 .1U_0402_16V7K K8
CLKTESTA
1

1 @ RV55 @ 1 2 51.1_0402_1% CV70 @1

@ 2 L7
PX@ PX@ CV67 .1U_0402_16V7K CLKTESTB
CV68 RV50 68P_0402_50V8J
120P_0402_50V8J 5.1K_0402_1% 2 Route 50ohms single-ended/100ohm diff and keep short
216-0856050 A0 JET LE S3
2 debug only, for clock observation,if not need, DNI. ?
2

Place close to GPU (within 25mm)

and place componment close to each other

D D

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2013/01/11 Deciphered Date 2013/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
SUN_MEM
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B091P
Wednesday, February 12, 2014 Sheet 22 of 55

1 2 3 4 5
 1 2 3 4 5

M_DA[63..0] UV3 UV4 UV5 UV6

<22,24> M_DA[63..0]
M_MA[15..0] VREFCA_UV3 M8 E3 M_DA19 VREFCA_UV4 M8 E3 M_DA14 VREFCA_UV5 M8 E3 M_DA41 VREFCA_UV6 M8 E3 M_DA58
<22,24> M_MA[15..0] VREFDQ_UV3 H1 VREFCA DQL0 F7 M_DA21 VREFDQ_UV4 H1 VREFCA DQL0 F7 M_DA9 VREFDQ_UV5 H1 VREFCA DQL0 F7 M_DA46 VREFDQ_UV6 H1 VREFCA DQL0 F7 M_DA63
M_DQM[7..0] VREFDQ DQL1 F2 M_DA18 VREFDQ DQL1 F2 M_DA15 VREFDQ DQL1 F2 M_DA43 VREFDQ DQL1 F2 M_DA59
<22,24> M_DQM[7..0] M_MA0 N3 DQL2 F8 M_DA22 M_MA0 N3 DQL2 F8 M_DA10 M_MA0 N3 DQL2 F8 M_DA44 M_MA0 N3 DQL2 F8 M_DA61
M_DQS[7..0] M_MA1 P7 A0 DQL3 H3 M_DA17 M_MA1 P7 A0 DQL3 H3 M_DA12 M_MA1 P7 A0 DQL3 H3 M_DA40 M_MA1 P7 A0 DQL3 H3 M_DA57
<22,24> M_DQS[7..0] M_MA2 P3 A1 DQL4 H8 M_DA23 M_MA2 P3 A1 DQL4 H8 M_DA11 M_MA2 P3 A1 DQL4 H8 M_DA45 M_MA2 P3 A1 DQL4 H8 M_DA62
M_DQS#[7..0] M_MA3 N2 A2 DQL5 G2 M_DA16 M_MA3 N2 A2 DQL5 G2 M_DA13 M_MA3 N2 A2 DQL5 G2 M_DA42 M_MA3 N2 A2 DQL5 G2 M_DA56
<22,24> M_DQS#[7..0] M_MA4 P8 A3 DQL6 H7 M_DA20 M_MA4 P8 A3 DQL6 H7 M_DA8 M_MA4 P8 A3 DQL6 H7 M_DA47 M_MA4 P8 A3 DQL6 H7 M_DA60
M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7
M_MA6 R8 A5 M_MA6 R8 A5 M_MA6 R8 A5 M_MA6 R8 A5
M_MA7 R2 A6 D7 M_DA4 M_MA7 R2 A6 D7 M_DA26 M_MA7 R2 A6 D7 M_DA39 M_MA7 R2 A6 D7 M_DA55
M_MA8 T8 A7 DQU0 C3 M_DA2 M_MA8 T8 A7 DQU0 C3 M_DA28 M_MA8 T8 A7 DQU0 C3 M_DA35 M_MA8 T8 A7 DQU0 C3 M_DA52
A M_MA9 R3 A8 DQU1 C8 M_DA7 M_MA9 R3 A8 DQU1 C8 M_DA27 M_MA9 R3 A8 DQU1 C8 M_DA38 M_MA9 R3 A8 DQU1 C8 M_DA51 A
M_MA10 L7 A9 DQU2 C2 M_DA0 M_MA10 L7 A9 DQU2 C2 M_DA31 M_MA10 L7 A9 DQU2 C2 M_DA32 M_MA10 L7 A9 DQU2 C2 M_DA50
M_MA11 R7 A10/AP DQU3 A7 M_DA5 M_MA11 R7 A10/AP DQU3 A7 M_DA25 M_MA11 R7 A10/AP DQU3 A7 M_DA37 M_MA11 R7 A10/AP DQU3 A7 M_DA53
M_MA12 N7 A11 DQU4 A2 M_DA1 M_MA12 N7 A11 DQU4 A2 M_DA29 M_MA12 N7 A11 DQU4 A2 M_DA33 M_MA12 N7 A11 DQU4 A2 M_DA49
M_MA13 T3 A12 DQU5 B8 M_DA6 M_MA13 T3 A12 DQU5 B8 M_DA24 M_MA13 T3 A12 DQU5 B8 M_DA36 M_MA13 T3 A12 DQU5 B8 M_DA54
M_MA14 T7 A13 DQU6 A3 M_DA3 M_MA14 T7 A13 DQU6 A3 M_DA30 M_MA14 T7 A13 DQU6 A3 M_DA34 M_MA14 T7 A13 DQU6 A3 M_DA48
M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7
A15/BA3 +1.35VGS A15/BA3 +1.35VGS A15/BA3 +1.35VGS A15/BA3 +1.35VGS

M_BA0 M2 B2 M_BA0 M2 B2 M_BA0 M2 B2 M_BA0 M2 B2

<22,24> M_BA0 M_BA1 N8 BA0 VDD D9 M_BA1 N8 BA0 VDD D9 M_BA1 N8 BA0 VDD D9 M_BA1 N8 BA0 VDD D9
<22,24> M_BA1 M_BA2 M3 BA1 VDD G7 M_BA2 M3 BA1 VDD G7 M_BA2 M3 BA1 VDD G7 M_BA2 M3 BA1 VDD G7
<22,24> M_BA2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
M_CLK0 J7 VDD N9 M_CLK0 J7 VDD N9 M_CLK1 J7 VDD N9 M_CLK1 J7 VDD N9
<22,24> M_CLK0 M_CLK#0 K7 CK VDD R1 M_CLK#0 K7 CK VDD R1 <22,24> M_CLK1 M_CLK#1 K7 CK VDD R1 M_CLK#1 K7 CK VDD R1
<22,24> M_CLK#0 M_CKE0 K9 CK VDD R9 M_CKE0 K9 CK VDD R9 <22,24> M_CLK#1 M_CKE1 K9 CK VDD R9 M_CKE1 K9 CK VDD R9
<22,24> M_CKE0 CKE/CKE0 VDD +1.35VGS CKE/CKE0 VDD +1.35VGS <22,24> M_CKE1 CKE/CKE0 VDD +1.35VGS CKE/CKE0 VDD +1.35VGS

VRAM_ODT0 K1 A1 VRAM_ODT0 K1 A1 VRAM_ODT1 K1 A1 VRAM_ODT1 K1 A1

<22,24> VRAM_ODT0 M_CS0B#0 L2 ODT/ODT0 VDDQ A8 M_CS0B#0 L2 ODT/ODT0 VDDQ A8 <22,24> VRAM_ODT1 M_CS1B#0 L2 ODT/ODT0 VDDQ A8 M_CS1B#0 L2 ODT/ODT0 VDDQ A8
<22> M_CS0B#0 M_RAS#0 J3 CS/CS0 VDDQ C1 M_RAS#0 J3 CS/CS0 VDDQ C1 <22> M_CS1B#0 M_RAS#1 J3 CS/CS0 VDDQ C1 M_RAS#1 J3 CS/CS0 VDDQ C1
<22,24> M_RAS#0 M_CAS#0 K3 RAS VDDQ C9 M_CAS#0 K3 RAS VDDQ C9 <22,24> M_RAS#1 M_CAS#1 K3 RAS VDDQ C9 M_CAS#1 K3 RAS VDDQ C9
<22,24> M_CAS#0 M_WE#0 L3 CAS VDDQ D2 M_WE#0 L3 CAS VDDQ D2 <22,24> M_CAS#1 M_WE#1 L3 CAS VDDQ D2 M_WE#1 L3 CAS VDDQ D2
<22,24> M_WE#0 WE VDDQ E9 WE VDDQ E9 <22,24> M_WE#1 WE VDDQ E9 WE VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
M_DQS2 F3 VDDQ H2 M_DQS1 F3 VDDQ H2 M_DQS5 F3 VDDQ H2 M_DQS7 F3 VDDQ H2
M_DQS0 C7 DQSL VDDQ H9 M_DQS3 C7 DQSL VDDQ H9 M_DQS4 C7 DQSL VDDQ H9 M_DQS6 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ

M_DQM2 E7 A9 M_DQM1 E7 A9 M_DQM5 E7 A9 M_DQM7 E7 A9

M_DQM0 D3 DML VSS B3 M_DQM3 D3 DML VSS B3 M_DQM4 D3 DML VSS B3 M_DQM6 D3 DML VSS B3
DMU VSS E1 DMU VSS E1 DMU VSS E1 DMU VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
B
M_DQS#2 G3 VSS J2 M_DQS#1 G3 VSS J2 M_DQS#5 G3 VSS J2 M_DQS#7 G3 VSS J2 B

M_DQS#0 B7 DQSL VSS J8 M_DQS#3 B7 DQSL VSS J8 M_DQS#4 B7 DQSL VSS J8 M_DQS#6 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
T2 VSS P9 DRAM_RST T2 VSS P9 DRAM_RST T2 VSS P9 DRAM_RST T2 VSS P9
<22,24> DRAM_RST RESET VSS T1 RESET VSS T1 RESET VSS T1 RESET VSS T1
L8 VSS T9 L8 VSS T9 L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
J1 B1 J1 B1 J1 B1 J1 B1
PX@ L1 NC/ODT1 VSSQ B9 PX@ L1 NC/ODT1 VSSQ B9 PX@ L1 NC/ODT1 VSSQ B9 PX@ L1 NC/ODT1 VSSQ B9
RV67 J9 NC/CS1 VSSQ D1 RV68 J9 NC/CS1 VSSQ D1 RV69 J9 NC/CS1 VSSQ D1 RV70 J9 NC/CS1 VSSQ D1
243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
2

2
VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
M_CLK0 RV71 1 2 PX@ VSSQ VSSQ VSSQ VSSQ
80.6_0402_1% 96-BALL 96-BALL M_CLK1 RV75 1 2 PX@ 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 80.6_0402_1% SDRAM DDR3 SDRAM DDR3
M_CLK#0RV72 1 2 PX@ H5TC2G63FFR-11C_FBGA96 H5TC2G63FFR-11C_FBGA96 H5TC2G63FFR-11C_FBGA96 H5TC2G63FFR-11C_FBGA96
80.6_0402_1% X76@ X76@ M_CLK#1RV76 1 2 PX@ X76@ X76@
1 80.6_0402_1%
CV143 1
.01U_0402_16V7-K CV166
PX@ .01U_0402_16V7-K
2 PX@
2

C C

+1.35VGS +1.35VGS +1.35VGS +1.35VGS +1.35VGS +1.35VGS

1

.1U_0402_16V7K
CV126

.1U_0402_16V7K
CV127

.1U_0402_16V7K
CV128

.1U_0402_16V7K
CV129

.1U_0402_16V7K
CV130

.1U_0402_16V7K
CV131

.1U_0402_16V7K
CV132

.1U_0402_16V7K
CV133

.1U_0402_16V7K
CV134

.1U_0402_16V7K
CV135

.1U_0402_16V7K
CV136

.1U_0402_16V7K
CV137

.1U_0402_16V7K
CV138

10U_0603_6.3V6M
CV139

10U_0603_6.3V6M
CV140

10U_0603_6.3V6M
CV141

10U_0603_6.3V6M
CV142
RV73 RV74 RV210 RV212 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
PX@ PX@ PX@ PX@
2

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

PX@

PX@

PX@

PX@
VREFCA_UV3 VREFCA_UV4 VREFCA_UV5 VREFCA_UV6
1

1 1 1 1
RV77 CV144 RV78 CV145 RV211 CV224 RV213 CV225
4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K
PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@
2 2 2 2 +1.35VGS
2

1U_0402_6.3V6K
CV146

1U_0402_6.3V6K
CV147

1U_0402_6.3V6K
CV148

1U_0402_6.3V6K
CV149

1U_0402_6.3V6K
CV150

1U_0402_6.3V6K
CV151

1U_0402_6.3V6K
CV152

1U_0402_6.3V6K
CV153

1U_0402_6.3V6K
CV154

1U_0402_6.3V6K
CV155

10U_0603_6.3V6M
CV156

1U_0402_6.3V6K
CV157

1U_0402_6.3V6K
CV158

1U_0402_6.3V6K
CV159

1U_0402_6.3V6K
CV160

1U_0402_6.3V6K
CV161

1U_0402_6.3V6K
CV162

1U_0402_6.3V6K
CV163

1U_0402_6.3V6K
CV164

1U_0402_6.3V6K
CV165
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@
+1.35VGS +1.35VGS +1.35VGS +1.35VGS
1

RV214 RV217 RV219 RV221

4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
PX@ PX@ PX@ PX@
D D
2

VREFDQ_UV3 VREFDQ_UV4 VREFDQ_UV5 VREFDQ_UV6

1

1 1 1 1
RV215 CV226 RV216 CV227 RV218 CV228 RV220 CV229
4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K
PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@
2 2 2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Title
Issued Date 2013/01/11 Deciphered Date 2013/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SUN_VRAM A Lower
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B091P
Wednesday, February 12, 2014 Sheet 23 of 55
1 2 3 4 5
 1 2 3 4 5

M_DA[63..0]
<22,23> M_DA[63..0]
M_MA[15..0]
<22,23> M_MA[15..0]
M_DQM[7..0] UV7 UV8 UV9 UV10
<22,23> M_DQM[7..0]
M_DQS[7..0] VREFCA_UV7 M8 E3 M_DA21 VREFCA_UV8 M8 E3 M_DA9 VREFCA_UV9 M8 E3 M_DA44 VREFCA_UV10 M8 E3 M_DA63
<22,23> M_DQS[7..0] VREFDQ_UV7 H1 VREFCA DQL0 F7 M_DA19 VREFDQ_UV8 H1 VREFCA DQL0 F7 M_DA14 VREFDQ_UV9 H1 VREFCA DQL0 F7 M_DA41 VREFDQ_UV10 H1 VREFCA DQL0 F7 M_DA58
M_DQS#[7..0] VREFDQ DQL1 F2 M_DA22 VREFDQ DQL1 F2 M_DA10 VREFDQ DQL1 F2 M_DA45 VREFDQ DQL1 F2 M_DA61
<22,23> M_DQS#[7..0] M_MA0 N3 DQL2 F8 M_DA18 M_MA0 N3 DQL2 F8 M_DA15 M_MA0 N3 DQL2 F8 M_DA43 M_MA0 N3 DQL2 F8 M_DA59
M_MA1 P7 A0 DQL3 H3 M_DA20 M_MA1 P7 A0 DQL3 H3 M_DA11 M_MA1 P7 A0 DQL3 H3 M_DA47 M_MA1 P7 A0 DQL3 H3 M_DA60
M_MA2 P3 A1 DQL4 H8 M_DA16 M_MA2 P3 A1 DQL4 H8 M_DA12 M_MA2 P3 A1 DQL4 H8 M_DA42 M_MA2 P3 A1 DQL4 H8 M_DA56
M_MA3 N2 A2 DQL5 G2 M_DA23 M_MA3 N2 A2 DQL5 G2 M_DA8 M_MA3 N2 A2 DQL5 G2 M_DA46 M_MA3 N2 A2 DQL5 G2 M_DA62
M_MA4 P8 A3 DQL6 H7 M_DA17 M_MA4 P8 A3 DQL6 H7 M_DA13 M_MA4 P8 A3 DQL6 H7 M_DA40 M_MA4 P8 A3 DQL6 H7 M_DA57
A M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7 A
M_MA6 R8 A5 M_MA6 R8 A5 M_MA6 R8 A5 M_MA6 R8 A5
M_MA7 R2 A6 D7 M_DA2 M_MA7 R2 A6 D7 M_DA28 M_MA7 R2 A6 D7 M_DA35 M_MA7 R2 A6 D7 M_DA52
M_MA8 T8 A7 DQU0 C3 M_DA4 M_MA8 T8 A7 DQU0 C3 M_DA26 M_MA8 T8 A7 DQU0 C3 M_DA37 M_MA8 T8 A7 DQU0 C3 M_DA55
M_MA9 R3 A8 DQU1 C8 M_DA0 M_MA9 R3 A8 DQU1 C8 M_DA31 M_MA9 R3 A8 DQU1 C8 M_DA32 M_MA9 R3 A8 DQU1 C8 M_DA50
M_MA10 L7 A9 DQU2 C2 M_DA7 M_MA10 L7 A9 DQU2 C2 M_DA27 M_MA10 L7 A9 DQU2 C2 M_DA39 M_MA10 L7 A9 DQU2 C2 M_DA51
M_MA11 R7 A10/AP DQU3 A7 M_DA3 M_MA11 R7 A10/AP DQU3 A7 M_DA30 M_MA11 R7 A10/AP DQU3 A7 M_DA34 M_MA11 R7 A10/AP DQU3 A7 M_DA48
M_MA12 N7 A11 DQU4 A2 M_DA6 M_MA12 N7 A11 DQU4 A2 M_DA24 M_MA12 N7 A11 DQU4 A2 M_DA38 M_MA12 N7 A11 DQU4 A2 M_DA54
M_MA13 T3 A12 DQU5 B8 M_DA1 M_MA13 T3 A12 DQU5 B8 M_DA29 M_MA13 T3 A12 DQU5 B8 M_DA33 M_MA13 T3 A12 DQU5 B8 M_DA49
M_MA14 T7 A13 DQU6 A3 M_DA5 M_MA14 T7 A13 DQU6 A3 M_DA25 M_MA14 T7 A13 DQU6 A3 M_DA36 M_MA14 T7 A13 DQU6 A3 M_DA53
M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7
A15/BA3 +1.35VGS A15/BA3 +1.35VGS A15/BA3 +1.35VGS A15/BA3 +1.35VGS

M_BA0 M2 B2 M_BA0 M2 B2 M_BA0 M2 B2 M_BA0 M2 B2

<22,23> M_BA0 M_BA1 N8 BA0 VDD D9 M_BA1 N8 BA0 VDD D9 M_BA1 N8 BA0 VDD D9 M_BA1 N8 BA0 VDD D9
<22,23> M_BA1 M_BA2 M3 BA1 VDD G7 M_BA2 M3 BA1 VDD G7 M_BA2 M3 BA1 VDD G7 M_BA2 M3 BA1 VDD G7
<22,23> M_BA2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
M_CLK0 J7 VDD N9 M_CLK0 J7 VDD N9 M_CLK1 J7 VDD N9 M_CLK1 J7 VDD N9
<22,23> M_CLK0 M_CLK#0 K7 CK VDD R1 M_CLK#0 K7 CK VDD R1 <22,23> M_CLK1 M_CLK#1 K7 CK VDD R1 M_CLK#1 K7 CK VDD R1
<22,23> M_CLK#0 M_CKE0 K9 CK VDD R9 M_CKE0 K9 CK VDD R9 <22,23> M_CLK#1 M_CKE1 K9 CK VDD R9 M_CKE1 K9 CK VDD R9
<22,23> M_CKE0 CKE/CKE0 VDD +1.35VGS CKE/CKE0 VDD +1.35VGS <22,23> M_CKE1 CKE/CKE0 VDD +1.35VGS CKE/CKE0 VDD +1.35VGS

VRAM_ODT0 K1 A1 VRAM_ODT0 K1 A1 VRAM_ODT1 K1 A1 VRAM_ODT1 K1 A1

<22,23> VRAM_ODT0 M_CS0B#1 L2 ODT/ODT0 VDDQ A8 M_CS0B#1 L2 ODT/ODT0 VDDQ A8 <22,23> VRAM_ODT1 M_CS1B#1 L2 ODT/ODT0 VDDQ A8 M_CS1B#1 L2 ODT/ODT0 VDDQ A8
<22> M_CS0B#1 M_RAS#0 J3 CS/CS0 VDDQ C1 M_RAS#0 J3 CS/CS0 VDDQ C1 <22> M_CS1B#1 M_RAS#1 J3 CS/CS0 VDDQ C1 M_RAS#1 J3 CS/CS0 VDDQ C1
<22,23> M_RAS#0 M_CAS#0 K3 RAS VDDQ C9 M_CAS#0 K3 RAS VDDQ C9 <22,23> M_RAS#1 M_CAS#1 K3 RAS VDDQ C9 M_CAS#1 K3 RAS VDDQ C9
<22,23> M_CAS#0 M_WE#0 L3 CAS VDDQ D2 M_WE#0 L3 CAS VDDQ D2 <22,23> M_CAS#1 M_WE#1 L3 CAS VDDQ D2 M_WE#1 L3 CAS VDDQ D2
<22,23> M_WE#0 WE VDDQ E9 WE VDDQ E9 <22,23> M_WE#1 WE VDDQ E9 WE VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
M_DQS2 F3 VDDQ H2 M_DQS1 F3 VDDQ H2 M_DQS5 F3 VDDQ H2 M_DQS7 F3 VDDQ H2
M_DQS0 C7 DQSL VDDQ H9 M_DQS3 C7 DQSL VDDQ H9 M_DQS4 C7 DQSL VDDQ H9 M_DQS6 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ

B B
M_DQM2 E7 A9 M_DQM1 E7 A9 M_DQM5 E7 A9 M_DQM7 E7 A9
M_DQM0 D3 DML VSS B3 M_DQM3 D3 DML VSS B3 M_DQM4 D3 DML VSS B3 M_DQM6 D3 DML VSS B3
DMU VSS E1 DMU VSS E1 DMU VSS E1 DMU VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
M_DQS#2 G3 VSS J2 M_DQS#1 G3 VSS J2 M_DQS#5 G3 VSS J2 M_DQS#7 G3 VSS J2
M_DQS#0 B7 DQSL VSS J8 M_DQS#3 B7 DQSL VSS J8 M_DQS#4 B7 DQSL VSS J8 M_DQS#6 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
T2 VSS P9 DRAM_RST T2 VSS P9 DRAM_RST T2 VSS P9 DRAM_RST T2 VSS P9
<22,23> DRAM_RST RESET VSS T1 RESET VSS T1 RESET VSS T1 RESET VSS T1
L8 VSS T9 L8 VSS T9 L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
J1 B1 J1 B1 J1 B1 J1 B1
DR@ L1 NC/ODT1 VSSQ B9 DR@ L1 NC/ODT1 VSSQ B9 DR@ L1 NC/ODT1 VSSQ B9 DR@ L1 NC/ODT1 VSSQ B9
RV79 J9 NC/CS1 VSSQ D1 RV80 J9 NC/CS1 VSSQ D1 RV81 J9 NC/CS1 VSSQ D1 RV82 J9 NC/CS1 VSSQ D1
243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
2

2
VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8
M_CLK0 RV83 1 2 PX@ VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
80.6_0402_1% VSSQ G1 VSSQ G1 M_CLK1 RV87 1 2 PX@ VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 80.6_0402_1% VSSQ G9 VSSQ G9
M_CLK#0RV84 1 2 PX@ VSSQ VSSQ VSSQ VSSQ
80.6_0402_1% 96-BALL 96-BALL M_CLK#1RV90 1 2 PX@ 96-BALL 96-BALL
1 SDRAM DDR3 SDRAM DDR3 80.6_0402_1% SDRAM DDR3 SDRAM DDR3
CV183 H5TC2G63FFR-11C_FBGA96 H5TC2G63FFR-11C_FBGA96 1 H5TC2G63FFR-11C_FBGA96 H5TC2G63FFR-11C_FBGA96
.01U_0402_16V7-K @ @ CV187 @ @
PX@ .01U_0402_16V7-K
2 PX@
2

C C

+1.35VGS +1.35VGS +1.35VGS +1.35VGS

1

RV85 RV86 RV223 RV225

4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
DR@ DR@ DR@ DR@
+1.35VGS +1.35VGS
2

VREFCA_UV7 VREFCA_UV8 VREFCA_UV9 VREFCA_UV10

1

.1U_0402_16V7K
CV167

.1U_0402_16V7K
CV168

.1U_0402_16V7K
CV169

.1U_0402_16V7K
CV170

.1U_0402_16V7K
CV171

.1U_0402_16V7K
CV172

.1U_0402_16V7K
CV173

.1U_0402_16V7K
CV174

.1U_0402_16V7K
CV175

.1U_0402_16V7K
CV176

.1U_0402_16V7K
CV177

.1U_0402_16V7K
CV178

.1U_0402_16V7K
CV179

10U_0603_6.3V6M
CV180

10U_0603_6.3V6M
CV181

10U_0603_6.3V6M
CV182

10U_0603_6.3V6M
CV184
1 1 1 1
RV88 CV185 RV89 CV186 RV222 CV230 RV224 CV231 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K
DR@ DR@ DR@ DR@ DR@ DR@ DR@ DR@
2 2 2 2
2

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

DR@

DR@

DR@

DR@
+1.35VGS +1.35VGS +1.35VGS +1.35VGS +1.35VGS
1

1U_0402_6.3V6K
CV188

1U_0402_6.3V6K
CV189

1U_0402_6.3V6K
CV190

1U_0402_6.3V6K
CV191

1U_0402_6.3V6K
CV192

1U_0402_6.3V6K
CV193

1U_0402_6.3V6K
CV194

1U_0402_6.3V6K
CV195

1U_0402_6.3V6K
CV196

1U_0402_6.3V6K
CV197

10U_0603_6.3V6M
CV198

1U_0402_6.3V6K
CV199

1U_0402_6.3V6K
CV200

1U_0402_6.3V6K
CV201

1U_0402_6.3V6K
CV202

1U_0402_6.3V6K
CV203

1U_0402_6.3V6K
CV204

1U_0402_6.3V6K
CV205

1U_0402_6.3V6K
CV206

1U_0402_6.3V6K
CV207
RV233 RV227 RV229 RV231 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
DR@ DR@ DR@ DR@
2

D 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 D

DR@

DR@

DR@

DR@

DR@

DR@

DR@

DR@

DR@

DR@

DR@

DR@

DR@

DR@

DR@

DR@

DR@

DR@

DR@

DR@
VREFDQ_UV7 VREFDQ_UV8 VREFDQ_UV9 VREFDQ_UV10
1

1 1 1 1
RV232 CV235 RV226 CV232 RV228 CV233 RV230 CV234
4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K
DR@ DR@ DR@ DR@ DR@ DR@ DR@ DR@
2 2 2 2
2

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2013/01/11 Deciphered Date 2013/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SUN_VRAM A Upper
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B091P
Wednesday, February 12, 2014 Sheet 24 of 55
1 2 3 4 5
 1 2 3 4 5

A A

B B

C C

D D

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2013/01/11 Deciphered Date 2013/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SUN_VRAM
Size Document Number
A Lower Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B091P
Wednesday, February 12, 2014 Sheet 25 of 55
1 2 3 4 5
 1 2 3 4 5

A A

B B

C C

D D

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2013/01/11 Deciphered Date 2013/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SUN_VRAM
Size Document Number
A Upper Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B091P
Wednesday, February 12, 2014 Sheet 26 of 55
1 2 3 4 5
 5 4 3 2 1

LCD Power Circuit W=60mils +3VS

Camera +3VS_CMOS
+3VS +LCDVDD_CONN

W=60mils U5 CMOS@
5 1 +LCDVDD_CONN Q4

4.7U_0603_6.3V6K
IN OUT LP2301ALT1G_SOT23-3
2

C128
GND 1 W=20mils W=20mils

D
3 1
4 3 1 1
EN OC CMOS@
SY6288C20AAC_SOT23-5 2 C129 C130 @

G
2
D D
.1U_0402_16V7K 10U_0603_6.3V6M
R119CMOS@ 2 2
150K_0402_5%
<9> PCH_ENVDD 4.7V
<35> CMOS_ON#

1
1
R120 C132 CMOS@
100K_0402_5% .1U_0402_16V7K
2 2

+3VS

5
U15
2
From PCH

P
<35,9> ENBKL B 4 DISPOFF#
1 Y
From EC <35> BKOFF# A

2
eDP CONN.

3
2
R124
C R211 U74AHC1G08G-AL5-R_SOT353-5 100K_0402_5% C
100K_0402_5%

1
+LEDVDD B+

1
R121
R123 1 2 0_0402_5% 0_0805_5%
1 2
1
@
C133
4.7U_0805_25V6-K
2

JLVDS1
1
2 1 41
3 2 G1 42
4 3 G2 43
R126 1 2 0_0402_5% EDP_HPD_R 5 4 G3 44
<9> EDP_HPD 5 G4
6 45
6 G5
1

7 46
<9> INVPWM 7 G6
DISPOFF# 8
R128 EDP_HPD_R 9 8
100K_0402_5% 10 9
W=60mils 11 10
+LCDVDD_CONN
2

12 11
13 12
eDP 14 13
C134 1 2 .1U_0402_16V7K EDP_AUXN_C 15 14
<5> EDP_AUXN 15
C135 1 2 .1U_0402_16V7K EDP_AUXP_C 16
<5> EDP_AUXP 17 16
C136 1 2 .1U_0402_16V7K EDP_TXP0_C 18 17
<5> EDP_TXP0 18
C137 1 2 .1U_0402_16V7K EDP_TXN0_C 19
<5> EDP_TXN0 20 19

EMI <5> EDP_TXP1

<5> EDP_TXN1
C138 1FHD@ 2 .1U_0402_16V7K
C139 1FHD@ 2 .1U_0402_16V7K
EDP_TXP1_C
EDP_TXN1_C
21
22
23
20
21
22
B
R125 2 1 0_0402_5% R293 1 2 0_0402_5% 24 23 B
<10> TS_Detect 25 24
Reserve T33 for Presence Detect <10> TS_INT#
26 25
<10> I2C_1_SDA 27 26
@
<10> I2C_1_SCL 27
4 L6 3 USB20_N5_R 28
<11> USB20_N5 4 3 28
USB20_P4_R 29
Touch Screen USB20_N4_R 30 29
Camera 1 2 USB20_P5_R 31 30
<11> USB20_P5 1 2 31
R122 1 2 0_0402_5% TS_RST# 32
<35> TS_DISABLE# 32
WCM-2012HS-900T +3VS R270 2 1 0_0603_5% +3VS_TS 33
34 33
+3VS_CMOS 34
R127 2 1 0_0402_5% USB20_N5_R 35
USB20_P5_R 36 35
37 36
Camera 38 37
<39> DMIC_CLK 38
DMIC <39> DMIC_DAT
39
39
40
+3VS 40
R129 2 1 0_0402_5%
2 1 E-T_0871K-F40N-00L
TS@ TS@ ME@
@ C242 C243 SP010011Z00
4 L7 3 USB20_N4_R .1U_0402_16V7K 10U_0603_6.3V6M
<11> USB20_N4 4 3 1 2
Touch Screen 1 2 USB20_P4_R
<11> USB20_P4 1 2
WCM-2012HS-900T Close JLVDS1
R130 2 1 0_0402_5%

+3VS_TS

R4452 1 2 100K_0402_5% TS_INT#

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS/CAMERA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B091P
Date: Wednesday, February 12, 2014 Sheet 27 of 55
5 4 3 2 1
 5 4 3 2 1

EMI
D For NoDocking Near JHDMI1 D
For Docking Near JHDMI1
L8 HDMI@
C229 <37> HDMI_CLK+_CK C229 1 2 .1U_0402_16V7K HDMI_CLK+_CK_C 1 2 HDMI_CLK+_CONN
0_0402_5% 1 2
Docking@ NoDocking@ +5V_Display
C230 <37> HDMI_CLK-_CK C230 1 2 .1U_0402_16V7K HDMI_CLK-_CK_C 4 3 HDMI_CLK-_CONN For NoDocking U6
0_0402_5% 4 3
Docking@ NoDocking@ MURATA DLW21HN900HQ2L +5VS 3
W=40mils
+3VS OUT
1
L9 HDMI@ 1
C231 C231 1 2 .1U_0402_16V7K HDMI_TX0+_CK_C 1 2 HDMI_TX0+_CONN IN C140
<37> HDMI_TX0+_CK 1 2 1
0_0402_5% 2
GND

2
Docking@ NoDocking@ C141 .1U_0402_16V7K 2
C232 <37> HDMI_TX0-_CK C232 1 2 .1U_0402_16V7K HDMI_TX0-_CK_C 4 3 HDMI_TX0-_CONN R133
0_0402_5% 4 3 1M_0402_5% Q5 .1U_0402_16V7K 2 AP2330W-7_SC59-3
Docking@ NoDocking@ MURATA DLW21HN900HQ2L NoDocking@ NoDocking@

2
G
2N7002H_SOT23-3

1
L10 HDMI@
C233 C233 1 2 .1U_0402_16V7K HDMI_TX1+_CK_C 1 2 HDMI_TX1+_CONN 3 1
0_0402_5%
<37> HDMI_TX1+_CK 1 2 <37,9> TMDS_B_HPD For CRT and HDMI

2
Docking@ NoDocking@
C234 <37> HDMI_TX1-_CK C234 1 2 .1U_0402_16V7K HDMI_TX1-_CK_C 4 3 HDMI_TX1-_CONN R137
0_0402_5% 4 3
20K_0402_5%
Docking@ NoDocking@ MURATA DLW21HN900HQ2L NoDocking@

1
L11 HDMI@
C235 <37> HDMI_TX2+_CK C235 1 2 .1U_0402_16V7K HDMI_TX2+_CK_C 1 2 HDMI_TX2+_CONN
0_0402_5% 1 2
Docking@ NoDocking@ JHDMI1 ZZZ 45@
C236 <37> HDMI_TX2-_CK C236 1 2 .1U_0402_16V7K HDMI_TX2-_CK_C 4 3 HDMI_TX2-_CONN HDMI_DET 19
4 3 <37> HDMI_DET 18 HP_DET
0_0402_5% +5V_Display
Docking@ NoDocking@ MURATA DLW21HN900HQ2L 17 +5V
For Docking HDMIDAT_R 16 DDC/CEC_GND
HDMICLK_R 15 SDA
14 SCL
Reserved HDMI Logo
13
HDMI_CLK-_CONN 12 CEC 20 RO0000003HM
C C
11 CK- G1 21
HDMI_CLK+_CONN 10 CK_shield G2 22
HDMI_TX0-_CONN 9 CK+ G3 23
8 D0- G4
HDMI_TX0+_CONN 7 D0_shield
HDMI_TX1-_CONN 6 D0+
5 D1-
HDMI_TX1+_CONN 4 D1_shield
HDMI_TX2-_CONN 3 D1+
2 D2-
HDMI_TX2+_CONN 1 D2_shield
D2+
For NoDocking For NoDocking CONCR_099ATAC19NBLCNF
+3VS ME@
+3VS DC232001K00

R143 1NoDocking@2 2.2K_0402_5% HDMIDAT_NB

Q6A
R144 1NoDocking@2 2.2K_0402_5% HDMICLK_NB NoDocking@
2

DMN65D8LDW-7 2N SOT363-6 For NoDocking

<37,9> HDMICLK_NB 1 6 HDMICLK_R
For Docking RP29
5

HDMI_TX1+_CK_C 5 4
HDMI_TX1-_CK_C 6 3
R143 4 3 HDMIDAT_R HDMI_CLK+_CK_C 7 2
<37,9> HDMIDAT_NB
10K_0402_5% HDMI_CLK-_CK_C 8 1
Docking@ Q6B
R144 NoDocking@ 470 +-5% 8P4R
10K_0402_5% DMN65D8LDW-7 2N SOT363-6 NoDocking@
Docking@
RP30
HDMI_TX0+_CK_C 5 4
HDMI_TX0-_CK_C 6 3
+5V_Display For Docking HDMI_TX2+_CK_C 7 2
HDMI_TX2-_CK_C 8 1
R145 1 HDMI@ 2 2.2K_0402_5% HDMIDAT_R <37> HDMICLK_R
B B
<37> HDMIDAT_R 470 +-5% 8P4R
R146 1 HDMI@ 2 2.2K_0402_5% HDMICLK_R NoDocking@

+3VS

1
D
2
ESD S
G
Q7

3
NoDocking@
E14@ D1 E14@ D2 E14@ D3 2N7002H_SOT23-3
HDMIDAT_R 9 10 1 1 HDMIDAT_R HDMI_CLK-_CONN 9 10 1 1 HDMI_CLK-_CONN HDMI_TX0+_CONN 9 10 1 1 HDMI_TX0+_CONN

HDMICLK_R 8 9 2 2 HDMICLK_R HDMI_CLK+_CONN 8 9 2 2 HDMI_CLK+_CONN HDMI_TX0-_CONN 8 9 2 2 HDMI_TX0-_CONN

HDMI_DET 7 7 4 4 HDMI_DET HDMI_TX1-_CONN 7 7 4 4 HDMI_TX1-_CONN HDMI_TX2+_CONN 7 7 4 4 HDMI_TX2+_CONN

6 6 5 5 HDMI_TX1+_CONN 6 6 5 5 HDMI_TX1+_CONN HDMI_TX2-_CONN 6 6 5 5 HDMI_TX2-_CONN

3 3 3 3 3 3

8 8 8

L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title
HDMI CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B091P
Date: Wednesday, February 12, 2014 Sheet 28 of 55
5 4 3 2 1
 5 4 3 2 1

+5VS +5VS_CRT

JP1
1 2
1 2
JUMP_43X39 Output Input Output Input
@
+1.8VS_CRT +1.8VS_RXVCC +1.8VS_CRT +1.8VS_DAC
+3VS +3VS_CRT

JP2 RT1 1 2 0_0402_5% RT2 1 2 0_0402_5%

1 2
1 2
Rated current 500mA, DC 0.1ohm Rated current 500mA, DC 0.1ohm
JUMP_43X39
@ Note: Depend on Note: Depend on
D D
Output Project, if Vp-p small Project, if Vp-p small
+3VS_CRT +1.8VS_CRT the 50mV change to 0 the 50mV change to 0
ohm ohm

1 1 1 1

10U_0603_6.3V6M

10U_0603_6.3V6M
.1U_0402_16V7K

1U_0402_6.3V6K
@ @

CT1

CT2

CT3

CT4
2 2 2 2
Output Input
+1.8VS_CRT +1.8VS_RXVDD

+3VS_CRT +1.8VS_RXVDD
RT3 1 2 0_0402_5%

1 1 1 1 1 1 1 Rated current 500mA, DC 0.1ohm

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
10U_0603_6.3V6M

4.7U_0603_6.3V6K
@
@ @ @ @

CT5

CT6

CT7

CT8

CT9

CT10

CT11
Note: Depend on
2 2 2 2 2 2 2 Project, if Vp-p small
the 50mV change to 0
ohm
ISPSDA_R RT4 1 2 0_0402_5%
ISPSCL_R RT5 1 2 0_0402_5% Pin.12 Pin.14 Pin.44 Pin.46

13
48

35
36

38
39

12
14
44
46
UT1

1
2
+5VS_CRT

DDCSCL

IVDD33
IVDD33
OVDD
OVDD

IVDD
IVDD
IVDD
IVDD
IVDDO
IVDDO
DDCSDA
RT6 1 2 0_0402_5% VGA_HPD 40
<9> DDI1_HPD HPD CT12
1

45 1 2 .1U_0402_16V7K
RT7 CT13 2 1 .1U_0402_16V7K CPU_DP1_C_P0 26 MCUVDDH
<5> CPU_DP1_P0 RX0P
4.7K_0402_5% CT14 2 1 .1U_0402_16V7K CPU_DP1_C_N0 27
<5> CPU_DP1_N0 RX0N +5VS
C CT15 2 1 .1U_0402_16V7K CPU_DP1_C_P1 29 47 RT8 C
<5> CPU_DP1_P1
2

2 1 .1U_0402_16V7K CPU_DP1_C_N1 30 RX1P MCURSTN 1 2

<5> CPU_DP1_N1
CT18
RX1N
Note: ISPSCL/ISPSDA for F/W update
1
28 22_0804_8P4R_5% @ 0_0402_5%
URDBG TT1
+3VS_CRT RT9 2 @ 1 1M_0402_5% CT19
RT10 2 @ 1 100K_0402_5% CT16 15 ISPSCL_R 4 5 CRT_CLK .1U_0402_16V7K
.1U_0402_16V7K ISPSCL 16 ISPSDA_R 3 6 2
ISPSDA

1
2 1 DDI1_AUX_C_DP 20 2 7 CRT_DATA
<9> DDI1_AUX_DP RXAUXP
2 1 DDI1_AUX_C_DN 19 23 1 8

OE#
P
<9> DDI1_AUX_DN RXAUXN VGADDCCLK 21 2 4
CT17 VSYNC CRT_VSYNC_1 RT18 1 2 33_0402_5% CRT_VSYNC_2
.1U_0402_16V7K VGADDCSDA A Y
RPT1

G
+3VS_CRT RT12 2 @ 1 100K_0402_5% DDI1_AUX_DP 18 3 VSYNC UT2 1
RT13 2 @ 1 1M_0402_5% DDI1_AUX_DN 17 DCAUXP VSYNC 4 HSYNC SN74AHCT1G125DCKR_SC70-5

3
DCAUXN HSYNC +1.8VS_DAC @ CT20
10P_0402_50V8J
2
+1.8VS_RXVCC
1 1

1U_0402_6.3V6K

.1U_0402_16V7K
@
25 10

CT21

CT22
+5VS
31 AVCC VDDC RT14
AVCC 2 2 1 2
1 1
IT6513FN
.1U_0402_16V7K
4.7U_0603_6.3V6K

+1.8VS_RXVCC
@

1
CT24

CT25

@ 0_0402_5%
22 CT23
2 2 PVCC 11 CRT_R
IORP .1U_0402_16V7K
2

1
+1.8VS_RXVDD 9 CRT_G

OE#
P
IOGP HSYNC 2 4 CRT_HSYNC_1 RT19 1 2 33_0402_5% CRT_HSYNC_2
24 A Y
Pin.25 DVDD18

G
8 CRT_B UT3
IOBP SN74AHCT1G125DCKR_SC70-5 1

3
41 @
NC/VGADETECT

8
7
6
5
+1.8VS_RXVCC CT26
5 1 2 RPT2 10P_0402_50V8J
32 RSET RT16 100_0402_1% 2
ASPVCC 75_0804_8P4R_1%
+5VS_CRT 7
RPT3

1
2
3
4
B VDDA +1.8VS_DAC B
1 8 CRT_DATA
2 7 CRT_CLK 6 1 2 CT27
3 6 PCSCL PCSDA 43 COMP .1U_0402_16V7K
4 5 PCSDA PCSCL 42 PCSDA
PCSCL 34 XTALIN_6511
XTALIN 33 XTALOUT_6511
2.2K_0804_8P4R_5% XTALOUT
PWDNB

PAD

IT6513FN_QFN48_6X6
37

49

+5VS_CRT

RT15 1 2 10K_0402_5% +5V_Display

CRT
ESD EMI LT1 6
JCRT1

FCM1608CF-470T07 0603 11
CRT_R 1 2 CRT_R_2 1
+5VS_CRT LT2 7
FCM1608CF-470T07 0603 CRT_DATA 12
CRT_G 1 2 CRT_G_2 2
DT1 E14@ LT3 8 G 16
CRT_HSYNC_2 6 3 CRT_DATA FCM1608CF-470T07 0603 CRT_HSYNC_2 13 17
I/O4 I/O2 1 2 3 G
CRT_B CRT_B_2
Reserve 9
10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J
CRT_VSYNC_2 14
5 2 1 1 1 1 1 1 4
VDD GND 10
CT28

CT29

CT30

CT31

CT32

CT33
@ RT17 CRT_CLK 15
1M_0402_5% 5
A XTALOUT_6511 XTALIN_6511 CRT_VSYNC_2 4 1 CRT_CLK 2 2 2 2 2 2 A
I/O3 I/O1 C-K_80443-5K1-152
@ YT1 AZC099-04S.R7G_SOT23-6 ME@
27MHZ 10PF 5YEA27000102IF50Q3 DC060006H00
Crystal +5VS_CRT DT2 E14@
3 4 CRT_R_2 6 3 CRT_B_2
OUT GND I/O4 I/O2
2 1
GND IN
1
18P_0402_50V8J

1 5 2
18P_0402_50V8J

@ VDD GND
CT34 @
Security Classification Compal Secret Data Compal Electronics, Inc.
2 CT35 2011/06/24 2012/07/12 Title
2 CRT_G_2 4 1
Issued Date Deciphered Date
I/O3 I/O1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT
AZC099-04S.R7G_SOT23-6 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B091P
Date: Wednesday, February 12, 2014 Sheet 29 of 55
5 4 3 2 1
 A B C D E F G H

HDD
SATA HDD Conn.
Near Connector
JHDD1
1
0.01U_0402_16V7K 2 1 C142 SATA_PTX_C_DRX_P0 2 GND
<7> SATA_PTX_DRX_P0 RX+
<7> SATA_PTX_DRX_N0 0.01U_0402_16V7K 2 1 C143 SATA_PTX_C_DRX_N0 3
4 RX-
C144 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N0 5 GND
<7> SATA_PRX_DTX_N0 C145 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P0 6 TX-
<7> SATA_PRX_DTX_P0 7 TX+
GND
1 1
8
R141 1 2 0_0805_5% +3V_HDD 9 3.3V
+3VS 3.3V
10
11 3.3V
R280 1 2 0_0402_5% HDD_DETECT#_R 12 GND
<35> HDD_DETECT# GND
13
14 GND
R142 1 2 0_0805_5% +5V_HDD 15 5V
+5VS 16 5V
17 5V
18 GND 23
19 Reserved GND1 24
Near HDD 20 GND GND2
21 12V
1 12V
+5V_HDD 22
C199 12V
.1U_0402_16V7K ALLTO_C166KH-122H9-L
2 ME@
1 1 1
@ SP011310171

2
C146
1000P_0402_50V7K
2
C147
.1U_0402_16V7K
2
C148
10U_0603_6.3V6M ESD

ODD
2 2

FOR 15"
SATA ODD FFC Conn.
JODD1
1
2 1
<7> SATA_PTX_DRX_P1 2
3
<7> SATA_PTX_DRX_N1 3
4
5 4
<7> SATA_PRX_DTX_N1 6 5
<7> SATA_PRX_DTX_P1 SATA_ODD_PRSNT_R 7 6
+5V_ODD 8 7
9 8
ODD_DA#_R 10 9
10 11
GND 12
GND
ACES_88058-100N
+5VALW +5VS NOZODD@ +5V_ODD ME@
SP010016C00
R147 1 2 0_0805_5%
1

ZODD@
S

R149 3 1
10K_0402_5%
3 3
ZODD@ Q8 C151 C153
2

R150 LP2301ALT1G_SOT23-3 E14@ E14@

G
2

100K_0402_5% ZODD@ 0.01U_0402_16V7K 0.01U_0402_16V7K

1 2 C152 C154 FOR 14"
1 1 E14@ E14@
SATA ODD Conn.
1

0.01U_0402_16V7K 0.01U_0402_16V7K
C149 C150
OUT

0.01U_0402_16V7K 10U_0603_6.3V6M Near Connector

2 ZODD@ 2 JODD2
2
<10> ODD_EN IN 1
GND

SATA_PTX_DRX_P1 B14@ C151 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P1_14 2 GND

Q9 SATA_PTX_DRX_N1 B14@ C152 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N1_14 3 A+
DRC2124E0L NPN MINI3-G3-B 4 A-
3

ZODD@ SATA_PRX_DTX_N1 B14@ C153 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N1_14 5 GND

SATA_PRX_DTX_P1 B14@ C154 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P1_14 6 B-
7 B+
GND

R151 1 2 0_0402_5% SATA_ODD_PRSNT_R 8

<7,9> SATA_ODD_PRSNT +5V_ODD 9 DP
10 +5V
R152 1 2 0_0402_5% ODD_DA#_R 11 +5V
<10> ODD_DA# 12 MD 15
13 GND GND 14
GND GND

ALLTO_C185S1-113H9-L
ME@
SP011312061

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD/BT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B091P
Date: Wednesday, February 12, 2014 Sheet 30 of 55
A B C D E F G H
 A B C D E

1 1

NGFF for WLAN / BT(Key E) +3VS +3VS_WLAN

Support ISCT(Intel Smart Connect Technology) NOISCT@
R153 1 2 0_0805_5%

ISCT@
+3VALW Q10
+3VS_WLAN AO3413_SOT23-3

D
JWLAN1 3 1
1 2 1 1
3 GND 3.3VAUX 4 C155 C156
<11> USB20_P6 USB_D+ 3.3VAUX
BT 5 6

G
<11> USB20_N6

2
7 USB_D- LED1# 8 4.7U_0603_6.3V6K @ .1U_0402_16V7K
GND PCM_CLK <35> WLAN_PWR_ON# 2 2
9 10 1
11 SIDO_CLK PCM_SYNC 12 ISCT@ ISCT@
13 SDIO_CMD PCM_IN 14 R154 C157
15 SDO_DAT0 PCM_OUT 16 150K_0402_5% .1U_0402_16V7K
2 2
17 SDO_DAT1 LED2# 18 2
19 SDO_DAT2 GND 20
21 SDO_DAT3 UART_WAKE# 22
23 SDIO_WAKE# UART_RX
SDIO_RESET#

24
25 UART_TX 26
27 GND UART_CTS 28
<11> PCIE_PTX_C_DRX_P4 29 PETP0 UART_RTS 30 R155 1 2 0_0402_5%
<11> PCIE_PTX_C_DRX_N4 PETN0 RESERVED EC_TX <33,35>
31 32 R156 1 2 0_0402_5%
GND RESERVED EC_RX <33,35>
33 34
<11> PCIE_PRX_DTX_P4 35 PERP0 RESERVED 36
WLAN <11> PCIE_PRX_DTX_N4
37 PERN0 COEX3 38
39 GND COEX2 40
<8> CLK_PCIE_WLAN REFCLKP0 COEX1
41 42 SUSCLK_R R157 1 2 0_0402_5%
<8> CLK_PCIE_WLAN# REFCLKN0 SUSCLK SUSCLK <9>
43 44 WL_RST#
R158 1 2 0_0402_5% WLANCLK_REQ#_R 45 GND PERST0# 46 BT_DISABLE_R R159 1 2 0_0402_5%
<8> WLANCLK_REQ# CLKEQ0# W_DISABLE2# WLBT_OFF# <10,9>
<9> PCH_PCIE_WAKE# R160 1 @ 2 0_0402_5% WAKE#_R 47 48 R161 1 2 0_0402_5%
PEWAKE0# W_DISABLE1# EC_WL_OFF# <35>
For ISCT <35,38> PCIE_LAN_WAKE# R162 1 2 0_0402_5% 49 50
51 GND I2C_DATA 52
53 RSRVD/PETP1 I2C_CLK 54
55 RSRVD/PETN1 ALERT 56
Note: The real behavior of BT_DISABLE are
57 GND RESERVED 58 BT_DISABLE=LOW, BT=OFF
59 RSRVD/PERP1 RESERVED 60
61 RSRVD/PERN1 RESERVED 62 BT_DISABLE=HIGH, BT=ON
63 GND RESERVED 64
65 RESERVED 3.3VAUX 66
67 RESERVED 3.3VAUX
GND
+3VS_WLAN
69 68
MTG77 MTG76

1
ISCT@ +3VS
LCN_DAN05-67306-0102 R163
ME@ 100K_0402_5% ISCT@

2
3 3
SP070013F00 Q11
2N7002K_SOT23-3

G
2
2

2
@
R507 R508 WL_RST# 1 3 PLT_RST# PLT_RST# <18,35,38,40,9>
100K_0402_5% 100K_0402_5%

S
1

1
R164 1NOISCT@ 2 0_0402_5%

4 4

Security Classification
2011/06/24
Compal Secret Data
2012/07/12 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card/NEW Card/SIM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B091P
Date: Wednesday, February 12, 2014 Sheet 31 of 55
A B C D E
 5 4 3 2 1

3 Channel
+3VS +3VGS

2
@
R165 R166 +3V_Thermal
0_0402_5% 0_0402_5%
SMSC thermal sensor

1
1
@ R167
C158
2 placed near JWLAN1 10K_0402_5%
.1U_0402_16V7K @
U7

2
1

D D
+3V_Thermal 1 10 EC_SMB_CK2
<19> REMOTE1+ VDD SMCLK EC_SMB_CK2 <19,35,8>
1
REMOTE1+ 2 9 EC_SMB_DA2
DP1 SMDATA EC_SMB_DA2 <19,35,8>
GPU C159
2200P_0402_50V7K REMOTE1- 3 8
2 DN1 ALERT# THM_ALERT# <19>
REMOTE2+
Near DDR <19> REMOTE1-
REMOTE2+ 4 7 THERM#
DP2 THERM#
1 1

1
C REMOTE2- 5 6
C160 2 Q12 C161 DN2 GND
100P_0402_50V8J B MMST3904-7-F_SOT323-3 2200P_0402_50V7K
2 E 2 EMC1403-2-AIZL-TR_MSOP10

3
REMOTE2-
Placed near U27 Address 1001_101xb
REMOTE1,2+/-:
Trace width/space:10/10 mil
Trace length:<8"

2 Channel
+3V_Thermal

@
C C329
2 SMSC thermal sensor C
.1U_0402_16V7K
placed near JWLAN1
1 @
U17
1 8 EC_SMB_CK2
VDD SCLK
1
@ REMOTE1+ 2 7 EC_SMB_DA2
C251 D+ SDATA
2200P_0402_50V7K REMOTE1- 3 6 THM_ALERT#
2 D- ALERT#
THERM# 4 5
THERM# GND

EMC1402-2-ACZL-TR MSOP 8P

Address is 1001100xb

CPU VGA NGFF NPTH Battery BD

H1 H2 H3 H17 H14 H15 H5 H13 H22 H23 H24 H8 H9
B B
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

1
H_2P6N H_2P6X4P0N H_2P6X4P0N H_2P0N

H_4P0 H_4P0 H_4P0 H_4P0 H_3P3 H_3P3 H_3P2 H_3P3 H_3P3

+5VS
FAN Conn
R168 JFAN1
2 1 +FAN 1 H10 H6 H18 H7 H20 H11 H21 H16 H19
2 1 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
<35> FAN_SPEED1 2
0_0603_5% <35> EC_FAN_PWM 3
4 3
5 4
2

1
6 G5
C162 G6
10U_0603_6.3V6M ACES_85205-04001 LANGAN
1 ME@ H_2P8X4P6 H_2P8X5P1 H_2P8X4P8 H_2P5 H_2P5 H_2P8 H_2P8 H_3P3 H_6P0
SP020008X00

FD1 FD2 FD3 FD4

1

1
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title
Fintek-Thermal IC/FAN/screw
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B091P
Date: Wednesday, February 12, 2014 Sheet 32 of 55
5 4 3 2 1
 KB For B15 KB For B14/E14
JKB2 JKB1
KSI[0..7] KSI1 1 KSI1 1
For Debug KSO[0..17]
KSI[0..7] <35>
KSI7
KSI6
2
3
1
2
KSI7
KSI6
2
3
1
2
KSO[0..17] <35> 4 3 4 3
KSO9 KSO9
JP3 +3VALW +3VALW +3VLP KSI4 5 4 KSI4 5 4
1 KSI5 6 5 KSI5 6 5
+3VALW 1 6 6
2 KSO0 7 KSO0 7
<31,35> EC_TX 2 7 7

2
3 KSI2 8 KSI2 8
<31,35> EC_RX 4 3 9 8 9 8
@ KSI3 KSI3
4 R274 R170 JPWRB1 KSO5 10 9 KSO5 10 9
ACES_85205-0400 100K_0402_5% 100K_0402_5% 1 KSO1 11 10 KSO1 11 10
2 1 KSI0 12 11 KSI0 12 11
ME@

1
PWR_LED# 3 2 KSO2 13 12 KSO2 13 12
ON/OFF# 4 3 KSO4 14 13 KSO4 14 13
<35,36> ON/OFF# 4 14 14
5 KSO7 15 KSO7 15
LID_SW# 6 5 KSO8 16 15 KSO8 16 15
<35> LID_SW# 6 16 16
KSO6 17 KSO6 17
J11: TOP 7 KSO3 18 17 KSO3 18 17
GND 18 18
J12: BOT J1
8
GND
KSO12 19
20 19
KSO12 19
20 19
KSO13 KSO13
20 20

2
1 2 ACES_88058-060N +3VS KSO14 21 KSO14 21
ME@ R263 KSO11 22 21 KSO11 22 21
SHORT PADS D24 D26 SP010010T00 470_0402_5% KSO10 23 22 KSO10 23 22
MESC5V02BD03 3P C/A SOT23 ESD
MESC5V02BD03 3P C/A SOT23 ESD KSO15 24 23 KSO15 24 23
J2 B14@ 24 24
KSO16 25 CAPS_LED#_R 25
1 2 <33,35> KSO16 26 25 26 25
ON/OFF# KSO17 CAPS_LED#
<33,35> KSO17

1
R263 2 B15@ 1 470_0402_5% CAPS_LED#_R 27 26 26 27
SHORT PADS 28 27 GND2 28
<35> CAPS_LED# 28 GND1
R264 2 B15@ 1 470_0402_5% NUM_LED#_R 29 31
30 29 GND 32
ESD <35> NUM_LED#
1 1 1 1
30 GND
ACES_88514-3001
ACES_88514-02601-071
ME@
ESD @ @ @ @ ME@ SP01000R500

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
C200 C201 C202 C203 SP010011A00
2 2 2 2

E14@
LED1 E14@
R171
PWR_LED# 1 2 1 2
Power (Green)
+3VS R258 1 2 0_0402_5% For B15/E14 (E14)
<35> PWR_LED#
200_0402_5%
+3VALW

LTST-C190KGKT 0603 GRN

+5VS R259 1 @ 2 0_0402_5% RP33 SC590KGK020
0_0804_8P4R_5%
@ E14@
C163
.1U_0402_16V7K RP34
0_0804_8P4R_5%
E14@ LED2
R172
Battery (Amber) <35> BATT_LOW_LED# BATT_LOW_LED# 1 2 1 2 +3VLP
RP33 JTP1 620_0402_5%
TP_VCC 1 8 B15_VCC_B14_R 1
1
(B14/B15/E14)
TP_CLK 2 7 B15_CLK_B14_L 2 19-217/S2C-FM2P1VY/3T 0603 ORANGE
<35> TP_CLK 3 6 3 2
TP_DATA B15_DATA_B14_GND SC500005T00 R173
<35> TP_DATA 3
1 1 4 5 4 200_0402_5%
@ @ 5 4 R294 1 @ 2 0_0402_5%
5 E14@
C164 C165 0_0804_8P4R_5% 6
100P_0402_50V8J 100P_0402_50V8J B15@ 6 R173
2 2 7 330_0402_5%
GND
3

RP34 8 LED3 B14@ B15@

1 8 B15_GND_B14_DATA GND R173
@ESD@ 2 7 B15_L_B14_CLK ACES_88058-060N Battery (Green) <35> BATT_CHG_LED# BATT_CHG_LED# R295 1 2 0_0402_5% 1 2 1 2 +3VLP
D5 3 6 B15_R_B14_VCC ME@ 330_0402_5%
PSOT24C_SOT23-3 TP_L 4 5 SP010010T00 (B14/B15/E14)
TP_R LTST-C190KGKT 0603 GRN
1

0_0804_8P4R_5% SC590KGK020 R174

B15@ 200_0402_5%
C166

C167
.1U_0402_16V7K

.1U_0402_16V7K

1 1 E14@
R174
ESD @
2
@
2
For B14 LED4 B14@
R174
B15@
330_0402_5%

PCH_SATALED# 1 2 1 2
RP35
HDD (Green) <7> PCH_SATALED#
330_0402_5%
+3VS
TP_VCC 1 8 B15_R_B14_VCC (B14/B15/E14)
TP_CLK 2 7 B15_L_B14_CLK LTST-C190KGKT 0603 GRN
TP_DATA 3 6 B15_GND_B14_DATA SC590KGK020
4 5

0_0804_8P4R_5%
B14@

1
RP36
8 B15_DATA_B14_GND
DC-In LED (Green) For B14 / E14
For B15/E14 TP module(100*50) For B14 TP module(84*42) TP_L 2 7 B15_CLK_B14_L
TP_R 3 6 B15_VCC_B14_R +3VLP
4 5
1 1 VCC 1 VCC 6 1 VCC 1 VCC R289 1 @ 2 0_0402_5% DC_LED R20 1 2 0_0402_5% DC_LED_Power
<45> ACPRN#
0_0804_8P4R_5% JLED1
B14@ 1
2 2 CLK 2 CLK 5 2 CLK 2 CLK 2 1
2

1
D 3 5
<36> DC_LED 3 G1
R298 1 2 0_0402_5% 2 Q20 4 6
3 3 DAT 3 DAT 4 3 DAT 3 DAT <19,35,45> VCIN1_AC_IN
G 2N7002K_SOT23-3 4 G2

<35,9> AC_PRESENT R299 1 @ 2 0_0402_5% S ACES_51512-0040N-P01

3
ME@
4 4 GND 4 L 3 4 GND 4 L SP01001J100

5 5 L 5 R 2 5 L 5 R
6 6 R 6 GND 1 6 R 6 GND
B15@
+3VALW R278 1 2 0_0402_5% +VCC_LID 1 R279 2
100K_0402_5%

2
C198
.1U_0402_16V7K 1

VDD
2 B15@
C248
ESD .1U_0402_16V7K
2 OUTPUT
3 LID_SW#

GND
L L R R 2
B15@
C249

1
B15@ 10P_0402_50V8J
B15@ E14@ SW3 B15@ SW2 E14@ U16 1
SW1 SW3 SMT1-05_4P SW2 SMT1-05_4P SW4
SMT1-05_4P SMT1-05_4P B14@ SMT1-05_4P B14@ SMT1-05_4P
5
6

5
6

5
6

5
6

TCS20DLR SOT-23F 3P
4 2 4 2 4 2 4 2
TP_L TP_L TP_R TP_R
3 1 3 1 3 1 3 1
Security Classification Compal Secret Data Compal Electronics, Inc.
2011/06/24 2012/07/12 Title
Issued Date Deciphered Date ROM/KBD/PWR/CR/LED/TP Conn.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B091P
Date: Friday, February 14, 2014 Sheet 33 of 55
 5 4 3 2 1

ESD
Finger Print U3RXDP1 8
E14@
U3RXDN1 9 10

9
D6
1 1 U3RXDN1

2 2 U3RXDP1 U3RXDP2 8
E14@
U3RXDN2 9 10

9
D7
1 1U3RXDN2

2 2U3RXDP2
U2DP1 3
E14@
I/O2 I/O4
D8
6 U2DP2 3
E14@
I/O2
D9
I/O4
6

U3TXDN1 7 7 4 4 U3TXDN1 U3TXDN2 7 7 4 4U3TXDN2 2 5 +USB3_VCCA 2 5 +USB3_VCCA

GND VDD GND VDD
U3TXDP1 6 6 5 5 U3TXDP1 U3TXDP2 6 6 5 5U3TXDP2
+3VS
3 3 3 3 1 4 U2DN1 1 4 U2DN2
JFP1 I/O1 I/O3 I/O1 I/O3
R291 1 2 0_0402_5% +3VS_FP 1 8 8
2 1 AZC099-04S.R7G_SOT23-6 AZC099-04S.R7G_SOT23-6
<11> USB20_P7 2
Finger Print 3
<11> USB20_N7 3
D
4 L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD D
(For B14/E14/B15) 5 4
6 5
6

2
1 7
8 GND
GND

USB3.0_Port

.1U_0402_16V7K
C247
D25
MESC5V02BD03 3P C/A SOT23 ESD ACES_88058-060N
2 ME@
EMI

1
SP010010T00 Intel_PCH_USB2.0
WCM-2012HS-900T
1 2 U2DN2
ESD <11> USB20_N1

4
1 2

3 U2DP2
<11> USB20_P1 4 USB2@ 3
L12

Left USB CONN

Intel_PCH_USB3.0
WCM-2012HS-900T +USB3_VCCA
1 2 U3RXDN2
<11> USB3_RX2_N 1 2
W=80mils
4 3 U3RXDP2 JUSB1
<11> USB3_RX2_P 4 USB3@ 3 U3TXDP2 9
L13 1 SSTX+
U3TXDN2 8 VBUS

EMI For B14 / B15 SSTX-

USB2.0_Port
+3VALW +3VLP U2DP2 3
7 D+
U2DN2 2 GND 10
D- GND 11

2
100K_0402_5%

100K_0402_5%
U3RXDP2 6
R177 2 @ 1 0_0402_5% @ C168USB3@ 4 SSRX+ GND 12
C GND GND 13 C
R275 R169 +USB_VCCB .1U_0402_16V7K WCM-2012HS-900T U3RXDN2 5
1 2 U3TXDN2_L 1 2 U3TXDN2 SSRX- GND
<11> USB3_TX2_N 1 2 J-L_TNBNRAC70010009
W=80mils

1
4 L14 3 USB20_N2_R ME@
<11> USB20_N2 4 3 1 2 U3TXDP2_L 4 3 U3TXDP2 DC23300ET10
<11> USB3_TX2_P 4
JIO1 USB3@ 3
Right USB2__I/O Port 1 2 USB20_P2_R 12 14 C169 USB3@ L15 Near HDMI CONN.
<11> USB20_P2 1 2 <39> HGNDB 12 G2 13
<39> HGNDA
11 .1U_0402_16V7K (Debug Port)
WCM-2012HS-900T 10 11 G1
<39> HPOUT_L 10
9
R178 2 @ 1 0_0402_5% 8 9
<39> HPOUT_R 8
7
<39> PLUG_IN 7
6
USB20_N2_R 5 6
USB20_P2_R 4 5
Right USB2__I/O Port 3 4
2 3 Intel_PCH_USB2.0
+5VALW
2A/Active Low +USB_VCCB 2 WCM-2012HS-900T
1
<35> NOVO# 1
W=80mils U8 W=80mils 1 2 U2DN1
<11> USB20_N0 1 2
1 ACES_88058-120N
5 OUT ME@
IN 2 SP010015H00 4 3 U2DP1
GND <11> USB20_P0 4 3
4 R179 USB2@
<35> USB_EN# EN L16
3 USB_OC1#_U8 1 2 USB_OC1#
OCB 0_0402_5%
1

SY6288D20AAC_SOT23-5
C195 1
.1U_0402_16V7K 1 Left USB CONN
2

+ @
C170 C171
Intel_PCH_USB3.0
220U_6.3V_M 470P_0402_50V7K WCM-2012HS-900T +USB3_VCCA
2 2 1 2 U3RXDN1
<11> USB3_RX1_N 1 2
W=80mils
4 3 U3RXDP1 JUSB2
<11> USB3_RX1_P 4 3
USB3@ U3TXDP1 9
L17 1 SSTX+
B VBUS B
U3TXDN1 8
U2DP1 3 SSTX-
7 D+
+5VALW +5V_CHGUSB U2DN1 2 GND 10
U3RXDP1 6 D- GND 11
C172USB3@ 4 SSRX+ GND 12

USB Charger .1U_0402_16V7K WCM-2012HS-900T U3RXDN1 5 GND

SSRX-
GND 13
GND
2

1 2 U3TXDN1_L 1 2 U3TXDN1
<11> USB3_TX1_N 1 2
E14@ J-L_TNBNRAC70010009
R297 +5V_CHGUSB ME@
10K_0402_5% 1 2 U3TXDP1_L 4 3 U3TXDP1 DC23300ET10
<11> USB3_TX1_P 4 3
U9 USB3@
80mil Near End User
1

1 12 +USB_VCCB C173USB3@ L18

9 IN OUT 10 USB20_P3_C .1U_0402_16V7K
<35> USB_CHG_STATUS# STATUS# DP_IN
R181 1 2 0_0402_5% USB_OC1#_U9 13 11 USB20_N3_C
<10,11> USB_OC1# FAULT# DM_IN
4 2
5 ILIM_SEL DM_OUT 3
USB20_N3_U <11> Right USB2__I/O Port
<35> USB_CHG_EN# EN DP_OUT USB20_P3_U <11>
(For E14) Place TX AC coupling Cap (C843~C850). Close to connector

R131 1
0_0805_5%
6 15 R182 1 @ 2 20K_0402_1%
<35> USB_CHG_CTL1 CTL1 ILIM_LO
7 16 R184 1 E14@ 2 16.5K_0402_1%
<35> USB_CHG_CTL2
<35> USB_CHG_CTL3
8 CTL2
CTL3
ILIM_HI
GND
14
17
@ For E14
T-PAD
1

E14@ 1 1 W=100mils

2
C174 TPS2544RTER WQFN 16P E14@ @ 2A/Active Low+USB3_VCCA
.1U_0402_16V7K E14@ + C175 C176 JIO2 +5VALW
2

220U_6.3V_M 470P_0402_50V7K HGNDB 18 20 W=80mils U10 W=80mils

2 HGNDA 17 18 G2 19 1
2 SF000006900 HPOUT_L 16 17 G1 5 OUT
15 16 IN 2
HPOUT_R 14 15 USB_EN# 4 GND R185
PLUG_IN 13 14 EN 3 USB_OC0#_R 1 2
13 OCB USB_OC0# <11>
12 0_0402_5%
12

1
11 SY6288D20AAC_SOT23-5
USB20_N3_R 10 11 C196
10 1
USB20_P3_R 9 .1U_0402_16V7K
Right USB2__I/O Port 1

2
8 9 + @
(For E14) 7 8 C178 C177
A
EMI USB20_N2_R
6
5
4
7
6
5
220U_6.3V_M
2 2
470P_0402_50V7K A

R186 2 @ 1 0_0402_5% USB20_P2_R 3 4

Right USB2__I/O Port 2 3
NOVO# 1 2

USB20_P3_C 4
4
E14@
L19
3
3 USB20_P3_R ESD 1
ACES_50505-0184N-001
ME@
3

SP010010X00
USB20_N3_C 1 2 USB20_N3_R
1 2 @ESD@ Security Classification Compal Secret Data Compal Electronics, Inc.
WCM-2012HS-900T D27 2011/06/24 2012/07/12 Title
MESC5V02BD03 3P C/A SOT23 ESD Issued Date Deciphered Date
R187 2 @ 1 0_0402_5% USB3.0/Left USB Ports
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 12, 2014 Sheet 34 of 55
5 4 3 2 1
 +3VLP
+3VALW
+3VLP
R188 1 @ 2 0_0603_5% 1@
C179
100P_0402_50V8J
R189 1 2 0_0603_5%
2
L20 +3VALW_EC
FBM-11-160808-601-T_0603 1 1 1 1
+EC_VCCA

.1U_0402_16V7K
C180

.1U_0402_16V7K
C181

1000P_0402_50V7K
C182

1000P_0402_50V7K
C183
1 2
+3VALW_EC +EC_VCCA
1 1
C185 @
C184 2 2 @ 2 @ 2

111
125
.1U_0402_16V7K 1000P_0402_50V7K U11

22
33
96

67
9
1 2 2 ECAGND 2
L21

EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC

EC_VDD/VCC

EC_VDD/AVCC
FBM-11-160808-601-T_0603

ECAGND
1 21
<34> USB_CHG_CTL3 GATEA20/GPIO00 GPIO0F VCCST_PWRGD <12>
2 23 BEEP#
<10> KB_RST# KBRST#/GPIO01 BEEP#/GPIO10 BEEP# <39>
3 26 EC_FAN_PWM
<10,9> SERIRQ 4 SERIRQ GPIO12 27 EC_FAN_PWM <32>
AC_OFF
<8> LPC_FRAME# LPC_FRAME# ACOFF/GPIO13 AC_OFF <45>
LPC_AD3 5
EMI
@EMI@ @EMI@
<8> LPC_AD3
<8> LPC_AD2
<8> LPC_AD1
LPC_AD2
LPC_AD1
LPC_AD0
7
8
10
LPC_AD3
LPC_AD2
LPC_AD1
PWM Output
BATT_TEMP/GPIO38
63
64 IMON_CPU_R
VCIN1_BATT_TEMP <44>
R309 1 E14@
R308 1 @
2 0_0402_5%
2 0_0402_5%
USB_CHG_STATUS# <34> For GPU
2 1 R190 2 1 10_0402_1% <8> LPC_AD0 LPC_AD0LPC & MISC GPIO39 65 IMON_CPU <52>
ADP_I/GPIO3A ADP_I <44,45> +3VS
C186 22P_0402_50V8J 12 AD Input 66
<8> CK_LPC_KBC 13 CLK_PCI_EC GPIO3B 75 GS_VOUTY <36>
ADP_ID
<18,31,38,40,9> PLT_RST# PCIRST#/GPIO05 GPIO42 ADP_ID <43>
1 2 EC_RST# 37 76 DS3 +5VALW
+3VALW_EC R192 47K_0402_5% EC_SCI# 20 EC_RST# IMON/GPIO43 ENBKL <27,9>
GPU_PWR_EN R310 1 @ 2 10K_0402_5%
<10> EC_SCI# 38 EC_SCII#/GPIO0E Reserve for +5VALW EN R194
2 <43> ADP_ID_CLOSE GPIO1D 68 USB_EN# 1 2
DAC_BRIG/GPIO3C 70 SUSACK# <46,9>
C187
EN_DFAN1/GPIO3D GPU_PWR_EN <20,51>
.1U_0402_16V7K DA Output 71 +3VALW 10K_0402_5%
IREF/GPIO3E DGPU_PWR_EN <20,48,51,9>
1

1 KSI0 55 72
56 KSI0/GPIO30 CHGVADJ/GPIO3F EC_WL_OFF# <31>
C188 KSI1
22P_0402_50V8J KSI2 57 KSI1/GPIO31 EC_MUTE# R198 1 @ 2 10K_0402_5%
2

KSO[0..15] KSI3 58 KSI2/GPIO32 83 +5VS +3VS +5VS +3VS

<33> KSO[0..15] KSI3/GPIO33 EC_MUTE#/GPIO4A EC_MUTE# <39>
KSI4 59 84
KSI[0..7] KSI4/GPIO34 USB_EN#/GPIO4B USB_EN# <34>
KSI5 60 85
<33> KSI[0..7] 61 KSI5/GPIO35 CAP_INT#/GPIO4C 86 PTC_PROTECT <44>
KSI6 PS2 Interface
KSI6/GPIO36 EAPD/GPIO4D CMOS_ON# <27>
KSI7 62 87 TP_CLK R199 1 @ 2 4.7K_0402_5%

+3VALW_EC ESD KSO0

KSO1
KSO2
39
40
41
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
TP_CLK/GPIO4E
TP_DATA/GPIO4F
88 TP_DATA
TP_CLK <33>
TP_DATA <33>
TP_CLK R260 1 2 4.7K_0402_5%

R201 KSO3 42 KSO2/GPIO22 97 R200 1 @ 2 4.7K_0402_5%

KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 TS_DISABLE# <27>
1 2 EC_SMB_CK1 KSO4 43 98
44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 HDD_DETECT# <30>
2.2K_0402_5% KSO5 TP_DATA R261 1 2 4.7K_0402_5%
R202 KSO6 45 KSO5/GPIO25 Int. K/B HDA_SDO/GPXIOA02 109
ME_EN <7>
1 2 EC_SMB_DA1 KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 VCIN0_PH1 <44>
KSO7/GPIO27 SPI Device Interface
2.2K_0402_5% KSO8 47
KSO9 48 KSO8/GPIO28 119 VCIN1_BATT_TEMP 1 2
49 KSO9/GPIO29 SPIDI/GPIO5B 120 EC_SPI_MISO <8>
KSO10 C189 100P_0402_50V8J
KSO10/GPIO2A SPIDO/GPIO5C EC_SPI_MOSI <8>
KSO11 50 SPI Flash ROM 126 VCIN1_AC_IN 1 2
KSO11/GPIO2B SPICLK/GPIO58 EC_SPI_CLK <8>
KSO12 51 128 C190 100P_0402_50V8J
52 KSO12/GPIO2C SPICS#/GPIO5A EC_SPI_CS0# <8> 1 2
KSO13
KSO14 53 KSO13/GPIO2D R203 @ 4.7K_0402_5%
KSO15 54 KSO14/GPIO2E 73
KSO15/GPIO2F ENBKL/GPIO40 GS_VOUTX <36>
KSO16 81 74
<33> KSO16 KSO16/GPIO48 PECI_KB930/GPIO41 SYS_PWROK <9>
KSO17 82 89
<33> KSO17 KSO17/GPIO49 FSTCHG/GPIO50 90 WLAN_PWR_ON# <31>
BATT_CHG_LED#/GPIO52 BATT_CHG_LED# <33>
91 R215 1 @ 2 0_0402_5% Reserve for +3VGS
77 CAPS_LED#/GPIO53 92 CAPS_LED# <33> GPU_3VGS_PWR_EN <20>
EC_SMB_CK1 GPIO
<44,45> EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 PWR_LED# <33>
EC_SMB_DA1 78 93
<44,45> EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_LOW_LED# <33>
EC_SMB_CK2 79 SM Bus 95 SYSON
<19,32,8> EC_SMB_CK2 80 EC_SMB_CK2/GPIO46 SYSON/GPIO56 121 SYSON <42,47> DS3
EC_SMB_DA2 PM_SLP_S4#_R
<19,32,8> EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 127
PM_SLP_S4#/GPIO59 DPWROK_EC <9>

6 100
<9> PM_SLP_S3# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 EC_RSMRST# <9>
DS3 <34> USB_CHG_CTL1
15 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 102
GS_SELFTEST <36>
R216 1 @ 2 0_0402_5%
<46> 3V/5VALW_PG 16 EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 103 VCIN1_ADP_PROCHOT <44> GPU_1.8VGS_PWR_EN <20,48> Reserve for +1.8VGS & +0.95VGS
<9> SUSWARN# GPIO0A H_PROCHOT#_EC/GPXIOA06 VCOUT1_PROCHOT# <44>
17 104
<9> SLP_SUS# GPIO0B VCOUT0_PH/GPXIOA07 VCOUT0_MAIN_PWR_ON <46>
18 GPO 105 BKOFF#
<34> USB_CHG_EN# 19 GPIO0C BKOFF#/GPXIOA08 106 BKOFF# <27> DS3
<33,9> AC_PRESENT GPIO0D GPIO PBTN_OUT#/GPXIOA09 BATT_LEN# <44>
25 107
<34> USB_CHG_CTL2 28 EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 108 PCH_PWR_EN <42>
<32> FAN_SPEED1 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 1.05V_VS_PG_PWR <50>
29
<44> ADP_65 EC_PME#/GPIO15
EC_TX 30
<31,33> EC_TX 31 EC_TX/GPIO16 110
EC_RX
<31,33> EC_RX EC_RX/GPIO17 AC_IN/GPXIOD01 VCIN1_AC_IN <19,33,45>
PCH_PWROK 32 112 EC_ON
<9> PCH_PWROK 34 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 114 EC_ON <46>
NOVO# ON/OFF# <33,36> VCOUT1_PROCHOT# R204 1 2 0_0402_5%
<34> NOVO# SUSP_LED#/GPIO19 ON/OFF/GPXIOD03
36 GPI 115 LID_SW#
<33> NUM_LED# NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# <33>
1 R207 2 116 SUSP#
SUSP#/GPXIOD05 117 SUSP# <42,47,49,50>
10K_0402_5% NUVOTON_VTT R205 1 2 0_0402_5% H_PROCHOT# <5>
GPXIOD06 <52> VR_HOT#
118 PECI 1 2
PECI_KB9012/GPXIOD07 H_PECI <5>
AGND/AGND

122 R208 43_0402_1%

<9> PBTN_OUT# XCLKI/GPIO5D

1
123 124 +V18R R209 1 @ 2 0_0402_5% D
Share ROM
GND/GND
GND/GND
GND/GND
GND/GND

<31,38> PCIE_LAN_WAKE# XCLKO/GPIO5E V18R +3VALW_EC

VCOUT1_PROCHOT# 2
C192
1 1
4.7U_0603_6.3V6K
GND0

G @
Q13 S C191

3
2N7002H_SOT23-3 47P_0402_50V8J
SA000079Y00 2 9012@ 2
11
24
35
94
113

69

S IC NPCE288NA0DX LQFP 128P KBC

+3VALW NPCE288NA0DX LQFP 128P KBC_14X14
ESD +3VALW
ECAGND

SYSON

1 2 PCIE_LAN_WAKE# LID_SW# 1 R206 2

C193
.1U_0402_16V7K
R212 10K_0402_5% @ESD@ 100K_0402_5%
1
1 2 HDD_DETECT#
ESD R281 100K_0402_5%
2 +1.05VS
1
C197 R269 2 1 0_0402_5%
.1U_0402_16V7K NUVOTON_VTT R210 1 2 0_0402_5%
2

+3VS

@
5

U14
2
P

<9> PM_SLP_S4# B 4 PM_SLP_S4#_R

1 Y
<9> PM_SLP_S5# A
G
3

+3VS
U74AHC1G08G-AL5-R_SOT353-5

1 2 FAN_SPEED1
R214 10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS & EC I/O Port
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B091P
Date: Wednesday, February 12, 2014 Sheet 35 of 55
 1 2 3 4 5

To Docking BD

+USB_VCCB

+3VS
A A
+3VLP
JDOCK1
1
1 2 D1-_Docking
2 3 D1+_Docking D1-_Docking <37>
3 4 D1+_Docking <37>
4 5 D0-_Docking
5 6 D0+_Docking D0-_Docking <37>
6 7 D0+_Docking <37>
7 8
8 9
9 10 USB3_TX3_N <11>
10 11 USB3_TX3_P <11>
11 12
12 USB3_RX3_N <11>
13
13 14 USB3_RX3_P <11>
14 15
15 16
16 17 Docking_DP_HPD
17 Docking_DP_HPD <37>
18
18 19
19 20 DC_LED <33>
20 21
21 AUXp_Docking <37>
22
22 AUXn_Docking <37>
23
23 24 Docking_Consumption <45>
24 ON/OFF# <33,35>
25 Docking_PRSNT#_R Docking@ 2 R227 1 1_0402_5%
31 25 26 Docking_PRSNT# <10,37>
32 G1 26 27
33 G2 27 28
34 G3 28 29
G4 29 USB20_P3_D <11>
35 30
G5 30 USB20_N3_D <11>
ACES_50406-03071-001
ME@
SP010015L00
B B

APS (G-Sensor)
C C
1

RS1
100K_0402_5%
GS@
US1 GS@
2

2 12 VOUTX RS2 1 GS@ 2 56K_0402_5%

<35> GS_SELFTEST ST Xout GS_VOUTX <35>
10 VOUTY RS3 1 GS@ 2 56K_0402_5%
+3VS +3VS_GS Yout 8 GS_VOUTY <35>
RS4 Zout
1 2 14
Vs
CS3

.1U_0402_16V7K

CS4

.1U_0402_16V7K

CS5

.1U_0402_16V7K

CS6

.1U_0402_16V7K
15
Vs
CS1

10U_0603_6.3V6M

CS2

.1U_0402_16V7K

0_0603_5% 1 1 1 1
GS@ GS@ 1 1 GS@ 1 GS@ GS@ GS@ GS@
NC 4
3 NC 9
5 COM NC 11 2 2 2 2
2 2 6 COM NC 13
7 COM NC 16
COM NC
APS_GND
LIS34ALTR_LGA16_4X4

APS_GND @ J3
1 2

2MM

APS_GND

D D

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2011/06/24 Deciphered Date 2012/07/12
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Docking
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B091P
Wednesday, February 12, 2014 Sheet 36 of 55
1 2 3 4 5
 5 4 3 2 1

+3VS +3VS_DP +3VS_DP

JP4
1 2
1 2
D 1 CD1 1 CD2 1 CD3 1 CD4 D

.1U_0402_16V7K
Docking@

0.01U_0402_16V7K
Docking@

.1U_0402_16V7K
Docking@

0.01U_0402_16V7K
Docking@
JUMP_43X39
@
2 2 2 2

Pin14 Pin28 Pin41 Pin56

DP_Switching Function (For Automatic Switching)
+3VS_DP +3VS_DP
H TMDS output has higher priority UD1
14 40
＊ L DP output has higher priority VDD33 DP_D0p D0+_Docking <36>

2
+3VS_DP RD3 1 @ 2 0_0402_5% 28 39
<10,36> Docking_PRSNT# VDD33 DP_D0n D0-_Docking <36>
<10,9> PCH_GPIO68 RD21 1 @ 2 0_0402_5% @ 41
RD2 56 VDD33 37
VDD33 DP_D1p D1+_Docking <36>
2

4.7K_0402_5% 36 D1-_Docking <36>

@ DP_CFG0 44 DP_D1n

1
RD14 DP_Switching 45 DP_CFG0/SCL_CTL 34
4.7K_0402_5%
TMDS_PRE Function I2C_CTL_EN 38 SW/SDA_CTL DP_D2p 33
To DP
I2C_CTL_EN DP_D2n For Docking
H DDC active buffer
1

2
TMDS_DDCBUF <5> CPU_DP2_P0 CD6 1 2 .1U_0402_16V7K Docking@ CPU_DP2_P0_C 3 31
Docking@ Docking@ CD7 1 2 .1U_0402_16V7K Docking@ CPU_DP2_N0_C 4 IN_D0p DP_D3p 30
M DDC pass through with 40 kohm pull up resistor <5> CPU_DP2_N0 IN_D0n DP_D3n
2

RD1 RD4
Docking@ L DDC pass through 4.7K_0402_5% 4.7K_0402_5% <5> CPU_DP2_P1 CD5 1 2 .1U_0402_16V7K Docking@ CPU_DP2_P1_C 6 55
1 2 7 IN_D1p DP_AUXp_SCL 54 AUXp_Docking <36>
RD17 <5> CPU_DP2_N1 CD8 .1U_0402_16V7K Docking@ CPU_DP2_N1_C
AUXn_Docking <36>

1
4.7K_0402_5% IN_D1n DP_AUXn_SDA 32
DP_HPD Docking_DP_HPD <36>
<5> CPU_DP2_P2 CD9 1 2 .1U_0402_16V7K Docking@ CPU_DP2_P2_C 9
1

CD10 1 2 .1U_0402_16V7K Docking@ CPU_DP2_N2_C 10 IN_D2p

<5> CPU_DP2_N2 IN_D2n 42 RD20 1Docking@ 2 1M_0402_5%
CD11 1 2 .1U_0402_16V7K Docking@ CPU_DP2_P3_C 12 DP_CA_DET
<5> CPU_DP2_P3 IN_D3p
From CPU <5> CPU_DP2_N3 CD12 1 2 .1U_0402_16V7K Docking@ CPU_DP2_N3_C 13 29 DP_CFG1
+3VS_DP IN_D3n DP_CFG1
CD13 1 2 .1U_0402_16V7K Docking@ DDI2_AUX_DP_C 52 19
HDMI_TX0+_CK <28>
<9> DDI2_AUX_DP IN_AUXp TMDS_CH0p
C CD14 1 2 .1U_0402_16V7K Docking@ DDI2_AUX_DN_C 51 18 HDMI_TX0-_CK <28> C
<9> DDI2_AUX_DN IN_AUXn TMDS_CH0n
2

@ 50 22 HDMI_TX1+_CK <28>
<28,9> HDMICLK_NB IN_DDC_SCL TMDS_CH1p
RD15 49 21
<28,9> HDMIDAT_NB IN_DDC_SDA TMDS_CH1n HDMI_TX1-_CK <28>
4.7K_0402_5% TMDS_RT Function 11 25 HDMI_TX2+_CK <28>
1

TMDS_RT IN_CA_DET TMDS_CH2p 24

H Open drain driver with termination resistors 5 TMDS_CH2n HDMI_TX2-_CK <28> To HDMI
<28,9> TMDS_B_HPD IN_HPD
2

16
@
L Standard open drain driver TMDS_CLKp 15
HDMI_CLK+_CK <28>
TMDS_CLKn HDMI_CLK-_CK <28>
RD18
4.7K_0402_5% 1 48
CEXT TMDS_SCL HDMICLK_R <28>

2.2U_0402_6.3V6M
CD15
Docking@
1 47
HDMIDAT_R <28>
1

TMDS_DDCBUF 2 TMDS_SDA
TMDS_DDCBUF 17
TMDS_HPD HDMI_DET <28>
DPSW_PEQ 8
2 PEQ 23 TMDS_RT
+3VS_DP 27 TMDS_RT 20 TMDS_PRE
REXT TMDS_PRE

4.42K_0402_1%
RD5
Docking@
1
46 26
PD GND
2

RD6 35
Docking@ 2 1 DP_MODE 53 GND 43
+3VS_DP MODE GND
RD16 TMDS_PRE Function 57
Thermal/GND

2
4.7K_0402_5%
RD7
Docking@
4.7K_0402_5% 4.7K_0402_5%

2
H 1.5dB pre-emphasis Docking@ PS8339BQFN56GTR2-A0_QFN56_7X7
1

TMDS_PRE Docking@
M 3.0dB pre-emphasis
2

1
@ L no pre-emphasis
RD19
4.7K_0402_5%
DP_MODE Function
1

H Automatic Switching Mode, HDMI ID disable

+3VS_DP ＊M (VDD33/2) Automatic Switching Mode, HDMI ID enable
B L Control Switching Mode, HDMI ID disable B
2

@
RD10 DPSW_PEQ Function
4.7K_0402_5%
H HEQ, compensate channel loss up to 15dB @ HBR2
1

DPSW_PEQ For NoDocking For NoDocking

M LLEQ, compensate channel loss up to 5dB @ HBR2
2

Near UD1.3, 4, 6, 7, 9, 10, 12, 13 Near UD1.15, 16, 18, 19, 21, 22, 24, 25
@ L default, LEQ, compensate channel loss up to 12dB @ HBR2 RP31 RP37
RD13 CPU_DP2_N1 1 8 CPU_DP2_N1_R 1 8 HDMI_TX1-_CK
4.7K_0402_5% CPU_DP2_P1 2 7 CPU_DP2_P1_R 2 7 HDMI_TX1+_CK
CPU_DP2_N0 3 6 CPU_DP2_N0_R 3 6 HDMI_TX2-_CK
1

CPU_DP2_P0 4 5 CPU_DP2_P0_R 4 5 HDMI_TX2+_CK

0_0804_8P4R_5% 0_0804_8P4R_5%
From CPU NoDocking@ NoDocking@
+3VS_DP
RP32 RP38
CPU_DP2_N3 1 8 CPU_DP2_N3_R 1 8 HDMI_CLK-_CK
2

CPU_DP2_P3 2 7 CPU_DP2_P3_R 2 7 HDMI_CLK+_CK

@ CPU_DP2_N2 3 6 CPU_DP2_N2_R 3 6 HDMI_TX0-_CK
RD8 DP_CFG0 Function CPU_DP2_P2 4 5 CPU_DP2_P2_R 4 5 HDMI_TX0+_CK
4.7K_0402_5%
H automatic EQ disable & AUX interception enable 0_0804_8P4R_5% 0_0804_8P4R_5%
1

DP_CFG0 NoDocking@ NoDocking@

M automatic EQ disable & AUX interception disable, no pre-emphasis, 800mVpp swing
2

@ L default, automatic EQ enable & AUX interception enable

RD11
4.7K_0402_5%
1

+3VS_DP
A A
2

@
RD9 DP_CFG1 Function
4.7K_0402_5%
H auto test enable & input offset cancellation enable
1

DP_CFG1
M auto test disable & input offset cancellation disable
2

@ L default, auto test disable & input offset cancellation enable

RD12
Security Classification Compal Secret Data Compal Electronics, Inc.
4.7K_0402_5% 2011/06/24 2012/07/12 Title
Issued Date Deciphered Date
HDMI CONN
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B091P
Date: Wednesday, February 12, 2014 Sheet 37 of 55
5 4 3 2 1
 5 4 3 2 1

+3VALW +3V_LAN
RL11
RL18 1 2 0_0603_5% 1 2
0_0603_5%
60mil W=60mil 8111GLDO@
+LAN_VDD
LL1
W=60mils
2 +LAN_SROUT1.05 1 2
2.2UH +-5% NLC252018T-2R2J-N

.1U_0402_16V7K
CL1 1 SWITCH@

4.7U_0603_6.3V6K
1U_0402_6.3V6K 1 1
1 CL15 CL16
.1U_0402_16V7K CL17
8111GLDO@ 2 SWITCH@ SWITCH@
D 2 2 D

LL1, CL16, and CL17 close to Pin24

( Should be place within 200 mils )

RJ-45 CONN.
+3V_LAN JLAN1
+LAN_VDD LED0 1 2 12
RL15 510_0402_5% Yellow LED-
要>1mS and <100mS
Rising Ame (10%~90%)要 W=40mils
+3V_LAN RL1 11

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
1 2+LAN_VDDREG Yellow LED+
+3V_LAN W=60mils 1 1 1 1 1 RJ45_TX3- 8

.1U_0402_16V7K

1U_0402_6.3V6K
4.7U_0603_6.3V6K
0_0603_5% PR4-
1 1
RJ45_TX3+ 7

CL8
CL9 CL10 CL4 CL5 CL6 CL7
.1U_0402_16V7K

PR4+

SWITCH@
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

2 2 2 2 2 RJ45_RX1- 6
1 1 1 1
.1U_0402_16V7K

@ @ 2 2 PR2-
CL2 CL3 CL20 CL21 RJ45_TX2- 5
PR3-
2 2 2 2 RJ45_TX2+ 4
PR3+
Pin3 Pin8 Pin22 Pin30 Pin22 RJ45_RX1+ 3
PR2+
C Close to Pin23 RJ45_TX0- 2
C

PR1- 13
RJ45_TX0+ 1 SHLD2 14
+3V_LAN PR1+ SHLD1
LED2 1 2 10
RL16 510_0402_5% Green LED-
CL2 close to Pin 11, only 8106E LDO mode unpop 9
CL3 close to Pin 32 Green LED+
SANTA_130452-0P
ME@
DC234007O00
LANGAN1 LANGAN

+LAN_VDD +LAN_VDD

+3VS
1 2
PCIE_PRX_DTX_P3 <11>
LAN_MDIP0 1 17 PCIE_PRX_DTX_P3_C CL11 .1U_0402_16V7K
MDIP0 HSOP

1
LAN_MDIN0 2 18 PCIE_PRX_DTX_N3_C 1 2 PCIE_PRX_DTX_N3 <11>
3 MDIN0 HSON 19 PLT_RST_BUF# CL12 .1U_0402_16V7K RL8
LAN_MDIP1 4 AVDD10 PERSTB 20 ISOLATE# PLT_RST# <18,31,35,40,9> 1K_0402_5%
LAN_MDIN1 5 MDIP1 ISOLATEB 21 PCIE_LAN_WAKE#
LAN_MDIP2 6 MDIN1 LANWAKEB 22 PCIE_LAN_WAKE# <31,35>

EMI

2
LAN_MDIN2 7 MDIP2 DVDD10 23 +LAN_VDDREG ISOLATE#
8 MDIN2 VDDREG 24 +LAN_SROUT1.05 +3V_LAN
LAN_MDIP3 9 AVDD10 REGOUT 25 LED2 TPL1
RL4 1 2 0.1U_0402_25V6K LAN_MDIN3 10 MDIP3 LED2 26 LED1_GPIO 1 @ 2
11 MDIN3 LED1/GPIO 27 LED0 RL17 10K_0402_5% RL10
+3V_LAN AVDD33 LED0
RL5 1 2 0.1U_0402_25V6K 12 28 XTLO TPL2 15K_0402_5%
<8> LANCLK_REQ# 13 CLKREQB CKXTAL1 29 XTLI
<11> PCIE_PTX_C_DRX_P3 14 HSIP CKXTAL2 30 reserved GPIO pin
<11> PCIE_PTX_C_DRX_N3 15 HSIN AVDD10 31 2.49K_0402_1% 2 1 RL9
LANGAN <8> CLK_PCIE_LAN 16 REFCLK_P RSET 32
<8> CLK_PCIE_LAN# REFCLK_N AVDD33 +3V_LAN
33
GND
@EMI@ RL6 1 2 0.1U_0402_25V6K UL2
B B
SA000065Y00
@EMI@ RL7 1 2 0.1U_0402_25V6K S IC RTL8106E-CG QFN 32P E-LAN CTRL
8106ELDO@

UL2 UL2 RTL8111GS-CG_QFN32_4X4

LANGAN1 SA00006N910 SA00005O700
S IC RTL8106EUL-CG QFN 32P E-LAN CTRL S IC RTL8111GS-CG QFN 32P E-LAN CTRL
8106ESW@

UL2
8111GLDO@

+V_DAC 1
TL1
24 MCT
EMI
SA00006ML10 TCT1 MCT1 RL19 CL19

CL13
S IC RTL8111GUL-CG QFN 32P E-LAN CTRL
8111GSW@ EMI LAN_MDIP3

LAN_MDIN3
2

3
TD1+ MX1+
23

22
RJ45_TX3+

RJ45_TX3-
1

75_0805_5%
2 1 2

10P_0603_50V
1 2 XTLO CL18 TD1- MX1-

10P_0402_50V8J
NOGCLK@
EMI 0.01U_0402_16V7K
1 2 +V_DAC

LAN_MDIP2
4

5
TCT2 MCT2
21

20 RJ45_TX2+
LANGAN
TD2 MX2+
1

@
YL1 DL1 LAN_MDIN2 6 19 RJ45_TX2-
OSC

NC

25MHZ_10PF_7V25000014 LAN_MDIN3 1 4 LAN_MDIP2 TD2- MX2-

NOGCLK@ I/O1 I/O3 +V_DAC 7 18 2 1
SJ10000E800 TCT3 MCT3
OSC

LAN_MDIP1 8 17 RJ45_RX1+ DL3

NC

2 5 TD3+ MX3+ BS4200N-C-LV_SMB-F2

GND VDD LAN_MDIN1 9 16 RJ45_RX1-
2

TD3- MX3-
CL14
+V_DAC 10 15
1 2

10P_0402_50V8J
XTLI LAN_MDIP3 3
I/O2
AZC099-04S.R7G_SOT23-6
I/O4
6 LAN_MDIN2
LAN_MDIP0 11
TCT4

TD4+
MCT4

MX4+
14 RJ45_TX0+ EMI
NOGCLK@
DL1 Only For GIGA SC300001G00 LAN_MDIN0 12 13 RJ45_TX0-
TD4- MX4-
GCLK
@ NS892407
RG6 1 GCLK@ 2 0_0402_5% XTLI DL2 TL1 GIGA@
<41> LAN_XTLI_GCLK 1 4
LAN_MDIN1 LAN_MDIP0 S0 X'FORM_ HH-065 10/100
I/O1 I/O3 100@
A A

FOR 10/100 data transferring 2013/08/27

2 5
GND VDD

LAN_MDIP1 3 6 LAN_MDIN0
I/O2 I/O4
AZC099-04S.R7G_SOT23-6
SC300001G00
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN RTL8411-CG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B091P
Date: Wednesday, February 12, 2014 Sheet 38 of 55
5 4 3 2 1
 A B C D E

+3VS +3VDD_CODEC +IOVDD_CODEC +3V_PCH

RA2 RA3
1 2 1 2

.1U_0402_16V7K

1U_0402_6.3V6K

.1U_0402_16V7K
0_0603_5% 1 1 0_0603_5%

1
CA4

CA5

CA6
+5VS

2
2 2
RA1 1 2 0_0805_5% +5VS_PVDD
Place near Pin1 Place near Pin9

.1U_0402_16V7K

.1U_0402_16V7K
4.7U_0603_6.3V6K
2 1 1
+5VDDA_CODEC +5VS

CA2

CA3
CA1
1 1 2 2 1
RA4
+IOVDD_CODEC 1 2

+1.5VS 0_0603_5%

.1U_0402_16V7K

1U_0402_6.3V6K
+3VDD_CODEC
1 2 0_0402_5%
1 1 Place RA41 on AGND/DGND moat

CA7
RA5

CA11
CA8 1 2 1U_0402_6.3V6K 2 2

Place near Pin40 +3VLP

Place near Pin26

41

46

26

40
1

9
UA1

PVDD1

PVDD2

AVDD1

AVDD2
DVDD

DVDD-IO
EXT_MIC_SLEEVE

1
233@
RA9
LINE1-L 22 100K_0402_5%
LINE1-L(PORT-C-L)

3
LINE1-R 21 43 SPK_L1-
LINE1-R(PORT-C-R) SPK-OUT-L- 42 SPK_L2+
wide 40MIL

2
24 SPK-OUT-L+
23 LINE2-L(PORT-E-L) 45 SPK_R2+ 5 233@
RA6 LINE2-R(PORT-E-R) SPK-OUT-R+ 44 SPK_R1- QA1B
SPK-OUT-R-

6
1 2 2.2K_0402_5% EXT_MIC_RING2 17 DMN65D8LDW-7 2N SOT363-6
+MIC2-VREFO

4
1 2 2.2K_0402_5% EXT_MIC_SLEEVE 18 MIC2-L(PORT-F-L) /RING2
RA7 MIC2-R(PORT-F-R) /SLEEVE 32 HP_OUTL 233@
31 HPOUT-L(PORT-I-L) 33 HP_OUTR HDA_RST_AUDIO# RA14 1 2 2 233@
+LINE1-VREFO-R
30 LINE1-VREFO-L HPOUT-R(PORT-I-R) Headphone 10K_0402_5% QA1A
EMI LINE1-VREFO-R 10
HDA_SYNC_AUDIO <7>
EMI KABINI need to use this part DMN65D8LDW-7 2N SOT363-6

1
2 SYNC 6
<27> DMIC_DAT LA1 1 2 BLM15BB221SN1D_2P DMIC_CLK_R 3 GPIO0/DMIC-DATA BCLK HDA_BITCLK_AUDIO <7> Due to RST is 1.5V power rail
External DMIC <27> DMIC_CLK RA8 1 @ 2 10K_0402_5% GPIO1/DMIC-CLK RA101 @EMI@ 2 33_0402_5% @EMI@ CA12 22P_0402_50V8J Intel project can use dual 2N7002

RA11 1 2 0_0402_5% 47 5
<35> EC_MUTE#
<7> HDA_RST_AUDIO# 11 PDB
RESETB
ALC233-CG SDATA-OUT
SDATA-IN
8 HDA_SDIN0_AUDIO RA12 1 2 33_0402_5%
HDA_SDOUT_AUDIO
HDA_SDIN0 <7>
<7>
For ALC233VB only
+3VS
48
SPDIF-OUT/GPIO2 +MIC2-VREFO
2 PC_BEEP 12 2
PCBEEP

2
16
PLUG_IN_R 13 MONO-OUT CA13 2 1 2.2U_0402_6.3V6M 233VB@
14 SENSE A RA38

37
SENSE B
MIC2-VREFO
29 CA14 2 1 2.2U_0402_6.3V6M 100K_0402_5% Combo Jack

1
CBP
CA15 2 1 1U_0402_6.3V6K 35
CBN LDO3-CAP
LDO2-CAP
7
39
LDO3
LDO2
CA16 2 1 2.2U_0402_6.3V6M RA39 1 2 0_0402_5%
(Normal Open)
27 LDO1 2 1
@ 36 LDO1-CAP RA15 100K_0402_5% PLUG_IN_R RA13 1 233@ 2 39.2K_0402_1% PLUG_IN
+3VDD_CODEC CPVDD PLUG_IN <34>
CA17 2 1 4.7U_0603_6.3V6K RA13

+3VLP 233VB@ RA161 2 100K_0402_5% 20

CPVREF
VREF
28

15
CA18 1 2 1U_0402_6.3V6K 200K_0402_5%
233VB@ EMI
JDREF RA17 1 233@ 2 20K_0402_1% W=40mils EXT_MIC_SLEEVE RA19 2 1 FCM1608CF-121T03 0603 HGNDB
JDREF HGNDB <34>
CA19 2 1 2.2U_0402_6.3V6M 19 34 CPVEE W=40mils EXT_MIC_RING2 RA20 2 1 FCM1608CF-121T03 0603 HGNDA
MIC-CAP CPVEE HGNDA <34>
HP_OUTL RA22 1 2 47_0402_5% HPOUT_L
HPOUT_L <34>
2 HP_OUTR RA23 1 2 47_0402_5% HPOUT_R
HPOUT_R <34>
RA18 1 @ 2 0_0402_5% 4
49 DVSS 25 CA20
Thermal PAD AVSS1 38
RA18 pop on ALC283, NC on ALC233 AVSS2 1
1U_0402_6.3V6K For Universal Audio Jack
ALC233-CG_MQFN48_6X6 LINE1-L CA21 2 1 1U_0402_6.3V6K

2
233@

RA26

RA27
220P_0402_50V7K

220P_0402_50V7K
LINE1-R CA22 2 1 1U_0402_6.3V6K
UA1

1
ALC233-VB2-CG MQFN 48P
233VB@ RA29 1 2 4.7K_0402_5%
EMI
+LINE1-VREFO-R
RA21 1 2 0_0402_5%
RA32 1 2
4.7K_0402_5%
RA24 1 2 0_0402_5%

RA25 1 2 0_0402_5%
3 3

RA28 1 @EMI@ 2 0_0402_5%

GND GNDA
11/20 Change symbol of JSPK1 to SP02000H700

EMI
wide 40MIL JSPK1
SPK_R1- @EMI@ LA5 1 2 FCM1608CF-121T03 0603 SPK_R1-_CONN 1
SPK_R2+ @EMI@ LA6 1 2 FCM1608CF-121T03 0603 SPK_R2+_CONN 2 1

PC Beep SPK_L1-
SPK_L2+
@EMI@
@EMI@
LA7
LA8
1
1
2
2
FCM1608CF-121T03 0603
FCM1608CF-121T03 0603
SPK_L1-_CONN
SPK_L2+_CONN
3
4
2
3
4
5
6 G5

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K
LA5 LA6 G6
0_0603_5% 0_0603_5% 1 1 1 1
ESD ACES_85205-04001
ME@

CA28

CA29

CA30

CA31
CA23 1 2 .1U_0402_16V7K CA25 +5VS SP020008X00
EC Beep <35> BEEP#
1 RA34 2 1 2 PC_BEEP
CA24 1 2 .1U_0402_16V7K LA7 LA8 2 2 2 2
PCH Beep <10> HDA_SPKR
1K_0402_5% .1U_0402_16V7K 0_0603_5% 0_0603_5% @ESD@ DA3
SPK_R1-_CONN 6 3 SPK_L2+_CONN
I/O4 I/O2
1

@
RA36 5 2
10K_0402_5% VDD GND
4 4
2

SPK_R2+_CONN 4 1 SPK_L1-_CONN
I/O3 I/O1
AZC099-04S.R7G_SOT23-6

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec_ALC3225
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B091P
Date: Wednesday, February 12, 2014 Sheet 39 of 55
A B C D E
 5 4 3 2 1

D D

+AV12 +DV12S

+3VS
1 1 1 1
CC1 CC2 CC3 CC4
CC5 1 2 4.7U_0603_6.3V6K
2 2 2 2

.1U_0402_16V7K

.1U_0402_16V7K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
CC6 1 2 .1U_0402_16V7K UCR1
9
+DV33_18 15 3V3_IN
+AV12 7 DV33_18
+Card_3V3 +DV12S 11 AV12
DV12_S
+Card_3V3 LC1 1 2 0_0603_5% +Card_3V3_R 10
Card_3V3 25
1 2 8 GND
RC1 6.2K_0402_1% RREF Close to UCR1
<11> PCIE_PTX_C_DRX_P2
1
2 HSIP SP1
12
13
RC2

RC3 1
1 2 0_0402_5%

2 0_0402_5%
SD_D1

SD_D0
EMI
<11> PCIE_PTX_C_DRX_N2 HSIN SP2
CC7 1 2 .1U_0402_16V7K PCIE_PRX_DTX_P2_C 5 14 SD_CLK_R RC9 1 2 33_0402_5% SD_CLK
<11> PCIE_PRX_DTX_P2 1 2 .1U_0402_16V7K 6 HSOP SP3 16
CC8 PCIE_PRX_DTX_N2_C RC5 1 2 0_0402_5% SD_CMD
<11> PCIE_PRX_DTX_N2 HSON SP4
C 17 RC6 1 2 0_0402_5% SD_D3 C
SP5 18 RC7 1 2 0_0402_5% SD_D2
SP6 1
<8> CLK_PCIE_CR 3 @EMI@
4 REFCLKP CC13
<8> CLK_PCIE_CR# REFCLKN
+DV33_18 5.6P 50V D NPO 0402
23 20 SD_WP 2
<18,31,35,38,9> PLT_RST# PERST# SD_WP
2 24 21 SD_CD#
EMI
1U_0402_6.3V6K

<8> CRCLK_REQ# CLK_REQ# SD_CD#

CC10
2 1 SD_GPIO1 19 22
+3VS GPIO MS_INS#
RC8 10K_0402_5%
1 RTS5229-GR_QFN24_4X4

+Card_3V3
JSD1
SD_D0 7 4
D0 VDD
B B
SD_D1 8
D1
SD_D2 9 10 SD_WP CC11 1 1

.1U_0402_16V7K
D2 WP CC12

4.7U_0603_6.3V6K
SD_D3 1 11 SD_CD#
D3 CD
3 2 2
SD_CLK 5 VSS1 6
CLK VSS2 12
SD_CMD 2 Shading 13
CMD Shading
TAITW_PSDBTC-09GLBS1N14H0
ME@
SP07000LN00

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P24-CardRead/RTS5229
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B091P
Date: Wednesday, February 12, 2014 Sheet 40 of 55
5 4 3 2 1
 5 4 3 2 1

D D

+CHGRTC_R

1
UG1
RG1
330_0402_5%
GCLK@

2
SLG3NB3375VTR TQFN 16P
GCLKUMA@
C 1 SA00006RE00 1 C
CG5 CG11
22U_0603_6.3V6M 2.2U_0402_6.3V6M
GCLK@ GCLK@
2 UG1 2

GCLK_VRTC 10 14 RTC_VOUT
VRTC VOUT

+3VLP
15

2
V3.3A EMI
1 +3VALW VDD
CG4 9 CPU_RTCX1_GCLK_R RG4 1 GCLK@ 2 0_0402_5%
.1U_0402_16V7K 32.768kHz CPU_RTCX1_GCLK <7> CPU_32.768KHz
1
GCLK@ CG10
2 .1U_0402_16V7K 11 12 GPU_XTALIN_GCLK_R RG5 1GCLKDIS@ 2 22_0402_5%
+1.8VGS VIOE_27M 27M GPU_XTALIN_GCLK <19> GPU_27MHz only for DIS
GCLK@
2 8 6 LAN_XTLI_GCLK_R RG7 1 GCLK@ 2 33_0402_5%
1 +3V_LAN VIO_25M 25M LAN_XTLI_GCLK <38> LAN_25MHz
CG1
.1U_0402_16V7K 1 3 5 CPU_XTAL24_IN_GCLK_R RG8 1 GCLK@ 2 0_0402_5%
+1.05VS VIOE_24M 24M CPU_XTAL24_IN_GCLK <8> CPU_24MHz
GCLKDIS@ CG3
2 .1U_0402_16V7K CLK_X2 16
1 X2 1
GCLK@ CG2 CLK_X1 1 CG9
2 X1

GND1
GND2
GND3

GND4
.1U_0402_16V7K 5P_0402_50V8C CG9 no stuff any of component
GCLK@ @
2 2
SLG3NB3374VTR_TQFN16_2X3

4
7
13

17
GCLKDIS@ 1
SA00006RD00 CG8
5P_0402_50V8C CG8 just can use 4.7pF~33pF
GCLK@
2

1
CLK_X1 RG10 1
510_0402_5% CG7
YG1 CLK_X2 @ 5P_0402_50V8C
4 3 @ CG7 no stuff any of component

2
NC OSC 2
1 2
B OSC NC B

1 25MHZ_10PF_7V25000014 1
CL28 GCLK@ CL29
12P_0402_50V_NPO SJ10000E800 15P_0402_50V8J
GCLK@ GCLK@
2 2

A A

Security Classification
2011/06/24
Compal Secret Data
2012/07/12 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GCLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B091P
Date: Wednesday, February 12, 2014 Sheet 41 of 55

5 4 3 2 1
 A B C D E

+3VALW to +3VALW_PCH
+3VALW +5VALW
DS3 +3VALW +3V_PCH

.1U_0402_16V7K

10U_0603_6.3V6M
NODS3@
1 1 2 R219 1
+3VALW to +3VS

C205

C206
0_0603_5%
@ +3VS
U13 J4
2 2 1 14 +3VALW_3VS 2 1 R235 1 @ 2 470_0603_5% 3 1
2 VIN1 VOUT1 13 2 1
VIN1 VOUT1 1 1

1
D

10U_0603_6.3V6M

.1U_0402_16V7K
JUMP_43X79 C208 DS3@ DS3@ DS3@

4.7U_0603_6.3V6K
C209
3 12 1 2 C207 1 1 2 SUSP 4.7U_0603_6.3V6K Q15
ON1 CT1

C211

C212
470P_0402_50V7K G LP2301ALT1G_SOT23-3
<35,47,49,50> SUSP#

2
1 2 2 1
4 11 @ S Q14 @

3
VBIAS GND 2N7002H_SOT23-3
+5VALW 5 10 1 2 C213 2 2
ON2 CT2 220P_0402_50V7K
6 9 +5VALW_5VS +5VALW
VIN2 VOUT2
.1U_0402_16V7K

10U_0603_6.3V6M

7 8 DS3@
VIN2 VOUT2
1 1
C214

C215

15 1 R221 2 PCH_PWR_EN#
@ GPAD +5VS
APE8990GN3B DFN 14P J5 47K_0402_5%
2 2 2 1
2 1 1 DS3@

1
D DS3@
+5VALW to +5VS C216

10U_0603_6.3V6M

.1U_0402_16V7K
JUMP_43X79 2 Q17
<35> PCH_PWR_EN .1U_0402_16V7K
1 1 G 2N7002K_SOT23-3
2

C217

C218
S

3
@
2 2

2 2

+5VALW +0.675VS +1.05VS

1
R230 R228 R229
@ @ @
100K_0402_5% 470_0402_5% 470_0402_5%

2
SUSP

1
Q23 D Q21 D Q22 D
SUSP# 2 @ SUSP 2 @ SUSP 2 @
G G G
S S S

3
2N7002H_SOT23-3 2N7002H_SOT23-3 2N7002H_SOT23-3

3 3

+5VALW

2
@
R233
220K_0402_5% +1.35V

1
SYSON#

@ Q24 R234

1
DRC2124E0L NPN MINI3-G3-B 470_0603_5%
@

OUT

1 2
D
2 2 SYSON#
<35,47> SYSON IN G

GND
S Q25

3
2N7002H_SOT23-3

1
@

3
R239
100K_0402_5%

2
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B091P
Date: Wednesday, February 12, 2014 Sheet 42 of 55
A B C D E
 5 4 3 2 1

EMI@ PL101 ADP_ID

JDCIN1 PF101
HCB2012KF-121T50_0805
1 2
VIN AC Adapter 90W 65W
1 APDIN 7A_32VDC_0437007.WRML
1 2 1 2 APDIN1 R(K ohm) open 10
2 3 EMI@ PL102
3 4 HCB2012KF-121T50_0805 ADP_ID(V) 3.3 1.65
4

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
5 1 2
5 Detection voltage >2.64 1.32~1.98
ACES_88299-0510

1
EMI@ PC101

EMI@ PC102

EMI@ PC103

EMI@ PC104
CONN@

2
D D

@PR101
@ PR101
0_0402_5%
1 2
PQ101A
2N7002KDW-2N_SOT363-6

680P_0603_50V7K
1 2 6 1
+3VALW ADP_ID <35>

0.1U_0402_16V7K
PR102
750_0402_1% A/D

1
PC105

PC106
2
PR103

2
2N7002KDW-2N_SOT363-6
100K_0402_5%
1 2
VIN

3
1

PQ101B
PR104
5 ADP_ID_CLOSE <35>
100K_0402_5%

4
+CHGRTC
PR105
1K_0603_5%
1 2
PD101 +3VLP
S SCH DIO BAS40CW SOT-323
2 +CHGRTC_R
+RTCBATT 1 JBATT1
C 3 PR106 C
1K_0603_5%
1 2 1 2
+ -

LOTES_AAA-BAT-019-K01
CONN@

RTC Battery

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR DCIN / RTC Battery
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: Wednesday, February 12, 2014 Sheet 43 of 55
5 4 3 2 1
 5 4 3 2 1

Posestor +3VLP
EMI@ PL201
VMB2 VMB HCB2012KF-121T50_0805 PTC@ PTC@ PTC@ PTC@ PTC@ PTC@

1
CONN@ PF201 1 2 PR202 PR203 PR204 PR205 PR206 PR207

2
100K_0402_1%
PTC@ PR208
JBAT1 F1206HB12V024TM 12A 24V UL FAST 1 2 1 2 1 2 1 2 1 2 TMSNS21 2
VL
1 1 2 VL PR209 PTC@
1 2 BATT+
EMI@ PL202 1K_0402_50% 316K_0402_1% 100K_0402_1%
2 3 EC_SMCA HCB2012KF-121T50_0805 1K_0402_50% 1K_0402_50% 1K_0402_50% 1K_0402_50%

2
3 4 EC_SMDA 1 2 PTC@ PTC@ PTC@ PTC@ PTC@

1
4

1
5 PR234 PR225 PR230 PR229 PR233
5 6 PR210 PTC@ 1 2 1 2 1 2 1 2 1 2 MOS_OTP <46>
6

1
7 0_0402_5%
7

1
100_0402_1%

100_0402_1%
8 1K_0402_50%
GND 9 PC201 EMI@ PC202 EMI@ 1K_0402_50% 1K_0402_50% 1K_0402_50% 1K_0402_50%

2
D GND 1000P_0402_50V7K 0.01U_0402_25V7K D

2
PR201

PR211
ALLTO_C144PF-K07H9-L PU201 PTC@ PTC@ PQ202

2
PC203 PTC@ 1 8 TMSNS1 2N7002KW_SOT323-3
VCC TMSNS1

1
D
2 7 PTC_PROTECT2
0.1U_0603_25V7K GND RHYST1 G

1
OT1 3 6 TMSNS2 S

3
OT1 TMSNS2
EC_SMB_CK1 <35,45> <35> PTC_PROTECT 4 5
OT2 RHYST2
CONN@
EC_SMB_DA1 <35,45>
G718TM1U_SOT23-8
MOS_OTP:
1
JBAT3
2
1 2
+3VLP Default:High
PR212
3 1
3
2
4
4 16.49K_0402_1%
2
+3VALW
Active :Low
5 6 PR213
7 5 6 8 @ 6.49K_0402_1%
9 7 8 10 1 2
PTC_PROTECT:
11 9 10 12 PR214
VCIN1_BATT_TEMP <35,44> PH201 under CPU botten side : Default:Low
13 11 12 14 10K_0402_5%
15 13 14 16
A/D CPU thermal protection at 93 +-3 degree C Active :High
17 15 16 18
19 17 18 20 Recovery at 56 +-3 degree C 20120314
21 19 20 22 VL +5VALW
23 21 22 24 Change to +EC_VCCA from +3VLP
25 23 24 26
27 25 26 28
29 27 28 30
29 30
1

1
0_0402_5%

+EC_VCCA
PR224

31 32 PR231
GND GND <35,45> ADP_I
0_0402_5%

16.5K_0402_1%
@

1
@
2

10K_0402_1%
<35> VCOUT1_PROCHOT#

PR215
C C

2
30K_0402_1%
+3VALW

PR216

PR217

2
@ <35> VCIN0_PH1

1
2
VL PR218

1
<35> VCIN1_ADP_PROCHOT
PC204 PR219 100K_0402_1% PH201
1

2
100K +-1% 0402 B25/50 4250K

6 1
1

0.01U_0402_25V7K 100K_0402_1%
BATT_OUT <45>

75K_0402_1%
PR222 PR220 PR221
2

2
2

1
75K_0402_1% 47K_0402_1% 100K_0402_1%

PR223
PQ201A

1
2 2N7002KDW-2N_SOT363-6
2

PC205
1

2
8

<35,44> VCIN1_BATT_TEMP 0.068U_0402_16V7K

3 PQ201B
P

+ 1 1 2 5 2N7002KDW-2N_SOT363-6 ECAGND
2 O
1N4148WS-7-F_SOD323-2

-
G

2
PD201

PU202A
4
1

1
AS393MTR-E1 SO 8P OP D
4
2

2 PQ203
PR227 PR226 G 2N7002KW_SOT323-3
1

100K_0402_1% S
1

3
PC206 1.5M_0402_5%
2

100P_0402_50V8J
1

+3VLP
2

B B
PR228 <35> ADP_65
ECAGND
100K_0402_1%
1

D
2 PQ205
<35> BATT_LEN#
G 2N7002KW_SOT323-3
S
3

A A

135W: 150W(Turbo_V=1.2) active 135W(Turbo_V=1.072) recovery

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title
90W : 100W(Turbo_V=1.2) active 90W(Turbo_V=0.903) recovery PWR-BATTERY CONN/OTP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
65W : 70W(Turbo_V=1.2) active 65W(Turbo_V=0.918) recovery AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number
Custom
Rev
1.0
45W : 65W(Turbo_V=1.2) active 45W(Turbo_V=0.829) recovery DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: Wednesday, February 12, 2014 Sheet 44 of 55
5 4 3 2 1
 5 4 3 2 1
AO4407AL Vds=-30V AO4423L Vds=-30V
Rds_on=12.7~17mohm@Vgs=-6V Rds_on=9.4~12mohm@Vgs=-6V
P3
B+ Need EC write ChargeOption() bit[8]=0
ID = 10A (Ta=70C) P2 ID = 12.1A (Ta=70C)
Power Rating = 1W Isat: 4A
to disable iFault_Hi function.
PQ301 PQ302
AO4407AL_SO8 VACP~VACN spec < 80.64mV DCR: 27mohm
AO4455_SO8 AO4407AL Vds=-30V
8 1 1 8 PR302
VIN 7 2 2 7 0.01_1206_1% EMI@ PL301 CHG_B+ Rds_on=12.7~17mohm@Vgs=-6V
6 3 3 6 1UH +-30% 2.8A 4X4X2 FERRITE ID = 10A (Ta=70C)
5 5 1 4 1 2 PQ303
AO4407AL_SO8
PR328 2 3 1 8

4
SD028000080 2 7

2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
0.022U_0402_25V7K
S RES 1/16W 0 +-5% 0402 3 6

PC324

PC304

PC305

@EMI@ PC306

EMI@ PC307
PQ304 NoDock@ 5
D D
1 2
47K_0402_5%

PR329 @EMI@ PC303

1

1
10U_0805_25V6K

10_0402_1%

10_0402_1%
SD028000080

200K_0402_1%
0.1U_0603_25V7K

4
1
PR301

Dock@ PR328

Dock@ PR329
DRA5144E0L PNP SOT323-3 PC302 S RES 1/16W 0 +-5% 0402 DISCHG_G

PC301

PR303

@RF@
5600P_0402_25V7K NoDock@

2
PR304
ACDET Dock@ 200K_0402_1%
2

2
2 PR330 DOCKING_CONSUMPTION <36> 1 2

2
3 CELL: PR312 = 64.9k ACN 1 2 VIN

2ACOFF-1
10_0402_1%
Typ Worst

1
1

L => H 16.896V 17.065V ACP No support docking vaule PR305

1DISCHG_G-1
H => L 16.509V 16.199V 47K_0402_1%

1SS355_UMD2-2
PR328 0_0402_5%
1

1
V1
PR329 0_0402_5%

PD302
P2-1 PR306

2
2 4 CELL: PR312 = 59.0k PR330 @ 200K_0402_1%
PQ305 Typ Worst PC308 PC309 PQ306
PC309 0.1U_0402_25V

1
0.1U_0402_25V6 0.1U_0402_25V6 DTC115EUA_SC70-3
L => H 18.346V 18.529V

2
DTC115EUA_SC70-3 PR307 1 2 1 2
20K_0402_1% H => L 17.925V 17.589V PD303
3

Dock@ 1SS355_UMD2-2
2 2 1 2
6

PC309
2N7002KW_SOT323-3
1

SE00000G880 PQ309
150K_0402_1%

1
PR308

PQ307A D PQ308 S CER CAP 0.1U 25V K X5R 0402 2N7002KW _SOT323-3

0.1U_0603_25V7K

1
2 2N7002KDW -2N_SOT363-6 2 ACPRN# NoDock@ P2 D
BATT_OUT <44,45>

1
PC311
G PC310 Rds(on) = 30mohm max 2PACIN_2
1 2 G
Vgs = 20V
1

S VIN
3

2
Vds = 30V S

3
0.1U_0402_25V6
392K_0402_1%
1 ID = 7A (Ta=70C)
P2-2

PACIN_2

5
C C
PR309

10_1206_5%
2N7002KDW-2N_SOT363-6

PR310

AON7408L 1N DFN
3
PQ307B

ACOK

CMPIN

CMPOUT

ACP

ACN
PR311 PR312 <35,44> ADP_I PR313
2

PQ310
47K_0402_1% 59K_0402_1% 21 0_0402_5%

2
PACIN 1 2 5 1 2 6 TP 1 2 4
ACDET PC314
4.7uH DCR = 35+/- 15% mohm
PC313 20 BQ24737VCC 1 2 Power Rating = 1W
Idc~Isat = 5.5~6 A
4

PC312 1 2 7 VCC
1 2 IOUT PL302 PR314
VACP~VACN spec < 81.28mV

3
2
1
1U_0603_25V6K
1

PQ311 2200P_0402_25V7K 100P_0603_50V8 19 4.7UH +-20% 5.5A 7X7X3 MOLDING 0.01_1206_1%

PHASE
DTC115EUA_SC70-3
<35,44> EC_SMB_DA1
8
SDA
PU301
1 2CHG 1 4
BATT+
Make sure BQ24737RGRR_VQFN20_3P5X3P5 LX_CHG
18 DH_CHG
there is pull HIDRV

5
1 PR315 2 ACOFF-1 2 9

@EMI@ PR319
2 3
<35> AC_OFF SCL SA00004RZ00

1
high for SMB<35,44>
on EC_SMB_CK1 PR317 PR318

4.7_1206_5%
10K_0402_1% HW side! 316K_0402_1% 2.2_0603_5% PC315

AON7408L 1N DFN
1

1 2 10 17 BST_CHG 1 2 1 2 SRP SRN

10U_0805_25V6K

10U_0805_25V6K
ILIM BTST
1

16251_SN
PR316 @ +3VLP 100K_0402_1%
PD301
3

PQ312
PR320

Make sure this pull high 0.047U_0603_16V7K 4

LODRV
0.01U_0402_25V7K

0_0402_5%
PC316

2
1

1
16 2 1

PC317

PC318
GND
Voltage is same with EC VCC

SRN

SRP
REGN

BM
2

680P_0603_50V7K
2

2
RB751V-40_SOD323-2

@EMI@ PC320
2N7002KW_SOT323-3

11

1 12

13

14

15

3
2
1
1

1
10_0603_5%
6.8_0603_5%

2
1

PR321
PQ313 D PC319
2
PR322
,45> BATT_OUT
VILIM = 20 X (VSRP - VSRN) 1U_0603_16V7 BQ24737VDD

2
G = 20 X ICHG X RSR
S 2
3

2
1

DL_CHG
PC321
B @ PR323 B
Battery out function just for C38/A39 only, 10K_0402_5% 1 2
other customers please remove
PQ313,PQ314,PR310,PR326
2

0.1U_0402_25V6
1

1
PC323
0.1U_0402_25V6 @ PC322
2

+3VALW 2 0.1U_0402_25V6
**Design Notes**
Maximum Charging current 2.0A BQ24737VDD
Battery discharge power 55W.
#Register Setting PR326
10K_0402_1%
1. 0X12 bit8 set 0 (default 1) to disable IFAULT HI if add ISN choke

1
1 2
2. 0X12 bit3 set 1 (default 0) to enable turbo boost function Module model information PR325
VCIN1_AC_IN <19,33,35>

3. 0X12 bit[12:11] set 00 (default 11) to set BAT PR324 10K_0402_1%

47K_0402_1%
Depletion Comparator Threshold BQ24737_V1.mdd for dual layer PACIN

2
Falling Threshold = 59.19% of voltage regulation limit (~2.486V/cell)
4. Disable turbo when AC only

1
#Circuit Design

1
D
1. Make sure there is pull high for SMB on HW side PR327
ACPRN# 2 PQ314
2. Use 10X10 choke and 3X3 H/L side MOSFET <33> ACPRN#
G 2N7002KW _SOT323-3
12K_0402_1%

2
Charge current 2.0A S

3
Power loss : 1.82W
Power density : 0.81 (15X15)
A 3. If use 4S per cell 4.35V battery, need change PR313 to 59K for ACDET setting) A
4. For hybrid design, need double check PQ301,PQ302,PQ303,PQ309 component rating For disable pre-charge circuit
#Protect function
1. ACOVP : ACDET voltage > 3.15V
2. Charger timeout : No communication within 175s(default)
3. ACOC : 3.33 X Input current DAC setting(default) Security Classification Compal Secret Data Compal Electronics, Inc.
4. CHGOCP : 3/4.5/6A based on current current setting Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title
5. BATOVP : 104%
6. BATLOWV : 2.5V THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Charger_BQ24737
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
7. TSHUT : 155C DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS BE_BDW 1.0
8. IFAULT HI : 750mV (default) MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, February 12, 2014 Sheet 45 of 55
9. IFAULT LOW : 135mV (default)
5 4 3 2 1
 A B C D E

Module model information

SY8208B_V2.mdd

1 EN1 and EN2 dont't floating 1

PR401
Change 3V5V_EN to 3VALW_EN 499K_0402_1%
ENLDO_3V5V 1 2
B+

1
150K_0402_1%
PU401 PC403 PR403
B+

PR404
EMI@ PL401 7 1 3V5V_EN 0.01U_0402_25V7K 1K_0402_5%
HCB2012KF-121T50_0805 IN EN1 1 2 1 2

2200P_0402_50V7K
1 2 3V_VIN 8 3 3V_FB
IN EN2 PR405 PC404

2
10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
6 1
BST_3V 2 1 2
BS
1

1
PC407
C407
2.2_0603_5%
@EMI@ PC401

PC405

PC406
0.1U_0603_25V7K
@
@P PL402
2

2
EMI@
10 LX_3V 1 2
LX +3VALWP
9 4 1.5UH_PCMB053T-1R5MS_6A_20%
GND OUT

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
PR406
1

1
680P_0603_50V7K 4.7_1206_5%
2 5
PG LDO +3VLP
<35> 3V/5VALW_PG

@EMI@

PC408

PC409

PC410

PC411
1
PR402 SY8208BQNC_QFN10_3X3

2
100K_0402_1% PC412

1 3V_SN
1 2 4.7U_0603_6.3V6M
+3VLP

2
Check pull up resistor of SPOK at HW side

@EMI@ PC413
3.3V LDO 150mA~300mA

2
2 PR407 2
2.2K_0402_5%
Vout is 3.234V~3.366V
<35> EC_ON 1 2

@ PR408
TDC=6A
1 2
<35> VCOUT0_MAIN_PWR_ON 0_0402_5%
EC VDD0 is +3VL, PC13 UNPOP
1
@ PJ401
2
EC VDD0 is +3VALW, PC13 POP +3VALWP 1 2 +3VALW
1 2
<44> MOS_OTP 0_0402_5%
3V5V_EN
JUMP_43X118
@PR409
@ PR409 EN1 and EN2 dont't floating
1M_0402_1%

4.7U_0402_6.3V6M
1

PR415 1 2 0_0402_5% 3V5V_EN

1
PR410

PC414

PR416 1 @ 2 2.2K_0402_5%
Reserve for USB Charger
SUSACK# <35,9>
2

@
2

PC429 1 2 4.7U_0402_6.3V6M

PR419 1 @ 2 1M_0402_1%
B+ EMI@ PL403
HCB2012KF-121T50_0805 PR417 1 @ 2 0_0402_5% VCOUT0_MAIN_PWR_ON
1 2 5V_VIN
PR418 1 @ 2 0_0402_5% MOS_OTP
2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6

PU402 PC415 PR412

8 1 5V_EN 6800P_0402_25V7K 1K_0402_5%
IN EN1 1 2 1 2
Vout is 4.998V~5.202V
1

1
PC416

PC418
C418

EMI@ PC419

@EMI@ PC420

3 5V_FB PR413 PC417

3 EN2 2.2_0603_5% 0.1U_0603_25V7K 3
@
@P 6 BST_5V 1 2 1 2
TDC=6A
2

BS

PL404
9 10 LX_5V 1 2 +5VALWP
GND LX
5V_VCC 5 4 1.5UH_PCMB053T-1R5MS_6A_20%
VCC OUT
1

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
@EMI@ PR414

680P_0603_50V7K 4.7_1206_5%

1
2 7
PG LDO VL
1

PC421

PC422

PC423

PC424

PC425

PC428
4.7U_0603_6.3V6M

SY8208CQNC_QFN10_3X3

2
1 5V_SN

@ PJ402
2

2
1

PC426
4.7U_0603_6.3V6M

+5VALWP 1 2 +5VALW
1 2
JUMP_43X118
2

@EMI@ PC427
2

Module model information 5V LDO 150mA~300mA

SY8208C_V2.mdd

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+3VALW/+5VALW
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: Wednesday, February 12, 2014 Sheet 46 of 55
A B C D E
 5 4 3 2 1

Module model information

RT8207M_V1.mdd For Single layer
RT8207M_V2.mdd For Dual layer

D D

Pin19 need pull separate from +1.5VP.

If you have +1.5V and +0.75V sequence question, 0.75Volt +/- 5%
EMI@ PL501 you can change from +1.5VP to +1.5VS. TDC 0.7A
HCB2012KF-121T50_0805
B+ 1 2 1.35V_B+ PR501 Peak Current 1A
2.2_0603_5%
BST_1.35V 1 2 BOOT_1.35V

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
+1.35VP
1

1
PC501

PC502

PC503

PC504
DH_1.35V +0.675VSP
2

2
EMI@
@EMI@

SW _1.35V

10U_0805_10V6K

10U_0805_10V6K
1

1
PC505

PC506

PC507
5
0.1U_0603_25V7K

16

17

18

19

20
2
C PU501 C

2
VLDOIN
PHASE

UGATE

BOOT

VTT
21
PQ501 PAD
AON7408L_DFN8-5 4 DL_1.35V 15 1
LGATE VTTGND
Change CS R to your estimation value
14 2
PL502 PR502 PGND VTTSNS

1
2
3
1UH +-20% 11A 7X7X3 MOLDING 18K_0402_1%
1 2 1 2 CS_1.35V 13 3
+1.35VP PC508 CS RT8207MZQW _W QFN20_3X3 GND
1

1U_0603_10V6K

5
1 2 12 4 +VTTREFP
@EMI@ PR503 PR504 VDDP VTTREF
ESR=9m ohm

1 4.7_1206_5% 5.1_0603_5%
330U_6.3V_ESR17M_6.3X6

1 2 VDD_1.35V 11 5
+5VALW +1.35VP
1 2

VDD VDDQ

1
+

PGOOD
PQ502
PC510

ESR=15m ohm MDV1524URH 1N PDFN33-8 4 PC509

TON
1
@EMI@ PC513 0.033U_0402_16V7K

FB
S5

S3

2
2 680P_0402_50V7K PC512
+5VALW
2

1U_0603_10V6K

10

6
1
2
3

FB_1.35V
EN_0.675VSP
TON_1.35V

EN_1.35V
PR506
8.2K_0402_1%
PR507 1 2 +1.35VP
887K_0402_1%
B 1 2 B
1.35V_B+ Change FB Rtop to 8.2K for 1.35V
MOSFET: 3x3 DFN

1
Co-Lay H/S Rds(on): 27mohm(Typ), 34mohm(Max)
Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C PR508
@ PR509 10K_0402_1%
1 2
<35,42> SYSON

2
Mode Level +0.75VSP VTTREF_1.5V L/S Rds(on): 9.9mohm(Typ), 13mohm(Max)
0_0402_5%
S5 L off off Idsm: 13.5A@Ta=25C, 11A@Ta=70C

1
@ PC514
S3 L off on 0.1U_0402_10V7K
S0 H on on Choke: 7x7x3

2
Rdc=8.3mohm(Typ), 10mohm(Max)
Note: S3 - sleep ; S5 - power off
@ PR510
Switching Frequency: 285kHz 1 2 @ PJ501
Ipeak=10A <35,42,49,50> SUSP# 0_0402_5% +1.35VP 1 2 +1.35V
1 2
Iocp~13A PR505 JUMP_43X118
OVP: 110%~120% 1 2 @ PJ502
MOSFET footprint: SIS412DN <16> DDR_VTT_PG_CTRL 0_0402_5% 1 2
1 2

1
@ PC515 JUMP_43X118
0.1U_0402_10V7K

2
PJ503 @
1 2
+0.675VSP 1 2 +0.675VS
A
JUMP_43X39 A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2011/06/24 Deciphered Date 2012/07/12
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RT8207M
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: Wednesday, February 12, 2014 Sheet 47 of 55
5 4 3 2 1
 A B C D

Module model information

APL5930_V1.mdd

1 1

+3VALW +5VALW

Ultra Low Dropout 0.23V(typical) at 3A Output Current

1
PC601

1
1U_0402_6.3V6K
JUMP_43X79

2
@ PJ601

2
2
@
PR607
100K_0402_5% PC602 PU601

1
1 2 4.7U_0805_6.3V6K APL5930KAI-TRG_SO8
<20,35,48> GPU_1.8VGS_PWR_EN 6
5 VCNTL 3
PJ602

2
PR601 9 VIN VOUT 4 @
60.4K_0402_1% VIN VOUT
+1.8VGSP +1.8VGSP 1
1 2
2 +1.8VGS

1
1 2 8

24K_0402_1%
<20,35,48,51,9> DGPU_PWR_EN EN

1
1 2 7 2 JUMP_43X79
+3VS

GND
POK FB

PR603
PC603
1

@ PR602 0.01U_0402_25V7K
2
Rup
0.1U_0402_16V7K
2

1
PC605

PR604 100K_0402_5% PC604

2
47K_0402_5% 22U_0603_6.3V6M
2

2
2

1
PR605
19.1K_0402_1%
Rdown

2
Vout=0.8V* (1+Rup/Rdown)
@
PR612
Module model information 60.4K_0402_1%
1 2
GPU_1.8VGS_PWR_EN <20,35,48>
SY8003_V1.mdd
PR606
10K_0402_1%
+0.95VSP_ON 1 2
DGPU_PWR_EN <20,35,48,51,9>

0.1U_0402_16V7K

1
PC606
1
PR608
3
1M_0402_5% 3

Note:Iload(max)=2.5A

2
PU602
9
1 PGND 8
FB SGND
@ 2 7 PL601
PJ603 PG EN S COIL 1UH +-30% 2.8A 4X4X2 FERRITE
+3VALW 1 2 3 6 LX_0.95V 1 2
1 2 IN LX +0.95VGSP
1

4 5

68P_0402_50V8J
JUMP_43X79 PC607 PGND NC

1
4.7_0603_5%

1
PR609

PC608
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
2

1
SY8003DFC_DFN8_2X2 PR610
Rup
@EMI@

PC609

PC610
11.8K_0402_1%

2
2

2
FB_0.95V

1
@
PJ604
1

FB=0.6V
680P_0402_50V7K
PC611

Note:Iload(max)=3A PR611 1 2
20K_0402_1%
Rdown +0.95VGSP 1 2 +0.95VGS
2

@EMI@

2
JUMP_43X79

4
Note: 4

When design Vin=5V, please stuff snubber

to prevent Vin damage
Vout=0.6V* (1+Rup/Rdown)
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.8VGS-+0.95VVGS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: W ednesday, February 12, 2014 Sheet 48 of 55
A B C D
 A B C D

1 1

Module model information

SY8003_V1.mdd

PR702
0_0402_5%
+1.5VSP_ON 1 2
SUSP# <35,42,47,50>

0.1U_0402_16V7K

1
PC702
1
PR703
@ 1M_0402_5%
Note:Iload(max)=2.5A

2
PU701
9
1 PGND 8
FB SGND
PJ701 @ 2 7 PL701
PG EN 1UH +-30% 2.8A 4X4X2 FERRITE
2 +3VALW 1 2 3 6 LX_1.5V 1 2 2

1 2 IN LX +1.5VSP

1
4 5

68P_0402_50V8J
JUMP_43X79 PC701 PGND NC

1
4.7_0603_5%

1
PR704

PC703
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
2

1
SY8003DFC_DFN8_2X2 PR705
Rup

@EMI@

PC704

PC705
15K_0402_1%

2
2

2
FB_1.5V

1
1
FB=0.6V

680P_0402_50V7K
PC706
Note:Iload(max)=3A PR706
Rdown
10K_0402_1%

@EMI@
@
PJ702

2
1 2
+1.5VSP 1 2 +1.5VS
JUMP_43X79

Note:
When design Vin=5V, please stuff snubber
to prevent Vin damage
Vout=0.6V* (1+Rup/Rdown)
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.5VS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: W ednesday, February 12, 2014 Sheet 49 of 55
A B C D
 5 4 3 2 1

D D

Module model information

SY8208D_V1.mdd

EN pin don't floating

If have pull down resistor at HW side, pls delete PR2

PR802
0_0402_5%
1 2
SUSP# <35,42,47,49>
C C

1
@ PC802
1M_0402_1%
0.22U_0402_10V6K

2
PR803
PJ801

2
+1.05VSP 1 2 +1.05VS
1 2
JUMP_43X118 @
@EMI@ PR804 @EMI@ PC803
4.7_1206_5% 680P_0603_50V7K
EMI@ PL801 1 2SNB_1.05V 1 2
HCB2012KF-121T50_0805 PU801
B+ 1 2 B+_1.05V 8
IN EN
1 PR805 PC804
2.2_0603_5% 0.1U_0603_25V7K
TDC 8A
10U_0805_25V6K

10U_0805_25V6K

6 1
BST_1.05V 2 1 2 PL802
0.1U_0402_25V6
2200P_0402_50V7K

BS
1

1UH +-20% 11A 7X7X3 MOLDING

PC805

PC806

PC807

3VLDO_1.05 9 10 LX_1.05V 1 2
+1.05VSP
PC801

GND LX
@EMI@
2

2
EMI@

15K_0402_1%

47U_0805_6.3V6M

47U_0805_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1

330P_0402_50V7K
1

1
PR806 4

PR807
FB

PC808

PC809

PC810

PC811

PC812
0_0402_5%
ILMT_1.05V3 7
Rup
@ +3VALW

2
ILMT BYP
2

2
4.7U_0603_6.3V6K
ILMT_1.05V
+3VS 1 21.05V_VS_PG_PWR 2
PG LDO
5 3VLDO_1.05

1
PR801

PC814
4.7U_0603_6.3V6K
1

10K_0402_5% SY8208DQNC_QFN10_3X3
PC813

FB = 0.6V
2

1
PR808 @
2

0_0402_5% PR809
Rdown
2

20K_0402_1%

2
<35> 1.05V_VS_PG_PWR
Pin 7 BYP is for CS.
B
The current limit is set to 8A, 12A or 16A when this pin Common NB can delete +3VALW and PC15 B
is pull low, floating or pull high
VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)
Vout=1.05V

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.05VS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: Wednesday, February 12, 2014 Sheet 50 of 55
5 4 3 2 1
 5 4 3 2 1

+VGA_CORE
GPU_B+
AMD TOPAZ
Module model information TDC 31A, EDC 46.5A
EMI@ PL901 OCP min 58.1A
ISL62771_V1A.mdd for IC portion HCB2012KF-121T50_0805
B+
1 2 AMD JET LE
ISL62771_V1B.mdd for SW portion LGATE1 TDC 20A, EDC 30A
OCP min 37.5A

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
PHASE1

1
@EMI@ PC902

EMI@ PC903

PC904

PC905
PR905 PC906
2.2_0603_1% 0.22U_0603_25V7K
BOOT11 2 1 2
PQ901

2
D D
6
PR904 7 G2
0_0402_5% S1/D2 5
UGATE1 1 2 1 S2
G1 4
2 S2
D1 3
S2

AON6932A_DFN5X6-8-7

@ PR946
1 2 Fsw=400K Hz

1
0_0402_5% PR902
LGATE_NB1
10K_0402_1%
1 2 SH00000NX00 (DCR:1.4± 5%)
@ PR947 PR945
1 2 41.2K_0402_1% PHASE_NB1
0_0402_5% PR903 10K_0402_1% +VGA_CORE

2
UGATE_NB1 1 2
1 4
PL902
PR906
0.22UH_PCME064T-R22MS_28A_20%
BOOT_NB12 1 +5VALW
2 3

390U_2.5V_M

390U_2.5V_M

330U_B2_2.5VM_R9M
330U_D2_2V_Y
1 1 1 1

1
41

40

39

38

37

36

35

34

33

32

31
1_0402_5% + + + +

PC910

PC907

PC908

PC909
PU901 PR907 @EMI@ 25W@PR938
25W@ PR938 25W@PR939
25W@ PR939
4.7_1206_5% 10K_0402_1% 10K_0402_1%

TP

ISUMP_NB

ISUMN_NB

VSEN_NB

FB_NB

COMP_NB

PGOOD_NB

LGATE_NB

PHASE_NB

UGATE_NB

BOOT_NB
ISEN1 1 2 1 2 ISEN2
2 2 2 2

2
PR901 100K_0402_1%
1 2 1 30 BOOT2 PR908

1
NTC_NB BOOT2 PC911 @EMI@ 3.65K_0603_1%
PR909 100K_0402_1%
1 2 IMON_NB 2 29 UGATE2 680P_0603_50V7K VSUM+ 1 2
IMON_NB UGATE2

2
3 28 PHASE2
<19> GPU_SVC SVC PHASE2 PR910
4 27 LGATE2 +5VALW 1_0402_1%
<19> GPU_PROCHOT# VR_HOT_L LGATE2
@ PR911 100K_0402_1% VSUM- 1 2
1 2 5 26
+3VS <19> GPU_SVD SVD VDDP
ISL62771HRTZ-T_TQFN40_5X5 PR913
+1.8VGS PR912 1 @ 2 0_0402_5% VDDIO 6 25 1 2
VDDIO VDD 1_0603_5%

1U_0603_10V6K
1

@PR914 0_0402_5% 7 24 LGATE1

<19> GPU_SVT SVT LGATE1

1
C 1 2 GPU_B+ C
@ PR915 LGATE2

1U_0603_10V6K
+1.5VS
PC901 1 2 ENABLE 8 23

PC913
PHASE1
<20,35> GPU_PWR_EN
2

ENABLE PHASE1

PC912
0.1U_0402_25V6K 0_0402_5%

2
1 PR937 2 @ 9 22 UGATE1
<51,9> DGPU_PWROK PWROK UGATE1
0_0402_5% PHASE2

2200P_0402_50V7K

25W@ 10U_0805_25V6K

25W@ 10U_0805_25V6K
0.1U_0402_25V6
1 2 IMON 10 21 BOOT1
IMON BOOT1 +3VS

@25WEMI@ PC915
PR916 25W@ PR928 25W@PC922
25W@PC922

1
PGOOD

25WEMI@ PC916

PC917

PC918
133K_0402_1% 2.2_0603_1% 0.22U_0603_25V7K 25W@
ISUMN
ISUMP

PQ902

COMP
ISEN2

ISEN1

VSEN

BOOT21 2 1 2
NTC

RTN

1 2 PC914 FB 6

2
G2

1
1000P_0402_50V7K 7
PR919 PR918 25W@ 0_0402_5% PR921 S1/D2 5
11

12

13

14

15

16

17

18

19

27.4K_0402_1% 20K_0402_1% 20 @ PR917 UGATE2 1 2 1 S2

1 2 1 2 100K_0402_1% G1 4
2 S2

2
D1 3
ISEN2

ISEN1

S2
DGPU_PWROK <51,9>
1 2
PR932 PH901 AON6932A_DFN5X6-8-7
2

1 2 ENABLE
0_0402_5%

10K_0402_1%

<20,35,48,9> DGPU_PWR_EN 470K +-5% 0402 B25/50 4700K

PR944

PR920

0_0402_5%
25W
0.22U_0402_10V6K

Reserve for GPU Sequence

0.22U_0402_10V6K

15W@
1

PC962
PC961

+5VS 15W@

15W +VGA_CORE
2

PR931 25W@ 25W@ PC920 25W@ 25W@ PL903

SD00000AN80 VSUM- PC919 PR922 270P_0402_50V7 @ PR923 1 4
S RES 1/16W 536 +-1% 0402 1000P_0402_50V7K 301_0402_1% 32.4K_0402_1% 0.22UH_PCME064T-R22MS_28A_20%
15W@ VSUM+ 1 2 1 2 1 2 1 2 2 3
330P_0402_50V7K
@ PC921

25W@PR940
25W@ PR940 25W@PR943
25W@ PR943
2.61K_0402_1%
1

1
25W@ PR924 PR925 PC923 PR929 @25WEMI@ 10K_0402_1% 10K_0402_1%
10K +-5% 0402 B25/50 4250K

1 2 1 2
PR926

0.047U_0402_25V7K

0.15U_0603_16V7K

PR924 866_0402_1% 137K_0402_1% 390P_0402_50V7K 4.7_1206_5% ISEN2 ISEN1

11K_0402_1%
1

1 2 1 2 1 2
25W@ PC924

SD034100180
2
1

1
PR927

25W@ PC925

S RES 1/16W 1K +-1% 0402

15W@ 25W@PR942
25W@ PR942
1 2

1 2
PR930 PC926 3.65K_0603_1%
2

2K_0402_1% 330P_0402_50V7K VSUM+ 1 2

2

PC925 1 2 1 2 PC927 @25WEMI@

PH902

SE042104K80 680P_0603_50V7K

2
B S CER CAP .1U 25V K X7R 0603 25W@PR941
25W@PR941 B
15W@ 25W@ PR931 1_0402_1%
2

422_0402_1% VSUM- 1 2
VSUM- 1 2
PC924
SE075223K80 @ PC929 @ PR933 +VGA_CORE
1

S CER CAP 0.022U 25V K X7R 0402 @ PR934 820P_0402_50V7K 0_0402_5%

15W@ PC928 100_0402_1% 1 2
0.1U_0603_50V7K 1 2 1 2 GPU_VDD_SEN <19>
2

@ PR935
PC920 0_0402_5%
SE071181J80 PR1046 set 536 ohm to OCP 26.32A 1 2

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M
GPU_VDD_RUN_FB_L <19>
0.01U_0402_50V7K

S CER CAP 180P 50V J NPO 0402

1
PC931

PC932

PC933

PC934

PC935

PC936

PC937

PC938

PC939

PC940

PC941

PC942

PC943

PC944

PC945

PC946
15W@
1

PC930

2
2

GPU 15W setting

PR931=536 ohm, PR924=1K ohm, PC925=0.1uF,

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
PR944 =0 ohm, PR920=10K ohm, PC924=0.022U

1
PC961 @, PC962 @, PR938 @ and PR939 @

PC947

PC948

PC949

PC950

PC951

PC952

PC953

PC954

PC955

PC956

PC957

PC958

PC959

PC960
while PR931=536 ohm to set OCP for GPU 15W application.

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title
PWR-+VGA_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: Wednesday, February 12, 2014 Sheet 51 of 55
5 4 3 2 1
 5 4 3 2 1

Base on BDW PDDG Rev_0_73

Module model information:
ISL95813 (for 15W & 28W CPU) 15W H-side MOS: MDV1525URH
Rds(on):
TDC 14A <10.1mohm@Vgs=10V
<14.0mohm@Vgs=4.5V
Location MAX 32A Note Id :24A@Vgs=10V
D D

OCP 39A
L-side MOS: MDU1511RH
Loadline=-2.0mv/A
Rds(on):
+1.05VS Follow intel guideline <2.4mohm@Vgs=10V
PR1102130_0402_1% PR1120 499 Ohm OCP
1 2 <3.3mohm@Vgs=4.5V
Id :100A@Vgs=10V
PR537 1.27kOhm Droop

PC528 0.022uF RC Match

PC1102 Choke: 0.12UH (Size:7*7*3)
1U_0402_6.3V6K PR110354.9_0402_1%
1 2 1 2 PR507 90.9kOhm PROG1 Rdc=0.62mohm +-5%
Heat Rating Current=41.5A
PR703 93.1kOhm IMON Saturation Current=41A
<12> VR_SVID_DAT
PC518 0.1uF ( 0402 ) RC Filter
Note:
VR_SVID_ALRT# Pull high on HW side
<12> VR_SVID_ALRT#

<12> VR_SVID_CLK PR1104 Note: CPU_B+ EMI@ PL1103

169K_0402_1% HCB2012KF-121T50_0805
C
1 2 PR1104=169K 1 2 B+ C
=>Icc(max)=33A

VR_SVID_ALRT#
CPU_B+
fsw=700KHz

VR_SVID_DAT
VR_SVID_CLK

2200P_0402_50V7K
10U_0805_25V6K

0.01U_0402_50V7K

0.022U_0402_25V7K
<12> VR_ON @EMI@ PL1104

10U_0805_25V6K
HCB2012KF-121T50_0805

MDV1525URH_PDFN33-8-5

33U_25V_M

68U_25V_M
EMI@PC1105

EMI@PC1106

@RF@ PC1107
1 1 1 2

PRGM1

1
PC1103

PC1104

PC1123

PC1122
@ PR1101
+1.05VS 1.91K_0402_1% + +

PQ1101
1.5K_0402_1%

1 2

2
1

PR1105
2 2
PR1122

0_0603_5%
21

20

19

18

17
<12> VGATE PU1101 1 2 4

SCLK

SDA
PAD

ALERT#

PRGM1
<35> IMON_CPU
2

PC1101 VR_ON 1 16 LAGTE

3
2
1
1000P_0402_50V7K VR_ON LGATE PL1102
1 2 .15UH 20% PCME064T-R15MS0R667 36A
2 15 PHASE 1 4
PR1106 PGOOD PHASE +CPU_CORE

4.7_1206_5%
@EMI@PR1107
Note: 97.6K_0402_1% 2 3

MDU1511RH_POWERDFN56-8-5
5

1
1 2 IMON_CPU 3 14 UAGTE

MDU1511RH_POWERDFN56-8-5
VR_HOT# Pull high on HW side IMON UGATE

5
PR1108 PC1108

PQ1102
ISL95813HRZ-T_QFN20_3X4 2.2_0603_5% 0.22U_0603_16V7K

1
PQ1103
<35> VR_HOT# VR_HOT_1# 4 13 BOOT 1 2 1 2
PH1101 VR_HOT# BOOT PR1109

2
47P_0402_50V8J

470K +-5% 0402 B25/50 4700K PR1110 4 3.65K_0603_1%

1 2 1 2 NTC 5 12 4
NTC VCC +5VS
1

680P_0603_50V7K
PC1109

@EMI@PC1110

2
1
3.83K_0402_1%
PR1111 COMP 6 11 PRGM2
2

3
2
1
COMP PRGM2

1
27.4K_0402_1%
ISUMN

ISUMP

3
2
1

2
1 2 PC1111
RTN

124K_0402_1% 0.1U_0402_25V6
FB

2
1
PR1112

B Over temperature protection: B

7

10

OTP Setting: 100C active @

909_0402_1%
1

Pin5 (NTC) voltage <0.88V, Protect

2

FB
ISUMN

ISUMP

Note:
PR1113

Pin5 (NTC) voltage >0.92v, recovery

33P_0402_50V8J PR1112=124K
1
6800P_0402_25V7K

2K_0402_1%

10_0402_1%

@ PC1112 =>Slew rate=53mV/us

2

@PR1115

Vboot = 1.7V
2

PR1114
1

1.27K_0402_1%
PC1113

PR1116

@
2

1
390P_0402_50V7K

4.99M_0402_1%
1

1
330P_0402_50V7K

PR1118
2
1

@PC1115

PR1117

4.42K_0402_1%
RC Match
2
PC1114

Droop
2

2
2

1
@ PC1116 PC1117 PR1119
0.033U_0402_25V7K 0.1U_0402_16V4Z 11K_0402_1%
2

1
<12> VCCSENSE
PH1102
10K +-5% 0402 B25/50 4250K

@ PC1118

2
0.082U_0402_16V7K

1 2 OCP Setting
@PC1119

330P_0402_50V7K
1

PR1120
1 2
A A
2

PC1120 287_0402_1%
1 2

0.01U_0402_50V7K
@ PC1121 @ PR1121

1 2 1 2
<12,14> VSSSENSE Compal Electronics, Inc.
4700P_0402_25V7K 1.5K_0402_1% Title

Local sense put on HW site ISL95813 for BDW-Y&U(15W/28W) CPU

Size Document Number Rev
1.0
BE_BDW
Date: Wednesday, February 12, 2014 Sheet 52 of 55

5 4 3 2 1
 5 4 3 2 1

+CPU_CORE
24 X 22u/0603

D D

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1 1 1 1 1 1 1 1 1 1
PC1201

PC1202

PC1203

PC1204

PC1205

PC1206

PC1207

PC1208

PC1209

PC1210
2

2 2 2 2 2 2 2 2 2
@ @ @ @ @ @
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1 1 1 1 1 1 1 1 1 1
PC1211

PC1212

PC1213

PC1214

PC1215

PC1216

PC1217

PC1218

PC1219

PC1220
2 2 2 2 2 2 2 2 2 2
@

C C
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1
1 1 1 1
+ @ PC1234
PC1221

PC1222

PC1223

PC1224

330U_D2_2VM_R9M
2 2 2 2 2

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Title
Issued Date 2011/06/24 Deciphered Date 2012/07/12
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-PROCESSOR_DECOUPLING
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: W ednesday, February 12, 2014 Sheet 53 of 55
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Reason for change PG# Modify List Date Phase

1
D D

C C
9

10

11

12

13

14

B B

15

16

17
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: W ednesday, February 12, 2014 Sheet 54 of 55
5 4 3 2 1
 5 4 3 2 1

ZIWB2/ZIWB3/ZIWE1 HW PIR List

Item Page MODIFICATION LIST PURPOSE
EVT TO DVT
1 P.36 Modify DP_SEL schematic Because the first design is wrong.

D 2 P.34 Delete D28 It already reserve in sub BD D

3 P.36 Modify HPD schematic Because the first design is wrong.

4 P.36 Modify DP AUX schematic Cap already reserve in sub BD
5 P.20 Reserve +1.05VS to +0.95VGS AMD's suggestion
6 P.33 Add D26 for ESD
7 P.42 Add RV198, RV199 AMD's suggestion
8 P.22~24 Add GPU Termination Resistance AMD's suggestion
DVT TO PVT
1 P.35 change U11.111 power rail to +3VLP It only use +3VLP
2 P.33 un-pop R294, pop R295. B series's LED need to follow E series
3 P.10 Add R247, R248 For BIOS Stap Pin
4 P.20 Add RV60, delete RV36 for GPU Sequence
C C

5 P.20 Add RV61, delete RV240 for GPU Sequence

6 P.37 Change DP Switch IC solution For HDMI audio issue
7 P.35 Add C197 for ESD
8 P.33 Add C198 for ESD
9 P.30 Add C199 for ESD
PVT TO PRE-MP
1 P.33 Reserve R298, R299 for DC-in LED control To avoid LED shimmer
2 P.38 Change DL1 and DL2 footprint for ESD

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B091P
Date: Wednesday, February 12, 2014 Sheet 55 of 55
5 4 3 2 1
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