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10kW Three-phase SiC PFC Rectifier

SEMICON® EUROPA, Nov 13-18, 2018, Munich, Germany

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Contents

• General PFC Concept

• 3 Phase System and PFC Control
• Simulation
• Understanding the losses
• 3 Phase PFC Implementation
• Results

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 General PFC Concept

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Definition of Power Factor

Real Power (W) Pavg I1, RMS

Reactive PF     cos1
Power Apparent Power (VA) VRMS I RMS I RMS
φ1 (VAR)
DISPLACEMENT
POWER
Real Power (W) FACTOR
FACTOR
DISTORTION
FACTOR
V V V
I I I

cos(1)

• DISTORTION FACTOR = 10.61 • DISTORTION FACTOR = 1 • DISTORTION FACTOR < 1

• DISPLAC. FACTORFACTOR
DISPLACEMENT = 0.96 = 1 • DISPLACEMENT FACTOR < 1 • DISPLACEMENT FACTOR = 1
• PF = 10.59 • PF < 1 • PF < 1
DIODE
PFC TARGET
BRIDGE
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 3 Phase System and PFC Control

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3-phase PFC: Selected Topology

Power Flow

• 3 Half Bridges.
• Each half bridge connected to a input
phase voltage.
• Input voltages form a unique system.

The 3-phase PFC control concept works as an inverter for motor application. Only the control strategy changes. This
configuration would allow to control the reactive power because of “Q” axis availability.

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3 Phase PFC: Voltage Relationship, ABC Model
d1 d2 d3
VDC
SYSTEM VOLTAGE EQUATIONS IN „ABC“ DOMAIN
σ𝑖=𝐴,𝐵,𝐶 𝐸𝑖𝑀 =0
di
EAN VLA vL,A  eAN  uN 0  VA0  LS  A  RS iA
A
dt
diB
N B
vL,B  eBN  uN 0  VB0  LS   RS iB
VA0
dt
C di
vL,C  eCN  uN 0  VC 0  LS  C  RS iC
dt
Goal of the PFC is to control the voltage across the inductors.
0
VN0

SUPPLY VOLTAGE TIME ES

400 B
300 EA(t1)
𝐸𝐴𝑀 = 𝐸ത ∙ cos(𝜔𝑡) 200
EC,(t1)
100 EB,(t1)
EB(t1)
𝐸𝐵𝑀 = 𝐸ത ∙ cos(𝜔𝑡 − 23𝜋) 0 EA,(t1)
-100 0 0.005 0.01 0.015 0.02
A
-200
𝐸𝐶𝑀 = 𝐸ത ∙ cos(𝜔𝑡 − 43𝜋) -300
EC(t1)
-400 C VECTOR SPACE

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Bus Voltage Limitation and Driving Capability
VDC
When the switches are modulating, the following vectors
SAH SBH SCH
can be provided in the vector space domain.

ES,MAX = 0.57 VDC

SAL SBL SCL

VOLTAGE SOURCE INVERTER

• When FETs are left “OPEN”, the HW is operating

as a diode bridge because of the FWD.
• The target DC BUS voltage has to be higher
than the line to line voltage amplitude:
𝑽𝑫𝑪 = 𝟔𝑬𝑹𝑴𝑺,𝑷𝑯𝑨𝑺𝑬
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System Reference: From 3φ Stationary To 2φ Rotating
β
B β
B D
ES ES
GEOMETRIC

EB,(t1) ES
α 𝜗
EC,(t1)
EA,(t1) φ Φ=0
A A α

Q
C CLARKE C PARK
(αβ) = [T0]·(ABC) (DQ) = [T 𝜗𝑆 ]·(αβ)
400
300
200
100
TIME

EAM 0 Eα ED
EBM -100
ECM -200 Eβ EQ
-300
-400
ϑ [rad] ϑ [rad] ϑ [rad]

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3 Phase PFC: (DQ) Model

diD • Input quantities are transformed by means of

eD  LS   RS iD LS iQ  VD Clarke/Park matrix.
dt • ED EQ are the supply voltages expressed in the DQ
diQ
eQ  LS   RS iQ LS iD  VQ domain.
dt • iD, iQ are the phase currents in the DQ domain.

 iDsD iQ sQ  

duDC uDC • ω is the fundamental frequency of the input
C voltage.
dt RL
• VD and VQ are the voltage generated by the control
in the DQ domain that will be used for the PWM
ELECTRICAL QUANTITIES ON DQ generation.
DOMAIN ARE CONSTANT VALUES

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3 Phase PFC Control Scheme on DQ Domain

SPECIFICATION

Input voltage:
230V RMS 3-Phase voltage, 50Hz.
3 MODULATION
Output Voltage: STRATEGIES TESTED
700V

Switching Frequency:
70kHz

Control Frequency:
20kHz DQ SYSTEM
MAKES PI
Source Inductance:
REGULATION
300uH
POSSIBLE!
Output capacitance:
470uF CONTROL ALGORITHM
FIXED DURING TEST
CONDITIONS
Ref. Fig 11.23 “Control in power electronics” Author. M.P. Kazmierkowski et al. 2002

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3 Phase PFC: Applied Modulation Strategies
PWM Adaptive
Modulator

• A modification into the zero sequence voltage doesn’t affect the voltage applied to the inverter phases, however it
will affect noise between DC output and PE.
• An impact on the input filter should be expected, even if in this presentation EMI FILTER was not considered.

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 Simulations

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3 Phase PFC Simulink Model, Behavioral

PARAMETERS
• FCLK = 84 Mhz
70kh pwm freq
• FPWM = 70 Khz
• FCNTR = 20 Khz
• DEAD TIME = 1.1%
ADC & PWM
Peripherals
HARDWARE
• LS = 300 uH
• RS = 0,04 Ohm
• RHL = 72 Ohm

PWM • RFL = 36 Ohm

Control Strategy OUTPUT
ANALOG INPUTS (C-code)

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3 Phase PFC SPICE Model, Quantitative

CONTROL STRATEGY POWER SENSING INPUTS

STAGE

THE PARAMETERS SELECTED FOR RUNNING SPICE SIMULATION WERE ALIGNED WITH THE SIMULINK ONES.

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 Understanding the Losses

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Choke Inductor Losses (simplified)
700V

𝑎 𝑐
𝑃𝐿,𝐶𝑂𝑅𝐸 = 𝑘 ∙ 𝑓 ∙ 𝐵𝑃𝐾 IX
VLX
X
LX

• k, a
EXN(t)
and c are core material dependent. VX0

• f is the high switching frequency N

0
• BPK is half the flux density ripple calculated considering
the current ripple introduced by the inductance selected
𝐵𝑃𝐾 = 𝜇0 𝜇𝑅 𝑁∆𝐼2.

𝑃𝐿,𝐽𝑂𝑈𝐿𝐸 = 𝑅𝑊 ·I 2RMS
• Where RW is the winding resistance.
• IRMS is the circulating current for a certain power level
with a known input voltage.

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FETs Losses in Space Vector Modulation (1/2)
tDT
1 2 3 4
iA
dA M2 D1 M1 D1 M2

iB
1 2 3 4
dB D4 M3 D4
iC

1 2 3 4
M1 M3 M5
dC D6 M5 D6

dA dB dC TPWM

HARD HARD SOFT SOFT

iA
A
ON – OFF OFF – ON ON - OFF OFF – ON
iB LEG A M2 - [1] M2 - [4] M1 - [3] M1 - [2]
B
iC LEG B M3 – [3] M3 – [2] M4 – [1] M4 – [4]
C
LEG C (as B) M5 – [3] M4 – [2] M6 – [1] M4 – [4]

SWITCHING LOSSES PL,SW → fPWM

M2 M4 M6
Notes
d'A d'B d'C
• During tDT both switches on each leg are fully OFF.
• FETs are bidirectional when turned ON and current flows according source and drain voltage potential.
• vA is depending on phase voltage and star voltage when low side FET OFF and current into the node.

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FETs Losses in Space Vector Modulation (2/2)

𝑃𝑆𝑊 = 3 ∙ 𝐸𝑂𝐹𝐹 + 𝐸𝑂𝑁 ∙ 𝑓𝑃𝑊𝑀

Note
By designing a different modulation strategy, the number of
transitions could be decreased by 33% and together with an
appropriate timing based on current amplitude, a switching loss
minimization can be achieved

• Since all the FETs are equal we simplify the calculation

with the following formula
2
𝑃𝐽 = 3 ∙ 𝑅𝐷𝑆,𝑂𝑁 𝑇 ∙ 𝐼𝑅𝑀𝑆

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 3 Phase PFC Implementation

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3 Phase PFC – Power Board Concept (1/2)
Note: 700V
VBUS,MIN = 265·√6 = 650V 3V3 15V 3V3 15V 3V3 15V
24V PWM
ISO-GATE
PWM
ISO-GATE
PWM
ISO-GATE
EN EN EN
DRIVER DRIVER DRIVER vBUS
FAULT FAULT FAULT

iA
vA
CURR SEN.
vB iB
CURR. SEN.
vC iC
CURR. SEN.
24V
3V3 15V 3V3 15V 3V3 15V
PWM PWM PWM
ISO-GATE ISO-GATE ISO-GATE
Inrush OFF EN
DRIVER
EN
DRIVER
EN
DRIVER
Note FAULT FAULT FAULT

Analog INP

Digital

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3 Phase PFC – Power Board Concept (2/2)

3V3 5V DESAT
390 V 24V IN+
DCDC CONVERTER DIGITAL IN- GATE
XEN
RSRC
[390-850]/24V ISOLATOR DRIVER
REF. RSINK
20V
ISO
15V
DCDC
ISO-GATE DRIVER
SIGNAL
CONDITIONING
FOR 3V3 uC

Note
Analog INP

Digital

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3 Phase PFC Power Board

SIZE
375 x 240mm

TOP VIEW Public Information

BOTTOM VIEW
 Results

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SiC Switching Behavior
INPUT VOLT: 230 Vrms
OUTPUT POWER: 10kW
EFFICIENCY: 97.6%
FPWM: 80kHz
DC OUT: 719.44V
DC RIPPLE: 29.4V
RG,ON: 22 Ohm TURN OFF ≈ 65 Vns-1 TURN ON ≈ 38 Vns-1
RG,OFF: 4.7 Ohm
L(Is = 0, F = 1kHz): 600 uH

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Overview of the Experiment
INDUCTOR [μH] 450 330
FACTORS

SWITCH. FREQUENCY [kHz] 70 120 70 120

MODULATION [type] DIS1 FBM SVM DIS1 FBM SVM DIS1 FBM SVM DIS1 FBM SVM

OUTPUT POWER [kW] [3..10] [3..10] [3..10] [3..10] [3..10] [3..10] [3..10] [3..10] [3..10] [3..10] [3..10] [3..10]

TOTAL HARMONIC DISTORTION [THD]

METRICS

EFFICIENCY [η] POWER FACTOR [PF] PHASE DELAY [φ]

Ideally 100% Ideally „1" Ideally „0°"
7.0 3.5 2.5 1.0 0.5 8

Testing conditions IEEE STD 519

Input voltage:
230VRMS @ 50Hz Public Information
Current Shape @ 10 kW
DISCONTINOUOS 1 FLAT BOTTOM SPACE VECTOR
70 kHz

THD1: 4.7% THD1: 4.9% THD1: 3.7%

THD2: 5.8% THD2: 5.6% THD2: 4.2%
THD3: 4.4% THD3: 5.0% THD3: 3.7%
120 kHz

THD1: 5.1% THD1: 8.1% THD1: 3.6%

THD2: 6.5% THD2: 8.3% THD2: 3.5%
THD3: 6.2% THD3: 8.0% THD3: 3.0%

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Efficiency Result
• Factor with the highest impact is the output power at
which the board is working.
• Efficiency is affected by the modulation strategy
selected, a variation in average of 0.5% can be
considered which, in turn, affects switching losses.
• Modulation frequency and inductor selection have a
smaller influence on efficiency result. Most likely
they are compensating each other.

Note
Thermal steady state reached @ 10kW.
Power Supply: Chroma 61511, DC Load: ELR-91500-30, Power Analyzer:
Zimmer LMG500 Oscilloscope: Yokogawa DLM6054
.
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Power Factor & THD

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 Thank you

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