Name: Atul Kumar Dwivedi

Reg. No.: 17BEC0813

Slot- C1
Faculty: Prof. Dhanabal R.
Registration No.-17BEC0813
Name- Atul Kumar Dwivedi

1. Explain how the selected paper related to COA syllabus/curriculum.

Ans: The title of the selected paper is “Design and Implementation of Low Power Floating Point
Arithmetic Unit”. In this paper new implementation of IEEE floating point (FP) multiplication and
division is proposed. In COA syllabus/ curriculum we have to study the implementation of different
architecture that are used for performing arithmetic operations. We have studied the norms that IEEE
provides to represent floating point numbers. How to perform all the arithmetic operation for both
fixed point and floating point. So, this paper directly relates to our syllabus.

2. Draw the Existing architectures discussed in the paper using Microsoft VISIO and
Adobe Photoshop software in Encapsulated PostScript (EPS) file format.
Ans: Existing architecture for floating point multiplication: (This picture is drawn in MS word and I
have converted it to eps format. It will be uploaded in the google drive link that I will provide in the
mail.)

IEEE Floating Point Multiplier (Existing):

Registration No.-17BEC0813
Name- Atul Kumar Dwivedi

3. Draw the Tabulated results and graphs using Microsoft office suite in Encapsulated
PostScript (EPS) file format.
Ans: The tabulated result given in the selected research paper is follows: (This table is drawn in MS
word and I have converted it to eps format using online tool. It will be uploaded in the google drive
link that I will provide in the mail.)

Floating point addition:

Library Area Leakage Dynamic Net Timing (Worst
Power (nw) Power (nw) Power (nw) path delay)(ps)
Typical 21991 415.369 6782560.328 6782975.698 16362.30
Slow fast typical 22021 81613.855 1093096.449 1174710.305 17847.80
Slow typical fast 22027 28684.396 1029314.977 1057999.373 23443.50
slow high_vt

Synthesis Report Floating point multiplication:

Library Area Leakage Power Dynamic Net Power Timing (Worst
(nw) Power (nw) (nw) path delay)(ps)
Typical 14829 221.505 2698250.634 2698472.139 38908.40
Slow fast typical 14122 50002.866 422211.905 472214.771 35610.40
Slow typical fast 14119 20363.537 399506.942 419870.479 44440.70
slow high_vt
Registration No.-17BEC0813
Name- Atul Kumar Dwivedi

4. Draw the Proposed architectures discussed in the paper using Microsoft VISIO
software in Encapsulated PostScript (EPS) file format.
Ans: The proposed architectures are as follows: (This picture is drawn in MS word and I have
converted it to eps format using online tool. It will be uploaded in the google drive link that I will
provide in the mail.)

Multiplier:
Registration No.-17BEC0813
Name- Atul Kumar Dwivedi

Carry Save Array Multiplier:

Registration No.-17BEC0813
Name- Atul Kumar Dwivedi

ADDER:
Registration No.-17BEC0813
Name- Atul Kumar Dwivedi

5. Draw the transistor level internal diagrams using Multisim or OrCAD tools in
Encapsulated PostScript (EPS) file format.
Ans:

RTL View for Typical Library – Adder: (EPS format will be in the mail)
Registration No.-17BEC0813
Name- Atul Kumar Dwivedi

RTL View for Typical Library – Multiplier: (EPS format will be in the mail)
Registration No.-17BEC0813
Name- Atul Kumar Dwivedi

6. Compare the proposed architecture with existing architecture in your reference

books.
Ans: Unlike fixed point numbers, floating point numbers have larger range of values but require either
costly processing hardware or lengthy software implementations. So powerful computations and
techniques which reduce hardware and improve the performance like power, area, timing etc is
required. IEEE sponsored a standard format for 32-bit and larger floating-point numbers, known as
the IEEE 754 standard, which has been widely adopted by computer manufacturers. Besides specifying
the permissible formats for M(Mantissa), E(Exponent) and B(Base), IEEE prescribes methods for
handling round-off errors, overflow, underflow and other exceptional conditions. While in this
architecture, the proposed technique efficiently solves the challenge of implementation of floating-
point addition and multiplication using the multi threshold voltage technique. The proposed
technique reduces the power consumption using the multi Vt method while keeping the area
optimized. This is the only difference between what we have studied and what is proposed in the
paper.

7. List the advantage of the proposed design over existing design.

Ans: The proposed technique efficiently solves the challenge of implementation of floating-point
addition and multiplication using the multi threshold voltage technique. The proposed technique
reduces the power consumption using the multi Vt method while keeping the area optimized. It also
enables time critical paths to be swapped by low Vt cells easily. It improves performance without an
increase in power. Also, there is significant reduction (up to 80 percent) in leakage power with a small
impact to timing.

8. List the merits and demerits of the proposed and existing techniques/hardware.
Ans:

Merits and Demerits of Existing Technique:

Merits:

• Existing technique is very easy for fabrication.

• Design time is very less.

Demerits:

• It uses more power.

• Its implementation acquires more area.
• There is waste of power in leakage.
• It is slow.
Registration No.-17BEC0813
Name- Atul Kumar Dwivedi

Merits and Demerits of Proposed Technique:

Demerits:

• Flip side of this technique is that Multi Vt cells increase fabrication complexity.
• Improper optimization of the design may utilize more Low Vt cells and hence could
end up with increased power

Merits:

• enables time critical paths to be swapped by low Vt cells easily.

• improves performance without an increase in power.
• significant reduction (up to 80 percent) in leakage power with a small impact to
timing.
• It is fast.

9. List the application of proposed design.

Ans: Application of the proposed architecture is as follows:

• Mobile application in idle state.

• Sub-threshold leakage current
• In power Gating:
o Low Vth Transistors for High performance Logic Gates
o High Transistors for Low Leakage Current Gates.
• Reduction in power leakage.
Registration No.-17BEC0813
Name- Atul Kumar Dwivedi

10. Draw the flowchart or algorithm or transistor level circuit proposed in the design in
Encapsulated PostScript (EPS) file format.
Ans: I have drawn the flowchart in MS word, and then I have converted it into EPS format. Both will
be available in the Google Drive link that I will send through mail.

Flow chart of IEEE Floating point multiplier:

Registration No.-17BEC0813
Name- Atul Kumar Dwivedi

Flow chart of IEEE Adder and Subtractor:

1. Compare the exponents of the two numbers.

Shift the smaller number to the right until its
exponent would match the larger exponent.

2. Add the Significands

3. Normalize the sum, either shifting right and

incrementing the exponent or shifting left and
decrementing the exponent.

4. Round the significand to the appropriate

number of bits.

Note: All editable flowcharts/architectures will be available in the google drive.