Design of 300W Interleaved Two-FET

Forward Converter with

Synchronous Rectification

By

Juan C. Dela Cruz

A Practicum Submitted to the School of Graduate Studies in

Partial Fulfilment of the Requirements for the Degree of

Master of Engineering Program in Electronics Engineering

Mapúa University

March 2014
 TABLE OF CONTENTS

TITLE PAGE

TABLE OF CONTENTS i

LIST OF TABLES iii

LIST OF FIGURES iv

Chapter 1: INTRODUCTION 1

Chapter 2: REVIEW OF LITERATURE 3

Two – FET Forward Converter 3

Synchronous Rectification 7

Interleaving 10

Voltage Mode vs. Current Mode 13

Chapter 3: METHODOLOGY 16

Introduction 16

AC – DC Block Design 18

Design of the Two-FET Forward Converter as Open-loop 23

Primary Switch 26

Synchronous Rectifier (Forward and Freewheeling MOSFET) 28

Power Transformer Turns Ratio 30

Design of the Output Filter 31

Design and Construction of Magnetics 34

Open Loop Circuit 42

Design for the feedback loop circuit 44

Design controller, gate-driver, and housekeeping (OVP, OCP, OPP) circuits48

i
 Design of Auxiliary Power Supply 49

Design of PWM Controller 52

Primary Switches Gate Drive Control 53

Synchronous Rectifier Gate Drive Control 56

Housekeeping Circuitries 60

Testing and Data Acquisition 64

REFERENCES 68

APPENDICES

ii
 LIST OF TABLES

Table 2.1 Two-FET reset operation 6

Table 3.1 Two-FET Forward Converter Design Specification 25

Table 3.2 Physical Characteristics of Kool Mu 77935-A7 37

Table 3.3 Transformer Core Specifications 40

Table 3.4 Primary Winding Specifications 42

Table 3.5 Auxiliary Power Supply Specification 51

Table 3.6 Pin Description of FAN3225C 58

Table 3.7 Line Regulation at Full Load 64

Table 3.8 Line Regulation at Half Load 65

Table 3.9 Line Regulation at No Load 65

Table 3.10 Load Regulation at Maximum Input Voltage 65

Table 3.11 Load Regulation at Typical Input Voltage 65

Table 3.12 Load Regulation at Minimum Input Voltage 66

Table 3.l3 OVP Testing 66

iii
 LIST OF FIGURES

Figure 2.1 Circuit Diagram of Forward Converter 3

Figure 2.2 Two-FET Reset Technique 5

Figure 2.3 Two-FET reset waveform 6

Figure 2.4 Basic Voltage-mode Control Circuit 14

Figure 2.5 Basic Current-mode Control Circuit 14

Figure 3.1 General Design Flow Chart for DC-DC conversion 17

Figure 3.2 AC – DC Block Schematic Diagram 18

Figure 3.3 VSIB2580 Single-Phase Single In-Line Bridge Rectifiers 19

Figure 3.4 Equivalent Circuit of VSIB2580 20

Figure 3.5 LGG2G102MELC50 Aluminum Electrolytic Capacitor of Nichicon 21

Figure 3.6 Power Stage Design Procedure Flowchart 23

Figure 3.7 Interleave Two-FET Forward Converter with Synchronous Rectification 25

Figure 3.8 STY139N65M5: (1) Gate, (2) Drain, (3) Source 27

Figure 3.9 STTH3R06 Turbo 2 Ultrafast High Voltage Rectifier 28

Figure 3.10 IRFSL3206PbF HEXFET Power MOSFET 29

Figure 3.11 16ZL120MEFCT1 6.3x11 34

Figure 3.12 Kool Mu Core Selector Chart 36

Figure 3.13 Permeability versus DC Magnetizing Force Curve, Kool Mu Cores 38

Figure 3.14 TDG PQ 32/20 Core Dimensions 40

Figure 3.15 Open-Loop Interleave Two-FET Forward Converter 43

with Synchronous Rectification

Figure 3.16 Design Flow Chart of the Feedback Loop 44

iv
Figure 3.17 Type 2 Error Amplifier Configuration 46

Figure 3.18 Design Flow Chart for controller, gate drive and housekeeping 48

Figure 3.19 Auxiliary Power Supply Circuit 50

Figure 3.20 GBPC-W Bridge Rectifier 50

Figure 3.21 Capacitor 35YXF33MEFCT1 51

Figure 3.22 Voltage Regulator MC7815AB 51

Figure 3.23 UC28025 N Package (Top View) 52

Figure 3.24 UC28025 Voltage Mode Control 53

Figure 3.25 Implementation of Gate Drive Transformer 55

Figure 3.26 FAN3225C Dual 4-A High-Speed, Low-Side Gate Driver 57

Figure 3.27 Pin Configuration of FAN3225C 57

Figure 3.28 Switches and Synchronous Rectifier Conduction Pattern 59

Figure 3.29 Implementation of Synchronous Rectifier Controller 60

Figure 3.30 Overvoltage Protection Circuit 61

Figure 3.31 LM 311 61

Figure 3.32 Overcurrent Protection Circuit 62

Figure 3.33 OVP and OCP integration 63

v
 Chapter 1

INTRODUCTION

Every design engineers pursue of having a reduced design of forward converter to achieve

higher efficiency at lower cost. It is business after all but reduction of design means smaller

components which promise a lot of advantages. Vis-à-vis to global change design engineers must

pursue reduction of design which today’s demanding market is expecting. But this goal is

unachievable as long as there is as existing large ripple current. Power dissipation of capacitor

depends on the amount of ripple it receives. If the capacitor conducts ripple current, it is dissipating

I^2 * ESR, where I is the ripple current and ESR is the equivalent series resistance of the capacitor.

The larger the ripple, the more heat is in the capacitor and which results to lower efficiency. With

this issue, design engineers should employ mechanism in the circuit that could address issues of

lower efficiency and design reduction.

Interleaving forward cells is used to address the issue of ripple current. However, based on

the study presented by J. Zhao, et.al., interleaved forward converter imposes disadvantages as well

such higher voltage stresses in switches and additional components for resetting transformer [1].

Thus, a suitable reset technique should be utilized. On the other hand engineers utilizing

synchronous rectification must consider shortening dead time between switches because body

diodes of MOSFET at higher frequency can still lessen the efficiency of the overall converter due

to voltage drop and reverse recovery characteristics of the body diodes of MOSFET’s.

Interleaved two-switch forward converter can be a good preference in studying better

combination of reset technique and interleaving which could lead to higher efficiency instead of

1
complicating the design with RCD reset, active clamp or having high cost using third winding.

There is also a need to investigate the importance of having a 45° phase margin and

-10dB gain margin. Setting phase margin and gain margin would help in designing as well as

maintaining stability of the closed-loop system.

The main purpose of this study is to build a 300W Interleave Two-FET forward design. It

specifically aims to construct a 400Vdc input and 12Vdc output considering a minimum 87%

efficiency. Synchronous rectification must be applied with analog controller to ensure higher

efficiency. To ensure stability, the design must maintain a 45deg phase and -10dB gain margin

from minimum and maximum load. Furthermore, it utilizes basic protection of circuits such as

Over Voltage Protection (OVP), Over Current Protection (OCP) and Over Power Protection

(OPP). The design must also give emphasis on proper PCB layout coordinated with industry

standards.

Through the utilization of the two-FET forward design can achieve a lower voltage stress

on MOSFET at Vinmax and 50% maximum duty ratio. The lower voltage stress can definitely

protect switches from damages. Also, the study could be a reference to power supplies companies

in providing high-efficient and good performing forward converters. The study would also

significantly assist further research of new topologies that could to improvement of performances

of present converters.

The main focus of the study is the design and construction of interleave two-FET forward

converter with synchronous rectification. There is no electromagnetic compatibility (EMC),

reliability and safety test to be conducted. Cost of design will not be validated in the study.

2
 Chapter 2

REVIEW OF RELATED LITERATURE

Two – FET Forward Converter

A forward converter is basically an isolated buck converter. It is known by its simplicity

and high efficiency. Such topology is being isolated by inserting a transformer. Unlike the flyback

converter which temporarily stores energy before transferring it to the secondary, the forward

converter directly transfers the energy between the primary and secondary. As stated by C. Arboy

and B. Cousin, isolated buck converter which is basically a forward converter has three advantages

[2]. First, it can prevent a possible electric shock. Second, a large voltage difference between input

and output voltage is made possible. Lastly, a smaller input power can be utilized compared to an

ordinary buck converter. The key reason for all of this is the transformer. The transformer is

basically the heart of the converter. Just like the human heart, without it the whole converter is

dead and it won’t function as what it should do. And just like any isolated converter, a forward

converter must have a reset winding which would adhere in demagnetization of the transformer.

Figure 2.1 Circuit Diagram of Forward Converter

3
 Fig. 2.1 shows the circuit diagram of a forward converter [3]. As an aid in understanding

the operation of the converter, the steady state characteristics of individual states of the switches

will be examined. When T1 switches ON, the primary winding will be energized. Therefore, the

dots of both windings will have the same polarity which forward-biased D2. The transformed input

voltage at the secondary winding will charge the choke. As a result, a linearly increasing current

flows to the choke and the load. And when T2 switches OFF, the current can no longer flow to the

primary winding. The polarity of the magnetic components reverses and which reverse-biased D2

so that as there is no longer input voltage at the secondary there would be no longer current flowing

from secondary winding to load via D2. In this case, the energy stored in L1 is transferred to the

load via D3. The current at the choke in this case decreases linearly. The core of the transformer

is magnetized due to magnetizing current that is why there is a need to demagnetize the core for it

might get saturate after few switching cycles.

Forward converter operates step-down conversion just like buck covnerter. The magnitude

as to how it down-convert a given voltage is basically determined by the turns-ratio of the

transformer. The forward converter therefore doesn’t need to have a small duty cycle to obtain a

low output voltage. Otherwise, efficiency would be lessened and every designer doesn’t want to

happen. With the aid of the turns-ratio, the converter would no longer require an impractical low

duty cycle.

The primary winding and the secondary winding of the forward converter conducts at the

same time. With this, the transfer on energy from the primary to secondary is a direct one, and that

explains how it got its name. The simultaneous conduction also leads to an almost complete

cancellation of flux inside the core. As a buck converter itself, it cannot exceed a duty cycle of

4
50%. Aside that it would already boost if exceeds but also it would ensure demagnetization. If

exceeds, then transformer would have a tendency to saturate, leading to efficiency loss.[4]

Demagnetization is a requirement in forward converter because without it the current

would build up in every cycle and may lead the core into saturation. Therefore, reset techniques

must be implemented because there is a need to “dispose” energy in the magnetizing inductor. One

of the reset techniques used by designers nowadays is a two-switch reset.

The two-FET forward converter uses two diodes to demagnetize so that no auxiliary

winding will be used. Fig. 2.2 shows the two-switch reset circuit diagram.

Figure 2.2 Two-FET Reset Technique

Fig. 2.3 and Table 2.1 illustrate the operation of the two-switch reset. The whole switching

operation is in DCM mode. At step 1, switches Q1 and Q2 are in on state. In this case, D1 is in on-

state and D2, D3 and D4 are in reverse bias. Magnetizing in this case is increasing. Step 2 operates

part of the 1-D portion of the total time of operation, meaning the whole time of demagnetization.

In this case, Q1 and Q2 are in off-state. In the other hand, D2, D3 and D4 are in on-state. Contrary

to step 1, magnetizing current is decreasing simply because reset is expected. Lastly, step 3 is the

remaining part of the 1-D where the magnetizing current is zero. In this part, D2 is in on-state and

Q1, Q2, D1, D3 and D4 are in off-state.[5]

5
 Table 2.1 Two-FET reset operation

Q1 and Q2 D1 D2 D3 and D4

Step 1 (On-Time) On On Off Off

Step 2 (Off Time) Off Off On On

Step 3 (Off Time) Off Off On Off

Figure 2.3 Two-FET reset waveform

Two-FET reset is advantageous because it is very easy to implement. And since the two

switches are in series, Vds would equal to Vin. In this case, switches would be protected from being

damaged. But there are also designers don’t like the fact that the two-switch reset requires high-

side driver for Q2 as well as losses incorporated from adding D3 and D4. But if you are concerned

with the protection of switches, then two-switch reset technique is favourable.

Two-FET forward converter is favourable as well because it is able to reduce the voltage

stress of the switches. Therefore, the Two-FET forward converter is commonly used in market

such as in Europe or in the Philippines where the AC voltage is 220V (rectified DC voltage is

nominally 308V) instead of the single-ended forward converter. It is pointed out that the voltage

stress of the switches can be as high as 550V in the single-ended forward converter operating

6
120Vac considering 15% transient above a 10% steady-state high line and a 30% leakage spike.

Although there may be transistor can be as high as 650V rating, but still most of the designers

prefer reliability overriding high cost.

Also, two-FET forward converter is advantageous for the energy in the leakage inductance

is not dissipated in any resistive element. Instead, because of its reset scheme, the energy stored is

delivered back to the input source. There is also no leakage inductance spike because the transistor

is not subjected to twice of the input DC voltage.

Synchronous Rectification

The main components used in the primary side of a typical forward converter are the

primary coil of the forward transformer, the switch which is mainly a MOSFET, a demagnetizing

coil, and a clamp circuit. For the secondary side of a typical forward converter, it consists of a

forward diode, a freewheeling diode, and the capacitor. However, in more recent forward converter

topology, the diodes in the secondary side are replaced by a MOSFET which are operated as

“synchronous rectifiers” (SR). The theory about this concept is that, the contribution of the

conduction loss of a rectifier diode is significant to the overall power loss of the power supply

especially for low voltage range, high current converters. Since the conduction loss of the

rectifying diode is the product of the forward-voltage drop and forward conduction current,

replacing the diodes by a MOSFET lowers the equivalent forward-voltage drop, hence as a result,

reduction in the conduction loss can be obtained. Although SRs using MOSFETs which are active

devices, the gate driving method and proper timing are critical for obtaining high efficiency [6].

Given that synchronous rectifiers are more efficient to use than the rectifying diodes, the

gate driving method is an integral part concerning synchronous rectifiers. Of all the methods that

7
have been researched, they can be classified into two groups which are self-driven and control-

driven. Briefly, self-driven SRs are driven directly from the output voltage of the secondary coil

of the forward transformer while control-driven SRs, as the name implies, are driven by gate drives

signals from the gate-drive of the main switch. And therefore, the approach of the self-driven SR

is simpler although its performance depends on the resetting method of the power transformer

because the freewheeling SR is driven by the reset voltage [7].

In detail, self-driven SRs are driven by the voltage of the secondary coil of the transformer;

it is consequently dependent on the transformer resetting method. Hence the process how the

transformer is reset, or the circuit used to control the resetting of the transformer affects the self-

driven synchronous rectifiers. For forward converters with RCD clamp, the SRs are cross-coupled

to the secondary winding if the transformer directly, making it the simplest implementation of

synchronous rectification, however, its performance is dependent on transformer core resetting

since the gate-drive signal is derived from the secondary voltage. Ideally, the desirable resetting

time is equal to the off-time of the primary switch then the entire output current would freewheel

through the SR for the entire off-time (freewheeling time). Although, this is an ideal case, hence

active clamp resetting was studied. The active clamp reset approach minimizes the duration of the

dead time since the transformer core is reset during the off time of the main switch. This results to

the maximized conduction time of the freewheeling transistor, and the time that the body diode of

the forward transistor conducting magnetizing current is minimized. Therefore, the active-camp

has improved conversion efficiency compared to the RCD clamp. Active-clamp approach also

minimizes voltage stress on the main switch and the main switch can be turned on at zero voltage

by properly adjusting the magnetizing inductance of the transformer. Although, active-clamp

requires extra switch and gate drive, hence it is much practical to implement a parallel Schottky

8
diode to the diode in RCD to improve the efficiency of the RCD-clamp circuit than utilizing the

active clamp. In conclusion to these facts, active-clamp is an approach for voltage stress and soft-

switching synchronous-rectifier applications.

For forward converter with control-driven SRs, the MOSFETs are driven by gate drive

signals derived from the primary switch gate drive. This results that the SR conduction times are

independent of transformer core resetting method and dependent only on the timing of gate drive

signals. However, while driving the SRs from the control circuit results in the maximum

conduction time of the freewheeling MOSFET, it has no effect on the conduction time of the

magnetizing current though the body diode of the forward MOSFET during the dead time. Ideally,

the gate-drive timing of SRs should allow no conduction of the body diodes of the SRs except for

the unavoidable conduction of the body diode of the forward MOSFET during the dead time. The

possibility for this is for the gate-drive timing where the gate-drive of one SR is applied or

terminated at the same instant the gate-drive of the other SR is terminated or applied to be very

precise, but in practical situations, ideally complementary drive is not possible. The critical part

when using control-driven SRs is that its performance is greatly dependent on the precise timing

of the gate drives to avoid unwanted additional losses in the system.

It should be noted that the conduction of the body diodes of self-driven SR method and the

reverse recovery affects the over-all efficiency of the system. The only method known to cure such

issue is to use Schottky diode parallel to the SR MOSFET. Meanwhile in control-driven scheme,

it might eliminate most of the loss of body diode (Note: body diodes conduct during dead time)

but driving the SR MOSFET is very tricky and requires great timing of the gate drive. [8] But

basing to high efficiency, control-driven wins.

9
Interleaving

To greatly improve the performance of power supply converters in general, paralleling

technique is devised, wherein instead of utilizing a high power bulky transformer, two transformers

are used in parallel connection to divide the high power input, therefore relieving stress to the

transformers used by dividing the total input power to two separate transformers instead of

applying it to only one. Not only to transformers do paralleling technique gives advantages but

also to magnetic components, and this technique helps reduce the power losses and thermal stresses

of components that are supposedly subjected to it hence, the technique eliminates “hot spots” in

the system. Since relatively smaller materials and components are used especially for transformers,

coils, and bulk capacitors, higher-power density and low-profile packaging can be achieved. There

are various forms and method on how to use paralleling technique and one that is most famous for

the power supply industry is the technique called “interleaving”.

Interleaving is a variation of paralleling technique that is widely used in converters with

applications in personal computer industry, in voltage regulation modules application to power

central processing units and the likes. Primarily, this topology is widely used because it reduces

the input and output capacitor ripple current. The reduction in input and output capacitor RMS

currents allowing reduction in the input and output capacitor banks that is required for the design

[9]. The concept of interleaving enables converter topologies to operate at increased power levels.

Some of the benefits of interleaving include: Reduced RMS current in the input capacitors enabling

the use of less expensive and fewer input capacitors, ripple current cancellation in the output

capacitor, enabling the use of less expensive and fewer output capacitors, reduction of peak

currents in primary and secondary transformer windings (two choke interleaved forward

converter), improved transient response as a result of reduced output filter inductance and higher

10
output ripple frequency, separation of heat generating components allowing for reduced heat sink

requirements, improved form factor for low profile solutions, and reduced EMI as a result of

reduced peak currents (two choke interleaved forward converter) [10]. A two phase interleaved

forward converter is just simply two forward converters operating 180 degrees out of phase. The

main and primary reason why interleaving is implemented because of the reduced input and output

capacitor RMS, the concept behind this reason is that, the design must provide lower ripple at the

input and especially the output because forward converters are basically DC-DC converters, and

the fact that if ripple exist in the input or the output, it is not purely DC, hence, an RMS portion is

incorporated in the input and output which is undesirable.

The operation of the interleaving technique, which can be viewed as a variation of the

paralleling technique, is that the switching instants are phase-shifted over a switching period. By

introducing an equal phase shift between the paralleled power stages, the output-filter-capacitor

ripple is lowered due to the ripple cancellation effect. At the same time, the effective ripple

frequencies of the output-filter-capacitor current and the input current are increased by the number

of interleaved modules. As a result, the size of the output filter capacitance can be minimized,

hence, higher-power density. Implementation of the interleaving technique is done in two ways;

two-choke approach and one-choke approach.

The two-choke approach is an interleaving approach that is to directly parallel the outputs

of the individual power stages so that they share a common output filter capacitor. This approach

distributes the transformer and output filter magnetics. In the implementing the reset of the

transformers, it is done by the resonance between the magnetizing inductance of the transformers

and the output capacitance of the MOSFETs (including external capacitance), or by an RCD-clamp

reset circuit whichever is desired [11]. Since the two modules operate in anti-phase with duty

11
cycles less than 50%, the current-sharing among the modules is ensured by employing the current-

mode control. The operation is identical to that of the single resonant-reset or RCD-clamp reset

forward converter. This makes interleaving reduces the ripple current through the common output-

filter capacitor.

The one-choke approach however is to parallel the power stages at the input of a common

LC output filter. This approach distributes the transformer magnetics only unlike the two-choke

which also distributes the output filter magnetics. Because in the one-choke interleaved forward

converter the two modules share the same freewheeling diode and output filter, these two modules

do not work independently. In fact, the operation of two interleaved forward converters with one

choke is quite different from that of the two-choke interleaved converters. Therefore, logic and

timing are required for proper functionality of the one-choke approach [12].

Due to its distributed-magnetics structure and minimum-size output filter, the interleaving

approach is especially attractive in high-power applications that call for high power-density and

low-profile packaging. Although with proper design, both two-choke approach and one-choke

approach may provide desirable outcomes, the two-choke approach promises simpler design since

no logic and timing are required unlike one-choke approach. But still one-choke approach offers

simplicity in design in terms of fewer components utilized. Therefore, it is up for the designer to

decide what approach will be utilized.

Voltage Mode vs. Current Mode

The basic voltage-mode control circuit can be shown in Fig.2.4. In this control circuit, the

power transistor or output current is not sensed directly. A portion of the output voltage (i.e. KVo)

is fed at the error amplifier and to be compared with Vref. Output of the comparator, Vea

12
determines the duration of the pulse of Vpwm. Vpwm is produced by the PWM voltage

comparator. In the PWM voltage comporator, the sawtooth Vst is fed to the non-inverting input

and the Vea is fed to inverting input. The sawtooth is produced by a fixed internal clock. The

period of the sawtooth is determined by T = Rt * Ct.

Vpwm affects the output voltage which is why the correct duty cycle must be produced by

the PWM so that the desired output voltage will be met and regulated. When the output voltage

rises up, the duration of Vpwm shortens. In contrary, when the output voltage decreases, the

duration of the Vpwm lengthens.

Figure 2.4 Basic Voltage-mode Control Circuit

The voltage-mode control basically rely on the ESR of the capacitor to ensure “loop

stability”. Take note that loop stability basically refers to the quick regulation of the output even

there is an undue ringing or oscillation. [13]

There is also a current-mode control which is shown at Fig. 2.5. Unlike the previous

control mode, the current-mode derives its PWM from the inductor or switch current.

13
 Figure 2.5 Basic Current-mode Control Circuit

The current-mode control circuit has two feedback loop – the outer loop is used for

sensing the output voltage and the inner loop which sense the primary peak current and the current-

sensing Ri which converts the ramp-on transistor step current into ramp-on step voltage. It can be

seen in Fig.2.5 that portion of the output voltage is fed back to the error amplifier. The output of

the error amplifier Veao is fed to the PWM comparator at the non-inveting input with the Vi at the

inverting input. The production of pulses useful at the operation is produced at the RS flip-flop.

One of the advantages of current-mode is having a constant average current waveform at

the input of the LC filter. With this, there is no need for the output inductor to change in phase. In

other words, the inductor cannot affect the change in phase of the forward cell. Other sources also

suggest that the current-mode is capable for a good line regulation and elimination of flux

imbalance at the transformer.

14
 Chapter 3

Methodology

A systematic way in attaining the goal of this study is presented in this chapter. The

trickiness of timing the gate drives for primary and SR MOSFET’s must be considered to avoid

overlapping which may cause losses.

The gain and phase margin requirement will also be the basis for designing the project

particularly in feedback loop.

Fig. 3.1 shows the over-all design flow chart of the two-FET forward converter. The study

initially starts with designing of the open-loop/Plant of the system. The first stage of the study

basically determines the bridge rectifier intended for AC to DC conversion, the construction of the

Two-FET forward cell which includes the proper choices of the semiconductors and suitable

magnetic design for the transformer. The first stage also must take into account the construction

of synchronous rectification as well as the interleaving technique as a requirement. In this stage

also computes for the output inductor and capacitor that serves as the output filter. After the

construction, testing will be followed. Bode plot will be produced as well.

The second stage is the design of the Feedback added to the Plant or the power stage to

complete the closed-loop. The construction of the compensator/Feedback is dependent on the Bode

plot of the Plant. In this study, the Type 2 error amplifier is chosen to meet the minimum -10dB

gain margin and 45˚ phase margin. The second stage also will be tested and which also includes

the Bode plotting.

15
 START Integration &
Controlled
Simulation of
the Whole
Design of the Two-FET System
forward converter as open
loop
PCB Lay-out
and
construction of
Design of
whole system
feedback
hardware
loop
circuit

Data
Acquisition
Design controller,
gate-driver, and
housekeeping (OVP,
OCP, OPP) circuits Finalization of
prototype
aesthetic

END

Figure 3.1 General Design Flow Chart for DC-DC conversion

The third stage of the study is the construction of the circuitry of the housekeeping (i.e.

OVP, OCP and OPP), the gate driver transformer and the PWM controller. Though included in the

over-all output, these do not necessarily affects the Bode plot of the closed-loop system. Testing

will be followed then.

16
 After the first three stages, they will be integrated and tested to know if the integration of

the different stages will harmonize each other and work to produce the intended output with the

given specifications. During this stage, it has to be made sure that everything required of the study

will be met. If this stage works fine, PCB lay-outing and prototyping will be followed. The

last two stages include data acquisition and finalization. In this stage, the required characteristics

and output of the whole system must be produced considering that the circuit is already in PCB.

Final adjustment must be done to make sure that the prototype works as what it is expected.

AC – DC Block

BRDG_RCT
MAIN_LINE
AC
VIN+
R
+
BULK

VIN-

Figure 3.2 AC – DC Block Schematic Diagram

Fig. 3.2 shows the schematic diagram of the first stage of the power supply which is the

AC – DC converter stage. The established input that will be implemented in this study is the

220VAC/60Hz main line supply. The needed input voltage of the interleaved two-FET forward

converter is 300VDC. The goal here is to provide a DC input voltage for the power stage with a

small amount of loss as much as possible.

17
 From the main line which is 220VAC, as shown in Figure 3.2, the bridge rectifier will

rectify the AC input voltage to convert voltage into a pulsating DC signal. As the signal passes

through the bridge rectifier, the peak voltage, VP, of the pulsating DC signal is calculated as shown

in the computation below.

= √2 ×

= √2 × 220 = 311.127

Since there will be voltage drop across the diodes due to its forward voltage in the bridge

rectifier, the output voltage will be VP minus the forward voltage rating of the chosen bridge

rectifier. As mentioned earlier, a small amount of losses must be considered in choosing the

components that will be used. For the bridge rectifier, VSIB2580 of Vishay General

Semiconductor will be utilized, shown in Fig. 3.3.

Figure 3.3 VSIB2580 Single-Phase Single In-Line Bridge Rectifiers

VSIB2580 is a single-phase in-line bridge rectifier of Vishay General Semiconductor is a

General purpose use in AC/DC bridge full wave rectification for switching power supply. It has a

low forward voltage rating that is only 1.0V, relatively lower than other bridge rectifiers. Other

18
parameters of VSIB2580 that are in favor for the design are the forward current which is rated

to 25A, IFSM of 350A and VRRM of 200-800V.

Figure 3.4 Equivalent Circuit of VSIB2580

Fig. 3.4 shows the equivalent circuit of VSIB2580. Taking into account the forward voltage

drop of the bridge rectifier, the peak voltage will now be,

= − − = 311.127 − 1.0 − 1.0 = 309.127 ≈ 310

Therefore, the input voltage of the bulk capacitor will be roughly around 310VDC. Notice

that the input voltage of the power stage is the potential across the bulk capacitor. The aim of the

capacitor is to filter the AC component of the pulsating DC output of the bridge rectifier, and

provide a somehow constant direct current voltage to the input of the power stage. The critical

parameters that must be met to choose the proper capacitor is that it can handle and store large

amount of voltage, as high as 310VDC, and provide an almost constant output of 300VDC. The

capacitor that will be used as the bulk capacitor is LGG2G102MELC50 of Nichicon, shown in

Fig. 3.5 below.

19
 Figure 3.5 LGG2G102MELC50 Aluminum Electrolytic Capacitor of Nichicon

LGG2G102MELC50 is an aluminum electrolytic capacitor that is a snap-in

terminal type of electrolytic capacitor of GL series of Nichicon. It has a voltage rating of 400VDC

and a capacitance rating of 1000uF. The voltage rating of this capacitor is just enough to handle,

and store the input and output voltages which are 310V and 300V respectively. Another parameter

of selection is the availability of material, since the higher the rated voltage is, the lower the

capacitance gets. But it is ideal to have high capacitance to reduce the effect of ESR; therefore the

selection was mainly a factor of rated voltage and the value of the capacitance. It is expected that

the voltage across the bulk capacitor will have ripple since the conversion is not stringent enough

to provide perfect DC.. Therefore, the capacitance and equivalent series resistance (ESR) can be

determined using the following formula, where frequency, f = 120Hz.

1 1
= = = 8.3333Ω
× 1000 × 120

The above computation shows the computation of the equivalent series resistance of the

bulk capacitor which is 8.3333Ω. As shown in Fig. 3.2 the a bleeder resistor is present before the

bulk capacitor. The bleeder resistor and ESR of the capacitor will provide the 300V required output

of the capacitor, which is the input of the power stage. The value of the bleeder resistor is calculated

as shown in the computations below.

20
= ×
+

= −1 ×

310
= − 1 × 8.3333Ω
300

= 277.777 Ω

21
 Design of the Two-FET Forward Converter as Open-loop

START
Determination of
Design
Specifications
Design of two-FET
Forward Primary Switch
and Synchronous
Rectifier Parameters Selection of the
MOSFETs used as
Primary Switch,
Design of the Forward Rectifier
Interleave Forward and Freewheeling
Converter Topology Rectifier

Calculation of Output
Calculation of Power
Filter Parameters
Transformer Turns
Inductance and
Ratio
Capacitance

Simulation of
Calculated Values in
SIMPLIS

Does the result of the YES Design and

NO
simulation coincide Construction of
with the expected Magnetics
results?

END

Figure 3.6 Power Stage Design Procedure Flowchart

22
Design Procedure

This section discusses the precise methodology and procedure to design a 300W

interleaved two-FET forward converter with synchronous rectification achieving 87% efficiency.

Figure 3.6 shows the power stage design procedure flowchart wherein the methodology in the

design of the plant. To jump start the procedure, the first thing that must be accomplished is the

design of the forward converter alone using the required topology which is two-FET forward

primary switch and the synchronous rectification. To be able to accomplish this stage, the design

specifications must be established, the MOSFETs used for primary switches and synchronous

rectification must be selected, and the transformer turns ratio must be computed. After calculating

the parameters of the two-FET forward primary switch and the synchronous rectification, the

output filter stage will be designed. This stage will complete the design of the interleaved two-

FET forward converter with synchronous rectification. The design will then be simulated, and if

the design provides the expected output, the process continues, or else, it will be redesigned. After

which, the design of magnetics of the plant, the power transformer and the output inductor,

terminates the procedure.

Design of the Two-FET Forward Converter Topology with Synchronous Rectification

The objective of this study is to design a 300W interleaved two-FET forward converter

with synchronous rectification. The schematic diagram is shown below in Fig. 3.7. To be able to

accomplish this objective, the first step is to design a single rail of forward converter to establish

the design of the two-FET switch at the primary side of the power transformer and the synchronous

rectifiers in the secondary side.

23
 +VIN

SW1
LOUT
VOUT+
D1
TX1
+
SR2
P1 S1 COUT
D2

VOUT-
SR1
SW2
PWM_DRVA
-VIN

SR1_GATE_DRV SR2_GATE_DRV
SW3

D3
TX2

P1 S1
D4

SR3
SW4
PWM_DRVB

SR3_GATE_DRV

Figure 3.7 Interleave Two-FET Forward Converter with Synchronous Rectification

Design Specifications

The parameter specifications to be used in the design are listed in the table below.

Table 3.1 Two-FET Forward Converter Design Specification

Design Specifications
Required Output Power (Pout) 300W
Expected Efficiency (η) 0.87
Regulated Output DC Voltage (Vout) 12V
Regulated Output DC Current (Iout) 25A
Duty Cycle (D) 0.45
Switching Frequency (fsw) 70kHz

24
 Given the following required output power and efficiency, the common 12V DC regulated

voltage and 25A DC current were adopted as output parameters. The duty cycle of the operation

was selected with respect to the minimum and maximum allowed duty cycle that the controller can

operate. The frequency of the switches was decided based on common operation of forward

converters.

The input power of the forward converter will be,

300
= = = 344.828 ≈ 345
0.87

= 300 as the input of the DC-DC converter from the output of the AC-DC conversion

block. Since the output of the AC-DC conversion block is not fully DC, a 5% ripple is assumed to

determine Vin max and Vin min.

= − 5% = 300 − 5% = 285

= + 5% = 300 + 5% = 315

The current that passes through the primary winding and switches must also be calculated.

The input current can also be calculated as shown in the computation below.

=
×

345
= = 2.55
300 × 0.45

Primary Switch

The MOSFET that we are going to use at the Primary of the Two-FET forward converter

switch is the STY139N65M5 (Q1 and Q2, Q3 and Q4) as shown in Fig.. 3.8 which is N-channel
25
650 V, 0.014 Ω, 130 A, MDmesh™ V Power MOSFET in Max247 package from

STMicroelectronics. The MOSFET has Vdsss of 650V and has an Rdson of 17mΩ maximum. With

this, the power dissipation of the MOSFET would be limited to a low value and the capacity to

withstand voltage stress is high as compared to other MOSFET. Knowing that the scheme for

demagnetization is a Two-FET scheme, there will be no problem with voltage stress at the

MOSFET.

Figure 3.8 STY139N65M5: (1) Gate, (2) Drain, (3) Source

The of the primary switch MOSFETs can be calculated, since the DC input current,

, is already computed, and is given by the datasheet. Therefore, Vds on of the switches

are computed as shown below.

= × = 2.55 × 17 = 43.35

The calculated value of the will be rounded off to 100mV in succeeding calculations.

This is to provide safety margin for the of the MOSFET and to properly calculate the power

transformer turns ratio later in this chapter. The same MOSFET, STY139N65M5, will be used for

the primary switches. Therefore,

= = = = 100

The reset technique used in two-FET primary switch is by using diodes, D1, D2, D3 and

D4, as shown in Fig. 3.9. If the primary switch is turned off, the primary winding of the transformer

must be demagnetized, and for it to demagnetize, the diodes conduct to provide a path for

26
demagnetization. Since this is located on the primary side of the power stage, the reset diode must

be rated according to the proper specifications. The preferred diode that will be used for the reset

diode is the FFP30S60S of Fairchild Semiconductor. The FFP30S60S is STEALTHTM II rectifier

with soft recovery characteristics. It is silicon nitride passivated ion-implanted epitaxial planar

construction, rated VRRM of 600V.

Figure 3.9 STTH3R06 Turbo 2 Ultrafast High Voltage Rectifier

According to its datasheet, this diode provides ultrafast switching, low forward voltage

drop, low thermal resistance, and low leakage current due to its platinum doping. This diode is

suited for switching power supplies with a repetitive reverse peak voltage V RRM of 600V with low

forward voltage drop VF of only 1.6V, and average forward current IF of 30A, since this will be

the reset diode of the primary winding with an input of 400V. Also, this diode provides fast reverse

recovery time trr which only about less than 40ns according to the datasheet. Hence, this diode is

sufficient to be the reset diode of the primary winding of the power transformer.

Synchronous Rectifier (Forward and Freewheeling MOSFET)

The MOSFET that will be used as the synchronous rectifiers; SR1, SR2, and SR3 which

are the forward, freewheel, and interleaved forward MOSFETs, is shown in Fig. 3.10, the

IRFSL3206PbF of HEXFET Power MOSFET of the International Rectifiers. This MOSFET was

27
chosen because compared to other available power MOSFETs, the R ds on of this particular

MOSFET is below the common 5mΩ resistance. The nominal drain-to-source resistance is R ds

on(nom) = 2.4mΩ, while the maximum is Rds on(max) = 3.0mΩ which is still below the common value.

Another factor in choosing this MOSFET is because of its high efficiency in synchronous

rectification in SMPS application. Lastly, this MOSFET can also operate of high frequency

operation which is required in the design of the plant.

Figure 3.10 IRFSL3206PbF HEXFET Power MOSFET

To calculate the drain-to-source on voltage of the MOSFET, the Ids on must be established.

The current flowing to the forward MOSFET (SR1), and likewise for interleaved forward

MOSFET (SR3), is ideally equal to the current output of the single rail forward converter therefore,

the current flowing through the MOSFET is given, the voltage across the MOSFET can be

computed as follows, using maximum Rds on for worst case condition. Since the required output

power is half of the output power of single rail, and the regulated output voltage remains 12V, the

regulated output voltage which is also halved in the output of the single rail forward converter.

= = 25

( ) = ( ) × =3 × 25 = 75

28
 To provide safety margin in the design of the power transformer and the calculation of its

turns ratio, ≈ 100 is considered. The computation above reiterates that the chosen

MOSFET will provide lesser loss compared to other available synchronous rectifiers.

Power Transformer Turns Ratio

As shown in the schematic diagram of a two switch forward converter, Fig. 3.7, the

topology utilizes two (2) MOSFETs as primary switch. After calculating the voltage drop across

the switches and the forward MOSFET of the synchronous rectifier, Eq. (1) can be used to compute

for turns-ratio (Np/Ns) of the power transformer (T1).

= × (1)
∗

300 − 100 − 100

= × 0.45
12 + .45 ∗ 100

= 11.200498

≈ 12

Therefore, the ratio of the primary turn to the secondary turn is 11.200498 is to 1. For

ease of construction, the ratio will be rounded up to the nearest whole number. Hence, Np/Ns =

12.

Design of the Interleaved Forward Converter Topology

Figure 3.7 shows the schematic diagram of the interleaved two-FET forward converter

with synchronous rectification. Interleaving is a paralleling technique is a two phase interleaving

scheme where in the two single rails of forward converters are operated 180 o out phase. This

characteristic provides the advantages of interleaving in designing a switch mode power supply.

29
Design of the Output Filter

The output filter is one of the vital parts of the forward converter. The basic role of the

output filter is to filter out the AC component of the current and provide DC component of the

current that will supply the load.

Output Inductor

The output inductor is responsible to filter out the AC component of the output current to

supply only DC current at the output of the converter. To calculate the inductance of the output

inductor, the formula below is used. Dissimilar to the method of calculation of inductance in other

forward converters, wherein the switching frequency is used in the inductance formula, since the

topology of the converter utilized in this study is interleaved two-FET forward converter, the

frequency used in calculating the inductance of the output inductor is twice the switching

frequency.

Using = 40% × , the formula for the output choke inductance will be computed

using the formula shown below.

2.5(1 − )
=
×2×

2.5(1 − 0.45)(12)
=
25 × 2 × 70 × 10

= 4.7143

30
Output Capacitor

The output capacitor together with the output inductor completes the output filter

of the forward converter. Similar to the output inductor, the output capacitor is also an essential

part of the converter. The main objective of the output capacitor is to filter out the AC component

of the output voltage and deliver the DC component of the output voltage signal. In practical

applications, the output filter minimizes the ripple of the output voltage. To compute the

capacitance of the output capacitor, the output voltage ripple (V ripple) and the current peak to peak

(ΔIout) are calculated as follows. Similar to the output inductor inductance calculation, the

frequency used in computing for the output capacitor capacitance is twice the switching frequency

because of interleaving topology.

= (10%)

= (10%)12

= 120

∆ = (40%)

∆ = (40%)25

∆ = 10

∆
=
2 (2 × )

10
=
2 (2 × 70 × 10 )(120 × 10 )

31
 = 94.7351

To be able to properly choose the appropriate capacitor to use, another parameter needed

to be known is the equivalent series resistance of the capacitor, ESR. This equivalent resistance

can be computed by dividing the voltage across the capacitor by the current that passes through

the capacitor which are and ∆ respectively. Since is dictated by the amount of

resistance that the capacitor exhibits, therefore:

120
= = = 12 Ω
∆ 10

The rated voltage of the capacitor must be greater than the output voltage of 12V therefore

a 16V rated voltage is enough. Also, the computed capacitance value is 94.7351 but there is

no capacitor with exact value on the market hence, 100uF rated capacitor will be assumed. The

computed ESR value is the maximum allowable ESR to provide the capacitance required, therefore

the capacitor to be selected must have a maximum value of 12 Ω or less. Therefore, the selected

capacitor to be used for the output filter is the Miniature Aluminum Electrolytic Capacitor ZL

series rated 16V and 120uF with dimensions 6.3x11 shown in Fig. 3.11 below.

Figure 3.11 16ZL120MEFCT1 6.3x11

32
Simulation

To be able to test if these computed figures will yield to the expected outputs, this design

will be simulated through SIMPLIS. If there will be problems that will be encountered during

simulation, the issue will be addressed properly and if ever recalculations or redesign is needed, it

will be employed. If the simulation projects the expected results, then the magnetics that will be

used will be designed.

Design and Construction of Magnetics

The transformer and the output inductor will be design during this part of the study. It is

imperative to properly design the magnetics of every power supply; hence the magnetics part is

tagged as the very heart of every power supply especially the switch-mode power supplies

(SMPS). This is because in the magnetics component is where the conversion of energy takes

place.

Output Choke

The design of the output choke is critical since this is where conversion is present. The

crucial part of designing the output choke is the selection of the type of the core to be used. In the

determination of the core will determine the wire needed to be used. But before choosing a core,

the type of core must be defined first. There are numbers of possible types of output choke cores

that can be utilized in this study such as powdered cores, ferrite cores, amorphous cores, etc. For

this study, a powder toroid core is proposed for several advantages that powder toroid cores offer

over other type of cores. Also since powder toroid cores are commonly used for output chokes.

33
 To be able to properly choose the compatible toroid core that must be used, the first step is

to compute for the product of LI2 where:

L = inductance required

I = DC current

= (4.7143 )(25 ) = 2.9464 −

To narrow down the choices of the cores, Kool Mu cores will be considered in the selection

of the core for the output choke. This consideration is because of the high output current that will

flow through the output choke, therefore the wire that will be used to wind the output choke must

be able to carry the current. Since larger wire size, larger core must be considered, which means

the core’s permeability will be small and Kool Mu cores offer those considerations. Using the chart

in Fig. 3.12 below, the product of LI2 will be used.

Figure 3.12 Kool Mu Core Selector Chart

34
 From the Fig. 3.12, the Geometry factor will be obtained using the calculated product of

the inductance and mean current, LI2. It can be seen from the figure that the first core size that lies

above the diagonal permeability line for a product of 2.9464 − is 77590. But there will be

an issue of available cores if 77590, therefore 77935 core size will be considered. Though there is

another available core which is 77354, 77935 will still be considered because it has larger core

size. The curve in Figure 3.1.5 also shows that the permeability of the core will be 75µ; hence the

manufacturer part number of the core for Kool Mu that will be used is 77935-A7.

Appendix A shows the datasheet for 77935-A7 Kool Mu toroid core. According to the

datasheet, the corresponding inductance factor of the core with permeability of 75µ is =

94 1000 ± 8%. The physical characteristics of this core are shown in Table 3.2

below.

Table 3.2 Physical Characteristics of Kool Mu 77935-A7

Physical Characteristics of Kool Mu 77590-A7

Window Area (Aw) 1.56 cm2

Cross Section (Ae) 0.654 cm2

Path Length (le) 6.35 cm

Volume (V) 4.15 cm3

Area Product (AeAw) 1.020 cm4

Since

the inductance factor AL is already determined, the number of turns can now be calculated as

shown by the computation below. The inductance factor will be subtracted by its percentage

tolerance to determine the minimum inductance factor. In the datasheet of the core, it shows that

the core has a ±8% tolerance.

35
 = 94 − 8% = 86.48 1000

× 10
=

0.0047143 × 10
=
52.44

= 7.3833 ≈ 8

After computing for the number of turns, the magnetizing DC bias is computed as shown

below:

0.4
=

0.4 × 8 × 25
= = 39.58
6.35

After computing for the magnetizing DC force, the per unit of initial permeability will be

determined using the graph shown in Fig. 3.13. Note that this curve only applies for MPP core

products.

36
 Figure 3.13 Permeability versus DC Magnetizing Force Curve, Kool Mu Cores

From Fig. 3.13, a DC magnetizing force of 39.58 yields approximately 63% of

per unit of initial permeability. Therefore, the minimum inductance factor AL earlier which is

86.48 will be multiplied to 63% per unit of initial permeability which yields to a new minimum

inductance factor AL’ of 54.4824. Given this new minimum inductance factor, the required

inductance will be computed as shown below determine if the inductance of the core will not be

below the required inductance.

× ′
=
10

8 × 54.4824
=
10

= 0.0034869

37
 This inductance is below the required output choke inductance. To be able to acquire the

required inductance, the number of turns will be incremented. It was iterated and determined that

12 turns is the needed number of turns to obtain the required inductance, as shown below.

= 10

′ × ′ 10 × 54.4824
= = = 0.00544824
10 10

The next step is to select what type of wire to use. The wire table in Appendix B shows a wire

table. According to the wire table, the wire gauge that can carry 25A of current is the AWG #9 and

above. In reality, it will be hard to turn the AWG #9 to 12 turns manually. Therefore, smaller wire

gauge will be utilized in this study. Since the wire size of AWG #9 is 14,350 circular mils, there

will be 15 AWG #21, which has 1000 circular mils, needed to be twisted to be able to have an

equivalent wire size to that of AWG #9.

Power Transformer

The type of the power transformer to be designed is a Planar Transformer. The reason why

planar transformer is selected for this study is the several advantages that planar transformers have

to offer compared to the conventional transformer some of which are; smaller physical dimension,

higher power density characteristics, lower leakages, lower loss, ease of design and construction.

It is suitable to forward converter unlike flyback since the latter involves storing energy, thus it

needs a special way of controlling the transformer. In contrast, the property of forward converter

of needing a direct transfer of energy fits.

The core specifications are presented in Table 3.3. Important parameters are only shown

for the computation.

38
 Table 3.3 Transformer Core Specifications
Parameters Value
Core Type PQ 32/20
Core Material TPW33
Manufacturer TDG
Effective Area (Ae) 169 mm2
Effective Volume (Ve) 9440 mm2
E 27.5±0.5 mm
F 13.5±0.25 mm

Figure 3.14 TDG PQ 32/20 Core Dimensions

Firstly, Nsec is set to 1 to determine the number of turns for N pri. Since the turns-ratio n

from the power stage is 12, the Npri in this case will be:

Npri = 12 * Nsec

= 22 * 1

Npri = 12 turns

In other words, there will be 12 turns of primary for every secondary bus bar.

For us to determine the peak to peak flux density Bpkpk of the core, the formula will be used

is:

n(Vout  Vf )D
Bpkpk 
f Ae N pri

And from the equation, the value of Bpkpk for the transformer will be:

39
 12(12V  0.1V)(0.45)
B pkpk 
(70  10 3 kHz)(1.69  10 - 4 m2)(12)

B pkpk  1.026 T

From this, the actual number of turns for the primary that will be needed to achieve such

flux density will be calculated based on the formula:

min∗
=
∗ ∗

It must be noted that the frequency that the primary side “sees” is the same with the

switching frequency. Therefore, will be equal to 70kHz.

380 ∗ 0.45
=
1.69  10 -4 m2 ∗ 1.026 ∗ 70

= 15.20

From this, 24 turns will be adopted. Since Np = 24 turns, the number of turns that will be

used for Nsec will be equal to 24 / 12 = 2 turns or 2 bus bars. In this way, the transformer will be

able to maintain the necessary turns-ratio. This would also reduce the magnetic flux density with

0.64992 T consequently the magnetic losses will be decreased too.

Based on the dimensions of the core, the difference of E and F is equal to 7 mm, which is

the total distance that the wire can be wound. For safety and convenience, an allowance of 5% will

be imposed. In this case, the new distance will be 6.65 mm. With a maximum 8 turns, the maximum

diameter of the wire should be 6.65mm / 8 = 0.831. Table 3.4 shows parameters necessary for the

primary winding.

40
 Table 3.4 Primary Winding Specifications
Parameters Value
Type TIW-3
Manufacturer Totoku
Conductor diameter 0.64 ± 0.02 mm
Overall diameter 0.81 ± 0.04 mm

As for the secondary winding, since Nsec is three, it follows that there will be three single

turn bus bar. To increase current capacity, every set will be composed of two cupper bus bar in

parallel effectively will just make a one bus bar.

Open Loop Circuit

Fig 3.15 apparently shows how the open loop of the study would look like. In the figure

shown it illustrates the two forward converter trails with the controller and drivers necessary for

the switches.

41
 +VIN

SW1
LOUT
PWM_DRVA GDT1
R1_GDT1 VOUT+

D1 TX1
+
P1 S1 SR2
COUT
P1 S1
D2
Q_GDT1

R2_GDT1 VOUT-
SR1 10V_AUX
Q_NOR
S2
D_GDT1
SW2

C_GDT1

R3_NOR
-VIN
R1_NOR R2_NOR
R_SR1
C_NOR
PWM_DRVA
SW3
PWM_DRVB PWM_DRVB
GDT2
R3_GDT2
INA+ INA-
TX2
D3 SR1_GATE_DRV
P1 S1 OUTA INB+
P1 S1
Q_GDT2 D4
10V_AUX VDD GND

R4_GDT2 OUTB INB-

SW4 SR3
D_GDT2 FAN3225C
S2
SR3_GATE_DRV U1

R_SR3
C_GDT2

Figure 3.15 Open-Loop Interleave Two-FET Forward Converter with Synchronous Rectification

42
 Design for the feedback loop circuit

START

Choosing type of
compensator to be used

Calculation
of the
components
for the
compensator

Simulation of the
compensator

No
Does the Simulation met
the expected output?

Yes

Choosing of
components
based on
calculations

END

Figure 3.16 Design Flow Chart of the Feedback Loop

43
 Fig.3.16 shows the design flow of the feedback loop. The first part is to choose the type of

compensation to ensure closed-loop stabilization. Then the components will be calculated which

basically depends on the phase and gain margin required. And using the components calculated,

simulation is done to validate the values and to affirm if they met the requirements. If the

simulation satisfies, components are chosen based on the calculated values and precision.

A closed-loop system will never be a closed-loop if there is no feedback. A feedback is

very essential for regulation and stabilization. It regulates the closed-loop system output DC

voltage by changing the duty cycle depending of the amount necessary to maintain the output

voltage being specified. The feedback loop basically increases Ton, time of on-state, when Vdc

decreases and decreases Ton when Vdc increases. In order to do that, stabilization of the feedback

must be ensured.

The first thing in stabilizing the feedback is by measuring the Bode Plot of the Plant. Using

the Simplis simulator, the Bode Plot of the Power Stage of the Two-FET forward converter is

produced. From this, the crossover frequency and the desired Phase Margin is chosen. As a

requirement, a Phase Margin of at least 45˚ must be settled. The final step is to choose the Error

Amplifier Compensator of the system to meet optimum performance with the desired Phase

Margin. The desired Error Amplifier Compensator must have a gain reciprocal to the gain of the

Plant and a phase lag such that the sum of the phase lag of the Plant and the Compensator and the

Phase Margin must be equal to 360˚.

Type 2 compensator as shown in Fig. 3.17 is used to attain a minimum 45˚ Phase Margin

from a minimum to a maximum load.

44
 The components of the Type 2 compensator can be calculated from the following:

UGF (unity gain frequency) =

∗ ∗( )

Zero =
∗ ∗

Pole = ∗
∗ ∗( )

Figure 3.17 Type 2 Error Amplifier Configuration

The figure shows the Type 2 compensator for the feedback. Rbias is basically necessary to

freely adjust the steady-state value of the sampled output voltage but it doesn’t affect the over-all

gain of the compensator. Type 2 error amplifier is chosen because its 90˚-maximum boost is

enough to achieve requirements. It has one zero and two-poles which can be used as basis in

adjusting the Bode plot and acquires the desired phase margin. [15]

45
 Simulation would eventually follow. The simulation will already consider the closed-loop

to see if the chosen poles and zeros would truly compensate the needed boost to meet phase and

gain margin. If satisfied, selection of the components that will be used in hardware implementation

would be followed. The simulator that will be utilized for Bode plotting will be the Simplis

simulator.

46
Design controller, gate-driver, and housekeeping (OVP, OCP, OPP) circuits

START

Design Auxiliary
Power Supply

Design for PWM

controller

Design SW and
SR gate-driver

Design Integration of
Housekeeping designed
Circuitry Yes circuitries

Simulation for each

circuitry Testing and
troubleshooting

No
Does the Simulation met
the expected output?
END

Figure 3.18 Design Flow Chart for controller, gate drive and housekeeping

47
 Fig. 3.18 basically shows the flow for designing the controller, gate drive and housekeeping

circuitry. The PWM controller must be chosen based on its capacity to satisfy the necessary

characteristics of the power supply. This would already include setting up external components

enabling the PWM controller to work and connect with the power supply. Gate drive designing

includes designing gate drive for the primary MOSFET’s, and SR MOSFET’s (which include the

forward and freewheeling SR). Lastly, designing circuitry for over-stress protection of the power

supply must be done to ensure longevity and safety.

Design of Auxiliary Power Supply

It is necessary to build another supply which serves as an external source for the controller

and gate drivers for the transistors of the forward converter in order to control the commutation. If

there is no isolated supply for the controller and gate drivers then there would be problem if the

supply is trying to auto-recover or the efficiency of the whole system would be lessen.

Fig.19 shows the external power supply scheme. It will undergo AC-DC conversion and

DC-DC conversion to achieve the desired DC supply. The input AC signal for the external power

supply will just be the same with the forward converter. In short, the auxiliary and the main power

supply is in parallel in terms of drawing input AC signal.

IN OUT
ADJ

AC 1 TX1 BR1
V1 C1
P1 S1 15V

48
 Figure 3.19 Auxiliary Power Supply Circuit

Before undergoing AC-DC conversion, the 220Vac or 311.13 Vp must be step-down to

24.7487 Vac or 35 Vp through the transformer. Therefore, the transformer must be design to have

a turns ratio of 311.13 / 35 = 8.889 or approximately equal to 9.

The bridge rectifier that will be used is GBPC W 12 – 005 as shown in Fig. 3.20 whose

maximum Vrms and DC blocking voltage is 35Vrms and 50V, respectively. It has a maximum

forward current If of 12A and maximum surge current Ifsm of 200A. The forward voltafe Vf of the

diode of the rectifier is 1.1 V. and And based on the necessary output voltage, the capacitor that

will be used is 35YXF33MEFCT1 from Rubycon shown in Fig. 3.21. And knowing that the

average voltage of the capacitor after rectification is 18V, a voltage regulator MC7815AB shown

in Fig. 3.22 will be used to produce the required 15V output of the auxiliary power supply. It has

an input range of

Figure 3.20 GBPC-W Bridge Rectifier

Figure 3.21 Capacitor 35YXF33MEFCT1

49
 Figure 3.22 Voltage Regulator MC7815AB

Significant parameters are shown in Table 3.5 for the auxiliary supply.

Table 3.5 Auxiliary Power Supply Specification

Auxiliary Power Supply
Vin AC 220 Vac
Vin ind 18 Vac
Vin rect 18 Vac
Vout 15Vdc
Iout 0.33A
Pout 4.95W
Turns ratio N 9

Based on appendix C, EE – 13 with a bobbin number 202-09905330 has maximum power

capacity of 5W using a 450 cir.mil/ A wire rating and Ae value is 0.173cm 2. Based on the oversized

Pout of 4.95W, the said core is suitable for the application.

Design of PWM Controller

The PWM controller that will be used in this study is the UC28025 suitable for high-

frequency switched-mode power supplies (SMPS) [16]. UC28025 suits for the design since it gives

a fixed frequency, varying duty cycle as long as you are able to familiarize the IC as to how you

would control it. It can be shown in Fig. 3.23 the N Package of UC28025 which displays the pin

configuration of the controller.

50
 Figure 3.23 UC28025 N Package (Top View)

Pin 1 and Pin 2 will be utilized for the error amplifier of the controller. Pin 16 as reference

voltage is an output pin which produced with a typical value of 5.10V. As for the ramp, the peak

ramp voltage has a 2.8V while the valley ramp voltage of 1.0V.

Based on the set switching frequency and with the aid of the datasheet [16], the values for

Ct and Rt are 10nF and 5kΩ, respectively. With that, we would be able to supply PWM signal with

an oscillating frequency of 70kHz.

Voltage-mode control will be used for the PWM controller. Fig. 3.24 illustrates the voltage

mode control which will be applied to UC28025 [17]. Its simple circuitry does no longer need I sense

either from the output side or the common way which is from switching current. The duty cycle

will be evaluated based on the limits set by the triangular signal. On that note, the time D is

generated by comparing the triangular signal with the error amplifier output Ve. The duty cycle D

can be calculated based on the waveform and using the formula below.

−
=
−

51
 Figure 3.24 UC28025 Voltage Mode Control

As for the reference of the error amplifier, the pin 16 of the controller will be utilized and

will be connected to pin 2 which is the Non-inverting input. In this case we would be expecting

that the output of the compensator would be connected to pin 1 which is the Inverting input of the

controller.

Primary Switches Gate Drive Control

The study is about designing an interleaved two-FET forward converter with synchronous

rectification. The schematic diagram of the open-loop circuit is shown in Figure 3.7. Two-FET

forward design is a topology that utilizes two primary switch MOSFETs for the primary winding

of the power transformer instead of only one primary switch which is common to ordinary forward

converter. One of the most noticeable advantages of two-FET topology over a single switch is that

the power transformer doesn’t need to have a demagnetizing coil to demagnetize the primary

winding of the power transformer. As shown in the schematic diagram, the two-FET topology

utilizes two reset diodes to magnetize the primary winding. Instead of having another coil for

demagnetization of the primary, or choose from other reset technique such as RCD clamp circuit

52
or active clamp which is another consideration, two-FET topology is intertwined with the two reset

diode which makes the design simpler.

Since the study deals with interleaving, there will be four primary switches that are needed

to be driven by the controller. There will be two MOSFETs for the primary rail, SW1 and SW2,

and another two MOSFETs for the secondary rail, SW3 and SW4. The switches of the primary

winding is located, as shown in the schematic diagram, one MOSFET is on the high side of the

primary winding, while the other is on the low side of the winding. This set-up is the same for both

rails. In this topology, one MOSFET is reference to the ground which is the MOSFET on the low

side of the winding; this MOSFET can be easily triggered since the source is ground terminated.

But for the other MOSFET, the source is connected to the leading terminal of the winding, there

might be a possibility that the potential present in the source terminal is higher than that of the

drain terminal which will make the MOSFET difficult to drive. To be able to drive both MOSFET,

a gate drive transformer will be employed. Fig. 3.25 shows the schematic diagram on how to

implement the primary switches gate drive control.

In Fig. 3.25, it shows that when the controller provides signal on PWM_DRVA terminal,

Q_GDT1 will be triggered and there will be current that will pass to the gate drive transformer,

and the secondary windings will induce a potential enough to drive the primary switches, SW1

and SW2, that will allow current to pass through the primary winding of the power transformer.

This is also true to the other rail when the controller provides a signal on PWM_DRVB terminal.

Whenever PWM_DRV is on logic low, no signal, Q_GDT will be open, but the excess current on

the primary winding will try to discharge to the ground through the D_GDT to divert the current

to Q_GDT that might destroy the MOSFET.

53
 +VIN

SW1
PWM_DRVA GDT1
R1_GDT1

D1 TX1

P1 S1
P1 S1
D2
Q_GDT1

R2_GDT1

S2
D_GDT1
SW2

C_GDT1

-VIN

SW3
PWM_DRVB
GDT2
R3_GDT2

TX2
D3
P1 S1
P1 S1
Q_GDT2 D4

R4_GDT2
SW4
D_GDT2
S2

C_GDT2

Figure 3.25 Implementation of Gate Drive Transformer

The use of gate drive transformer is to provide galvanic isolation. Galvanic isolation is a

barrier between two systems that stops a direct current from flowing from one system to the other.

This is imperative since the controller is located on the secondary side. Gate drive transformers

carries very small amount of average power but delivers high peak currents at turn-on and turn-off

of MOSFET/IGBT. Other advantages that gate drive transformer offers are: there won’t be any

need for an isolated DC-to-DC Converter for driving an upper MOSFET/IGBT, there will be

practically no propagation delay in a transformer to carry signals from primary side to the

secondary side, and several thousand volts of isolation can be built in between windings by proper

54
design and layouts [18]. Using gate drive transformer, the MOSFET located on the high side of

the primary winding, which is initially floating, will have reference by using gate drive

transformer; this allows effortless drive for the MOSFET.

Synchronous Rectifier Gate Drive Control

Figure 3.56 shows the circuit diagram of an interleaved two-FET forward converter with

synchronous rectification with only one choke at the output filter stage. Given that the circuit is

interleaved and has only one choke, this will correspond to two forward MOSFET and one

freewheeling MOSFET as shown in the figure above.

Interleaving is a technique that is to say when one rail of the forward converter is

conducting, the other rail is not conducting, therefore, this circuit is a two phase interleaved circuit.

This means that while the first forward MOSFET (SR1) is conducting, the second forward

MOSFET (SR3) is not conducting and vice versa. Therefore, it can be observed that when SW1

and SW2 of the primary switch is turned on, SR1must also be turned on, and if SW3 and SW4 is

turned on, SR3 must also be turned on, hence, the frequency of operation of the two forward

MOSFET depend on their corresponding primary switches. Therefore, to drive the forward

MOSFETs, FAN3225C synchronous rectifier controller IC will be used.

Figure 3.26 FAN3225C Dual 4-A High-Speed, Low-Side Gate Driver

55
 FAN3225C, shown in Fig. 3.26, is a Dual 4-A High-Speed, Low-Side Gate Driver for

synchronous rectifiers from Fairchild Semiconductors. According to its datasheet, in FAN3225C,

each channel has dual inputs of opposite polarity, which allows configuration as non-inverting or

inverting with an optional enable function using the second input. This controller is selected base

from its operating parameters that is within the operating parameter of the forward converter;

unlike other controller which require higher supple voltage and higher gate drive potential. The

pin configuration of FAN3225C is shown in Fig. 3.27 below. The following pins of FAN3225C

are described in the Table 3.6.

Figure 3.27 Pin Configuration of FAN3225C

Table 3.6 Pin Description of FAN3225C

Symbol Pin Number Description
INA- 1 Inverting Input to Channel A
INB+ 2 Non-Inverting Input to Channel B
GND 3 Ground
INB- 4 Inverting Input to Channel B
OUTB 5 Gate Drive Output B
VDD 6 Supply Voltage
OUTA 7 Gate Drive Output A
INA+ 8 Non-Inverting Input to Channel A

56
 While the forward MOSFETs are dependent of their respective primary switches, the

operation of the freewheeling MOSFET is different. The function of the freewheeling MOSFET

is to discharge the inductor while the converter is in off-stage. In normal operation, for a single

rail forward converter, the operation of the freewheeling MOSFET with respect to the forward

MOSFET is just reversed, whenever the forward MOSFET is on, the freewheel is off and vice

versa. But using an interleaved one choke topology, the freewheeling MOSFET (SR2) will only

conduct if SR1 is turned off and until SR3 is turned on, and if SR3 is turned off and until SR1 is

turned on, as shown by the waveforms in Fig. 3.28 below.

SW1&SW2 ton1 toff1

SR1

T1
tdead1

SW3&SW4 ton2 toff2

SR3

T2
tdead2

SR2

Figure 3.28 Switches and Synchronous Rectifier Conduction Pattern

57
 From the Figure 3.28, it is obvious that the frequency of operation of SR2 is twice the

operating frequency of SR1 and SR3. This means that the operation of SR2 is not exclusively

dependent to the operation of the primary switches, but is dependent to both rails. SR2 will only

conduct if both rails are turned off at the same time. Hence, the gate drive circuit will differ to SR1

and SR3, shown in Figure 3.29 below.

LOUT

VOUT+

TX1
+
SR2
COUT
P1 S1

VOUT-
SR1 10V_AUX
Q_NOR

R3_NOR

R1_NOR R2_NOR

R_SR1
C_NOR
PWM_DRVA

PWM_DRVB

INA+ INA-
TX2
SR1_GATE_DRV
OUTA INB+
P1 S1
10V_AUX VDD GND

OUTB INB-
SR3
FAN3225C
SR3_GATE_DRV U1

R_SR3

Figure 3.29 Implementation of Synchronous Rectifier Controller

Housekeeping Circuitries

58
 Housekeeping for the power supply basically commences system protection from

damaging instances that may occur. Housekeeping protects the whole system such as from over

voltage, over current and over power. In this study, the power supply must have an overvoltage

protection (OVP), overcurrent protection (OCP) and overpower protection (OPP).

System with OVP turns off the whole system or put it into zero-output whenever the output

voltage achieves a certain voltage level higher than the expected one. In this study, OVP triggers

whenever the output voltage reaches 130% of the desired voltage. Fig 3.30 shows that OVP

circuitry that will be used in the study. LM311 Single Comparator as shown in Fig. 3.31 will be

used in implementing the OVP circuit.

Vout 5V

5V
R1
1K C1
R3 1u
X1
D1
Q1
Q2N2222
BAS516
R2 LM339 150k
5V ref R4
Gnd Sec to Controller

Figure 3.30 Overvoltage Protection Circuit

59
 Figure 3.31 LM 311

The ratio would be 1/3 so as to satisfy the needed voltage for the Op-Amp. OVP

operates this way given the Vout is increasing; whenever V- (portion of Vout based on voltage

divider) slightly higher than Vref (in this cae the V+), output of the Op-Amp Vo would start to

decrease. Portion of the output would be fed back to Vref and decreases its value. The decrease of

Vref would eventually decreases the value of Vo until it becomes zero. Eventually this commands

the PWM to produce no pulses. Without pulses, there will be zero output voltage and the system

is now protected.
P1

Lout Vout

L1
S1

TX1
C1
Cout
Rsense

R1 Gnd Sec
5V

X1

D1
5V ref
LM311

To Controller
Vout

Figure 3.32 Overcurrent Protection Circuit

For the OCP, we will be using the concept of current transformer as the current sense at

the output side. Fig 3.32 shows the OCP circuit that will be used in the study. The current

transformer by virtue of turns-ratio based on current relationship would sense the current at the

output and induce current. This induced current will be converted to voltage using Ohm’s Law

60
(Rsense as the resistor). The voltage will be compared with the Vref of the comparator. This

comparator will be connected to the controller which would eventually send signal depending as

to how it would want the controller do. In the case of OCP, if the current would reach 33% of the

output current, the comparator would eventually asked the controller to shut down the whole circuit

by not providing pulses.

As for OPP, the study would just consider the concept of OCP since we have a regulated

output voltage which 12V and when a certain current that would eventually lead to a higher output

power. This is apparently OCP acting in the entire system. On that note, OPP will just be doing

OCP in a sense.

OVP and OCP will be “OR-ed” and the output will be connected to pin 7 of the controller.

Fig. 3.33 shows the “OR” connection of two protection circuits.

61
 P1
Lout Vout

L1

S1
TX1
C1
Cout
Rsense Gnd Sec
R1

15V

X1
5V ref

D1
LM311

To Controller
Vout

15V
R3

X2
5V ref

D2
R2 LM311

Gnd Sec

Figure 3.33 OVP and OCP integration

Testing and Data Acquisition

After designing the different stages of the interleave two-FET forward converter with

synchronous rectifier which are the main power stage, the feedback circuit, the controllers, and

housekeeping circuits, the stages where simulated in SIMPLIS independently of each other to

properly design each stage to provide the expected function of each stage. If ever there will be

62
problems that will occur in the simulation, the proper correction will be addressed, else the stages

will be integrated as a whole. The whole circuitry will then be simulated as one circuit. If the

designs of the different circuit parameters are correct, the simulation output must yield the

expected results, if not, troubleshooting will be employed.

The results acquired during the simulation of the design, the results that will be acquired

are the results of the hardware prototype. After simulating the whole circuit and yields to the

expected output, a prototype of the design will be constructed. This prototype will then be tested

if it will yield to the considered design specifications, refer to Table 3.x for design specifications.

Line Regulation Testing

Line regulation testing is to test the consistency of the output voltage regulation of the

power supply while the input varies from maximum input to minimum input voltage while the

load is constant to a certain level either full load, half load or no load condition.

Table 3.7 Line Regulation at Full Load

Line Regulation at Full Load (IOUT = 25A)
Vin Iin Pin VOUT IOUT POUT Efficiency

Table 3.8 Line Regulation at Half Load

Line Regulation at Half Load (IOUT = 12.5A)
Vin Iin Pin VOUT IOUT POUT Efficiency

63
Table 3.9 Line Regulation at No Load
Line Regulation at No Load (IOUT = 0A)
Vin Iin Pin VOUT IOUT POUT Efficiency

Load Regulation Testing

Load regulation testing is to test the consistency of the output voltage regulation of the

power supply as the load varies from no load to full load while the input voltage is constant either

maximum input, typical input, or minimum voltage input condition.

Table 3.10 Load Regulation at Maximum Input Voltage

Load Regulation at Maximum Input Voltage (Vin = 240Vac)
Vin Iin Pin VOUT IOUT POUT Efficiency

Table 3.11 Load Regulation at Typical Input Voltage

Load Regulation at Typical Input Voltage (Vin = 220Vac)
Vin Iin Pin VOUT IOUT POUT Efficiency

Table 3.12 Load Regulation at Minimum Input Voltage

Load Regulation at Minimum Input Voltage (Vin = 210Vac)
Vin Iin Pin VOUT IOUT POUT Efficiency

64
Protection Circuit Testing

This portion is to test how the protection circuit incorporated on the power supply behaves,

if the protection circuit triggers as expected whenever a fault is detected.

Over Voltage Protection Test

OVP circuitry can be test even though it is isolated from the whole system of power supply

as long the circuit would produce the expected results. For guidance, Table 3.l3 shows the expected

results per changes of the inverting input or basically the Vout of the power supply (Vsense).

Table 3.l3 OVP Testing

OVP Testing Vref = 5V
Vsense VOUT(OVP)
0 – 12V 15V
12 and above 0V

Due to open current theory, when Vout(ovp) is equal to 15V reverse-biased the diode at

the output. On the other hand, when it produces 0V it forward biases the diode or “grounded” in

effect to the output produced.

Over Current Protection Test

Overcurrent Circuit testing will just be the same with the OVP since it would also utilize

comparator then diode before connecting to the controller. In effect, same procedure of testing

Ovp will be implemented to the OCP.

65
References

[1] J. Zhao, M. Sekine, et.al., “An Improved Interleaved Forward Converter,” Japan.

[2] C. Arboy and B. Cousin, “Advantages of an isolated Buck,”Analysis And Design Of A

Forward Converter, pp 8-9, 2006.

[3] Wurth Elektronik

66
[4] S. Manikatala, “Off-line Converter Design and Magnetics,” Switching Power Supplies A

to Z, pp 154-155, Newnes-Elsevier, USA, 2006.

[5] Application note: AND8373/D “2 Switch-Forward Current Mode Converter”

[6] Steve Mappus, “Synchronous Rectification for Forward Converters”, Fairchild

Semiconductor Power Seminar,2010-2011.

[7] Michael Tao Zhang, “ELECTRICAL, THERMAL, AND EMI DESIGNS OF HIGH-

DENSITY, LOW-PROFILE POWER SUPPLIES – Chapter 2: Synchronous Rectification”,

February 17, 1997.

[8] M. Jovanovic et.al. Design Consideration for Forward Converter with Synchronous

Rectifiers. Power Conversion. October 1993.

[9] Michael O’Loughlin, “200-W Interleaved Forward Converter Design Review Using TI’s

UCC28221 PWM Controller”, Texas Instruments, SLUA312, May 2004.

[10] Brian Shaffer, “Interleaving Contributes Unique Benefits to Forward and Flyback

Converters”, Texas Instruments Incorporated, 2005.

[11] Ki-Bum Park, Chong-Eun Kim, Gun-Woo Moon, and Myung-Joong Youn, “Interleaved

Forward Converter for High Input Voltage Application with Common Active-Clamp Circuit”,

Samsung Electro-Mechanics Co. Ltd.

[12] Michael Tao Zhang, “ELECTRICAL, THERMAL, AND EMI DESIGNS OF HIGH-

DENSITY, LOW-PROFILE POWER SUPPLIES – Chapter 3: Paralleling Techniques”, February

17, 1997.

[13] S. Manikatala, “The Principles of Power Switching Conversion,” Switching Power

Supplies A to Z, pp 16-17, Newnes-Elsevier, USA, 2006.

[14] Datasheet: Infineon - Product Brief - PowerMOSFETs - 600V 650V CoolMOS- - C6 E6.

67
[15] Optimum Feedback Amplifier Design For Control Systems, VENABLE TECHNICAL
PAPER # 3 – Optical Feedback Design, Venable Industries.

[16] Datasheet: Texas Instrument : UC28025 “ Economy High-Speed PWM Controller”.

[17] Mammano, R. Design Note: Switcing Power Supply Topology Voltage Mode vs. Current

Mode. Unitrode Corporation. Texas Instruments.

[18] Pathak, Abhijit and Locher, Ralph, “HOW TO DRIVE MOSFETs AND IGBTs INTO THE

21ST CENTURY”, IXYS Corporation, Santa Clara, CA 95054, IXAN0009

Appendix A

68
Appendix B

69
70