Seat No.:____________ Enrolment no.

:_________________

BE –Semester-VI Examination
B.E. (EC) SEMESTER VI
Subject Code:
Subject Name: VLSI Technology and Design Date:
Time: Total Marks: 70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions whenever necessary.
3. Figure to the right indicates full marks.

Q-1 (a) What are the problems associated with LOCOS isolation technique? Explain each of the fabrication steps 07
involved in LOCOS technique with suitable diagrams
(b) Answer the following: 07
(I) Compare Semi-custom and Full custom VLSI design style
(II) Discuss general architecture of FPGA

Q-2 (a) Explain Band Diagram of the MOS structure, at surface Inversion. Derive the expression of threshold 07
Voltage.
(b) Effect of channel length modulation and substrate bias on drain current of NMOS transistor. 07
OR
(b) Consider a CMOS inverter circuit with the following parameters: 07
VDD = 3.3 V,
For NMOS VTO, n = 0.6 V, μn Cox=60 μ A/V2 , (W/L)n=8
For PMOS VTO, p = - 0.7 V, μp Cox=25 μ A/V2 , (W/L)p=12.
Calculate noise margin and Vth of the circuit.

Q-3 (a) Draw the CMOS Inverter circuit and Voltage Transfer Characteristic (VTC) for different operating regions 07
of the nMOS and pMOS transistors. Derive critical voltage points VIL,VIH.
(b) Derive equivalent resistance of the CMOS transmission gate (pass gate). 07
OR
Q-3 (a) Implement the following Boolean function using CMOS. 07
(1) F =[(C+D+E) . (B+A)]’

(b) What is Scaling? Compare Field scaling with Voltage scaling. 07

Q-4 (a) What is the need of voltage bootstrapping? Draw dynamic boot-strapping arrangement and explain it. 07
(b) Prove that oscillation frequency of a CMOS ring oscillator is inversely proportional to the propagation 07
delay of the inverter.
OR
Q-4 (a) Explain the basic principles of pass transistor circuits. Also explain logic “0” and logic “1” transfer. 07
(b) Draw input and output waveform during high to low transition of output for a CMOS inverter and derive 07
expression for τPHL.

Q-5 (a) Explain the Built-In-Self-Test techniques to test VLSI circuit. 07

(b) Explain Latch up problem in CMOS inverter. Mention causes and remedy for avoiding latch up. 07
OR
Q-5 (a) Explain On Chip Clock Generation and Distribution. 07
(b) Discuss Ad Hoc testable design techniques. 07