Author: MCUXpresso IDE Team

Version: 2.0.1 10 th August 2018

Using the MIMXRT1050-EVK(B) with MCUXpresso IDE v10.2.1

Table of Contents
1 Overview.................................................................................................................................2
2 Read Me First..........................................................................................................................2
IMXRT1050 EVK and EVKB.....................................................................................................2
SDK Changes..........................................................................................................................3
Debug Restrictons.................................................................................................................3
Also supplied with this Document.........................................................................................3
3 Overview of Board features related to Debug.......................................................................4
4 Debug Connecton..................................................................................................................5
5 DAPLink Firmware version.....................................................................................................6
Updatng the DAPLink irmware............................................................................................6
6 Memories...............................................................................................................................7
Memory atributes and Cache(s)r...........................................................................................9
7 Flash Drivers...........................................................................................................................9
8 New Project Creaton...........................................................................................................10
New Project issues...............................................................................................................11
9 XIP How and Why.................................................................................................................13
10 Project Debug.....................................................................................................................13
11 SDK Examples.....................................................................................................................15
Importng an example.........................................................................................................15
12 Resets.................................................................................................................................16
13 Building and Debugging Projects for RAM.........................................................................17
Using the SDRAM region.....................................................................................................17
14 SDK Examples: Convertng a RAM project to XIP from Flash.............................................19
Bootng the Applicaton.......................................................................................................21
15 Troubleshootng.................................................................................................................22
Erasing the Hyperfash.........................................................................................................22
Obtaining debug control via a debug Connect Script.........................................................23
Using external Debug Probes..............................................................................................23
Debug performance and the Data Cache............................................................................24

© 2018 NXP Semiconductors. All right reserved 1

1 Overview

This document is intended to assist users who are new to using the MIMXRT1050-EVK(B)r
board. It assumes some familiarity with creatng and debugging projects with MCUXpresso
IDE v10.2.1. It is also assumes an SDK for the MIMXRT1050-EVK(B)r board has been installed
into MCUXpresso IDE, and the LinkServer/CMSIS-DAP debug connecton (DAPLink)r will be
used for all debug operatons.

Note: it is strongly recommended that the latest available SDK is installed – at the tme oo
writng this is the EVK-IMXRT10505 version .4.4.4

For more informaton on using MCUXpresso IDE, please see the MCUXpresso IDE User
Guide.

Note: this is a guide only and not intended as a defnitve document

2 Read Me First

Some early EVK boards shipped with an image in fash (hyperfash)r that when run can
prevent a successful debug connecton. Therefore, it is strongly recommended that the fash
is irst erased.

To erase this fash, please follow the procedure described in the Troubleshootng secton at
the end of this document before any other debug operatons are atempted.

Please also refer to the secton DAPLink Firmware version to ensure your board is
programmed with the correct debug probe irmware.

IMXRT1050 EVK and EVKB

The original IMXRT1050 EVK board has been replaced by an updated EVK B variant. This new
board contains a later revision of the IMXRT1050 silicon and also various improvements
including observed improved debug stability when using the external 20 way JTAG header.

A new SDK – MIMXRT1050-EVKB, is available to support this later board. It is recommended

that this SDK is used in preference to earlier SDKs whether debugging EVK or EVK(B)r boards.

For further informaton on the I.MX-RT1050 and the EVK development boards please see
the following link: htps://www.nxp.com/pages/:i.MX-RT1050

For guidance migratng from Rev A0 to Rev A1 silicon, please see:

htps://www.nxp.com/docs/en/nxp/applicaton-notes/AN12146.pdf

© 2018 NXP Semiconductors. All right reserved 2

SDK Changes

SDK_2.x_EVKB-IMXRT1050 version 2.4.x incorporates a number of changes and

improvements from previous SDK versions. Some of the signiicant changes from the point
of view of general build and debug are listed below:

• Example projects now typically target executon from external fash

◦ previously most examples linked to execute from RAM
• Onchip SRAM is typically chosen for data storage rather than SDRAM
• Example projects now default to output text via the SDK Debug Console UART
◦ this text output can be captured using the DAPLink built in VCOM support (not
available when using an external debug probe)r
▪ MCUXpresso IDE now includes a terminal view suitable for capturing this
output within the IDE. Please see the MCUXpresso IDE User Guide secton
18.9 ‘Using Terminal View for UART communicaton with target’
◦ this default can of course be changed during example import
• MPU memory coniguratons regions setngs are improved

Debug Restrictins

Despite the extensive feature set of this MCU/Board, some debug capabilites are not
available. While the MCU does support SWO, due to multplexing issues this feature is not
available on the EVK(B)r boards. Also ETB based instructon trace is not supported by this
MCU.

Alsi supplied with this Dicument

• LinkServer Connect Script to initalise SD-RAM

• LinkServer Connect Script to recover debug connectons if the default connecton
mechanism fails
• QSPI XIP header iles for EVK(B)r board modiied to use QSPI fash

© 2018 NXP Semiconductors. All right reserved 3

3 Overview if Biard features related ti Debug

Below is a photo of the MIMXRT1050-EVKB board with key elements numbered and
described:

1. Power LED - If this LED is not lit, the MCU/board is not powered and cannot be
debugged.
2. J1 - Link positon (top)r for board powered externally (see 5)r.
3. J1 - Link positon (middle)r for board powered via the OpenSDA DAPLink debug probe
connecton (see 4)r.
4. J28 - OpenSDA DAPLink (CMSIS-DAP)r connecton (see 3)r. This is the recommended
debug connecton for inital use.
5. J2 - External power connecton. If used, this should be 5v, centre +ve, and J1 set (see
2)r. This allows power to the board to be controlled via switch SW1 (to the right of
(5)r)r.
6. 20 way JTAG style connecton for use with external debug probes such as the LPC-
Link2. External debug probes will typically achieve signiicantly faster debug
operatons than the onboard OpenSDA debug probe. Note: highlighted links will
disable OpenSDA debug io removed4 1his may improve external debug probe stability4
7. SW7 - DIP switches to select boot optons. Initally this should be set for boot from
Hyperfash: so set as 1-of, 2-on, 3-on, 4-of.
8. J27 – OpenSDA Bootloader selecton. Set jumper 1-2 for bootloader mode, 2-3 for
OpenSDA debug.
9. SW4 – Reset for use with OpenSDA irmware programming when J27 is set 1-2.
10. Target USB – can also be used to provide power to the target if J1 – Link positon set
between (top and middle)r.

© 2018 NXP Semiconductors. All right reserved 4

4 Debug Cinnectin

For inital use, we recommend using the OpenSDA USB connecton (see 4 above)r for the irst
debug operaton(s)r.

Boards are delivered with DAPLink debug probe irmware (CMSIS-DAP)r pre-programmed
into the OpenSDA hardware (please also see DAPLink Firmware version below)r.

Once an OpenSDA USB connecton has been made (on Windows)r, 'Devices and Printers' will
show the devices as below:

This connecton can also power the board if the J1 link is set to the mid positon (see point 2
in Overview of Board features ... above)r.

Note: io this link is set correctly, the LED next to J0 will light green4 Mo the LED is not lit, the
XCU will not be powered and debug will oail, resultng in an error similar to that below
(despite the DAPLink debug connecton being available):

© 2018 NXP Semiconductors. All right reserved 5

5 DAPLink Firmware versiin

Some of the inital shipments of boards contain a version of DAPLink irmware which has
known issues. To check the version on your board, simply make a USB connecton to the
OpenSDA USB connecton (as described above)r and open a iler window on the EVK(B)r-
MIMXRT drive.

Open the ile DETAILS.TXT on this drive and conirm the ‘Interface Version:’ is 0244 or
greater.

If this is not the case, then the irmware should be updated following the procedure
detailed below.

Updatng the DAPLink frmware

From MCUXpresso IDE go to Help -> Additonal resources -> OpenSDA Firmware Updates,
this will open a web page ‘OPENSDA: OpenSDA Serial and Debug Adapter’. From this page,
locate the dropdown and select the MIMXRT 1050-EVK board.

Note: at the tme oo writng only EVK boards are listed here4

Download the latest DAPLink binary – at the tme this document was created this reports as
DAPLink v0244.

To install the irmware, follow the procedure below:

1. Power of the board

2. Locate J27- identied in the board features as (8)r.
a. Set the J27 Jumper between pins 1 and 2 (this is the lower positon with the
board oriented as the photograph above)r.
3. Press and hold SW4 – identied in the board features as (9)r.
4. Connect a USB cable to the OpenSDA connector
5. Release SW4

© 2018 NXP Semiconductors. All right reserved 6

 6. Open a iler window and observe a drive labelled MAINTENANCE appears:

7. Open this drive and drag the previously downloaded irmware onto the iler window
a. The iler window should close when the irmware update has completed
8. Eject the device
9. Power of the board
10. Restore the J27 Jumper to between pins 2-3 (this is the upper positon with the
board oriented as the photograph above)r.

Now conirm the updated version number as described at the beginning of this secton.

Important Note: 1wo versions oo OpenSDA frmware are available, one oor onboard
HyperFlash (fied as standard to the XMXRT10505IEVK(-) boards) and one oor onboard
QSPMIflash (only accessible to reworked boards)4 1hese version indicate the flash type that
will be supported oor the boards when programmed via drag and drop I mass storage
devices4 For users of standard boards be sure to install the HyperFlash version.

6 Memiries

Below is a list of the usable memories on this MCU and board. Some, or all of these regions
will be visible within an MCUXpresso IDE project's Memory Coniguraton Editor (as below)r:

• External board memories are highlighted in blue4 LinkServer Flashdriver oor the
hyperflash device highlighted in red4

• Note: -y deoault, projects will be linked to the frst flash memory in this list and use
the frst TAX region oor data, heap and stack4 However, the SDK (projects and
examples) may select a subset oo these memories and/or change their order to
control linkage (and also override deoault linkage using the LinktoTAX oeature – see
later)4

© 2018 NXP Semiconductors. All right reserved 7

Board_Flash (Hyperfash) at 0x60000000: This 64MB device is board memory external to
the MCU. Programming of this device is provided by a fash driver called MIMXRT1050-
EVK_S26KS512.cfx (for LinkServer CMSIS-DAP debug connectons)r. On reset, (if SW7 is set
for Flash Boot)r the BootROM will interrogate this device and atempt to identfy a speciic
image header, if found, the header data will be used to conigure its operaton (and also
initalise the SDRAM)r. If a correct header is not found, this device will be unavailable.

Note: XCURpresso MDE will automatcally generate and locate an appropriate header orom
inoormaton supplied by the SDK oor new projects and as required oor example projects4

Code can be run directly from this Flash, this is known as Execute in Place (XIP)r. This Flash
can be cached by the MCU.

Note: 1he term RMP is used to diferentate orom an alternatve boot strategy, where the
-ootTOX will relocate code (and data) orom flash oor TAX executon4 1his mode oo
operaton is not directly supported within XCURpresso MDE v054.4x4

Note: Also see the secton on Flash Drivers4

SRAM_OC at 0x20200000. This 256KB (FlexRAM)r is on chip SRAM accessed over AXI and is
cacheable by the MPU. Code or data accessed from this memory will use space within the
cache. If this memory is marked as not cacheable, performance will be signiicantly reduced.

SRAM_ITC at 0x0: This 128KB device (FlexRAM)r is on chip SRAM, and tghtly coupled to the
MCU and will 'seen' by the CPU before the cache, therefore the contents of this RAM will
not cached. This RAM will provide the best deterministc performance for program
executon.

SRAM_DTC at 0x20000000.: This 128KB (FlexRAM)r is on chip SRAM, and tghtly coupled to
the MCU and will 'seen' by the CPU before the cache, therefore the contents of this RAM
will not be cached. This RAM will provide the best deterministc performance for data
accesses.

Note: 1ightly coupled memories may be described to the XPU with cacheable aiributes,
however their contents will not actually be cached4 1hey are intended to be used oor code
(and data) requiring the maximum deterministc peroormance (and minimum power I this is
a complex area and will not be discussed ourther in this document)4

SDRAM at 0x8000000: This 32MB device is board memory external to the MCU. This RAM
block must be initalised before it can be used. An XIP Flash header contains the data for the
BootROM to use to initalise this RAM memory. Alternatvely, if a project is targeted to run
from this RAM, a debug Script can be run to initalise this device.

Note: Mo this initalisaton does not occur, then the TAX will not be available and a debug
operaton targetng this memory will oail!4

Code can be run directly from this RAM. This RAM can be cached by the MPU.

© 2018 NXP Semiconductors. All right reserved 8

Memiry attributes and Cache(s)t

Complex memory systems present considerable fexibility to any system designer and much
of this detail is beyond the scope of this document. However, it should be understood that
this MCU contains a cache designed to improve the system performance when accessing
board memories (SDRAM, Flash and OC_RAM)r. Furthermore, memory regions can be
assigned propertes governing how memory access are treated inside that region by the
CPU.

A Memory Protecton Unit (MPU)r is present on this MCU to control these memory region
propertes.

New and example (board)r projects will contain a functon -OATD_ConfgXPU within the ile
board.c . This functon performs the MPU coniguraton for the various memory regions
including cache setup and the exact behaviour of this functon is controlled by a number of
deined symbols. It is strongly recommended that (if used) this functon is examined and
understood to ensure the memory system is confgured as desired.

Note: Mn SDK versions .4. and .4.40, the External Flash is confgured as TeadWrite:

MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U)r;

MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512MB)r;

This is not ideal - it is suggested that ARM_MPU_AP_RO is a more appropriate setng for
the fash region. This will be corrected in a future SDK release.

Furthermore, since the MPU controls access to actual memory regions, the selected region
sizes should match the actual memories, thereby enabling the MPU to trap accesses outside
of real memories.

Note: in SDK version 2.4.x the 32MB SDRAM region is confgured so the last 2MB will not
be cached:

MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U)r;

MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB)r;

If a project is created with the SDRAM as the irst RAM region then the stack will
automatcally be located at the end of this region i.e. within this uncached region of
memory. Since uncached SDRAM will see hugely degraded performance, this situaton
should be avoided! Please refer to the MCUXpresso IDE User Guide Secton 16.10 Xodioying
heap/stack placement for details on controlling stack placement, alternatvely the MPU
setngs can of course be changed etc.

7 Flash Drivers

The SDKs EVK(B)r-IMXRT1050 ships with a hyperfash driver for CMSIS-DAP debug
connectons. This driver MIMXRT1050-EVK_S26KS512S.cfx targets a single hyperfash ‘chip’
as ited as standard to the MIMXRT1050-EVK(B)r board. Also supplied are drivers for speciic

© 2018 NXP Semiconductors. All right reserved 9

QSPI and EcoXiP devices, known as MIMXRT1050-EVK_IS25WP064A.cfx and MIMXRT1050-
EcoXiP_ATXP032.cfx respectvely.

New in MCUXpresso IDE version 10.2.1 is the source project for these driver located at:
<MDE install Directory>\ide\Examples\Flashdrivers\NRP\iXRT14 These driver project are
supplied as a base for users to develop CMSIS-DAP fash drivers for alternatve fash devices.

Also new in MCUXpresso IDE version 10.2.1 are two drivers that self conigure from fash
JEDEC SFDP data, and are supplied in binary form only:

MIMXRT1050_SFDP_HYPERFLASH.cfx
MIMXRT1050_SFDP_QSPI.cfx

These drivers are located at: <MDE install Directory>\ide\bin\Flash and should be used in
preference for any new project targetng fash devices that supports the JEDEC SFDP
standard. Please see the MCUXpresso IDE User Guide Secton 14.2.4 for more informaton.

8 New Priject Creatin

The MCUXpresso IDE New Project wizard defaults to creatng projects to execute in place
(XIP)r from the board HyperFlash using the SRAM_OC for data.

1 – To create a New Project, Click 'New Project' to launch the New Project Wizard:

2 - Ensure the EVK board is selected (otherwise board features including fash memory will
not be available)r:

3 - Click Next (acceptng all the default optons)r:

© 2018 NXP Semiconductors. All right reserved 10

4 - Then click Finish.

A new project (as below will be created)r.

This is a 'Hello World' project/applicaton that will execute (XIP)r from the Hyperfash
memory using the irst RAM region (SRAM_OC)r for stack and global data. This RAM region is
used because the SRAM_OC is marked by the SDK as the irst RAM region for new projects
(this selected RAM can of course be changed)r.

Note: Previous SDKs selected the SDTAX as the frst TAX region4 1he SDTAX memory io
used will be initalised by the -ootTOX (using the data orom the RMP boot header) beoore
being used by the applicaton4

New Priject issues

SDKs prior to version 2.4 had a number of issues impactng new project creaton. These have
been corrected in SDK 2.4.x. The informaton below (in grey)r is supplied for reference.

For a project conigured to XIP from hyper fash, a deine XIP_EXTERNAL_FLASH should also
be created. This deine is used to select some clock setup for the fash and change its MPU
cacheable propertes. Currently, the SDK does not specify this deine for new projects.

Without this symbol, the projects performance will be reduced.

© 2018 NXP Semiconductors. All right reserved 11
Also, for projects using the SDRAM, a deine SDRAM_MPU_INIT should also be set since this
is used to determine the MPU propertes for the SDRAM region. Currently, the SDK does not
specify this deine for new projects.

Without this symbol, the projects performance will be reduced.

Note: A new project defne can be added in a number oo ways, oor example:

1. Select the project in the Project Explorer4

2. From the QuickStart Panel I> Quick Setngs I> Defned Symbols
3. Click +, enter the new symbol
4. Click OK, OK

By default, the stack will be placed at the end of the irst RAM region, therefore in our
example project the stack will grow down from 0x82000000. However, the memory
propertes (as set in the MPU)r for the last 2MB of the SDRAM are not optmal for stack
operatons. This problem can be corrected in a number of ways for example:

1. Edit the project propertes and relocate the stack from the End of the memory
region, to instead follow afer the project’s data – Post Data (as shown below)r.

2. Alternatvely, edit the MPU descripton of the SDRAM region within the ile board.c
by simply deletng the Region 8 setngs (in blue)r.

#if defined(SDRAM_MPU_INIT)
/* Region 7 setting */
MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0,
ARM_MPU_REGION_SIZE_32MB);

/* Region 8 setting */
MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0,
ARM_MPU_REGION_SIZE_2MB);
#endif

© 2018 NXP Semiconductors. All right reserved 12

9 XIP Hiw and Why

Traditonally a standard Cortex M applicaton image is programmed into an internal fash

memory (of an MCU)r, this image is automatcally executed once the MCU is reset (a
bootable fash)r. Although essentally hidden from the user; when an MCU is reset, the irst
code to run is (usually)r an internal BootROM, which is responsible for internal hardware
setup and passing control to the users applicaton in Flash. From the perspectve of the user
however, it appears as though their applicaton is run immediately on reset.

In the case of the RT1050, all fash memory is external to the MCU and therefore unknown
to the BootROM. For the BootROM to boot an image from this fash, some additonal
informaton must be supplied to allow fash initalisaton and optmal coniguraton etc. The
BootROM speciicaton expects this coniguraton data to be located in an 8KB header at the
start of the users image (applicaton)r. An XIP image supplies this informaton in an 8KB
header at the start image itself. Once programmed into fash, this informaton can be read
by the BootROM using basic subset of fash operatons.

When the New Project Wizard is used and a board (evk(b)rimxrt1050)r is selected, board
components will automatcally be pre-selected - including an xip driver. This driver
component will ‘pull in’ the required header iles into a project folder (xip)r. The iles within
this folder work in conjuncton with our Managed Linker Script mechanism to create and
locate an appropriate header for this target fash device.

Note: this image header will only be created io the image is linked to the start oo Hyperflash
at 5x65555555 (the New Project deoault)4

10 Priject Debug

To debug this new project, check the secton at the start of this document and ensure the
board is correctly conigured and powered. Then simply select the Project and from the
Quickstart panel, click Debug.

A probe discovery operaton will be performed, which should locate the on board DAPLink
debug probe. Select this and click OK.

© 2018 NXP Semiconductors. All right reserved 13

The project will build and a debug operaton will commence. If all goes well, you should see
the following Debug stack and the applicaton halted on main()r.

The debug operatons are logged (within the Console Debug Messages)r and will look as
below:

MCUXpresso IDE RedlinkMulti Driver v10.2 (Jun 28 2018 13:51:56 -

crt_emu_cm_redlink build 554)
Found chip XML file in
C:/Users/peter/Documents/MCUXpressoIDE_10.2.1_792_alpha/workspace1/MIMXRT10
52xxxxB_Project/Debug\MIMXRT1052xxxxB.xml
Reconnected to existing link server
Connecting to probe 1 core 0:0 (using server started externally) gave 'OK'
Probe Firmware: DAPLink CMSIS-DAP (ARM)
Serial Number: 0227000041114e45004b3003b60f003aa6e1000097969900
VID:PID: 0D28:0204
USB Path: \\?\hid#vid_0d28&pid_0204&mi_03#8&1745eda8&0&0000#{4d1e55b2-f16f-
11cf-88cb-001111000030}
Using memory from core 0:0 after searching for a good core
debug interface type = Cortex-M7 (DAP DP ID 0BD11477) over SWD TAP 0
processor type = Cortex-M7 (CPU ID 00000C27) on DAP AP 0
number of h/w breakpoints = 8
number of flash patches = 0
number of h/w watchpoints = 4
Probe(0): Connected&Reset. DpID: 0BD11477. CpuID: 00000C27. Info: <None>
Debug protocol: SWD. RTCK: Disabled. Vector catch: Disabled.
Content of CoreSight Debug ROM(s):
RBASE E00FD000: CID B105100D PID 000008E88C ROM dev (type 0x1)
ROM 1 E00FE000: CID B105100D PID 04000BB4C8 ROM dev (type 0x1)
ROM 2 E00FF000: CID B105100D PID 04000BB4C7 ROM dev (type 0x1)
ROM 3 E000E000: CID B105E00D PID 04000BB00C ChipIP dev SCS (type 0x0)
ROM 3 E0001000: CID B105E00D PID 04000BB002 ChipIP dev DWT (type 0x0)
ROM 3 E0002000: CID B105E00D PID 04000BB00E ChipIP dev (type 0x0)

ROM 3 E0000000: CID B105E00D PID 04000BB001 ChipIP dev ITM (type 0x0)
ROM 2 E0041000: CID B105900D PID 04001BB975 ARCH 23B:4A13r0 CoreSight dev
type 0x13 Trace Source - core
ROM 2 E0042000: CID B105900D PID 04004BB906 CoreSight dev type 0x14 Debug
Control - Trigger, e.g. ECT
ROM 1 E0040000: CID B105900D PID 04000BB9A9 CoreSight dev type 0x11 Trace
Sink - TPIU
ROM 1 E0043000: CID B105F00D PID 04001BB101 System dev (type 0x0)
Inspected v.2 External Flash Device on SPI MIMXRT1050-EVK_S26KS512S.cfx
Image 'MIMXRT1050-EVK_S26KS512S Jul 17 2018 18:22:12'
Non-standard DAP stride detected - 1024 bytes
NXP: MIMXRT1052xxxxB
Connected: was_reset=true. was_stopped=false
Awaiting telnet connection to port 3333 ...
GDB nonstop mode enabled
Opening flash driver MIMXRT1050-EVK_S26KS512S.cfx
Sending VECTRESET to run flash driver
Writing 25020 bytes to address 0x60000000 in Flash
Erased/Wrote page 0-0 with 25020 bytes in 1387msec
Closing flash driver MIMXRT1050-EVK_S26KS512S.cfx
Flash Write Done
Flash Program Summary: 25020 bytes in 1.39 seconds (17.62 KB/sec)
Starting execution using system reset and halt target
© 2018 NXP Semiconductors. All right reserved 14
Note - system reset leaves VTOR at 0x200000 (not 0x60000000 which a booted
image might assume)
Stopped: Breakpoint #1

11 SDK Examples

The EVK-IMXRT10505 SDK version .4.4x contains many examples, the majority of which
target executon (XIP)r from hyperfash.

Note: Examples orom earlier SDKs typically targeted TAX regions and required modifcaton
to executed orom hyperflash4

Impirtng an example

From the QuickStart panel select the Import SDK example wizard. Ensure the Board is
selected as in the previous wizard and click Next.

Use the Filter to quickly locate the required example. For example: type 'led' as shown
below:

Select the required projects and Click Finish.

© 2018 NXP Semiconductors. All right reserved 15

The Project Explorer will look as below:

Note: the two projects demonstrate a simple delay based blinky and an interrupt based
version4 -oth import the required RMP header and executed orom Flash4

This project(s)r can be debugged directly and you should see the board’s LED fash. If the
board is power cycled, you should see the LED fash program re-run from Flash.

12 Resets

When is a reset not a reset ...

The standard way a project is debugged is (afer fash programming)r for the MCU to be reset
(by the debug probe)r and user debug control made via an automatc breakpoint set on
main()r. This scheme though will only work if the applicaton being debugged can be
launched via the BootROM. In our case above, that would be an XIP image in Hyperfash
with a correct header to describe the world and initalise the hyper fash.

However, it can also be useful to develop and debug applicatons running directly in a RAM
region. For this to work the user must stll gain control of the executng code i.e. via a
breakpoint on main()r again. However, a real reset cannot be used since this will run the
BootROM and this will control the boot process and not lead us to our RAM locaton ...

Instead for RAM projects, the debugger will issue a virtual reset using the type SOFT. A SOFT
reset type, simulates some parts of a real reset including setng up the PC, SP, PSR etc.
Since this is not a real reset, the MCU hardware can inherit some setup from its (pre reset)r

© 2018 NXP Semiconductors. All right reserved 16

world, for example multplexing, RAM and/or FLASH coniguratons. Note: This may be
beneicial, but may also cause problems or confusion if not well understood.

SDK projects that target RAM use this SOFT reset mechanism.

Note: A project running orom TAX may not restart successoully since Global data may only
have the intended inital values on the frst executon4 1his is a consequence oo the
mechanism and not a oault as such4 1he expected result can be achieved by using the
QuickStart ‘1erminate, -uild and Debug’ oeature4 All inoormaton will oo course be lost io the
target board is powercycled4

13 Building and Debugging Prijects fir RAM

Some example projects (for the iMX RT1050)r are conigured to link to RAM. This can been
achieved using an MCUXpresso IDE feature that ensures any deined Flash region is ignored
by the Linker resultng in an image being linked to the irst deined RAM region.

Note: Some older SDK examples that target TAX executon target the D1CX TAX region at
5x.5555555 using the SOF1 reset type4 1hey also make use oo the above 'Link to TAX'
oeature while not actually including the defniton oo any Flash region I this oeature is only
intended oor the case where flash is also present and is redundant io no flash is defned and
may lead to user conousion (see the secton below oor more inoormaton)4

Using the SDRAM regiin

The TCM and OC memories should always be present when the part is powered on.
However, the largest RAM on this board is the 32MB SDRAM. As mentoned above, this
RAM is conigured by the XIP header code for Flash projects - but for RAM projects to use
this RAM area an alternatve initalisaton scheme is needed.

Note: Mo you wish to target the SDTAX region, this must be the frst TAX region defned in
the projects memory confguraton4 Mo a flash region is also defned, the Link applicaton to
TAX opton must also be set4

LinkServer debug operatons can run script iles at the debug connect stage and also at the
debug reset stage. In this situaton, a connect script can be used to enable the SDRAM -

© 2018 NXP Semiconductors. All right reserved 17

therefore making this available for an image to download into the RAM (at 0x80000000)r.
Such a script 1050RT_SDRAM_Init.scp.

The appropriate script can be dropped directly into the project folder (as below)r or copied
into the product itself at <install dir>/ide/bin/Scripts4

To use the Script, edit the existng LinkServer Launch coniguraton (double click)r and click
inside the Connect Script Value ield to browse for the Script. Select the Script and click OK.

Note: to create a new launch confguraton either peroorm a debug operaton via a
LinkServer/CXSMSDAP probe or right click on the project and select Launch Confguratons I>
Create new444 I> XCURpresso MDE LinkServer 444

When run, the script will cause the following output in the connectons Debug log.

============= SCRIPT: RT1050_SDRAM_Init.scp =============

Setup SDRAM
Clock Init Done
SDRAM Init Done
============= END SCRIPT ================================

and of course SDRAM memory will be available for image download.

© 2018 NXP Semiconductors. All right reserved 18

New and example (board)r projects will contain a functon -OATD_ConfgXPU within the ile
board.c . This functon performs the MPU coniguraton for the various memory regions
including cache setup and the exact behaviour of this functon is controlled by a number of
deined symbols.

It is strongly recommended that (if used) this functon is examined and understood to
ensure the memory system is confgured as desired.

14 SDK Examples: Cinvertng a RAM priject ti XIP frim Flash

Project built to run from RAM will of course be lost if power is removed however they can
be converted to run from Flash (XIP)r by following the procedure outlined below.

There are three (or four!)r steps to convert an image for XIP from Flash.

1 - Change the projects memory coniguraton to include the HyperFlash region and add a
fash driver.

Right click on the project and select Propertes -> C/C++ Build -> MCU setngs -> Edit
Click Add Flash

The hyper fash on this board is located at 0x60000000 and is 64MB in size.

Enter the new Locaton address at 0x60000000, and the Size as 0x400000 (or 64M)r, then
click in the Driver ield to select the fash driver 'MIMXRT1050-EVK_S26KS512S.cfx. Be sure
to click outside of the edited feld (i.e. inside a blank feld) to ensure the edit completes.

Your memory coniguraton will look like below:

Note: the frst TAX (STAX Data 1CX in this case) will automatcally be used oor the project's
stack and global memory usage4 1he order oo the memory regions can be changed using the
right hand (up/down) buions io required4

© 2018 NXP Semiconductors. All right reserved 19

Click OK.

2 - Add the XIP iles.

To add XIP iles to a project, select the Project and then click the Manage SDK Components
as shown below:

3 - Add the symbol deiniton(s)r as discussed above.

Right click on the project and select Propertes -> C/C++ Build -> Setngs -> Preprocessor ->
click + and add the new deine – XIP_EXTERNAL_FLASH=1

4 – Restore Linkage to Flash (if required)r.

For projects built to execute from Flash (the historically normal case)r - there is a quick
setng that can be used to force a project to instead link against the irst RAM bank. The

© 2018 NXP Semiconductors. All right reserved 20

SDK is causing this feature to be set even when no Flash is conigured. Hence when the
project is rebuilt, it will link stll to RAM even though we have just deined a Flash region.

To restore linkage to Flash:

Right click on the project and select Propertes -> C/C++ Build -> Setngs -> Managed Linker
Scripts -> Uncheck - Link applicaton to RAM

Now, debug this applicaton as before:

You should see the PC stopped at a Hyperfash address i.e. in the 0x60000000 range as
below:

Note: as discussed above, projects targetng TAX will use a SOF1 reset type4 1his reset type
is assumed by the MDE to be the deoault oor TAX projects however, some examples may
explicitly set this reset type within the launch confguraton4 1hereoore, io a TAX based
project already has a launch confguraton this SOF1 reset type may remain afer the
conversion to RMP4 1he simplest way to fx this problem is to delete any existng launch
confguraton orom the project and allow a new one to be automatcally reIcreated4
Alternatvely, it can be edited and the SOF1 opton removed leaving no entry oor reset type4

Biitng the Applicatin

Switch of power to the board (or unplug the OpenSDA debug connecton)r. Remember to
ensure the DIP switch (SW7)r is set boot from Hyperfash, then reapply power. The board
should boot the image.

Note: examples that use semihostng oor print, can stll run without debug support io a
hardoault handler ‘semihost_hardoault4c’ is included within the image4 1his handler is usually
included by deoault4

© 2018 NXP Semiconductors. All right reserved 21

15 Triubleshiitng

Erasing the Hyperfash

If for any reason a 'bad' applicaton is programmed into fash and the BootROM boots this
image, the resultng executed code may afect the part in such a way that prevents new
debug operatons succeeding. Should this occur, the following operaton should recover the
situaton.

1. Power of the board.

2. Change the DIP switch (SW7)r to prevent bootng from hyperFlash e.g. set 1- on.
3. As a precauton, kill any actve debug components
 to do this, click the icon:

4. Use the GUI Flash Tool to Erase the data in HyperFlash.

 to do this, select a project that is conigured for XIP from fash (e.g. a New
project as described above)r and click the GUI Flash Tool icon (the chip)r:

5. Select the probe as for a normal debug operaton, then ensure the 'Erase fash
memory' tab is selected. Click the 'Mass erase' radio buton and then click OK.

© 2018 NXP Semiconductors. All right reserved 22

 6. This will cause a mass erase of the hyper fash, leading to the following dialogue.

Remember to restore the DIP switch (SW7)r to set boot from Hyperfash and also power
cycle the board. Next tme the board boots, the BootROM will identfy the Flash as erased
and avoid running any fash image.

Note: 1he tme taken to erase this flash is proportonal to the current contents and may take
some minutes to complete4

Obtaining debug cintril via a debug Cinnect Script

It has been observed that debug control may be impacted by certain applicatons running in
Flash. This problem can manifest in being unable to make a debug connecton – if this
occurs, even a mass erase may be impossible.

As discussed earlier in this document, LinkServer debug operatons can run script iles at the
debug connect stage, a script to work around connecton problems called
RT0505_Debug_Connect4scp is supplied with this document.

This script can be dropped directly into the project folder or copied into the product itself at
<install dir>/ide/bin/Scripts and then referenced in a debug launch coniguraton.

Using external Debug Pribes

The onboard DAPLink OpenSDA debug interface does not deliver partcularly high debug
performance. The standard 20way ‘JTAG’ header may be used with external debug probes
such as the LPC-Link2 for faster debug operaton.

If the LPC-Link2 is used it is recommended that the board be both powered externally and
the Link JP2 should be ited to the LPC-Link2 probe.

Please note: It has been observed that debug via these external debug probes may be less
reliable with certain images. Such debug problems will manifest as wire ack faults. This
problem may be improved if the OpenSDA debug interface is disabled, please see Overview
of Board features … point (6)r for more informaton.

If these are seen it is recommended that the OpenSDA debug connecton is used.

© 2018 NXP Semiconductors. All right reserved 23

Debug perfirmance and the Data Cache

When debugging images that make use of SDRAM or OC_RAM for storage of variable data
(globals, stack, heap etc.)r then the following opton should be set within the LinkServer
debug launch coniguraton as shown below:

This module ensures that debug cache coherence is maintained, and correct debug
operatons may fail if this module is not speciied. However there will be a debug
performance penalty when this module is used.

Note: this module is not required io the SDTAX (or OC_TAX) only contains constant or
uncached data4

© 2018 NXP Semiconductors. All right reserved 24