Contents

1: INTRODUCTION: ANALOG VS.

DIGITAL............................................................... 1

1.1 DIFFERENCES BETWEEN ANALOG AND DIGITAL

SYSTEMS .................................................. 1 1.2 ADVANTAGES OF DIGITAL
SYSTEMS OVER ANALOG SYSTEMS ............................................ 2 2:
NUMBER
SYSTEMS................................................................................................. 7

2.1 POSITIONAL NUMBER

SYSTEMS ..................................................................................... 7

Abstract
VHDL is a comprehensive language for digital system design and
documentation, encompassing system to gate levels of abstraction. This
introduction to the language first provides a short history of the language,
concentrating on the needs identified by the developers and on the principles
behind the its design. Then, an overview of the language’s semantic model is
discussed; finally, features introduced in the latest version of the language are
briefly explored.

Abstract

From the Publisher:

A practical guide to help electronics designers and students make the most of VHDL with the latest, most

widely-used design tools available.This book presents both the professional and academic side of designing

with VHDL, and shows how to take full advantage of VHDL with today's design tools. It contains many

worked examples developed with Synopsys, Mentor Graphics and ViewLook tools. It reviews concurrent,

sequential and structural VHDL, RAM and ROM development, state machines, and RTL synthesis. Test

methodologies and rapid prototyping are covered, as well as examples of quality design and common errors to
avoid. End-of-chapter exercises and laboratories are included throughout.For both engineering professionals

and students interested in using VHDL as effectively as possible in their environments.

Introduction

 VHDL(Very High Speed IC Hardware description Language) is one of the standard hardware
description language used to design digital systems.
 VHDL can be used to design the lowest level (gate level) of a digital system to the highest
level(VLSI module).
 Other than VHDL there are many hardware description languages available in the market for the
digital designers such as Verilog, ABEL, PALASM, CUPL, and etc
 VHDL and Verilog are the most widely used HDLs .The major difference between hardware
description programming languages and others is the integration of time.
 Timing specifications are used to incorporate propagation delays present in the system.

Introduction

VHDL is one of the most widely used hardware description languages, despite perceptions that it is
difficult to learn and use, slow to simulate, hard to synthesize, impossible to formally prove, and
otherwise difficult to employ for its intended purposes. It thus may seem that some sinister force is
behind VHDL. The truth is that VHDL is a world-wide, voluntarily adopted standard, owned and
administered by the IEEE. Thus, despite its detractors, it would seem that VHDL must confer some
benefits. My opinion is that most of the misconceptions about VHDL result from a lack of knowledge of
the history and design principles of the language, of the conditions of its development, standardization
and maintenance, and of how these antecedents are reflected in its specific features. In this chapter, I
provide this information in the hope that it will form a rational basis for understanding, using, and
improving the language. I first present a short history of VHDL in Section 2. During VHDL's initial
specification a number of design principles were identified; these are discussed in Section 3. Section 4
presents the semantic model underlying all VHDL descriptions. In Section 5, I present a number of
features new with the latest version of VHDL, VHDL '92. Section 6 lists some features requested for
VHDL'92 but not included.
History of VHDL
VHDL arose out of the United States government's Very High Speed
Integrated Circuits (VHSIC/ program. In the course of this program, it became
clear that there was a need for a standard language for describing the
structure and function of integrated circuits (ICs). Hence the VHSIC Hardware
Description Language (VHDL) was developed. It was subsequently developed
further under the auspices of the Institute of Electrical and Electronic
Engineers (IEEE) and adopted in the form of the IEEE Standard 1076,
Standard VHDL Language Reference Manual, in 1987. This first standard
version of the language is often referred to as VHDL-87

Like all IEEE standards, the VHDL standard is subject to review at least every
five years. Comments and suggestions from users of the 1987 standard were
analyzed by the IEEE working group responsible for VHDL, and in 1992 a
revised version of the standard was proposed. This was eventually adopted in
1993, giving us VHDL-93. A further round of revision of the standard was
started in 1998. That process was com

pleted in 2001. In 2002,the current VHDL standard (IEEE-1076-2002)was

adopted

Summary: History of VHDL

1981 Initiated by US DoD to address hardware life-cycle crisis
1983-85 Development of baseline language by Intermetrics, IBM
and TI
1986 All rights transferred to IEEE
1987 Publication of IEEE Standard
1987 Mil Std 454 requires comprehensive VHDL descriptions to be
delivered with ASICs
1994 Revised standard (named VHDL 1076-1993)
2000 Revised standard (named VHDL 1076 2000, Edition)
2002 Revised standard (named VHDL 1076-2002)
2007 VHDL Procedural Language Application Interface standard
(VHDL 1076c-2007)
2009 Revised Standard (named VHDL 1076-2008)

VHDL Language Development

Tools
Semantic Designs offers the following VHDL development tools:

 Formatter
 Obfuscator
  Smart Differencer
Service or Enterprise Solution for VHDL:

 Large scale Source Code Search

 Clone Detection
 Migration from VHDL to another language
 Modernizing a legacy VHDL system
For building custom tools for VHDL:

 Front End
 Customizable Analyzer
 Source-to-Source Transformation Tool
 Migration Tool
If your desired tool is not in this list, it can likely be custom-built using the DMS® Software
Reengineering Toolkit.

VHDL Invariants

Case Sensitivity

VHDL is not case sensitive

An example of VHDL case insensitivity.

Dout <= A and B; doUt <= a AnD b;

White Space

VHDL is not sensitive to white space (spaces and tabs) in the source document.

nQ <= In_a or In_b; nQ <=in_a OR in_b;

Comments

Comments in VHDL begin with the symbol “--" (two consecutive dashes). The VHDL synthesizer ignores
anything after the two dashes and up to the end of the VHDL Invariants line in which the dashes appear
.

Two typical uses of comments.

--This next section of code is used to blah-blah

--This type of comment is the best fake for block-style commenting.

PS_reg<=NS_reg;

--Assign next_state value to present_state

Appropriate use of comments increases both the readability and the

understand ability of VHDL code

Parentheses
VHDL is relatively lax on its requirement for using parentheses. Like other
computer languages, there are a few precedence rules associated with the various
operators in the VHDL language. But a better idea is to practice liberal use of
parentheses to ensure the human reader of your source code understands the
purpose of the code.
Example of parentheses that can improve clarity.
if x = ’0’ and y = ’0’ or z = ’1’ then
blah; -- some useful statement
blah; -- some useful statement
end if;
if ( ((x = ’0’) and (y = ’0’)) or (z = ’1’) )
blah; -- some useful statement
blah; -- some useful statement
end if;

VHDL Statements
Similar to other algorithmic programming languages, every VHDL statement is
terminated with a semicolon. This fact helps when attempting to remove compiling
errors from your code since semicolons are often omitted during initial coding.

if, case and loop Statements

 Every if statement has a corresponding then component
 Each if statement is terminated with an end if;
 If you need to use an else if construct, the VHDL version is elsif
 Each case statement is terminated with an end case;
 Each loop statement has a corresponding end loop; statement

Identifiers
An identifier refers to the name given to various items in VHDL. Examples of
identifiers in higher-level languages include variable names and function
names. Examples of identifiers in VHDL include variable names, signal names
and port names.

 Identifiers should be self-describing.

 Identifiers can be as long as you want (contain many characters).
 Shorter names make for better reading code, but longer names present more
information.
 Identifiers can only contain a combination of letters (A-Z and a-z), digits (0-9)
and the underscore character (\").
 Identifiers must start with an alphabetic character.
 Identifiers must not end with an underscore and must never have two
consecutive underscores.
 The best identifier for a function that calculates the position of the Earth is
CalcEarthPosition or calc earth position.

Valid identifiers Invalid identifiers

data_bus--descriptive name 3Bus_val -- begins with a number chr
WE--classic "write enable" DDD--not self commenting
div_flag--provides some info mid_$num--illegal character
port_A--provides some info last__val--consec. underscores
in_bus--input bus str_val_--ends with underscore
clk--classic clock in--uses VHDL reserved word
clk_in @#$%%--total garbage
clk_out Big_vAlUe--valid but ugly
mem_read_data pa--possibly lacks meaning
sim-val--illegal character (dash)
DDE_SUX--no comment

VHDL Design Units

 The “black-box" approach to any type of design implies a hierarchical
structure in which varying amounts of detail are available at each of the
different levels of the hierarchy.
 In the black-box approach, units of action which share a similar purpose
are grouped together and abstracted to a higher level.
  Once this is done, the module is referred to by its inherently more simple
black-box representation rather than by the details of the circuitry that
actually performs that functionality.

This approach has two main advantages.

1. It simplifies the design from a systems standpoint.
2. The black-box approach allows for the reuse of previously written code.

Entity
The VHDL entity construct provides a method to abstract the functionality of a
circuit description to a higher level. It provides a simple wrapper for the lower-
level circuitry. This wrapper effectively describes how the black box interfaces
with the outside world

The entity declaration.

Entity my_entity is
port(
port_name_1 :in std_logic ;
port_name_2 :out std_logic;
port_name_3 :inout std_logic );--do not forget the semicolon
endmy_entity;--do not forget this semicolon either

 Bundles are easily described in the VHDL entity. All that is needed is a new
data type and a special notation to indicate when a signal is a bundle or not.
 The std logic data type has now been replaced by the word std logic vector
to indicate that each signal name contains more than one signal.
 The signals in the bus can be listed in one of two orders
  which are specified by the to and down to keywords. If you want the most
significant bit of your bundle to be on the the first bit on the left you use
downto keyword.

entity mux4 is
port ( a_data : in std_logic_vector(0 to 7);
b_data : in std_logic_vector(0 to 7);
c_data : in std_logic_vector(0 to 7);
d_data : in std_logic_vector(0 to 7);
sel1,sel0 : in std_logic;
data_out : out std_logic_vector(0 to 7));
end mux4;

VHDL Standard Libraries

-- library declaration
library IEEE;
use IEEE.std_logic_1164.all; -- basic IEEE library
use IEEE.numeric_std.all;
std_logic_signed
std_logic_unsigned
std_logic_arith
VHDL libraries allow you to store commonly used packages and entities that you can use in
your VHDL files. A VHDL package file contains common design elements that you can use in
the VHDL file source files that make up your design.
In Project Navigator, a VHDL library is a container, which holds files that define entities,
architectures, or packages. You can view and manage VHDL libraries in the Libraries panel.
Following are the basic steps for creating and using VHDL libraries in Project Navigator:

1.  Create a VHDL library.

2.  Add VHDL files to the VHDL library.
3.  Reference the VHDL library and associated package or entities in a VHDL source file
in your project.

A VHDL library is not stored as a separate file on disk. VHDL libraries and their
corresponding sources are referenced in the ISE® project file and are passed to the
synthesis or simulation tool to be compiled.

Architecture
An architecture can be written by means of three modeling techniques plus any
combination of these three.There is the data flow model, the behavioral model, the
structural model and the hybrid models.
Signal and Variable Assignments In VHDL there are several object types. Among
the most frequently used we will mention the signal object type, the variable object
type and the constant object type. The signal type is the soft ware representation of
a wire. The variable type, like in C or Java, is used to store local information. The
constant is like a variable object type, the value of which cannot be changed. A
signal object can be of different types; for example, a signal object can be of type
std logic or of other types like integer, custom types, etc. The same applies for
variable objects.
library ieee;
use Ieee.std_logic_1164.all; --the ENTITY
entity circuit1 is
port (
A,B,C : in std_logic;
F : out std_logic);
end circuit1;
-- the ARCHITECTURE
architecture circuit1_arc of circuit1 is
signal sig_1: std_logic; -- signal definition
variable var_1: integer;
begin
F <= not (A and B and C); -- variable definition
sig_1 <= A; -- signal assignment
var_1 := 34; -- another signal assignment
end circuit1_arc; -- variable assignment

Signal and Variable Assignments

 Signal and variable assignments can be performed inside a process
 Fundamental difference between signal and variable assignments
 “Variable assignments occur immediately, signalassignments are
scheduled to occur at some point in the future.”

 Inside a process signals are effectively constant

 You can perform a signal assignment, however ...
 ... the assignment only occurs when the process is suspended
 A process suspends when it completes execution or reaches a wait

signal and variable assignment

In VHDL, variable assignments (:=) take effect immediately, the way they 
would in a software language like C, such that subsequent lines see the 
changed value.  Signal assignments (<=) take effect only at the end of 
the delta cycle, which for synthesizable code is the same as saying at 
the end of that run through the process.  Subsequent statements in the 
same process continue to see the old value; only on the next invocation 
of the process will the new value be visible. 

Variable Assignment

The variable assignment statement modifies the value of the variable. The new value
of the variable is obtained by assigning an expression to this variable. In order to
distinguish variable assignment from signal assignment, the variable assignment
symbol is different (:=).

The expression assigned to a variable must give results of the same type as the
variable. The target at the left-hand side of the assignment can be either a name of a
variable or an aggregate.

Example 1

variable X, Y : REAL;
variable A, B : BIT_VECTOR (0 to 7);
type BIT_RECORD is record
  bitfield : BIT;
  intfield : Integer;
end record;
variable C, D : BIT_RECORD;
X := 1000.0;
A := B;
A := "11111111";
A (3 to 6) := ('1','1','1','1');
A (0 to 5) := B (2 to 7);
A (7) := '0';
B (0) := A (6);
C.bitfield := '1';
D.intfield := C.intfield;

Signal Assignment
A Signal assignment statement can appear inside a process (sequential statement) or directly in an
architecture (concurrent statement). The target signal can be either a name (simple, selected, indexed, or
slice) or an aggregate.

A signal assignment with no delay (or zero delay) will cause an event after delta delay, which means that
the event happens only when all of the currently active processes have finished executing (i.e. after one
simulation cycle).

The default delay mode (inertial) means that pulses shorter than the delay (or the reject period if
specified) are ignored. Transport means that the assignment acts as a pure delay line.

VHDL'93 defines the keyword unaffected which indicates a choice where the signal is not given a new
assignment. This is roughly equivalent to the use of the null statement within case (see Examples).

Example:

W <=
A * B;
X <=
transport C after Delay;
Y <=
'0', '1' after 10 ns, '0' after 20 ns;
Z <=
reject 2 ns inertial Inp after 10 ns;
P <=
E1 when C1 else
E2 when C2 else
E3;
Q <= D when Enable = '1' else unaffected;

Concurrent Statements

 All concurrent statements in an architecture are executed simultaneously

  Concurrent statements are used to express parallel activity
 Concurrent statements are executed with no predefined order by the
simulator . So the order in which the code is written does not have any
effect on its function
 Process is a concurrent statement in which sequential statements are
allowed
 All processes in an architecture are executed simultaneously
 Concurrent statements are executed by the simulator when one of the
signals in its sensitivity list changes . This is called occurrence of ‘event’ (c
<= a or b; is executed when either signal ‘a’ or signal ‘b’ changes

 block statement
 process statement
 concurrent procedure call statement
 concurrent assertion statement
 concurrent signal assignment statement
 conditional signal assignment statement
 selected signal assignment statement
 component instantiation statement
 generate statement

Concurrent statements
 The operations in real systems are executed concurrently;
 The VHDL language model sreal systems as a set of subsystems that operate
concurrently;
 Each of these subsystems maybe specified as a separate process and
communication between processes may be accomplished via signals;
 The modeling of real systems in this form may be achieved with concurrent
statements.
 These statements are for use in Architectures
 Types of concurrent statements:
- processstatement
- concurrentsignalassignmentstatement:
▪ simple signal assignment statement
 ▪ conditional signal assignment statement
▪ selected signal assignment statement
- blockstatement
- componentinstantiationstatement
- generatestatement
- concurrentassertionstatement
- concurrentprocedurecallstatement

Concurrent Statements
In VHDL the behaviour of a component can be defined in several ways:

 Processes may be used to describe the behaviour algorithmically. While all

processes included in a design virtually operate in parallel, the
statements within a process are executed sequentially similar to common
programming languages like C, C++, or Pascal. However, there are special
statements defined in VHDL which allow to suspend/resume execution of a
process. Actually, this statements (or a similar construct) must be used in order
to increase simulation time during simulation.
 Concurrent signal assignment statements calculate new values for signals from
an expression. The expression is reevaluated and reassigned whenever a signal
within the expression changes its value. Actually, concurrent signal
assignments are represented by specialised processes.
 Component instantiation statements are used to construct a component from a
set of smaller components. These statements are executed at elaboration time
only. Their single effect is to instantiate other components and connect them
with the current component.

Processes, concurrent signal assignments, and component instantiations may be mixed

arbitrarily in order to describe the structure respectively behaviour of a new
component.

Note, after elaboration the entire VHDL model consists solely of a set of processes
and signals. The processes communicate with each other by reading/writing on these
signals respectively shared variables.
signal assignment operator
The operator <= is known as a signal assignment operator to highlight its true purpose. The
signal assignment operator specifies a relationship between signals. In other words, the
signal on the left side of the signal assignment operator is dependent upon the signals on
the right side of the operator. (Source: Digital_Mclogic_Design by Bryan Mealy, Section:
The Signal Assignment Operator: “<=”, page 339)I couldn't find anything specific on the =>
operator.

VHDL Operators 
 
VHDL supports different classes of operators that operate on signals, variables and constants.
The different classes of operators are summarized below.
 
Class            
1. Logical operators and or nand nor xor xnor
2. Relational operators = /= < <= > >=
3. Shift operators sll srl sla sra rol ror
4.Addition operators + = &      
5. Unary operators + -        
6. Multiplying op. * / mod rem    
7. Miscellaneous op. ** abs not      
 
The order of precedence is the highest for the operators of class 7, followed by class 6 with the
lowest precedence for class 1. Unless parentheses are used, the operators with the highest
precedence are applied first. Operators of the same class have the same precedence and are
applied from left to right in an expression. As an example, consider the following
std_ulogic_vectors, X (=’010’), Y(=’10’), and Z (‘10101’). The expression
 
            not X & Y xor Z rol 1 
 
is equivalent to  ((not X) & Y) xor (Z rol 1)  = ((101) & 10) xor (01011)  =(10110) xor (01011)
= 11101. The xor is executed on a bit-per-bit basis.
 
 
 
 
a.       Logic operators
 
The logic operators (and, or, nand, nor, xor and xnor)  are defined for the “bit”, “boolean”,
“std_logic” and “std_ulogic” types and their vectors. They are used to define Boolean logic
expression or to perform bit-per-bit operations on arrays of bits.  They give a result of the same
type as the operand (Bit or Boolean). These operators can be applied to signals, variables and
constants.
 
Notice that the nand and nor operators are not associative. One should use parentheses in a
sequence of nand or nor operators to prevent a syntax error:
 
X nand Y nand Z will give a syntax error and should be written as (X nand Y) nand Z.
 
b.      Relational operators
 
The relational operators test the relative values of two scalar types and give as result a Boolean
output of “TRUE” or “FALSE”.
 
Operator Description Operand Types Result Type
= Equality any type Boolean
/= Inequality any type Boolean
< Smaller than scalar or discrete array Boolean
types
<= Smaller than or equal scalar or discrete array Boolean
types
> Greater than scalar or discrete array Boolean
types
>= Greater than or equal scalar or discrete array Boolean
types
 
Notice that symbol of the operator “<=” (smaller or equal to) is the same one as the assignment
operator used to assign a value to a signal or variable. In the following examples the first “<=”
symbol is the assignment operator. Some examples of relational operations are:
 
            variable STS               : Boolean;
constant A                  : integer :=24;
            constant B_COUNT   : integer :=32;
            constant C                  : integer :=14;
            STS <= (A < B_COUNT) ;  -- will assign the value “TRUE” to STS
            STS <=  ((A >= B_COUNT) or (A > C));    -- will result in “TRUE”
            STS <=  (std_logic (‘1’, ‘0’, ‘1’) < std_logic(‘0’, ‘1’,’1’));--makes STS “FALSE”
 
            type new_std_logic is (‘0’, ‘1’, ‘Z’, ‘-‘);
            variable A1: new_std_logic :=’1’;
            variable A2: new_std_logic :=’Z’;
            STS <=  (A1 < A2); will result in “TRUE” since ‘1’ occurs to the left of ‘Z’.
           
For discrete array types, the comparison is done on an element-per-element basis, starting from
the left towards the right, as illustrated by the last two examples. 
 
c.       Shift operators
 
These operators perform a bit-wise shift or rotate operation on a one-dimensional array of
elements of the type bit (or std_logic) or Boolean.
 
Operator Description Operand Type Result Type
sll Shift left logical (fill right Left: Any one-dimensional Same as left type
vacated bits with the 0) array type with elements of
type bit or Boolean; Right:
integer
srl Shift right logical (fill left  same as above Same as left type
vacated bits with 0)
sla Shift left arithmetic (fill right same as above Same as left type
vacated bits with rightmost bit)
sra Shift right arithmetic (fill left same as above Same as left type
vacated bits with leftmost bit)
rol Rotate left (circular) same as above Same as left type
ror Rotate right (circular) same as above Same as left type
 
The operand is on the left of the operator and the number (integer) of shifts is on the right side of
the operator. As an example,
 
            variable NUM1          :bit_vector := “10010110”;
            NUM1 srl 2;
 
will result in the number “00100101”.
 
When a negative integer is given, the opposite action occurs, i.e. a shift to the left will be a shift
to the right. As an example
 
NUM1 srl –2 would be equivalent to NUM1 sll 2 and give the result “01011000”.
 
Other examples of shift operations are for the bit_vector A = “101001”
 
variable A: bit_vector :=”101001”;
 
A sll 2   results  in      “100100”
A srl 2   results
in                  “001010”
A sla 2   results
 in                  “100111”
A sra 2   results
in                 “111010”
A rol 2   results
in                  “100110”
A ror 2   results
in                 “011010”
 
 
d.      Addition operators
 
The addition operators are used to perform arithmetic operation (addition and subtraction) on
operands of any numeric type. The concatenation (&) operator is used to concatenate two vectors
together to make a longer one. In order to use these operators one has to specify the
ieee.std_logic_unsigned.all or std_logic_arith package package in addition to the
ieee.std_logic_1164 package.
 
Operator Description Left Operand Right Operand Result Type
Type Type
+ Addition Numeric type Same as left Same type
operand
- Subtraction Numeric type Same as left Same type
operand
& Concatenation Array or element Same as left Same array type
type operand
 
An example of concatenation is the grouping of signals into a single bus [4].
 
signal MYBUS                        :std_logic_vector (15 downto 0);
signal STATUS                       :std_logic_vector (2 downto 0);
signal RW, CS1, CS2             :std_logic;
signal MDATA                                  :std_logic_vector ( 0 to 9);
MYBUS <= STATUS & RW & CS1 & SC2 & MDATA;
 
Other examples are
 
MYARRAY (15 downto 0) <= “1111_1111” & MDATA (2 to 9);
NEWWORD <= “VHDL” & “93”;
 
The first example results in filling up the first 8 leftmost bits of MYARRAY with 1’s and the rest
with the 8 rightmost bits of MDATA. The last example results in an array of characters
“VHDL93”.
 
e.       Unary operators
 
The unary operators “+” and “-“ are used to specify the sign of a numeric type.
 
 Operator Description Operand Type Result Type
+ Identity Any numeric type Same type
- Negation Any numeric type Same type
 
f.        Multiplying operators
 
The multiplying operators are used to perform mathematical functions on numeric types (integer or
floating point).
 
 
Operator Description Left Operand Right Operand Result Type
Type Type
    Any integer or Same type Same type
* Multiplication floating point
Any physical Integer or real Same as left
type type
Any integer or Any physical Same as right
real type type
/ Division Any integer or Any integer or Same type
floating point floating point
Any physical Any integer or Same as left
type real t ype
Any physical Same type Integer
type
mod Modulus Any integer type Same type
rem Remainder Any integer type Same type
 
The multiplication operator is also defined when one of the operands is a physical type and the other an
integer or real type.
 
The remainder (rem) and modulus (mod) are defined as follows:
 
            A rem B = A –(A/B)*B                        (in which A/B in an integer)
            A mod B = A – B * N              (in which N is an integer)
 
The result of the rem operator has the sign of its first operand while the result of the mod operators has
the sign of the second operand.
 
Some examples of these operators are given below.
 
11 rem 4                      results in 3
(-11) rem 4                   results in -3
9 mod 4                        results in 1
7 mod (-4)                    results in –1  (7 – 4*2 = -1).
 
g.       Miscellaneous operators
 
These are the absolute value and exponentation operators that can be applied to numeric types.
The logical negation (not) results in the inverse polarity but the same type.
 
Operator Description Left Operand Right Operand Result Type
Type Type
** Exponentiation Integer type Integer type Same as left
Floating point Integer type Same as left
abs Absolute value Any numeric type Same type
not Logical negation Any bit or Boolean type Same type
 
Delays or timing information

CONCLUSIONS

 This talk has only covered a small part of the VHDL language; many
constructs and features of state of the art FPGA have been omitted (memory,
high speed serial links, processor implementation ….)
 For those interested in learning the VHDL language a good book together
with a Xilinx or Altera supported evaluation board could be the next step
   If the choice is for the XLINX products a good starting point could be an
evaluation board based on Zynq FPGA e.g. the ZedBoard, a development kit
based on Xilinx Zynq-7000 All Programmable SoC.

V CONCLUSION
Fast adders have the advantage to scale better with increasing word widths, since
the delay of the n-bit fast adders is O(log(n)) (carry-look ahead adder). It has been
found that CLA occupies less area which considered from the utilization of LUTs,
slices and over all gate count and total path delay shown in Fig.10 and Fig. 11.
Different bit Carry-lookahead adder design using VHDL is successfully designed,
simulated, tested and implemented onto the Spartan 3E FPGA. It is not possible to
use CLA to realize constant delay for the wider-bit adders since there will be a
substantial loading capacitance, and hence larger delay and larger power
consumption. The CLA has the fastest growing area and power requirements with
respect to the bit size. Similarly the other types of adders can also be designed and
simulated using software and hardware used in this paper.