Analog to digital converter

ADC
Lecturer
Mohand Lokman
 Most signals are
Need to Sample an analog
analog signal
Then convert to digital
by A/D converter

Are sensor outputs Analog ?

Eg. Seatbelt ? EEG, oil temp

Figure 9.36 The process of periodically sampling an analog signal. (a) Sample-and-hold (S/H) circuit.
The switch closes for a small part (t seconds) of every clock period (T). (b) Input signal waveform. (c)
Sampling signal (control signal for the switch). (d)2Output signal (to be fed to A/D converter).
A/D converter
Converts analog signals into binary words
Analog  Digital Conversion
2-Step Process:

• Quantizing - breaking down analog value to set of

finite states (but it still analog)
• Encoding - assigning a digital word or number to each
state
Step 1: Quantizing
Example: a 3 bit A/D , N=23=8 (no. of steps)

Output Discrete Voltage

States Ranges (V)
0-10V signals. 0 0.00-1.25
Separated into discrete
states with 1.25V 1 1.25-2.50
increments. 2 2.50-3.75
Analog quantization size: 3 3.75-5.00
Q=(Vmax-Vmin)/N = (10V 4 5.00-6.25
– 0V)/8 = 1.25V
5 6.25-7.50
6 7.50-8.75
7 8.75-10.0
A/D Conversion Basics: Quantization

Quantization is to convert the

input voltage range into Q=2N
Volt
bands to encode a continuous
analog signal to discrete digital
levels.

Quantization Interval:
Vru  Vrl
Time V 
Q
Quantization Error:
V
emax

2Q
q

6
A/D Conversion Basics: Quantization
saturation error

Quantization error

7
 A/D Conversion Basics: Resolution
• Related to input range, typically
• Lowest bit determines resolution
• Resolution: smallest analog change resulting from changing one
bit
• Since the output of an A/D converter changes in discrete steps,
there is a resolution error (uncertainty), known as a
quantization error.
• The quantization error is ±0.5 LSB. In input units, this is
expressed as
Vru -Vrl
input resolution error   0.5 N volts
• For an 8-bit converter 2
Vru -Vrl
input resolutionerror   0.5 8
 0.002(Vru -Vrl ) volts
2
• For a 12-bit converter
Vru -Vrl
input resolutionerror   0.5 12
 0.0001(Vru -Vrl ) volts
2
8
 Estimating digital output of DAC

• To calculate the output of simple ADC use the

following eq:
Where:
Vi: input voltage
Vrl: lower range voltage
Vru: upper range voltage
N: number of bits
int: rounding the number to the nearest integer
• To calculate the output of 2s’complement ADC use the
following eq:
 Simple ADC

• Example : a 4-bit ADC has input range of 0-10 volt. Calculate the digital
output for the input voltage of 6.115?

• Sol:
6.115 − 0 4
𝐷0 = 𝑖𝑛𝑡 2 = 𝑖𝑛𝑡 9.78 = 10
10 − 0
 2’s complement ADC

• Example: a 12-bit ADC with 2’s complement output has an input range -
10 to +10. calculate the digital output when the input voltage is -11, -5,
0, 6.115 and 12 volt?

Solution:
 A/D Converter Types

• Flash ADC
• Digital ramp ADC
• Successive Approximation ADC
 Flash Analog to Digital Converter
Fast – but more expensive :
Single cycle - Uses many Comparators in parallel with
different reference voltages
Analog
• 2N-1 comparators for N-bits
• Each reference voltage
equivalent to a quantization
level Digital
• Encoding logic produces
word

Figure 9.45 Parallel, simultaneous, or flash A/D conversion.

13
Diagram of a flash ADC [1]

AD/DA (v.5b) 14
How Flash Works
• As the analog input voltage exceeds the reference voltage at each
comparator, the comparator outputs will sequentially saturate to a
high state.
• The priority encoder generates a binary number based on the
highest-order active input, ignoring all other active inputs.
Type 4 ADC : Flash ADC (cont’d)

• Very fast for high quality audio and video.

• Very expensive for wide bits conversion.
• Sample and hold circuit usually NOT required.
• The number of comparators needed is 2N-1 which
grows rapidly with the number of bits
• E.g. for 4-bit, 15 comparators;
• for 6-bit, 63 comparators.

AD/DA (v.5b) 16
Digital ramp ADC
• One of the simplest solution to solve the problem of flash ADC (the number of the comparators)
is to use digital-ramp ADC and this consist of DAC, binary counter and one comparator, see fig
 Digital ramp ADC
• the clock to increment the counter one step at a time until VAX >=VA. It is called a digital-
ramp ADC because the wave form at VAX is a step-by-step ramp. The comparator output
serves as the active-LOW end-of conversion signal. the operation of ramp ADC proceeds
as follows
• 1. A START pulse is applied to reset the counter. The HIGH at START also inhibits clock
pulse form passing through the AND gate into the counter.
• 2. With all 0’s at its input, the DAC’s output will be VAX = 0V.
• 3. Since VA > VAX, the comparator output, EOC, will be HIGH.
• 4. When START returns LOW, the AND gate let the clock pulses get through to the
counter.
• 5. As the counter advances, VAX increases one step at a time.
• 6. This continues until VAX > VA. Then EOC will go LOW so that the counter will stop
counting.
• 7. The conversion process is now complete as signaled by the HIGH-to- LOW transition at
EOC, and the contents of the counter are the digital representation of VA.
Digital ramp ADC
Problem: Assume the 10-bit ramp ADC has the following values, clock
frequency = 1 MHz and with F.S. (full scale) output = 10.23 V.
Determine
a. The digital equivalent obtained for VA = 3.728 V.
b. The conversion time.
c. The resolution error of this converter.
Solution
a. D0=int(3.728/10.23)*2^10=373
d. Tc= 373*1/1M=373usec
c. Re=±.5*10.23/2^10=4.9mv
Digital ramp ADC
Note:
1. from this problem we realized that the conversion time depend on the steps that the counter should
count to reach the input voltage (the worst case, Va=Full scale).
2. Even that, it still the cheapest ADC
Successive-Approximation ADC
Successive-Approximation ADC
Successive-Approximation ADC (conversion
time)