TABLE 5.

1
Unloaded BJT Transistor Amplifiers

Configuration Zi Zo Av Ai
Fixed-bias: Medium (1 k) Medium (2 k) High (- 200) High (100)
VCC
Io = RB 7 bre = RC 7 r o (RC 7 ro) bRBro
RC = - =
RB re (ro + RC)(RB + bre)
Ii
+ ⬵ bre ⬵ RC
Vo RC ⬵ b
+ Zo
– (RB Ú 10bre) (ro Ú 10RC) ⬵ -
Vi re
Zi (ro Ú 10RC,
–
(ro Ú 10RC) RB Ú 10bre)

Voltage-divider Medium (1 k) Medium (2 k) High (- 200) High (50)

bias: VCC
Io RC = R1 7 R2 7 bre = RC 7 r o RC 7 r o b(R1 7 R2)ro
R1 = - =
Ii
re (ro + RC)(R1 7 R2 + bre)
+ ⬵ RC
+ Zo RC b(R1 7 R2)
Vo (ro Ú 10RC) ⬵ - ⬵
Vi Zi R2 re R1 7 R2 + bre
RE CE
– – (ro Ú 10RC) (ro Ú 10RC)

Unbypassed High (100 k) Medium (2 k) Low (- 5) High (50)

emitter bias: VCC
= RB 7 Zb = RC RC bRB
Io RC = - ⬵ -
RB r e + RE RB + Zb
Ii Zb ⬵ b(re + RE) (any level of ro)
+
+ Zo ⬵ RB 7 bRE ⬵ -
RC
Vo RE
Vi
Zi RE (RE W re)
(RE W re)
– –

Emitter- High (100 k) Low (20 ) Low ( ⬵1) High (- 50)
follower: VCC
= RB 7 Zb = RE 7 r e RE bRB
Ii RB = ⬵ -
RE + r e RB + Zb
Zb ⬵ b(re + RE)
+ ⬵ re
⬵ RB 7 bRE ⬵ 1
Vi Io RE + (RE W re)
Zi Vo
– Zo (RE W re)
–
Common-base: Low (20 ) Medium (2 k) High (200) Low (- 1)
Ii
= RE 7 r e = RC RC ⬵ -1
⬵
+ Io RC + re
Vi Zi
RE
Vo ⬵ re
Zo
VEE VCC
– – (RE W re)

Collector Medium (1 k) Medium (2 k) High (- 200) High (50)

feedback: VCC
Io
RC re ⬵ RC 7 RF RC bRF
RF = ⬵ - =
1 RC re RF + bRC
+ (ro Ú 10RC)
Ii + b RF
(ro Ú 10RC) RF
+ Zo Vo (ro Ú 10RC) ⬵
(RF W RC) RC
Vi Z
o
– –

293
 TABLE 5.2
BJT Transistor Amplifiers Including the Effect of Rs and RL

Configuration AvL ⴝ Vo >Vi Zi Zo

- (RL 储 RC) RB 7 bre RC

re

Including ro:

(RL 7 RC 7 ro)
- RB 7 bre RC 7 r o
re

- (RL 7 RC) R1 7 R2 7 bre RC

re

Including ro:

- (RL 7 RC 7 ro)
R1 7 R2 7 bre RC 7 r o
re

RE = RL 7 RE Rs = Rs 7 R1 7 R2
Rs
⬵ 1 R1 7 R2 7 b(re + RE) RE 储 a + re b
b

Including ro:
Rs
⬵ 1 R1 7 R2 7 b(re + RE) RE 储 a + re b
b

- (RL 7 RC) RE 7 r e RC
⬵
re

Including ro:

- (RL 7 RC 7 ro)
⬵ RE 7 r e RC 7 r o
re

VCC

- (RL 7 RC)
R1 7 R2 7 b(re + RE) RC
RC RE
R1
Vo
Rs Vi Including ro:
Zo
- (RL 7 RC)
+ RL R1 7 R2 7 b(re + Re) ⬵ RC
Vs Zi R2 RE
RE
–

294
 TABLE 5.2 (Continued)
BJT Transistor Amplifiers Including the Effect of Rs and RL

Configuration AvL ⴝ Vo >Vi Zi Zo

VCC

- (RL 7 RC)
RC RB 7 b(re + RE1) RC
RB RE1
Vo
Rs Vi

Zo Including ro:
+ RE1 RL
Zi - (RL 7 RC)
Vs RB 7 b(re + RE) ⬵ RC
– REt
RE2 CE

VCC

- (RL 7 RC) RF
RC bre 储 RC
re 兩 Av 兩
RF
Vo

Rs Vi
Zo
Including ro:
+ RL
- (RL 7 RC 7 ro) RF
Vs bre 储 RC 7 RF 7 r o
– Zi re 0 Av 0

VCC

- (RL 7 RC) RF
RC bRE 储 ⬵ RC 7 RF
RE 0 Av 0
RF
Vo

Rs Vi
Zo Including ro:

+ RL - (RL 7 RC) RF
⬵ ⬵ bRE 储 ⬵ RC 7 RF
Vs
Zi RE
L
RE 0 Av 0
–

packaged system relates to the actual amplifier or network. The system of Fig. 5.61 is
called a two-port system because there are two sets of terminals—one at the input and the
other at the output. At this point it is particularly important to realize that
the data surrounding a packaged system is the no-load data.
This should be fairly obvious because the load has not been applied, nor does it come with
the load attached to the package.

Ii Io

+ +
Zi Zo
Vi AvNL Vo

– –

Thévenin

FIG. 5.61
Two-port system.
295