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EE-382M

VLSI–II

FLIP-FLOPS

Gian Gerosa, Intel


Fall 2008

EE 382M Class Notes Page # 1 / 31 The University of Texas at Austin


OUTLINE

• Trends
• LATCH Operation
• FLOP Timing Diagrams & Characterization
• Transfer-Gate Master-Slave FLIP-FLOP
• Merged Functions
• Clock Skew
• Other Topologies
• SCAN
• References
• Homework Discussion

EE 382M Class Notes Page # 2 / 31 The University of Texas at Austin


Where are we going?

• Trends in high-performance systems


– Higher clock frequency leads to …..
– Deeper pipelines or more parallelism leads to ….
– More transistors which leads to ….
– More sequentials (FLOP or LATCH) which leads to ….

• Consequences
– Increased flip-flop overhead
• Cycle time in 12-15 stage pipeline uArchitectures ~22 FO4 delays
• FLOP overhead ~3 FO4 delay (D-Q delay) ~14%
– Clock uncertainty (jitter & skew) also affects cycle time
– Clock power

EE 382M Class Notes Page # 3 / 31 The University of Texas at Austin


Why work on Sequentials ?

In a 3.3 GHZ processor (90n CMOS) cycle=300pS


- Typical D-Q delay is ~ 90ps.
- If one can design a faster sequential, say D-Q delay of ~
60pS, this represents ~10% processor performance
improvement.
- If in addition one can absorb 15ps of clock uncertainties
and/or embed one level of logic, this will yield an additional
5-10% processor performance improvement.

- Attaining a 10-20% performance improvement via


architecture enhancements is very expensive (area, power,
complexity, etc.)!

EE 382M Class Notes Page # 4 / 31 The University of Texas at Austin


Basic LATCH Operation

Dout Dout

Din Din

clock clock
Transparent-low Transparent-high

transparent opaque transparent opaque


clock clock

Din Din

Tdq Tdq
Dout Dout

Tsu Th Tsu Th

EE 382M Class Notes Page # 5 / 31 The University of Texas at Austin


Difference between a LATCH and a FLOP

Data Q Edge triggered


F-F

Clock

Clock

Data

Q Q only changes at
the rising edge of
the clock

Data Q
Latch
Transparent / Opaque
Clock

Clock

Data

Q ‘follow’s the
input DATA
EE 382M Class Notes Page # 6 / 31 The University of Texas at Austin
Building a FLOP with Two Latches

Dout

Din

clock

EE 382M Class Notes Page # 7 / 31 The University of Texas at Austin


FLOP Delay
• Sum of setup time and Clk-output delay is the only true
measure of the performance with respect to the system
speed (MAXDELAY)
• Tcycle = Tcq + Tlogic + Tsu + Tskew
• Tlogic contains interconnect delay

D Q logic D Q N loads

CLK CLK

Tcq Tlogic Tsu

EE 382M Class Notes Page # 8 / 31 The University of Texas at Austin


FLOP Timing Diagrams

Clock
volts

Din Tsu Thold

Dout Tcq

100 200 300 400 500 600 700 800 900 1000

picoseconds

Tsu : input setup time


Thold : input hold time
Tcq : clock to out

Tdata to out = Tsu + Tcq

EE 382M Class Notes Page # 9 / 31 The University of Texas at Austin


Functional Pass/Failure vs. Tsu and Th
Master internal node clock
clock

fail

fail

pass
pass

Input setup time Input hold time


EE 382M Class Notes Page # 10 / 31 The University of Texas at Austin
FLOP Characterization

Tsu : input setup time


Thold : input hold time
Tcq : clock to out

Tdata to out = Tsu + Tcq


picoseconds

Tdata to out

10%
Tcq
Tsu Thold

minimum Tcq

-250 -200 -150 -100 -50 0 50 100 150 200 250

Data to Clock (picoseconds)

EE 382M Class Notes Page # 11 / 31 The University of Texas at Austin


Q1 D1’
MAXDELAY D1 D Q logic D Q Q1’

CLK CLK

Tcycle

CLK
Tcq Tcq
D1

Q1

D1’ Tlogic

Q1’
Tsu Tsu

Tlogic < Tcycle – (Tcq + Tsu) or Tcycle <= Tlogic + Tcq + Tsu

EE 382M Class Notes Page # 12 / 31 The University of Texas at Austin


Q1 D1’
MAXDELAY D1 D Q logic D Q Q1’
with Clock Skew
CLK CLK

CLK CLK’
Tcycle
CLK
Tcq Tskew
CLK’
Tsu Tcq

D1

Q1

D1’ Tlogic’
Tsu
Q1’

Tlogic < Tcycle – (Tcq + Tsu + Tskew)


EE 382M Class Notes Page # 13 / 31 The University of Texas at Austin
Q1 D1’
MINDELAY D1 D Q logic D Q Q1’

CLK CLK

CLK CLK
Tcycle

CLK
Tcq
D1

Q1
Tlogic
D1’

Q1’
Tsu Thold

Tlogic > Thold – Tcq + Tskew


EE 382M Class Notes Page # 14 / 31 The University of Texas at Austin
DESIGN WINDOW

Thold – Tcq + Tskew < Tlogic

and

Tlogic < Tcycle – (Tcq + Tsu + Tskew)

If Tcq > Thold + Tskew, then MINDELAY hazard


is removed since Tlogic >= 0 always.

EE 382M Class Notes Page # 15 / 31 The University of Texas at Austin


T-G Master-Slave FLOP TIMING:
(buffered non-inverting) Tsu ~ 1 TG + 2 inverters
Th ~ 1 inverter
Tcq ~ 1 TG + 1 inverter

Dout

Din

Non time-borrowing

Isolates SLAVE latch timing


optimization/sensitivities from
output load.
clock

Time borrowing keeps the MASTER


open longer by ~ 2 inverter delays;
need to be careful about
MINDELAYS
EE 382M Class Notes Page # 16 / 31 The University of Texas at Austin
Merged Function inverting FLOP

Dout
A
B

clock

EE 382M Class Notes Page # 17 / 31 The University of Texas at Austin


RESETABLE Master-Slave FLOP (asynchronous)

Dout

Din

Rb

clock

EE 382M Class Notes Page # 18 / 31 The University of Texas at Austin


Clock Skew Impact to Fmax

Din
master

master
slave

slave
Dout

clock
clock

τ1 τ3
LCB

LCB
local clock
τ2 buffer

GLOBAL clock

Tcycle = Tcq + Tlogic + Tsu + Tclock_uncertainty

Tclock_uncertainty = clock skew + clock jitter clock skew = τ1 – τ2 – τ3

EE 382M Class Notes Page # 19 / 31 The University of Texas at Austin


Other Circuit Topologies for M-S FLOPS

• C2MOS
• Hybrid Latch Flip-Flop (HLFF)
• Pulse Latch
• In Backup:
• True Single-Phase Clock FLOP
• K-6 Dual-Rail ETL
• Semi-Dynamic Flip-Flop (SDFF)

EE 382M Class Notes Page # 20 / 31 The University of Texas at Austin


C2MOS FLOPS clk
slave

CLK CLKB

Din Q
CLKB CLK

master
clk

CLKB CLK

CLK CLKB

CLKB CLKD
CLK Robustness to clock slope
Low power feedback
Poor driving capability

EE 382M Class Notes Page # 21 / 31 The University of Texas at Austin


Hybrid Latch Flip-Flop (HLFF)
(AMD K-6, Partovi, ISSCC 1996)

Dout
N

Din

Dclk_
Clk

EE 382M Class Notes Page # 22 / 31 The University of Texas at Austin


Hybrid Latch Flip-Flop (HLFF) waveforms
TIMING:
Sampling Window ~ 3 inverters
Tsu ~ 0 to slightly negative
Th > sampling window
Tcq ~ 2 inverters

Clk

Dclk_

Din valid

N valid

Dout valid

EE 382M Class Notes Page # 23 / 31 The University of Texas at Austin


Pulse Latch

Din

Dout

pclk
Clock

EE 382M Class Notes Page # 24 / 31 The University of Texas at Austin


Pulse Latch Waveforms
TIMING:
Sampling Window ~ NAND + τ
Tsu ~ 0 to slightly negative
Th > sampling window
Tcq ~ 2 inverters

Clock

Pclk

Din valid

Dout valid

EE 382M Class Notes Page # 25 / 31 The University of Texas at Austin


FLOP with SCAN p
in out

BCLK
n
SCAN GADGET

ACLK

Scan_in Scan_out
ACLKB

ACLK

FUNCTIONAL
ACLKB
ACLK

Din Dout

clock

EE 382M Class Notes Page # 26 / 31 The University of Texas at Austin


A Typical Scan Path

scanable FLOPS
CLK#

CLK#
scanable
DI ACLK
Store_en Latches
Q ACLK ACLK

SI
DO

SO
CLK CLK#
BCLK CLK CLK#
CLK
CLK#_P CLK
BCLK BCLK
ACLK BCLK

Store_en ACLK
Q

CLK#
Hold_scan FLOPS CLK#
CLK CLK
BCLK
(non-destructive scan) CLK#_P
ACLK BCLK

EE 382M Class Notes Page # 27 / 31 The University of Texas at Austin


QUICK AREA and TIMING budgets in 130nm

Inverting FLIP-FLOP:

Area ~ 60 μm2
Tsu ~ 35ps
Tcq ~ 65ps

Total FLOP timing overhead ~ 100ps

Scan Gadget area ~ 35 μm2

TOTAL scan inverting FLOP ~ 95 μm2

This layout does not include scan.

EE 382M Class Notes Page # 28 / 31 The University of Texas at Austin


QUICK AREA and TIMING budgets in 65nm

Inverting FLIP-FLOP:

Area ~ 15 μm2
input output
Tsu ~ ? ps
Tcq ~ ? ps 0.45 μm Rest 0.90 μm

of
Total FLOP timing overhead ~ ? ps 0.25 μm FLOP 0.50 μm

Scan Gadget area ~ 9 μm2

TOTAL scan inverting FLOP ~ 24 μm2

EE 382M Class Notes Page # 29 / 31 The University of Texas at Austin


Design Goals
Target:
Small clock load
Shortest Din to Dout direct path
Low-power feedback
Simultaneously optimize both master and slave latches
High driving capability
Optimize speed * power product

while:
Minimizing Tsu + Thold (smallest sampling window)
Reducing sensitivity to clock slew rate and skew
Not allowing floating nodes

Characterization:
Use worst case Tcq + Tsu for MAXDELAY analysis.
Use worst case Thold for MINDELAY analysis.
Take into account all sources of power dissipation

EE 382M Class Notes Page # 30 / 31 The University of Texas at Austin


References
1. A. Chandrakasan, W.J. Bowhill, F. Fox, Design of High-Performance
Microprocessor Circuits, IEEE Press, New York, 2001. Chapter 11
“Clocked Storage Elements” by Hamid Partovi, pages 207-234.
2. V. G. Oklobdzija, The Computer Engineering Handbook, CRC Press,
Boca Raton, Florida, 2002. Chapter 10.2 “Latches and Flip-Flops” by
Fabian Klass, pages 10.34-10.69.
3. R. J. Baker, H.W. Li, D.E. Boyce, CMOS Circuit Design, Layout, and
Simulation, IEEE Press, New York, 1998. Chapter 13, pages 255-
274.
4. V. G. Oklobdzija et. al. , Digital System Clocking: High-Performance
and Low-Power Aspects, A Wiley-IEEE Press Publication, 264 pages,
2003.

Reference 2 has a very nice treatment of FLOPS/LATCHES, MIN/MAXDELAY,


SKEW, etc with plenty of timing diagrams.

EE 382M Class Notes Page # 31 / 31 The University of Texas at Austin


BACKUP

EE 382M Class Notes Page # 32 / 31 The University of Texas at Austin


Transfer-Gate (T-G) Master-Slave FLOP

• Low power feedback


• Un-buffered inputs
– input capacitance depends on the phase of the clock
– over-shoot and under-shoot with long routes
– Wire length must be restricted at the input
• Buffered input addresses above issues
• Low power
• Small clk-output delay, but positive setup
• Easily embedded scan, mux, other simple functions

EE 382M Class Notes Page # 33 / 31 The University of Texas at Austin


Hybrid Latch Flip-Flop Highlights

• Flip-flop features:
– single phase clock
– edge triggered, on one clock edge
• Latch features: Soft clock edge property
– brief transparency, equal to 3 inverter delays
– negative setup time
– allows slack passing
– absorbs skew
– minimum delay between flip-flops must be controlled
• Fully static
• Possible to incorporate logic

EE 382M Class Notes Page # 34 / 31 The University of Texas at Austin


ATPG Sequence Timing
Aclk, Bclk Freq = 1/16 GCLK

DI ACLK CLK#
ACLK

1st System Cycle


SI DO
1st Capture 2nd System Cycle
SO
in Slave CLK#
CLK
BCLK
2nd CLK
BCLK
launch
GCLK

CLK
DC STUCK @
CLK#

Capture at speed in slave

Capture at speed in master


CLK

Transition Fault testing


CLK#

Observe Master
BCLK
BCLK BCLK

ACLK ACLK
ACLK

STORE_EN

SHIFT_EN

EE 382M Class Notes Page # 35 / 31 The University of Texas at Austin


Merged Function MUX-FLOP

SelA_
SelB_
SelC_
SelD_
A

Dout

D
clock

EE 382M Class Notes Page # 36 / 31 The University of Texas at Austin


Another RESETABLE Master-Slave FLOP (synchronous)

Dout
Din

Rb

clock

EE 382M Class Notes Page # 37 / 31 The University of Texas at Austin


True Single-Phase Clock (TSPC) FLOP

Y
Dout
clock
X
Din

MASTER PRE-CHARGE SLAVE

Clock power is low; no local inversion required.

EE 382M Class Notes Page # 38 / 31 The University of Texas at Austin


True Single-Phase Clock FLOP Waveforms
TIMING:
Tsu ~ 2 inverters
Th ~ 2 inverters
Tcq ~ 3 inverters

clock

Din valid

X valid

Y valid

Dout valid

EE 382M Class Notes Page # 39 / 31 The University of Texas at Austin


Semi-Dynamic Flip-Flop (SDFF)

Dclk

• Soft edge conditioned by data since first stage is pre-charged - cross-coupled


latch is added for robustness
• Small penalty for adding logic
• Latch has one transistor less in stack - faster than HLFF, but 1-1 glitch exists

EE 382M Class Notes Page # 40 / 31 The University of Texas at Austin


Semi-Dynamic Flip-Flop Waveforms
TIMING:
Sampling Window ~ 2 inverters + 1 NAND
Tsu ~ 0 to slightly negative
Th > sampling window
Tcq ~ 2 inverters

Clk

Dclk

D valid

N valid

K valid

Q valid

EE 382M Class Notes Page # 41 / 31 The University of Texas at Austin


K-6 Dual-Rail ETL

Pch

A B

Dclk_
Determines A, B, Q,
and Q_ pulse widths

EE 382M Class Notes Page # 42 / 31 The University of Texas at Austin


K-6 Dual-Rail Waveforms TIMING:
Sampling Window ~ 3 inverters
Tsu ~ 0 to slightly negative
Th > sampling window
Tcq ~ 2 inverters

Clk

Dclk_

D valid

A valid

B valid

T is determined by 4 inversions
Pch
T

Q valid

Q_ valid
EE 382M Class Notes Page # 43 / 31 The University of Texas at Austin
HMK#3 Problem 1.
For both Din transitions (0->1 and 1->0), determine the input setup Tsu, input hold Thold, and
clock to out Tcq for the following 4 FLIP FLOPS (a, b, c, d). Use 70ps slew rate (full rail)
for Din and clock; use the 130 nm CMOS transistor models. These designs are all driving a
4.2/2.1 inverter.

Show ALL your work; also answer the following questions pertaining to each design:

a. List 3 deficiencies with this design. Hint: look at b, c designs. Will this design work
for a cycle time of 450ps? Why or why not?
b. Is the Din input capacitance lower than design a.? What about the clock
capacitance?
c. What are the benefits of placing the slave latch off to the side? Is this a time-
borrowing FLOP? Is the clock capacitance lower than design b? Any benefit in
clocking the master LATCH feedback?
d. This design is a pulsed LATCH. Describe it’s behaviour with timing diagrams;
Compared to a traditional FLIP-FLOP scheme, list ONE advantage and ONE
disadvantage.

Simulation Tips:
• Use HSPICE ic statements to properly initialize these sequential circuits.

EE 382M Class Notes Page # 44 / 31 The University of Texas at Austin


Homework # 3, Problem #1
FLOP design A

0.28/0.6 0.28/0.6

0.13/0.6 0.13/0.6
4.2
0.56 1.4
din dout Out
Din 18.0
0.28 0.28 0.28 0.7
2.1

0.28

0.28
clock

clock

EE 382M Class Notes Page # 45 / 31 The University of Texas at Austin


Homework # 3, Problem #1
FLOP design B

0.28/0.6 0.28/0.6

0.13/0.6 0.13/0.6

0.28 0.28 4.2


0.56 0.56 1.4
din Dout_b Out
Din 18
0.28 0.28 0.28 0.28 0.7
2.1
0.56 0.56

clock

clock

EE 382M Class Notes Page # 46 / 31 The University of Texas at Austin


Homework # 4, Problem #2
FLOP design C

0.28

0.28

0.28
0.28 0.28/0.6
0.28
0.28 0.13/0.6

0.28

0.13

0.28 0.28 4.2


0.56 0.56 1.4 Dout_b
din Out
Din 18.0
0.28 0.28 0.28 0.28 0.7
2.1
0.28 0.28

0.13 0.13

0.13 0.13 clock


clock

EE 382M Class Notes Page # 47 / 31 The University of Texas at Austin


Homework # 4, Problem #2
FLOP design D

0.28/0.6

0.13/0.6

0.28

0.13

0.28 4.2
0.56 1.4
din Dout Out
Din 18.0
0.28 0.28 0.7
0.56 0.28 2.1

pclk
0.56
clock
clock
0.28 0.13 0.28 0.13 0.28
0.56
0.13 0.13 0.13 0.13 0.13

EE 382M Class Notes Page # 48 / 31 The University of Texas at Austin

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