Field Effect Transistor (FET) : Electronic II Second Year, 2015-2016 Part II Lectures

University of Missan Field Effect Transistor(FET)
Electrical Engineering Department

Second Year, Electronic II,2015-2016
University of Missan
Electronic II
Second Year,2015-2016
Part II Lectures
Field Effect Transistor (FET)

Assistant Lecture: Maab Alaa Hussain
1
1. Field-Effect Transistors (FETs)
Basic Definitions:
The FET is a semiconductor device whose operation consists of
controlling the flow of current through a semiconductor channel by application
of an electric field (voltage)There are two categories of FETs: the junction
field-effect transistor (JFET) and the metal-oxide-semiconductor field-effect
transistor (MOSFET). The MOSFET category is further broken-down into:
depletion and enhancement types.
A Comparison between FET and BJT:
 FET is a unipolar device. It operates as a voltage-controlled device

with either electron current in an n-channel FET or hole current in a p-
channel FET.
 BJT made as npn or as pnp is a current-controlled device in which both
electron current and hole current are involved.
 The FET is smaller than a BJT and is thus for more popular in integrated
circuits)ICs).
 FETs exhibit much higher input impedance than BJTs.
 FETs are more temperature stable than BJTs.
 BJTs have large voltage gain than FETs when operated as an amplifier.
 The BJT has a much higher sensitivity to changes in the applied
signal (faster
response) than a FET.
2
Junction Field-Effect Transistor (JFET(:

The basic construction of n-channel (p-channel) JFET is shown
in Fig. 1-1a (b).Note that the major part of the structure is n-type (p-
type) material that forms the channel between the embedded layers of p-type
(n-type) material. The top of the n-type(p-type) channel is connected through
an ohmic contact to a terminal referred to as the drain "D", while the lower end
of the same material is connected through an ohmic contact to a terminal
referred to as the source "S". The two p-type materials are connected
together and to the gate "G" terminal.
Fig. (1-1)
Basic Operation of JFET:
 Bias voltages are shown, in Fig. 1-2, applied to an n-channel JFET

devise.
 VDD provides a drain-to-source voltage, VDS, (drain is positive
relative to source) and supplies current from drain to source, ID,
(electrons move from source to drain(.
 VGG sets the reverse-bias voltage between the gate and the
source, VGS, (gate is biased negative relative to the source).
 Input impedance at the gate is very high, thus the gate current IG =
0 A.
3
 Reverse biasing of the gate-source junction produces a

depletion region in the n-channel and thus increases its
resistance.
 The channel width can be controlled by varying the gate voltage,
and thereby, ID can also be controlled.
 The depletion regions are wider toward the drain end of the
channel because the reverse-bias voltage between the gate and the
drain is greater than that between the gate and the source.
Fig. (1-2)
JFET Characteristics:
When VGS = 0 V and VDS < VP (pinch-off voltage): ID

rises linearly with VDS (ohmic region, n-channel resistance is
constant), as shown in Fig. 1-3.
 When VDS is increased to a level where it appears that the two

depletion regions would "touch", a condition referred to as pinch-
off will result. The level of VDS that establishes this condition is
referred to as the pinch-off voltage and is denoted by VP.
4
Fig. (1-3)
 When VGS = 0 V and VDS ≥VP : ID remains at its saturation

value IDSS beyond VP, as shown in Fig. 1-4.
Fig. (1-4)
When VGS < 0 and VDS some positive value: The effect of the
applied negative-bias VGS is to establish depletion regions similar to
those obtained with VGS = 0 V but at lower levels of VDS. Therefore,
the result of applying a negative bias to the gate is to reach the saturation
level at lower level of VDS, as shown in Fig. 1-5.
Fig. (1-5)
5
Summary:
 For n-channel JFET:

1. The maximum current is defined as IDSS and occurs when VGS
= 0 V and VDS ≥ VP as shown in Fig. 1-6a.
2. For gate-to-source voltages VGS less than (more negative than) the
pinch-off level, the drain current is 0 A (ID = 0 A) as appearing in
Fig. 1-6b.
3. For all levels of VGS between 0 V and the pinch-off level, the
current ID will range between IDSS and 0 A, respectively, as
shown in Fig. 1-6c.
Fig. (1-6)
 For p-channel JFET:
6
a similar list can be developed (see Fig. 1-7(.
Fig.(1-7)
Shockley's Equation:
For the BJT the output current IC and input controlling current IB were
related by β, which was considered constant for the analysis to be
performed. In equation form:
In the above equation a linear relationship exists between IC and IB.
Unfortunately, this linear relationship does not exist between the output
(ID) and input (VGS) quantities of a JFET. The relationship between
ID and VGS is defined by Shockley's equation:
[1.1]
7
The squared term of the equation will result in a nonlinear relationship

between ID and VGS, producing a curve that grows exponentially with
decreasing magnitude of VGS.
Transfer Characteristics:
Transfer characteristics are plots of ID versus VGS for a fixed value of

VDS. The transfer curve can be obtained from the output characteristics
as shown in Fig. 1-8, or it can be sketched to a satisfactory level of
accuracy (see Fig. 1-9) simply using Shockley's equation with the
four plot points defined in Table 1-1.
Fig.(1-8)
Table 1-1
Fig.(1-9)
8
Important Relationships:
A number of important equations and operating characteristics have

introduced in the last few sections that are of particular importance for the
analysis to follow for the dc and ac configurations. In an effort to isolate
and emphasize their importance, they are repeated below next to a
corresponding equation for the BJT. The JFET equations are defined
for the configuration of Fig. 1-10a, while the BJT equations relate
to Fig. 1-10b.
Fig.(1-10)
Transconductance Factor:
The change in drain current that will result from a change in gate-to-
source voltage can be determined using the transconductance factor gm in
the following manner:
9
The transconductance factor, gm,
)on specification sheets, gm is provided as
yfs) is the slop of the characteristics at the
point of operation, as shown in Fig. 1-11.

Fig.(1-11)
That is,
An equation for gm can be derived as follows:
[1.2]
And
[1.3]
where g mo is the value of gm at VGS = 0 V. Equation [1.2] then

becomes:
[1.4]
10
JFET Output Impedance:
The output impedance (rd) is defined on the drain (output) characteristics

of Fig. 1-12 as the slope of the horizontal characteristic curve at the point
of operation. In equation form:
[1.5]
where yos is the output admittance, with the units of μS.
Fig.[1-12]
JFET AC Equivalent Circuit:
The control of Id by Vgs is include as a current source g mVgs

connected from drain to source as shown in Fig. 1-13. The current source
has its arrow pointing from drain to source to establish a 180o phase shift
between output and input voltages as will as occur in actual operation.
The input impedance is represented by the open circuit at the input
terminals and the output impedance by the resistor rd from drain to
source.
11
Fig.(1-13)
Exercises:
1. Sketch the transfer curve defined by IDSS = 12 mA and VP = − 6 V.
2. For a JFET with IDSS = 8 mA and VP = − 4 V, determine:
a. the maximum value of gm (that is, g mo ), and
b. the value of gm at the following dc bias points:
VGS = − 0.5 V, VGS = − 1.5 V, and VGS = − 2.5 V.
4. Given yfs = 3.8 mS and yos = 20 μS, sketch the JFET ac

equivalent model.
12
2. DC Biasing Circuits of JFETs
1. Fixed-Bias Configuration:
For the circuit of Fig. 1-1,

I G 0 A ,
And VRG =IG RG = 0V .
For the input circuit,
And: VGS=- VGG
Fig(2-1)
A graphical analysis is shown in
Fig.(2-2).
Fig.(2-2)
13
Example 2-1:
For the circuit of Fig. 2-1 with the following parameters: IDSS = 10 mA,
VP = − 8 V, VDD = + 16 V, VGG = 2 V, RG = 1 MΩ, and RD = 2
kΩ, determine the following: VGSQ, IDQ, VDS, VD, VG, and VS.
Fig.(2-3)
2. Self-Bias Configuration:
Fig.(2-4)
14
A graphical analysis is shown in Fig.(2-5)
Fig.(2-5)
Example 2-2:
For the circuit of Fig. 2-4 with the following parameters: IDSS = 8 mA,
VP = − 6 V, VDD = + 20 V, RG = 1 MΩ, RS = 1kΩ, and RD = 3.3 kΩ,
determine the following:
VGSQ, IDQ, VDS, VG, VS, and VD.
Fig. (2-6)
15
Example 2-3 (Common-Gate Configuration(:
For the common-gate configuration of Fig. 2-7, determine the following:
VGSQ, IDQ, VD, VG, VS, and VDS.
Fig. (2-7)
Fig. (2-8)
16
Example 2-4 (Design)
For the circuit of Fig. 2-9, the levels of VDQ and IDQ are
specified. Determine the required values of RD and RS.
Fig. (2-9)
(2-10)
Fig. (2-10)
17
3. Voltage-Divider Bias Configuration:
Fig. (2-11)
A graphical analysis is shown
in Fig. (2-12).
Fig. (2-12)
Example 2-5:
For the circuit of Fig. 2-11 with the following parameters: IDSS = 8
mA, VP = − 4 V, VDD = + 16 V, R1 = 2.1 MΩ, R2 = 270 kΩ, RD = 2.4
kΩ, and RS = 1.5 kΩ, determine the following: VGSQ, IDQ, VD, VS,
VDS, and VDG.
18
Fig. (2-13)
Example 2-6 (Two Supplies(:
Determine the following for the circuit of Fig. 2-14; VGSQ, IDQ, VDS, VD,
and VS.
Fig. (2-14)
19
Fig. (2-15)
Example 2-7 (p-channel JFET):
Determine VGSQ, IDQ, and VDS for the p-channel JFET of Fig. 2-16.
Fig. (2-16)
20
Fig. (2-17)
21
4. JFET Small-Signal Analysis
Common-Source Configuration:
The common-source configuration circuit of Fig. 3-1 includes a source

resistor (RS (that may or may not be bypassed by a source capacitor (C S)
in the ac domain.
Fig. (3-1)
Bypassed (absence of RS):
For the ac equivalent circuit of Fig. 3-2,
Fig. (3-2)
Fig. (3-2)
22
Unbypassed (include of RS):
For the approximate ac equivalent circuit ( rd Ω) of Fig. 3-3,
Fig.(3-3)
23
Common-Drain (Source-Follower) Configuration:
The common-drain (source-follower) configuration circuit is shown in

Fig. 3-4.
Fig. (3-4)
For ac equivalent cct. Of Fig. (3-5),
Fig. (3-5)
24
Common-Gate Configuration:
The common-gate configuration circuit is shown in Fig. 3-6.
Fig. (3-6)
For the approximate ac equivalent circuit ( rd ≈ Ω ) of Fig. 3-7,
25
Fig. (3.7)
26
Example 3-1 (Analysis):
For the JFET amplifier circuit of Fig. 3-8 with parameter gm = 2.2 mS,
determine: Zi, Zo, Z o′ , Av = Vo/Vi, Ai = Io/Ii, Avs =Vo /Vs and Vo .
Assume rd >10RD .
Fig. (3-8)
27
Example 3-2 (Design)
Complete the design of the JFET amplifier circuit shown in Fig. 3-9 to
have a voltage gain =7.5, using a relatively high level of gm for this
device defined at VGSQ = VP/4. Assume rd >10RD
Fig. (3-9)
28
MOSFET
1. DEPLETION-TYPE MOSFET
There are two types of FETs: JFETs and MOSFETs. MOSFETs are
further broken down into depletion type and enhancement type. The
terms depletion and enhancement define their basic mode of operation,
while the label MOSFET stands for metal-oxide-semiconductor-field-
effect transistor. Since there are differences in the characteristics and
operation of each type of MOSFET, they are covered in separate sections.
In this section we examine the depletion-type MOSFET, which happens
to have characteristics similar to those of a JFET between cutoff and
saturation at IDSS but then has the added feature of characteristics that
extend into the region of opposite polarity for VGS.
Basic Construction
The basic construction of the n-channel depletion-type MOSFET is

provided in Fig. (1-1).
Fig. (1-1)
29
 There is no direct electrical connection between the gate terminal

and the channel of a MOSFET.
In addition:
 It is the insulating layer of SiO in the MOSFET construction that

accounts for the very desirable high input impedance of the device.
Basic Operation and Characteristics
In Fig. 1-2 the gate-to-source voltage is set to zero volts by the direct
connection from one terminal to the other, and a voltage V DS is applied
across the drain-to-source terminals. The result is an attraction for the
positive potential at the drain by the free electrons of the n-channel and a
current similar to that established through the channel of the JFET. In
fact, the resulting current with VGS =0 V continues to be labeled IDSS, as
shown in Fig. 1-3.
Fig. (1-2)
Fig.(1-3)
30
In Fig. 1-4, VGS has been set at a negative voltage such as 1 V. The
negative potential at the gate will tend to pressure electrons toward the p-
type substrate and attract holes from the p-type substrate (opposite
charges attract) as shown in Fig. 1-4. Depending on the magnitude of the
negative bias established by VGS , a level of recombination between
electrons and holes will occur that will reduce the number of free
electrons in the n-channel available for conduction. The more negative
the bias, the higher the rate of recombination. The resulting level of drain
current is therefore reduced with increasing negative bias for VGS as
shown in Fig. 1-3 for VGS= 1 V, 2 V, and so on, to the pinch-off level of 6
V. The resulting levels of drain current and the plotting of the transfer
curve proceeds exactly as described for the JFET.
Fig.(1-4)
Example
Sketch the transfer characteristics for an n-channel depletion-type

MOSFET with I DSS =10 mA and VP =4V
Solution
31
all of which appear in Fig. 1-5.Before plotting the positive region of VGS
, keep in mind that ID increases very rapidly with increasing positive

values of V GS. In other words, be conservative with the choice of values
to be substituted into Shockley’s equation. In this case, we will try 1 V as
follows:
Fig.(1-5)
32
p-Channel Depletion-Type MOSFET
The construction of a p-channel depletion-type MOSFET is exactly the

reverse of that appearing in Fig. 1-1. That is, there is now an n-type
substrate and a p-type channel, as shown in Fig. 1-6a. The terminals
remain as identified, but all the voltage polarities and the current
directions are reversed, as shown in the same figure.
(a) (b) (c)
Fig. (1-6)
Symbols of n-channel and p-channel MESFET are shown in Fig.(1-7).
Fig. (1-7)
33
2. ENHANCEMENT-TYPE MOSFET
Although there are some similarities in construction and mode of
operation between depletion-type and enhancement-type MOSFETs, the
characteristics of the enhancement-type MOSFET are quite different from
anything obtained thus far. The transfer curve is not defined by
Shockley’s equation, and the drain current is now cut off until the gate-to-
source voltage reaches a specific magnitude. In particular, current control
in an n-channel device is now effected by a positive gate-to-source
voltage rather than the range of negative voltages encountered for n-
channel JFETs and n-channel depletion-type MOSFETs.
Basic Construction
The basic construction of the n-channel enhancement-type MOSFET
is provided in Fig. 2-1. A slab of p-type material is formed from a silicon
base and is again referred to as the substrate.
Fig. (2-1)
34
Basic Operation and Characteristics

If VGS is set at 0 V and a voltage applied between the drain and source
of the device of Fig. 2-1, the absence of an n-channel (with its generous
number of free carriers) will result in a current of effectively zero
amperes — quite different from the depletion-type MOSFET and JFET
where ID = IDSS. It is not sufficient to have a large accumulation of
carriers (electrons) at the drain and source (due to the n-doped regions) if
a path fails to exist between the two. With VDS some positive voltage, V
at 0 V, and terminal directly connected to the source, there are in fact two
reverse-biased p-n junctions between the n-doped regions and the p-
substrate to oppose any significant flow between drain and source.
Fig. (2-2)
As VGS is increased beyond the threshold level, the density of free carriers
in the induced channel will increase, resulting in an increased level of
drain current. However, if we hold VGS constant and increase the level of
VDS , the drain current will eventually reach a saturation level as occurred
for the JFET and depletion-type MOSFET. The leveling off of IDDS is due
35
to a pinching-off process depicted by the narrower channel at the drain

end of the induced channel as shown in Fig. 2-3. Applying Kirchhoff’s
voltage law to the terminal voltages of the MOSFET of Fig. 2-3, we find
that
VDG=VDS- VGS
Fig. (2-3)
In fact, the saturation level for VDS is related to the level of applied VGS
by:
Obviously, therefore, for a fixed value of VT , then the higher the level of
VGS , the more the saturation level for VDS, as shown in Fig. 2-3 .
36
Fig.(2-4)
 For values of VGS less than the threshold level, the drain current
of an enhancement-type MOSFET is 0 mA.
Figure 2-4 clearly reveals that as the level of VGS increased from VT to
8 V, the resulting saturation level for ID also increased from a level of 0 to
10 mA. In addition, it is quite noticeable that the spacing between the
levels of VGS increased as the magnitude of VGS increased, resulting in
ever-increasing increments in drain current. For levels of VGS>V , the
drain current is related to the applied gate-to-source voltage by the
following nonlinear relationship:
37
Symbols of Enhancement MOSFET of P-channel and n-channel are

shown in Fig. (2-5).
Fig.(2-5)
38
MOSFET Biasing
1- DEPLETION-TYPE MOSFETs
The similarities in appearance between the transfer curves of JFETs and

depletion type MOSFETs permit a similar analysis of each in the dc
domain. The primary difference between the two is the fact that
depletion-type MOSFETs permit operating points with positive values of
VGS and levels of ID that exceed IDSS. In fact, for all the configurations
discussed thus far, the analysis is the same if the JFET is replaced by a
depletion-type MOSFET.
EXAMPLE :1
For the n-channel depletion-type MOSFET of Fig. 6.29, determine:
(a) IDQ and VGSQ.
(b) VDS.
39
Solution
(a) For the transfer characteristics, a plot point is defined by ID= IDSS/4 _
6mA/4 _1.5 mA and VGS=VP/2 =3 V/2 =1.5 V. Considering the level of
VP and the fact that Shockley’s equation defines a curve that rises more
rapidly as VGS becomes more positive, a plot point will be defined at
VGS=+1 V. Substituting into Shockley’s equation yields.
The resulting transfer curve appears in the following Figure. Proceeding

as described for JFETs, we have:
Fig.(1-1)
The plot points and resulting bias line appear in Fig.(1-1), the resulting
operating points:
40
 H.W: Repeat Example 1 with RS=150Ω.
Example:2
Determine the following for the network below:
a) IDQ and VGSQ.

b) VD.
Solution:
41
 H.W2: Determine
VDS for the
following network.
42
2- ENHANCEMENT-TYPE MOSFETs
The transfer characteristics of the enhancement-type MOSFET are quite
different from those encountered for the JFET and depletion-type
MOSFETs, resulting in a graphical solution quite different from the
preceding sections. First and foremost, recall that for the n-channel
enhancement-type MOSFET, the drain current is zero for levels of gate-
to-source voltage less than the threshold level VGS(Th) , as shown in Fig. 2-
1. For levels of VGS greater than VGS(Th), the drain current is defined by
Fig.(2-1)
And:
43
a- Feedback Biasing Arrangement

A popular biasing arrangement for enhancement-type MOSFETs is
provided in Fig. 2-2. The resistor RG brings a suitably large voltage to the
gate to drive the MOSFET “on.” Since IG= 0 mA and V RG = 0 V, the dc
equivalent network appears as shown in Fig. 2-3. A direct connection
now exists between drain and gate, resulting in
VD=VG
VDS=VGS
Fig.(2-2) Feedback biasing arrangement Fig.(2-3) DC Equivalent cct.
For the output circuit:

VDS=VDD-IDRD
VGS=VDD-IDRD
44
Example**: determine IDQ and VDSQ for the following E-MOSFET.
Solution:
45
For VGS =10v< VGS(Th)
For the network bias line:
For the bias line appear below
b- Voltage-Divider Biasing Arrangement:
Applying Kirchhoff's voltage law

around the indicated loop will result in:
46
Example : determine IDQ,VGSQ and VDS for the following network:
Solution:
When VGS=0v
47
 COMBINATION NETWORKS
Now that the dc analysis of a variety of BJT and FET configurations is
established, the opportunity to analyze networks with both types of
devices presents itself. Fundamentally, the analysis simply requires that
we first approach the device that will provide a terminal voltage or
current level. The door is then usually open to calculate other quantities
and concentrate on the remaining unknowns. These are usually
particularly interesting problems due to the challenge of finding the
opening and then using the results of the past few sections to find the
48
important quantities for each device. The equations and relationships used
are simply those we have now employed on more than one occasion—no
need to develop any new methods of analysis.
Example:
Determine the level of VC and VD for the following network:
Solution:
49
 H.W: For the following network determine VD.
50
Example :(Design)
For the voltage-divider bias configuration, if VD= 12 V and V GSQ =2 V,

determine the value of RS.
51
 H.W: The levels of VDS and ID are specified as VDS=1/2VDD and ID

= I D(on) for the network bellow. Determine the level of VDD and
RD.
52
MOSFET Small Signal Analysis
1. DEPLETION-TYPE MOSFETs
The fact that Shockley’s equation is also applicable to depletion-type
MOSFETs results in the same equation for gm. In fact, the ac equivalent
model for D-MOSFETs is exactly the same as that employed for JFETs
as shown in Fig. 1-1.The only difference offered by D-MOSFETs is that
VGSQ can be positive for n-channel devices and negative for p-channel
units. The result is that gm can be greater than gm0 as demonstrated by the
example to follow. The range of rd is very similar to that encountered for
JFETs.
Fig.(1-1)
Example:
The network of 1-2 was analyzed as (first H.W), resulting in VGSQ= 0.35V
and IDQ= 7.6 mA.
(a) Determine gm and compare to g m0.
(b) Find rd.
(c) Sketch the ac equivalent network for
Fig. 1-2.
(d) Find Zi.
(e) Calculate Zo.
(f ) Find Av. Fig. (1-2)
53
Solution:
54
2. Enhancement-TYPE MOSFETs:
The enhancement-type MOSFET can be either an n-channel (nMOS) or

p-channel (pMOS) device, as shown in Fig. 2-1. The ac small-signal
equivalent circuit of either device is shown in Fig. 2-1,revealing an open-
circuit between gate and drain source channel and a current source from
drain to source having a magnitude dependent on the gate-to-source
voltage. There is an output impedance from drain to source rd, which is
usually provided on specification sheets as an admittance yos. The device
transconductance, gm, is provided on specification sheets as the forward
transfer admittance, yfs.
Fig.(2-1)
55
2-1 E-MOSFET DRAIN-FEEDBACK CONFIGURATION

The E-MOSFET drain-feedback configuration appears in Fig. 2-2. Recall
from dc calculations that RG could be replaced by a short-circuit
equivalent since IG= 0 A and therefore VRG=0 V. However, for ac
situations it provides an important high impedance between Vo and Vi.
Otherwise, the input and output terminals would be connected directly
and Vo=Vi.
Fig.(2-2)
Zi: Applying Kirchhoff's current law to the output circuit (at node D in
Fig.2-2) results in:
56
Zo: Substituting Vi=0 V will result in Vgs= 0 V and gmVgs=0, with a short
circuit path from gate to ground as shown in Fig. 2-3. RF, rd and , RD are
then in parallel.
Zo=RFrdRD
Normally, RF is so much larger than rdRD that
Zo rdRD
And with rd≥10RD
ZoRD RF>> rdRD, rd≥10RD
Av: Applying Kirchhoff's current law at node D in fig.(2-2) will result in
57
Example: The E-MOSFET of Fig 2-4 was analyzed in Example **, with
the result that k =0.24 x 10-3A/V2, VGSQ= 6.4 V, and IDQ= 2.75 mA.
(a) Determine gm.
(b) Find rd.
(c) Calculate Zi with and without rd. Compare results.
(d) Find Zo with and without rd. Compare results.
(e) Find Av with and without rd. Compare results.
Fig.(2-4)
Solution:
58
2-2 E-MOSFET VOLTAGE-DIVIDERCONFIGURATION

The last E-MOSFET configuration to be examined in detail is the
voltage-divider network of Fig. 2-5.
59
Fig.(2-5)
The ac equivalent circuit is shown in fig.(2-6)
Fig.(2-6)
60
EXAMPLE(design): Design the fixed-bias network below to have an ac

gain of 10. That is, determine the value of RD.
Solution:
61
 H.W: Choose the values of RD and Rs for the network bellow that
will result in a gain of 8 using a relatively high level of gm for this
device defined at VGSQ=1/4-VP.
 H.W: Determine RD and RS for the network above to establish a

gain of 8 if the bypass capacitor CS is removed.
62

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University of Missan Field Effect Transistor(FET)

Electrical Engineering Department

Field Effect Transistor (FET)

1. Field-Effect Transistors (FETs)

A Comparison between FET and BJT:

 FET is a unipolar device. It operates as a voltage-controlled device

Junction Field-Effect Transistor (JFET(:

Basic Operation of JFET:

 Bias voltages are shown, in Fig. 1-2, applied to an n-channel JFET

 Reverse biasing of the gate-source junction produces a

When VGS = 0 V and VDS < VP (pinch-off voltage): ID

 When VDS is increased to a level where it appears that the two

 When VGS = 0 V and VDS ≥VP : ID remains at its saturation

 For n-channel JFET:

 For p-channel JFET:

a similar list can be developed (see Fig. 1-7(.

In the above equation a linear relationship exists between IC and IB.

The squared term of the equation will result in a nonlinear relationship

Transfer characteristics are plots of ID versus VGS for a fixed value of

A number of important equations and operating characteristics have

The transconductance factor, gm,

)on specification sheets, gm is provided as

yfs) is the slop of the characteristics at the

point of operation, as shown in Fig. 1-11.

An equation for gm can be derived as follows:

where g mo is the value of gm at VGS = 0 V. Equation [1.2] then

JFET Output Impedance:

The output impedance (rd) is defined on the drain (output) characteristics

where yos is the output admittance, with the units of μS.

JFET AC Equivalent Circuit:

The control of Id by Vgs is include as a current source g mVgs

1. Sketch the transfer curve defined by IDSS = 12 mA and VP = − 6 V.

2. For a JFET with IDSS = 8 mA and VP = − 4 V, determine:

a. the maximum value of gm (that is, g mo ), and

b. the value of gm at the following dc bias points:

VGS = − 0.5 V, VGS = − 1.5 V, and VGS = − 2.5 V.

4. Given yfs = 3.8 mS and yos = 20 μS, sketch the JFET ac

2. DC Biasing Circuits of JFETs

For the circuit of Fig. 1-1,

A graphical analysis is shown in

For the circuit of Fig. 2-4,

A graphical analysis is shown in Fig.(2-5)

VGSQ, IDQ, VDS, VG, VS, and VD.

Example 2-3 (Common-Gate Configuration(:

For the common-gate configuration of Fig. 2-7, determine the following:

VGSQ, IDQ, VD, VG, VS, and VDS.

Example 2-4 (Design)

3. Voltage-Divider Bias Configuration:

For the circuit of Fig. 2-11,

A graphical analysis is shown

Example 2-6 (Two Supplies(:

Example 2-7 (p-channel JFET):

4. JFET Small-Signal Analysis

The common-source configuration circuit of Fig. 3-1 includes a source

Bypassed (absence of RS):

For the ac equivalent circuit of Fig. 3-2,

Unbypassed (include of RS):

For the approximate ac equivalent circuit ( rd Ω) of Fig. 3-3,

Common-Drain (Source-Follower) Configuration:

The common-drain (source-follower) configuration circuit is shown in

For ac equivalent cct. Of Fig. (3-5),

The common-gate configuration circuit is shown in Fig. 3-6.

For the approximate ac equivalent circuit ( rd ≈ Ω ) of Fig. 3-7,