Question 4

a) What is the purpose of interrupt mechanism found in processors? Describe by using an

appropriate examples.
Most of external devices are much slower than the processor. Interrupts are provided primarily as
a way to improve processing efficiency by eliminating the time needed for “polling” input/output
devices. So the purpose of the interrupt is to increase the CPU efficiency.

Suppose the processor is transferring data to a printer using the above instruction cycle (when
there is no interrupts). After each write operation, the processor must pause and remain idle until
the printer catches up. The length of this pause may be on the order of many hundreds or even
thousands of instruction cycles that do not involve memory. This is a very wasteful use of the
processor.

The problem with programmed I/O is that the processor has to wait a long time for the I/O
module of concern to be ready for either reception or transmission of data. The processor, while
waiting, must repeatedly interrogate the status of the I/O module. As a result, the level of the
performance of the entire system is severely degraded.

An alternative is for the processor to issue an I/O command to a module and then go on to do
some other useful work. The I/O module will then interrupt the processor to request service when
it is ready to exchange data with the processor. The processor then executes the data transfer, as
before, and then resumes its former processing.

As an example: when interfacing keyboard there is no interrupts,

 Not known when or if keyboard is used

 Not known if keyboard is used
 “Polling” Keyboard
 Waste of CPU time (Inefficiency)
But, if there are interrupts when keyboard activity occurs,

 CPU is informed about the keyboard activity

 CPU interrupts current program execution
 CPU takes necessary actions
 CPU returns to normal program execution

Thus, interrupts increase the CPU efficiency by using instruction cycle (with interrupts) below
shown.
 b) How does the program execution transfer happen due to an interrupt? Use an appropriate
diagram to explain

Let’s consider an interrupt occurs during instruction N. After the execution of instruction N,
CPU checks for possible interrupts and finds information on the occurred interrupt. Then,
Execution process pass to first instruction of ISR (Interrupt service Routine). CPU executes ISR
instructions from begin to last. Then executes RFTFIE. After completing ISR execution,
execution returns to instruction N+1.

c) How does the Interrupt Vector table (IVT) is been utilized in Intel x86 processors to
implement interrupts?

An interrupt vector table is a group of several memory addresses. An interrupt vector is only one
memory address of one interrupt handler. On the x86 architecture, the interrupt vector table
specifies the addresses of all 256 interrupt handlers used in real mode. It means IVT contains 256
vectors holding ISR addresses of all 256 interrupt types.

Vectors 0, 1, 2, 3...255 hold ISR addresses of interrupt types 0, 1, 2...255, receptively.

Each IVT vector has four bytes.

 Two bytes for Offset address of ISR

 Two bytes for Segment address of ISR

IVT is in memory address space from address 0000h to 03FFh. The block diagram of an IVT is
shown below.

Also the interrupt types are shown below.

d) How interrupts are used by hardware designers?
 Software Interrupts by Hardware Designer

– Set of procedures to easily handle hardware are programmed into EEPROM

– This EEPROM is positioned in memory address space

– Addresses of these procedures are kept in interrupt vector table

– Through INT n, programmer can call these procedures

– These procedures are known as BIOS interrupts

 Hardware Interrupts by Hardware Designer

– Intensively use NMI and INTR to interface IO

– Corresponding ISR are also provided

– IVT is loaded accordingly

e) Draw a block diagram of the interface of x86 hardware interrupts. Mention the purpose of
INTR, INTA, Data Bus Signals in the interface.

 INTR

– External device requests CPU for an interrupt

 INTA

– CPU acknowledges interrupt request

– CPU request interrupt type number

 External device sends interrupt type number via D0-7

Question 5
Instruction pipeline of a certain processor has 6 stages

FI – Fetch Instruction
DI – Decode instruction
CO – Calculate Operands
FO – Fetch Operands
EI – Execute Instructions
WR – Write Results /WO – write operand which store the results in memory
a) Draw the timing diagram for the instruction pipeline operation for 9 instructions,
assuming no branches.
 b) Derive the general formula for the total time required to execute n instructions by the
pipeline as a function of pipeline cycle time T and number of pipeline stages k.

T = pipeline cycle time

k = number of pipeline stages

n = number of instructions

Let’s consider the number of pipeline stage k is equal to 5.

k = 5;

The time for: instruction 1= (5+1-1) T = 5T

Instruction 2 = (5+2-1) T = 6T

Instruction 3 = (5+3-1) T = 7T

Instruction n = (5+n-1) T

Therefore,

𝑇ℎ𝑒 𝑡𝑜𝑡𝑎𝑙 𝑡𝑖𝑚𝑒 𝑟𝑒𝑞𝑢𝑖𝑟𝑒𝑑 𝑡𝑜 𝑒𝑥𝑒𝑐𝑢𝑡𝑒 𝒏 𝑖𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛𝑠 = (𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑝𝑖𝑝𝑒𝑖𝑛𝑒 𝑠𝑡𝑎𝑔𝑒𝑠 +

𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑖𝑛𝑠𝑡𝑟𝑢𝑡𝑖𝑜𝑛𝑠 − 1) 𝑝𝑖𝑝𝑒𝑙𝑖𝑛𝑒 𝑐𝑦𝑐𝑙𝑒 𝑡𝑖𝑚𝑒

Total time required to execute n instructions = (k + n – 1) T

c) Derive the formula for pipeline speedup S defined as

𝑇𝑜𝑡𝑎𝑙 𝑡𝑖𝑚𝑒 𝑟𝑒𝑞𝑢𝑖𝑟𝑒𝑑 𝑡𝑜 𝑒𝑥𝑒𝑐𝑢𝑡𝑒 𝑛 𝑖𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛𝑠 𝑤𝑖𝑡ℎ𝑜𝑢𝑡 𝑝𝑖𝑝𝑒𝑙𝑖𝑛𝑒
𝑆=
𝑇𝑜𝑡𝑎𝑙 𝑡𝑖𝑚𝑒 𝑟𝑒𝑞𝑢𝑖𝑟𝑒𝑑 𝑡𝑜 𝑒𝑥𝑒𝑐𝑢𝑡𝑒 𝑛 𝑖𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛𝑠 𝑤𝑖𝑡ℎ 𝑝𝑖𝑝𝑒𝑙𝑖𝑛𝑒

Total time required to execute n instructions with pipeline = (k + n – 1) T

Total time required to execute n instructions without pipeline = nkT

𝑛𝑘𝑇 𝑛𝑘
Therefore, 𝑆𝑘,𝑛 = =
(𝑘+𝑛−1)𝑇 (𝑘+𝑛−1)
 d) Calculate the speedup for 25000 instructions.

𝑛𝑘𝑇 𝑛𝑘
𝑆𝑘,𝑛 = =
(𝑘 + 𝑛 − 1)𝑇 (𝑘 + 𝑛 − 1)
𝑛 𝑛
When 𝑘 → ∞; 𝑆𝑘→∞,𝑛 = 𝑛−1 = =𝑛
1+( ) 1
𝑘

Thus, for n = 25000, 𝑆𝑘→∞,𝑛 = 25000

e) What will happen if 3rd instruction is a branch instruction. Describe by using a timing
diagram.

Assume that instruction 3 is a conditional branch to instruction 15. There is no way to knowing
which instruction will come next until the instruction is executed. If the branch is taken
(determined at the end of time unit 7), the pipeline must be cleared of instructions that are not
useful. During time unit 8, instruction 15 enters the pipeline. No instructions complete during
time units 9 through 12; this is the performance penalty incurred due to branch.
 f) Name and describe an available architectural solution to the problem of branching in
pipelines.

Solution to the problem of branching Description

Multiple streams • Have two pipelines
• Prefetch each branch into a separate pipeline
• Use appropriate pipeline
• Leads to bus & register contention
• Multiple branches lead to further pipelines
being needed
Pre-fetch branch target • Target of branch is prefetched in addition to
instructions following branch
• Keep target until branch is executed
• Used by IBM 360/91
Loop buffer • Very fast memory
• Maintained by fetch stage of pipeline
• Check buffer before fetching from memory
• Very good for small loops or jumps
• c.f. cache
• Used by CRAY-1
Branch prediction • Predict never taken
–Assume that jump will not happen
–Always fetch next instruction
–68020 & VAX 11/780
–VAX will not prefetch after branch if a
page fault would result (O/S v CPU design)

• Predict always taken

–Assume that jump will happen
–Always fetch target instruction
 • Predict by Opcode
–Some instructions are more likely to result
in a jump than thers
–Can get up to 75% success
• Taken/Not taken switch
–Based on previous history
–Good for loops
Delayed branching • Delayed Branch
–Do not take jump until have to
–Rearrange instructions