E3: 231 Digital System Design with FPGA’s

DESE, Indian Institute of Science, Bangalore

Mini Projects 2020

Mini Projects are done batch wise, in batches of two. This need not be the same as the batch
formed for Lab Exercises, you can choose your project partner. You can choose to do it alone
if you prefer. CPU project can be done by up to 3 batches together. Please go through the
literature for clarification on algorithms. Choose the appropriate device for the design to fit
in. Documentation should consist of the following. Mini project should be demonstrated on
FPGA Board. A specific project is allotted to a maximum of 3 batches.

Once you decide on the project partner, send me an email with names of batch members and
a list of at least 5 projects in the order of preference. I would allot project on first come first
basis.

Verbal description of the problem, with clear specifications

Functional partition diagram with suitable designations to all the signals. (Architecture)
Detailed timing diagrams.
State diagram(s)
VHDL source code with Test bench
Timing Constraints, Timing Analysis Reports, Timing Simulation results
Conclusion
References

Go through the references and evolve a realistic specification for the project. You are free to
choose the format for various registers. Concentrate on the core functionality first. Take care
of various issues like timing, synchronization (at various levels), interlocks, contention,
arbitration, overflow, underflow, initialisation, reliability, (fault tolerance), scalability etc.

You can use Digilent BASYS3 Board or Digilent ZYBO FPGA Board for implementation,
these FPGAs has built-in ADC (XADC).

Following Pmods that can be interface to these boards are available. Keypad, LCD Display,
ADC, and DAC.

Only few references are provided, search the IEEE Explore, ACM Digital Library and
Internet for additional literature.

Mini Projects

1. Dual Clock FIFO with different port sizes

Design this from scratch, i.e. using basic blocks like flops and combinational circuits, depth
could be 16. There should be 2 implementations, first one with 2 ports of same width and
second one with 2 ports of different sizes. I.e. if one port is of size 8 bits, other port should be
16 bits.

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2. Hardware SORT (One student Project)
Design hardware to sort 8-bit numbers stored in an array. Core functionality can consist of a
variable length array.

3. Viterbi decoder and encoder

Design convolutional encoder and Viterbi decoder. Demonstrate the error correction
capability.
4. Analog Signal Interface and Filtering
Read the digitized values of an analog signal connected to ADC on FPGA board, do some
digital filtering on these samples and output through the DAC interfaced to board, display
both the input and output on an Oscilloscope.

5. Analog Signal Interface and Processing

Read the digitized values of an analog signal connected to ADC FPGA board, measure the
frequency, find the peak value, average value etc. and display it on LCD or on discrete LEDs.

6. Keyboard and LCD Interface

Interface PmodKYPD Keyboard and PmodCLP LCD Display to BASYS3 Board. Display the
keypress on LCD display. Add some Extra functionalities like scroll, erase, insert, clear etc.

7. Keyboard and VGA Interface

Interface PmodKYPD Keyboard to Xilinx BASYS3 Board and display the characters
received from keyboard on VGA display.

8. Keyboard and HDMI Interface

Interface a keyboard to Xilinx ZYBO Board and display the characters received from
keyboard on LED Monitor through HDMI Port.

9. Sine waveform generator

Generate sine wave using CORDIC, with variable frequency. Implement such that maximum
frequency is very high.

10. Video Display

Connect a video source to this board (e.g. DVD/VCD player) display the video on a LED
Monitor through the HDMI port of ZYBO Board.

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11. Digital PLL Implementation
Implement a DPLL, this should be designed to have minimum synchronization time, i.e. if
input clock changes, within minimum clock cycles output should be synchronized.

12. RISC CPU (Up to 6 Students)

8-bit RISC CPU with following specifications:
Address space: 1 Kbytes
Arithmetic, Logical, load, Store and Jump instructions (Conditional Jump and Call
instructions are optional)
1 interrupt
Reference:
“Computer Organization & Design” By David A Patterson and John L Hennessy

13. Fault Tolerance in FSM

An exploratory project about detecting Single Event Upset (SEU) in FSM with various
coding schemes (binary, gray, one-hot) and to avoid them by using error correction
techniques like parity. Also incorporating Triple Mode Redundancy (TMR) can be
investigated. This could be study of various schemes, example implementations and
demonstrating the fault tolerance.

14. Auto volume leveller

This is about maintaining constant volume in digital audio play out. Assume digital stream
input and maintain constant volume and play out. Think how this could be demonstrated,
using digital port of a DVD/CR-ROM drive?

15. Implementation of Cryptographic algorithms

You can try encoding and decoding of RSA algorithm for smaller key widths.

16. HDMI Interface

Build a HDMI interface and display colour bands / Text on Screen.

17. Audio Player 1

Record the audio samples from Mic input through the Codec in ZYBO Boards, output it to
Line out connector through Codec

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18. Audio Player 2
Play out a stored wave file through Line Out Codec in ZYBO Board, output it to Line out
through Codec

19. UART
Design a UART. Baud rate is fixed. Use a single clock, 16 times the baud rate as the system
clock. A control register sets the number of data bits (7 or 8), number of stop bits (1 or 2) and
the parity scheme (odd/even/none). Interrupt (INT) line goes high on Receive buffer full,
transmit buffer empty, Parity error, receive buffer overflow and Transmit buffer overflow.
These should be controllable through an Interrupt mask register and the individual status
should be available in an Interrupt status register. The registers Transmit buffer, receive
buffer, Control Register, Interrupt mask register and Interrupt status register should be
accessible through the microprocessor bus interface (CS/, RD/, WR/, A2-A0, D7-D0). Serial
transmission pins are (CLK, TxD, RxD).
Reference:
a. USART 8251 data sheet, UART 16550 data sheet
b. “Digital Systems Design Using VHDL”. By Charles H Roth

20. Floating-point multiplication unit with 16-bit significant and 8-bit exponent
Reference:
“Computer Architecture A Quantitative Approach”. By John L Hennessy & David A
Patterson. Appendix. A

21. Floating-point adder unit with 16-bit significant and 8-bit exponent
Reference:
“Computer Architecture A Quantitative Approach”. By John L Hennessy & David A
Patterson. Appendix. A

22. Floating-point Divider unit with 16-bit significant and 8-bit exponent

23. Integer Square Root Unit for 16-bit Numbers

24. Digital Filter (e.g. FIR Filter)

You can either use boards with ADC and DAC to apply signals and get output. Or Simulate
in MATLAB and get Digital inputs and store it in BRAM of FPGA and display Digital
output, you can also take this output to MATLAB and plot it

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25. Image Filter
Store 32 x 32 Gray scale image in BRAM of FPGA, do some filtering (e.g. Denoising) and
display the output.

26. QPSK Modulator

27. FFT Hardware

28. Electrical Power computation Hardware

Calculate Active Power, Reactive Power and Power factor. You can simulate voltage and
current input through signal supplied through ADC.